Groove type MOSFET device and manufacturing method thereof

Abstract

The invention discloses a trench MOSFET device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, wherein an epitaxial layer of a first doping type is formed on the upper surface of the substrate; forming a base region of a second doping type in the epitaxial layer; forming a well region and a source region of which the side edges are connected with the base region in the epitaxial layer; etching the epitaxial layer to form a groove connected to the base region; sequentially forming a first injection buried layer of a first doping type and a second injection buried layer of a second doping type at the bottom of the groove; depositing polycrystalline silicon in the groove to form a grid electrode, wherein the polycrystalline silicon is provided with a dug hole; forming a source metal layer connecting the base region and the source region on the upper surface of the epitaxial layer; the source metal layer is also formed in the digging hole of the polycrystalline silicon, so that the source metal layer passes through the well region and the source region to be connected to the second injection buried layer. The problems caused by the charge storage / accumulation effect can be effectively solved, the device is not easily influenced by the groove, and the design window and the process window of the device can be larger.

Description

Technical Field

[0001] This application relates to the field of semiconductor power devices, and in particular to a trench MOSFET device and a method for manufacturing the same. Background Technology

[0002] Trench MOS (Trench Metal-Oxide-Semiconductor Field-Effect Transistor) is a transistor structure that is an advanced technology developed from the traditional Planar MOS (Plane Metal-Oxide-Semiconductor Field-Effect Transistor). Trench MOS technology achieves higher integration and better electrical performance by etching deep trenches on the surface of semiconductor material and forming transistors on the sidewalls of the trenches.

[0003] Trench MOSFETs embed the gate into the substrate, forming a vertical channel. Compared to planar MOSFETs, this reduces the area occupied by the gate, allowing for a smaller cell pitch and a larger current-carrying area, resulting in more efficient use of the chip area. For the same chip area, a smaller cell size allows for more cells to be connected in parallel, increasing cell and channel density and reducing on-resistance. The gate width of a trench MOSFET is much smaller than that of a planar structure, significantly reducing parasitic gate-drain capacitance Cgd (Miller capacitance) and switching losses. However, at high drain voltages, a large electric field exists at the bottom of the trench, making it susceptible to breakdown and affecting the device's voltage withstand capability and reliability.

[0004] In related technologies, patent CN111755525A discloses a Trench MOS power device and its fabrication method, relating to the field of semiconductor power device technology. It is used to reduce the on-resistance of the device while effectively ensuring the breakdown voltage. It includes: an epitaxial layer, a gate trench, and a buried implantation layer; the gate trench is disposed on the epitaxial layer; the buried implantation layer is located directly below the gate trench and contacts the bottom and sidewalls of the gate trench, and the buried implantation layer includes an N-type buried layer and a P-type buried layer.

[0005] Regarding the aforementioned technologies, if we want to further improve the device's voltage resistance, we need to increase the thickness of the implanted buried layer. However, increasing the thickness of the implanted buried layer will increase the difficulty of the process and increase the cost. In addition, after repeated switching of the device, charge will accumulate at the implanted buried layer, affecting the internal electric field distribution of the device and reducing the overall performance of the device. Summary of the Invention

[0006] To improve the voltage resistance and extend the service life of the device, this application provides a trench MOSFET device and a method for manufacturing the same.

[0007] The first aspect of this application provides a method for manufacturing a trench MOSFET device using the following technical solution: A method for manufacturing a trench MOSFET device includes the following steps: S10. Provide a substrate, wherein an epitaxial layer of a first doping type is formed on the upper surface of the substrate; S20. Ions are implanted into the epitaxial layer for the first time to form multiple base regions of the second doping type in the epitaxial layer; S30. Ions are implanted into the epitaxial layer for a second time to form a well region and a source region in the epitaxial layer, wherein the sides of the well region and the source region are connected to the base region. S40. Etch the epitaxial layer to form a trench that penetrates the well region and the source region, wherein the trench is not connected to the base region; S50. Ions are implanted into the epitaxial layer for the third time to form a first implanted buried layer and a second implanted buried layer sequentially at the bottom of the trench. The first implanted buried layer is of a first doping type, and the second implanted buried layer is of a second doping type different from the first doping type. The first implanted buried layer and the second implanted buried layer are not connected to the base region. S60. Polysilicon is deposited in the trench to form a gate, wherein the polysilicon has a hole. S70. A source metal layer is formed on the upper surface of the epitaxial layer to connect the base region and the source region; the source metal layer is also formed in the hole of the polysilicon, so that the source metal layer passes through the well region and the source region and is connected to the second implanted buried layer.

[0008] By adopting the above technical solution, a unique P-type and N-type region with a trench bottom structure is formed, effectively reducing the on-resistance of the device while improving its withstand voltage and reliability. Repeated switching of the device leads to charge accumulation, increasing parasitic capacitance and reducing switching speed. Furthermore, repeated switching increases the on-resistance, affecting power consumption. Therefore, this application effectively solves the problems caused by charge storage / accumulation effects by grounding through a second implantation buried layer. Additionally, implantation only at the bottom of the trench means the device's turn-on and turn-off performance are affected by the trench depth and morphology. By implanting base regions on both sides of the first and second implantation buried layers, the device is less affected by the trench, allowing for a larger design and process window.

[0009] Optionally, step S50 includes: S51. A mask is formed on the upper surface of the epitaxial layer, the mask also covering the trench sidewalls; S52. Ions are implanted to form a first implantation layer in the bottom of the trench. By controlling the implantation angle, the first implantation layer has a structure that is thin in the middle and thick on both sides. S53. Ions are implanted to form a second implantation layer within the first implantation layer. Through vertical implantation, the second implantation layer is distributed in a ring shape.

[0010] By adopting the above technical solution, a trench bottom implantation layer with a special structure is formed. Specifically: 1. The first implantation layer, by controlling the injection angle, forms a structure that is thin in the middle and thick at both ends. This structure can effectively shield the electric field at the bottom of the trench, reducing the concentration of large electric fields at the bottom of the trench, thereby improving the device's voltage resistance and reliability. 2. The second implantation layer, through vertical injection, forms a ring-shaped distribution, further enhancing the electric field dispersion effect at the bottom of the trench, effectively reducing the local electric field intensity, and improving the device's breakdown voltage and reliability. 3. This special injection structure not only improves the electric field distribution at the bottom of the trench but also reduces the on-resistance, improving the overall performance of the device.

[0011] Optionally, step S50 includes: S51. A mask is formed on the upper surface of the epitaxial layer, the mask also covering the trench sidewalls; S52. Ions are implanted to form a first implantation layer at the bottom of the trench. Through vertical implantation, the first implantation layer is distributed in a ring shape. S53. Ions are implanted to form a second implantation layer within the first implantation layer. Through vertical implantation, the second implantation layer is distributed in a ring shape.

[0012] By adopting the above technical solution, a ring-shaped first buried layer is formed through vertical injection, resulting in a more uniform electric field distribution at the bottom of the trench and reducing the risk of breakdown caused by localized high electric fields. A second ring-shaped buried layer is formed through further vertical injection, which further optimizes the electric field distribution at the bottom of the trench, reduces the electric field strength at the bottom of the trench, and thus improves the overall compressive strength and reliability of the device.

[0013] Optionally, step S50 includes: S51. A mask is formed on the upper surface of the epitaxial layer, the mask also covering the trench sidewalls; S52. Ions are implanted to form a first implantation layer in the bottom of the trench. By controlling the implantation angle, the first implantation layer has a structure that is thin in the middle and thick on both sides. S53. Ions are implanted to form a second implanted layer within the first implanted layer. The second implanted layer has a structure that is thick in the middle and thin at both sides. The middle part of the second implanted layer penetrates the middle part of the first implanted layer and contacts the epitaxial layer.

[0014] By adopting the above technical solution and controlling the injection angle, the first implanted buried layer is made thinner in the middle and thicker at both sides at the bottom of the trench. This structure can form a relatively uniform electric field distribution at the bottom of the trench, avoiding breakdown problems caused by local electric field concentration. Through vertical injection, the second implanted buried layer emerges from the middle of the first implanted buried layer and contacts the epitaxial layer. This design further optimizes the electric field distribution at the bottom of the trench, enhances the contact between the second implanted buried layer and the epitaxial layer, reduces on-resistance, and improves the overall performance of the device.

[0015] Optionally, step S50 includes: S51. A first mask is formed on the upper surface of the epitaxial layer, and the first mask also covers the trench sidewall; S52. Ions are implanted to form a first implantation layer in the bottom of the trench. By controlling the implantation angle, the first implantation layer has a structure that is thin in the middle and thick on both sides. S53. A second mask is formed on the upper surface of the epitaxial layer, wherein the first mask also covers the trench sidewall, and the opening of the second mask is smaller than the opening of the first mask; S54. Ions are implanted through the second mask to form a second implanted buried layer within the first implanted buried layer. Through vertical implantation, the second implanted buried layer has a uniformly thick cuboid structure, and the middle part of the second implanted buried layer penetrates the first implanted buried layer and contacts the epitaxial layer.

[0016] By employing the above technical solution and using two different masking and implantation methods, a first implantation layer, thicker at the bottom edge and thinner in the middle, is first formed, enhancing the electric field dispersion effect at the bottom of the trench, reducing the local electric field intensity, and improving the device's stress resistance and reliability. Then, using a second mask with a smaller opening and vertical implantation, a second implantation layer, rectangular in shape and penetrating the center of the first implantation layer, is formed. This further optimizes the electric field distribution at the bottom of the trench, reduces charge accumulation, and effectively prevents the risk of gate oxide layer breakdown, thereby improving the overall performance and stability of the device.

[0017] Optionally, step S30 includes: S31. Ions are implanted into the epitaxial layer to form a first channel region of the second doping type; S32. Ions are implanted into the epitaxial layer to form a second channel region of the first doping type, and the first channel region and the second channel region are combined to form a well region; S33. Ions are implanted into the epitaxial layer to form a source region of the first doping type.

[0018] The base region has a higher doping concentration than the first channel region, and the second channel region has a lower doping concentration than the source region, to form an internal negative feedback resistor between the first channel region and the source region, thereby achieving gate-source breakdown voltage.

[0019] By adopting the above technical solution, the second channel region can be equivalent to a negative feedback resistor connected in series with the source electrode of the insulated gate semiconductor chip. When VGS is applied to the gate electrode and source electrode of the insulated gate semiconductor chip from the outside, the resistor can achieve voltage division, improve the gate-source withstand voltage performance, and reduce the risk of the gate oxide layer being broken down.

[0020] Optionally, step S70 includes: S71. An insulating layer is formed inside the hole and on the upper surface of the epitaxial layer; S72. A mask is formed on the upper surface of the insulating layer, and the insulating layer located above the base region and the source region is etched to form a contact hole, and the insulating layer in the trench is etched to form a grounding hole; S73. Fill the contact hole and the ground hole with metal to form a source metal layer, the source metal layer connecting the base region and the source region and passing through the well region and the source region to connect to the second buried injection layer.

[0021] By employing the above technical solution and setting an insulating layer, different functional areas are effectively isolated, preventing short circuits. Further etching of the insulating layer above the base and source regions forms contact holes, and etching of the insulating layer within the trench forms grounding holes, ensuring good electrical connectivity and stability after metal filling. Finally, metal is filled into the contact holes and grounding holes, forming a source metal layer that connects the second implanted buried layer and the base and source regions. This achieves effective connection of all parts within the device, improving the overall reliability and performance of the device.

[0022] Optionally, before step S73, the following steps are also included: S730, depositing metal at the bottom of the contact hole and the bottom of the grounding hole to form a conductive layer.

[0023] By adopting the above technical solution, good electrical contact can be formed in the contact hole and grounding hole, ensuring effective connection between the source metal layer and the second implanted buried layer, base region and source region, reducing contact resistance and improving the reliability and electrical performance of the device.

[0024] The second aspect of this application also provides a trench MOSFET device using the following technical solution: A trench MOSFET device, comprising: Substrate; An epitaxial layer of the first doping type is formed on the upper surface of the substrate; Multiple base regions of the second doping type are disposed within the epitaxial layer; A well region and a source region are disposed within the epitaxial layer, with the sides of the well region and the source region adjacent to the base region; A gate is disposed between the base regions, and the bottom end of the gate extends through the well region and the source region; A first buried layer and a second buried layer are formed at the bottom of the gate. The first buried layer and the second buried layer are not connected to the base region. The first buried layer is of a first doping type, and the second buried layer is of a second doping type different from the first doping type. A source metal layer is formed on the upper surface of the epitaxial layer to connect the base region and the source region. The source metal layer also extends through the well region and the source region to connect to the second implanted buried layer.

[0025] Optionally, the first injection layer has a structure that is thin in the middle and thick at both sides, and the second injection layer is distributed in a ring shape; Alternatively, the first injection layer is distributed in a ring shape, and the second injection layer is distributed in a ring shape; Alternatively, the first implanted layer has a structure that is thin in the middle and thick on both sides, and the second implanted layer has a structure that is thick in the middle and thin on both sides, with the middle part of the second implanted layer penetrating through the middle part of the first implanted layer and contacting the epitaxial layer. Alternatively, the first implanted layer has a structure that is thin in the middle and thick at both sides, and the second implanted layer has a cuboid structure with uniform thickness, and the middle part of the second implanted layer penetrates the first implanted layer and contacts the epitaxial layer.

[0026] In summary, this application includes at least one of the following beneficial technical effects: 1. This application can effectively solve the problems caused by charge storage / accumulation effect by grounding through the second implantation buried layer; at the same time, if the implantation is only performed at the bottom of the trench, the performance of device conduction and turn-off will be affected by the depth and morphology of the trench. However, by implanting the base region on both sides of the first and second implantation buried layers, the device is less affected by the trench, and the design window and process window of the device can be larger. 2. By introducing a first channel region, a second channel region, and a source region structure, the risk of gate oxide layer breakdown is reduced. At the same time, the second channel region is used to achieve voltage division, improve the gate-source breakdown voltage performance, and further improve the reliability of the device. 3. Good electrical contact can be formed in the contact holes and grounding holes, ensuring effective connection between the source metal layer and the second buried layer, base region and source region, reducing contact resistance and improving device reliability and electrical performance. Attached Figure Description

[0027] Figure 1This is a partial structural schematic diagram of a trench MOSFET device according to some preferred embodiments of this application, wherein... Figure 1 (A) is a schematic diagram showing the connection between the source metal layer and the base region and the source region. Figure 1 (B) is a schematic diagram of the connection between the source metal layer and the second implanted buried layer; Figure 2 This is a schematic diagram of the first and second buried layers of a trench MOSFET device according to some preferred embodiments of this application, wherein... Figure 2 (A), (B), and (C) represent variations of different embodiments; Figure 3 This is a schematic diagram illustrating the provision of a substrate and the growth of an epitaxial layer on the substrate during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 4 This is a schematic diagram of the formation of a base region in the epitaxial layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 5 This is a schematic diagram of the formation of a well region and a source region in the epitaxial layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 6 This is a schematic diagram of the process of etching a trench downwards on the upper surface of the epitaxial layer to form a trench MOSFET device in some preferred embodiments of this application. Figure 7 This is a schematic diagram of forming a first buried layer and a second buried layer at the bottom of the trench during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 8 This is a schematic diagram of the first and second buried implantation layers during the fabrication of a trench MOSFET device according to some preferred embodiments of this application, wherein... Figure 8 (A), (B), and (C) represent variations of different embodiments; Figure 9 This is a schematic diagram of activating a trench MOSFET device after forming a protective layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application. Figure 10 This is a schematic diagram showing the formation of oxide layers on the upper surface of the epitaxial layer and the inner surface of the trench during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 11 This is a schematic diagram of polysilicon deposition in a trench during the fabrication of a trench MOSFET device according to some preferred embodiments of this application; Figure 12 This is a schematic diagram illustrating the etching of polysilicon to form vias during the fabrication of trench MOSFET devices according to some preferred embodiments of this application, wherein... Figure 12(A) is a top view of a trench MOSFET device. Figure 12 (B) is a sectional view along line BB in (A). Figure 12 (C) is a sectional view along line CC in (A); Figure 13 This is a schematic diagram illustrating the process of fabricating an insulating layer within the hole and on the upper surface of the epitaxial layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application. Figure 13 (A) is a top view of a trench MOSFET device. Figure 13 (B) is a sectional view along line BB in (A). Figure 13 (C) is a sectional view along line CC in (A); Figure 14 This is a schematic diagram illustrating the etching of the insulating layer to form contact holes and grounding holes during the fabrication of a trench MOSFET device according to some preferred embodiments of this application. Figure 14 (A) is a top view of a trench MOSFET device. Figure 14 (B) is a sectional view along line BB in (A). Figure 14 (C) is a sectional view along line CC in (A); Figure 15 This is a schematic diagram illustrating the formation of conductive layers at the bottom of contact holes and grounding holes during the fabrication of trench MOSFET devices according to some preferred embodiments of this application. Figure 15 (A) is a top view of a trench MOSFET device. Figure 15 (B) is a sectional view along line BB in (A). Figure 15 (C) is a sectional view along line CC in (A); Figure 16 This is a schematic diagram illustrating the formation of a source metal layer, a passivation layer, a resin layer, and a drain metal layer during the fabrication of a trench MOSFET device according to some preferred embodiments of this application. Figure 16 (A) is a schematic diagram showing the connection between the source metal layer and the base region and the source region. Figure 16 (B) is a schematic diagram of the connection between the source metal layer and the second implanted buried layer.

[0028] Explanation of reference numerals in the attached figures: 10. Substrate; 20. Epitaxial layer; 21. Trench; 30. Base region; 40. First channel region; 41. Second channel region; 42. Source region; 50. First buried implantation layer; 51. Second buried implantation layer; 60. Mask; 61. Protective layer; 62. Oxide layer; 70. Gate; 71. Hole; 72. Insulating layer; 73. Contact hole; 74. Grounding hole; 75. Conductive layer; 80. Source metal layer; 81. Passivation layer; 82. Resin layer; 83. Drain metal layer. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments for understanding the inventive concept of the present invention, and cannot represent all embodiments, nor are they interpreted as the only embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art under the premise of understanding the inventive concept of the present invention are within the scope of protection of the present invention.

[0030] It should be noted that if any directional indication (such as up, down, left, right, front, back, etc.) is involved in the embodiments of the present invention, such directional indication is only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indication will also change accordingly. To better understand the technical solution of the present invention, the manufacturing method of the trench MOSFET device of the present invention will be described and explained in further detail below, but this should not be construed as limiting the scope of protection of the present invention.

[0031] In specific applications of the variations, the source of the example can be used as the drain, and the drain of the example can be used as the source. The source and drain represent the relative flow direction of electrons. When the source described in the specification is used as the source, the drain described in the specification must be used as the drain; when the drain described in the specification is used as the drain, the drain described in the specification must be used as the source. For ease of understanding of the technical solution of this application, the specification and the scope of protection still use "source" and "drain," but in fact, they are not limited to source and drain, but rather use a first electrode and a second electrode that represent two different potential poles. Therefore, those skilled in the art can interchange the "source" and "drain" of the semiconductor device after understanding the technical solution of this invention, and the scope of protection of this invention naturally includes such equivalent interchange.

[0032] Furthermore, the first doping type in this application is the opposite of the second doping type. When the first doping type is N-type, the second doping type is P-type; when the first doping type is P-type, the second doping type is N-type. The embodiments in this application are described with the first doping type being N-type and the second doping type being P-type.

[0033] The accompanying drawings only illustrate the commonalities among multiple embodiments; differences or distinctions are described in text or presented in comparison with the drawings. Based on industry characteristics and the nature of the technology, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features or any combination thereof described below can characterize the same embodiment, or whether multiple mutually exclusive technical features can only characterize different variations of the embodiment.

[0034] Figures 1 to 2This is a schematic diagram of the trench MOSFET device of this application; Figures 3 to 16 This is a partial cross-sectional schematic diagram of the corresponding component during the manufacturing process of the trench MOSFET device of this application (corresponding to steps S10 to S70).

[0035] The trench MOSFET device provided in this application embodiment refers to... Figure 1 (A) and Figure 1 (B) includes a substrate 10, an epitaxial layer 20, a base region 30, a well region, a source region 42, a gate 70, a first buried implantation layer 50, a second buried implantation layer 51, and a source metal layer 80. The substrate 10 can be made of SiC or other suitable materials. The epitaxial layer 20 is formed on the upper surface of the substrate 10 and is of the first doping type, i.e., an N-type epitaxial layer 20.

[0036] In this embodiment, multiple parallel P+ base regions 30 are formed by implanting P-type ions into the epitaxial layer 20.

[0037] The well region and source region 42 are disposed within the epitaxial layer 20, with their sides adjacent to the base region 30. Specifically, the well region includes a first channel region 40 and a second channel region 41 from bottom to top. The first channel region 40 is of a second doping type, and the second channel region 41 is of a first doping type. The source region 42 is disposed above the second channel region 41. Simultaneously, the doping concentration of the base region 30 is higher than that of the first channel region 40, and the doping concentration of the second channel region 41 is lower than that of the source region 42, forming an internal negative feedback resistor between the first channel region 40 and the source region 42 to achieve gate-source breakdown voltage. Specifically, the base region 30 is a P+ region, the first channel region 40 is a P- region, the second channel region 41 is an N- region, and the source region 42 is an N+ region.

[0038] Preferably, the gate 70 is disposed between the base regions 30 and the bottom end of the gate 70 extends through the well region and the source region 42.

[0039] Specifically, the epitaxial layer 20 is etched to form a trench 21 that penetrates the well region and the source region 42. The trench 21 is filled with polysilicon to form the gate 70. In addition, an oxide layer 62 is disposed between the polysilicon and the inner wall of the trench 21.

[0040] Before setting the oxide layer 62, ions are sequentially implanted into the trench 21 through a mask 60 to form a first implanted layer 50 and a second implanted layer 51. The first implanted layer 50 and the second implanted layer 51 are not connected to the base region 30. The first implanted layer 50 is of a first doping type, and the second implanted layer 51 is of a second doping type different from the first doping type. Specifically, the first implanted layer 50 is an N-type region, and the second implanted layer 51 is a P-type region.

[0041] Reference Figure 1 (B) In this embodiment, the first implanted buried layer 50 has a structure that is thin in the middle and thick at both sides, and the second implanted buried layer 51 is distributed in a ring shape. This structure can form an effective electric field shield at the bottom of the trench 21, reduce the concentration of large electric fields at the bottom of the trench 21, improve the device's voltage resistance and reliability, and further enhance the electric field dispersion effect at the bottom of the trench 21, effectively reducing the local electric field strength and improving the device's breakdown voltage and reliability. Reference Figure 2 (A) In another embodiment, the first implanted buried layer 50 is arranged in a ring shape, and the second implanted buried layer 51 is arranged in a ring shape. This structure makes the electric field distribution at the bottom of the trench 21 more uniform, reducing the risk of breakdown caused by local high electric fields.

[0042] Reference Figure 2 (B) In another embodiment, the first buried implantation layer 50 has a structure that is thin in the middle and thick at both sides, and the second buried implantation layer 51 has a structure that is thick in the middle and thin at both sides. The middle portion of the second buried implantation layer 51 penetrates the middle portion of the first buried implantation layer 50 and contacts the epitaxial layer 20. This structure further optimizes the electric field distribution at the bottom of the trench, while enhancing the contact between the second buried implantation layer 51 and the epitaxial layer 20, reducing the on-resistance, and improving the overall performance of the device.

[0043] Reference Figure 2 (C) In another embodiment, the first implanted buried layer 50 has a structure that is thin in the middle and thick at both sides, and the second implanted buried layer 51 has a uniformly thick cuboid structure, with the middle portion of the second implanted buried layer 51 penetrating through the first implanted buried layer 50 and contacting the epitaxial layer 20. This structure forms a cuboid-shaped second implanted buried layer 51 that penetrates through the middle portion of the first implanted buried layer 50, further optimizing the electric field distribution at the bottom of the trench 21, reducing charge accumulation, and effectively preventing the risk of gate oxide layer breakdown, thereby improving the overall performance and stability of the device.

[0044] Reference Figure 1 (A) and Figure 1 (B) A source metal layer 80 is formed on the upper surface of the epitaxial layer 20 to connect the base region 30 and the source region 42. The source metal layer 80 also penetrates the well region and the source region 42 to connect to the second implanted buried layer 51.

[0045] Specifically, after filling the trench 21 with polysilicon, a hole 71 is formed by opening a hole in the polysilicon. An insulating layer 72 is provided on the sidewall of the hole 71 and the upper surface of the epitaxial layer 20. Then, the insulating layer 72 located above the base region 30 and the source region 42 is etched to form a contact hole 73. The insulating layer 72 in the trench 21 is etched to form a grounding hole 74. Then, a conductive layer 75 is provided at the bottom of the contact hole 73 and the grounding hole 74. Finally, metal is filled in the contact hole 73 and the grounding hole 74 to form a source metal layer 80. The source metal layer 80 connects the base region 30 and the source region 42 and passes through the well region and the source region 42 to connect to the second implanted buried layer 51.

[0046] Optionally, the conductive layer 75 may be a silicide layer or a titanide layer, and the material of the source metal layer 80 may include, but is not limited to, pure Al / Cu and its alloys (AlSi alloy, AlCu alloy and AlSiCu alloy) or their stacked combinations.

[0047] In addition, a passivation layer 81 is disposed on the upper surface of the source metal layer 80, a resin layer 82 is disposed on the upper surface of the passivation layer 81, and a drain metal layer 83 is disposed on the lower surface of the substrate 10.

[0048] Optionally, the passivation layer 81 has a thickness of 0.1µm-20µm, and the material of the passivation layer 81 includes, but is not limited to, SiO2, SiN and combinations thereof; the resin layer 82 has a thickness of 1µm-50µm, and the material of the passivation layer 81 may include at least one of polyimide, polyamide and polybenzoxazole, with a preferred thickness range of 10-15µm in this embodiment; the drain metal layer 83 has a material including, but is not limited to, Ti / Ni / Ag / Pd / Au, and alloys or combinations thereof.

[0049] This application creates P-type and N-type regions at the bottom of the trench 21 with a unique structure, effectively reducing the on-resistance of the device while improving its breakdown voltage and reliability. The base region 30 forms a P-type region at the bottom of the trench 21, protecting the bottom of the trench 21 and preventing breakdown caused by high electric fields. The combination of the base region 30 with the subsequent P-type and N-type regions at the bottom of the trench 21 further optimizes the electric field distribution, improving the device's breakdown voltage and reliability.

[0050] The method for manufacturing a trench MOSFET device provided in this application includes the following steps: Reference Figure 3 S10, a substrate 10 is provided, wherein an epitaxial layer 20 of a first doping type is formed on the upper surface of the substrate 10.

[0051] Optionally, an N-type epitaxial layer 20 is used, and the substrate 10 material can be SiC or other suitable materials. The growth of the epitaxial layer 20 can be achieved by chemical vapor deposition (CVD) or other suitable methods to ensure the uniformity and doping concentration of the epitaxial layer 20.

[0052] Reference Figure 4 S20, ions are implanted into the epitaxial layer 20 for the first time to form a plurality of base regions 30 of the second doping type in the epitaxial layer 20.

[0053] Optionally, a P+ base region 30 is formed by implanting P-type ions. The formation of the base region 30 can be achieved by various methods, such as ion implantation or diffusion. Specifically, a mask 60 is formed on the epitaxial layer 20, and then the required openings are formed on the mask 60 by photolithography and etching processes. Finally, multiple parallel P+ base regions 30 are formed by ion implantation.

[0054] Reference Figure 5 S30, a second ion implantation is performed on the epitaxial layer 20 to form a well region and a source region 42 within the epitaxial layer 20, the sides of the well region and the source region 42 being adjacent to the base region 30. S30 further includes: S31. Ions are implanted into the epitaxial layer 20 to form a first channel region 40 of the second doping type.

[0055] S32. Ions are implanted into the epitaxial layer 20 to form a second channel region 41 of the first doping type, and the first channel region 40 and the second channel region 41 are combined to form a well region.

[0056] S33. Ions are implanted into the epitaxial layer 20 to form a source region 42 of the first doping type.

[0057] The base region 30 has a higher doping concentration than the first channel region 40, and the second channel region 41 has a lower doping concentration than the source region 42, so as to form an internal negative feedback resistor between the first channel region 40 and the source region 42, thereby realizing gate-source breakdown voltage.

[0058] Preferably, a self-aligned region is formed between adjacent base regions 30, and the first channel region 40 and the second channel region 41 are formed in the self-aligned region using a self-aligned process. The first channel region 40 and the second channel region 41 are lightly doped regions, and the source region 42 is a heavily doped region.

[0059] Optionally, base region 30 is a P+ region, first channel region 40 is a P- region, second channel region 41 is an N- region, and source region 42 is an N+ region.

[0060] Specifically, firstly, a P-region window is defined in the self-aligned region. Under certain target temperatures, different energies and doses, B11 ions are injected multiple times through the P-region window under high-temperature conditions to advance the P-region. Then, the injected ions form N-regions, and high-concentration ion implantation is performed in the N-regions to form N+ regions.

[0061] Reference Figure 6S40, Etch the epitaxial layer 20 to form a trench 21 that penetrates the well region and the source region 42, the trench 21 being not connected to the base region 30.

[0062] Optionally, the groove 21 can be flat-bottomed or round-bottomed, and the sidewall angle of the groove 21 is generally 80-91°, preferably 86°. The connection between the bottom and the sidewall of the groove 21 can be arc-shaped to reduce stress concentration.

[0063] Reference Figure 7 S50, ions are implanted into the epitaxial layer 20 for the third time to form a first implanted buried layer 50 and a second implanted buried layer 51 in sequence at the bottom of the trench 21. The first implanted buried layer 50 is of a first doping type, and the second implanted buried layer 51 is of a second doping type different from the first doping type. The first implanted buried layer 50 and the second implanted buried layer 51 are not connected to the base region 30.

[0064] In this embodiment, the first injection layer 50 is N-type and the second injection layer 51 is P-type.

[0065] In this embodiment, step S50 further includes: S51. A mask 60 is formed on the upper surface of the epitaxial layer 20, the mask 60 also covering the sidewall of the trench 21.

[0066] Specifically, the mask 60 extends to the bottom of the arc of the trench 21.

[0067] S52. Ions are implanted to form a first implanted buried layer 50 at the bottom of the trench 21. By controlling the implantation angle, the first implanted buried layer 50 has a structure that is thin in the middle and thick on both sides.

[0068] Optionally, an injection angle of 10-20° can be used to form a thicker N-type region on both sides of the bottom of the trench 21, while a thinner N-type region is formed in the center.

[0069] S53. Ions are implanted to form a second implantation layer 51 within the first implantation layer 50. The second implantation layer 51 is distributed in a ring shape by vertical implantation.

[0070] Optionally, a vertical injection angle can be used to create a ring-shaped distribution of P-type ions at the bottom of trench 21.

[0071] The design of the N-type and P-type regions includes, but is not limited to, that described in this embodiment. Modifications can be made based on this embodiment in terms of size, shape, position, and relative positional relationship between the two regions, but all such modifications fall within the scope of this patent. See embodiments 2, 3, and 4.

[0072] Reference Figure 8 (A) In Example 2, step S50 includes: S51. A mask 60 is formed on the upper surface of the epitaxial layer 20, the mask 60 also covering the sidewall of the trench 21.

[0073] Optionally, silicon dioxide (SiO2) can be used as the mask material 60, and the mask 60 can be formed by chemical vapor deposition (CVD) or other suitable methods.

[0074] S52. Ions are implanted to form a first implanted layer 50 at the bottom of the trench 21. The first implanted layer 50 is formed in a ring shape by vertical implantation.

[0075] A vertical injection angle can be used to create an annular N-type region at the bottom of trench 21 for N-type ions.

[0076] S53. Ions are implanted to form a second implantation layer 51 within the first implantation layer 50. The second implantation layer 51 is distributed in a ring shape by vertical implantation.

[0077] A vertical injection angle can be used to create a ring-shaped distribution of P-type ions at the bottom of trench 21.

[0078] Reference Figure 8 (B) In Example 3, step S50 includes: S51. A mask 60 is formed on the upper surface of the epitaxial layer 20, the mask 60 also covering the sidewall of the trench 21.

[0079] S52. Ions are implanted to form a first implanted buried layer 50 at the bottom of the trench 21. By controlling the implantation angle, the first implanted buried layer 50 has a structure that is thin in the middle and thick on both sides.

[0080] For example, an injection angle of 10-20° can be used to form an N-type region at the bottom of trench 21 that is thin in the middle and thick on both sides.

[0081] S53. Ions are implanted to form a second implanted buried layer 51 within the first implanted buried layer 50. The second implanted buried layer 51 has a structure that is thick in the middle and thin at both sides. The middle part of the second implanted buried layer 51 penetrates the middle part of the first implanted buried layer 50 and contacts the epitaxial layer 20.

[0082] For example, the vertical implantation angle can be used to change the implantation depth, so that P-type ions form a P-type region at the bottom of the trench 21 that extends from the middle of the first implanted buried layer 50 and contacts the epitaxial layer 20.

[0083] Reference Figure 8 (C) In Example 4, step S50 includes: S51. A first mask is formed on the upper surface of the epitaxial layer 20, and the first mask also covers the sidewall of the trench 21.

[0084] S52. Ions are implanted to form a first implanted buried layer 50 at the bottom of the trench 21. By controlling the implantation angle, the first implanted buried layer 50 has a structure that is thin in the middle and thick on both sides.

[0085] Optionally, an injection angle of 10-20° can be used to form an N-type region at the bottom of trench 21 that is thin in the middle and thick on both sides.

[0086] S53. A second mask is formed on the upper surface of the epitaxial layer 20. The first mask also covers the sidewalls of the trench 21. The opening of the second mask is smaller than the opening of the first mask. By adding mask 60, the size of the injection region is changed.

[0087] S54. Ions are implanted through the second mask to form a second implanted buried layer 51 within the first implanted buried layer 50. Through vertical implantation, the second implanted buried layer 51 has a uniformly thick cuboid structure, and the middle part of the second implanted buried layer 51 penetrates the first implanted buried layer 50 and contacts the epitaxial layer 20.

[0088] Optionally, a vertical injection angle can be used to form a cuboid P-type region at the bottom of the trench 21 with P-type ions, which then penetrate the first implantation layer 50 from the center.

[0089] By using different injection methods in the above embodiments, the electric field dispersion effect at the bottom of trench 21 is enhanced, the local electric field intensity is reduced, and the device's compressive strength and reliability are improved.

[0090] S60. Polysilicon is deposited into the trench 21 to form a gate 70, the polysilicon having a via 71. Before step S60, the method further includes: Reference Figure 9 S57. Using photolithography or sputtering, a protective layer 61 is formed on the upper surface of the epitaxial layer 20 and the inner wall of the trench 21. Then, the internal structure of the trench MOSFET device is activated at high temperature. The protective layer 61 includes, but is not limited to, a photoresist protective layer 61, a carbon protective layer 61, and an aluminum nitride protective layer 61. In this embodiment, the activation temperature range is 1400-2100℃, with a preferred range of 1700-1800℃. After activation, the protective layer 61 is removed.

[0091] S58. The surface of the epitaxial layer 20 is oxidized at high temperature, and then the sacrificial oxide layer 62 on the surface is removed.

[0092] Reference Figure 10 S59. An oxide layer is formed on the surface by means of thermal oxidation or chemical vapor deposition.

[0093] Step S60 includes: Reference Figure 11 S61. A layer of polysilicon is deposited in the trench 21 and on the upper surface of the epitaxial layer 20. Then, the polysilicon in the trench 21 is retained by an etching process. The polysilicon in the trench 21 forms the required gate 70.

[0094] Reference Figure 12 (A) Figure 12 (B) and Figure 12 (C), S62, forming a mask 60 to create a hole 71 in the polysilicon.

[0095] In this embodiment, the perforation 71 cuts through the polysilicon laterally but not longitudinally, so that the perforation 71 is in the shape of a first window. The perforation 71 can have different forms, forming various layouts of the perforation 71. The perforation 71 method includes, but is not limited to, that described in this embodiment. Modifications can be made based on this embodiment in terms of size, shape (square, circular, hexagonal, etc.), position, number, and relative positional relationship of adjacent holes, but all of these modifications fall within the scope of this patent.

[0096] S70, a source metal layer 80 is formed on the upper surface of the epitaxial layer 20 to connect the base region 30 and the source region 42; the source metal layer 80 is also formed in the hole 71 of the polysilicon, so that the source metal layer 80 passes through the well region and the source region 42 and is connected to the second implanted buried layer 51.

[0097] Step S70 includes: Reference Figure 13 (A) Figure 13 (B) and Figure 13 (C), S71, forming an insulating layer 72 inside the hole 71 and on the upper surface of the epitaxial layer 20.

[0098] Optionally, the insulating layer 72 may be made of materials including but not limited to silicon dioxide, silicon nitride, or combinations thereof, and may be formed by chemical vapor deposition (CVD) or other suitable methods.

[0099] Reference Figure 14 (A) Figure 14 (B) and Figure 14 (C), S72, Forming a mask 60 on the upper surface of the insulating layer 72, etching the insulating layer 72 located above the base region 30 and the source region 42 to form a contact hole 73, and etching the insulating layer 72 in the trench 21 to form a grounding hole 74.

[0100] Reference Figure 15 (A) Figure 15 (B) and Figure 15 (C), S730, depositing metal at the bottom of the contact hole 73 and the grounding hole 74 to form a conductive layer 75.

[0101] Optionally, silicon or titanium can be deposited, followed by high-temperature annealing to form a silicide or titanium layer, removing excess metal, and the silicide or titanium layer forming a conductive layer 75.

[0102] Reference Figure 16 (A) and Figure 16 (B), S73, fill the contact hole 73 and the ground hole 74 with metal to form a source metal layer 80, the source metal layer 80 connecting the base region 30 and the source region 42 and connecting the second buried injection layer 51 through the well region and the source region 42.

[0103] Optionally, the material of the source metal layer 80 includes, but is not limited to, pure Al / Cu and its alloys (AlSi alloy, AlCu alloy and AlSiCu alloy) or their stacked combinations.

[0104] Following step S73, the following is also included: S74. A passivation layer 81 is provided on the upper surface of the source metal layer 80, and the thickness of the passivation layer 81 is 0.1um-20um.

[0105] Optionally, the material of the passivation layer 81 may include, but is not limited to, SiO2, SiN, and combinations thereof.

[0106] S75. A resin layer 82 is provided on the upper surface of the passivation layer 81, and the thickness of the resin layer 82 is 1um-50um.

[0107] Optionally, the material of the passivation layer 81 may include at least one of polyimide, polyamide and polybenzoxazole, and the preferred thickness range in this embodiment is 10-15 μm.

[0108] S76. Thinning of substrate 10, the thickness of substrate 10 after thinning is 80um-250um.

[0109] In this embodiment, the preferred thickness range is 150-200 μm.

[0110] S77. A drain metal layer 83 is formed on the lower surface of the substrate 10.

[0111] The material of the drain metal layer 83 includes, but is not limited to, Ti / Ni / Ag / Pd / Au, and their alloys or combinations.

[0112] In the prior art, repeated switching of a device will lead to charge accumulation, increasing the device's parasitic capacitance and reducing the switching speed. At the same time, repeated switching of the device will increase the device's on-resistance, affecting the device's power consumption. Therefore, this application can effectively solve the problems caused by the charge storage / accumulation effect by grounding through the second implantation buried layer 51. In addition, if the implantation is only performed at the bottom of the trench 21, the device's conduction and turn-off performance will be affected by the depth and morphology of the trench 21. However, by implanting the base region 30 on both sides of the first implantation buried layer 50 and the second implantation buried layer 51, the device is less affected by the trench 21, and the device's design and process windows can be larger.

[0113] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A method for manufacturing a trench MOSFET device, characterized in that, Includes the following steps: S10. Provide a substrate (10) having an epitaxial layer (20) of a first doping type formed on the upper surface of the substrate (10). S20. Ions are implanted into the epitaxial layer (20) for the first time to form a plurality of base regions (30) of the second doping type in the epitaxial layer (20). S30. Ions are implanted into the epitaxial layer (20) for the second time to form a well region and a source region (42) in the epitaxial layer (20), the sides of the well region and the source region (42) being connected to the base region (30). S40. Etch the epitaxial layer (20) to form a trench (21) that penetrates the well region and the source region (42), the trench (21) not being connected to the base region (30). S50. Ions are implanted into the epitaxial layer (20) for the third time to form a first implanted buried layer (50) and a second implanted buried layer (51) in sequence at the bottom of the trench (21). The first implanted buried layer (50) is of the first doping type, and the second implanted buried layer (51) is of the second doping type, which is different from the first doping type. The first implanted buried layer (50) and the second implanted buried layer (51) are not connected to the base region (30). S60. Polysilicon is deposited in the trench (21) to form a gate (70), the polysilicon having a hole (20). S70, a source metal layer (80) is formed on the upper surface of the epitaxial layer (20) to connect the base region (30) and the source region (42); the source metal layer (80) is also formed in the hole (20) of the polysilicon, so that the source metal layer (80) passes through the well region and the source region (42) and is connected to the second implanted buried layer (51).

2. The method for manufacturing a trench MOSFET device according to claim 1, characterized in that, Step S50 includes: S51. A mask (60) is formed on the upper surface of the epitaxial layer (20), the mask (60) also covering the sidewall of the trench (21); S52. Ions are implanted to form a first implanted buried layer (50) at the bottom of the trench (21). By controlling the implantation angle, the first implanted buried layer (50) has a structure that is thin in the middle and thick on both sides. S53. Ion implantation forms a second implantation layer (51) within the first implantation layer (50). Through vertical implantation, the second implantation layer (51) is distributed in a ring shape.

3. The method for manufacturing a trench MOSFET device according to claim 1, characterized in that, Step S50 includes: S51. A mask (60) is formed on the upper surface of the epitaxial layer (20), the mask (60) also covering the sidewall of the trench (21); S52. Ions are implanted to form a first implanted buried layer (50) in the bottom of the trench (21). The first implanted buried layer (50) is distributed in a ring shape by vertical implantation. S53. Ion implantation forms a second implantation layer (51) within the first implantation layer (50). Through vertical implantation, the second implantation layer (51) is distributed in a ring shape.

4. The method for manufacturing a trench MOSFET device according to claim 1, characterized in that, Step S50 includes: S51. A mask (60) is formed on the upper surface of the epitaxial layer (20), the mask (60) also covering the sidewall of the trench (21); S52. Ions are implanted to form a first implanted buried layer (50) at the bottom of the trench (21). By controlling the implantation angle, the first implanted buried layer (50) has a structure that is thin in the middle and thick on both sides. S53. Ion implantation forms a second implanted buried layer (51) within the first implanted buried layer (50). Through vertical implantation, the second implanted buried layer (51) has a structure that is thick in the middle and thin on both sides. The middle part of the second implanted buried layer (51) penetrates the middle part of the first implanted buried layer (50) and contacts the epitaxial layer (20).

5. The method for manufacturing a trench MOSFET device according to claim 1, characterized in that, Step S50 includes: S51. A first mask is formed on the upper surface of the epitaxial layer (20), and the first mask also covers the sidewall of the trench (21); S52. Ions are implanted to form a first implanted buried layer (50) at the bottom of the trench (21). By controlling the implantation angle, the first implanted buried layer (50) has a structure that is thin in the middle and thick on both sides. S53. A second mask is formed on the upper surface of the epitaxial layer (20), the first mask also covers the sidewall of the trench (21), and the opening of the second mask is smaller than the opening of the first mask; S54. Ions are implanted through the second mask to form a second implanted buried layer (51) in the first implanted buried layer (50). By vertical implantation, the second implanted buried layer (51) has a uniformly thick cuboid structure, and the middle part of the second implanted buried layer (51) penetrates the first implanted buried layer (50) and contacts the epitaxial layer (20).

6. The method for manufacturing a trench MOSFET device according to claim 1, characterized in that, Step S30 includes: S31. Ions are implanted into the epitaxial layer (20) to form a first channel region (40) of the second doping type. S32. Ions are implanted in the epitaxial layer (20) to form a second channel region (41) of the first doping type, and the first channel region (40) and the second channel region (41) are combined to form a well region; S33. Ions are implanted into the epitaxial layer (20) to form a source region (42) of the first doping type. The base region (30) has a higher doping concentration than the first channel region (40), and the second channel region (41) has a lower doping concentration than the source region (42), so as to form an internal negative feedback resistor between the first channel region (40) and the source region (42) to realize gate-source breakdown voltage.

7. The method for manufacturing a trench MOSFET device according to claim 1, characterized in that, Step S70 includes: S71, forming an insulating layer (72) inside the hole (20) and on the upper surface of the epitaxial layer (20); S72. Form a mask (60) on the upper surface of the insulating layer (72), etch the insulating layer (72) above the base region (30) and the source region (42) to form a contact hole (73), and etch the insulating layer (72) in the trench (21) to form a ground hole (74). S73. Fill the contact hole (73) and the ground hole (74) with metal to form a source metal layer (80), the source metal layer (80) connecting the base region (30) and the source region (42) and connecting the second buried injection layer (51) through the well region and the source region (42).

8. The method for manufacturing a trench MOSFET device according to claim 7, characterized in that, Before step S73, the following are also included: S730, depositing metal at the bottom of the contact hole (73) and the grounding hole (74) to form a conductive layer (75).

9. A trench MOSFET device, characterized in that, include: Substrate (10); An epitaxial layer (20) of the first doped type is formed on the upper surface of the substrate (10); Multiple base regions (30) of the second doping type are disposed within the epitaxial layer (20); A well region and a source region (42) are disposed within the epitaxial layer (20), and the sides of the well region and the source region (42) are connected to the base region (30). A gate (70) is disposed between base regions (30) and the bottom end of the gate (70) extends through the well region and the source region (42). A first buried layer (50) and a second buried layer (51) are formed at the bottom of the gate (70). The first buried layer (50) and the second buried layer (51) are not connected to the base region (30). The first buried layer (50) is of a first doping type, and the second buried layer (51) is of a second doping type different from the first doping type. A source metal layer (80) is formed on the upper surface of the epitaxial layer (20) to connect the base region (30) and the source region (42). The source metal layer (80) also extends through the well region and the source region (42) to connect to the second implanted buried layer (51).

10. A trench MOSFET device according to claim 9, characterized in that, The first injection layer (50) has a structure that is thin in the middle and thick on both sides, and the second injection layer (51) is distributed in a ring shape; Alternatively, the first injection layer (50) is arranged in a ring shape, and the second injection layer (51) is arranged in a ring shape; Alternatively, the first implanted layer (50) has a structure that is thin in the middle and thick on both sides, and the second implanted layer (51) has a structure that is thick in the middle and thin on both sides. The middle part of the second implanted layer (51) penetrates the middle part of the first implanted layer (50) and contacts the epitaxial layer (20). Alternatively, the first implanted layer (50) has a structure that is thin in the middle and thick on both sides, and the second implanted layer (51) has a cuboid structure with uniform thickness, and the middle part of the second implanted layer (51) penetrates the first implanted layer (50) and contacts the epitaxial layer (20).

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