Shield gate trench MOSFET device and preparation method thereof
By optimizing the electric field distribution of the shielded gate trench MOSFET device through a three-step trench etching and ion implantation process, the problems of high on-resistance and breakdown caused by electric field concentration in the drift region were solved, thereby reducing on-resistance and increasing breakdown voltage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICONDUCTOR MANUFACTURING (WUXI) LTD
- Filing Date
- 2026-01-07
- Publication Date
- 2026-05-12
AI Technical Summary
In shielded gate trench MOSFET devices, the electric field distribution in the drift region is too concentrated, resulting in high on-resistance and even potential device breakdown. Existing improvement methods have high process requirements and are difficult to manufacture.
A three-step trench etching process followed by one ion implantation step is employed to form an ion diffusion region in the epitaxial layer, thereby optimizing the electric field distribution in the depletion layer, reducing the on-resistance of the drift region, and increasing the breakdown voltage.
The electric field distribution within the device depletion layer was optimized, reducing the on-resistance of the drift region and decreasing the thickness of the depletion layer, thereby improving the device's breakdown voltage.
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Figure CN122028449A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a shielded gate trench MOSFET device and its fabrication method. Background Technology
[0002] In the reverse cutoff state, the electric field distribution in the MESA region (mesa region) of a shielded gate trench MOSFET (SGT-MOSFET) device exhibits a catenary-like pattern. The fully depleted drift region typically displays two electric field peaks along the silicon substrate / trench gate oxide interface. The first peak occurs at the PN junction formed by the P-type body region and the N-type drift region, while the second peak occurs at the bottom of the trench gate oxide (near the bottom of the trench). A low electric field is generated in most of the middle of the depletion region. The MESA region refers to the raised area between trenches in the device's cell structure. It is a key carrier of the device's core functional layers (such as the gate, source, and body regions), directly determining the device's on-resistance, breakdown voltage, and switching characteristics.
[0003] Because the electric field strength at both ends of the catenary is high, the entire drift region must maintain a low doping concentration to prevent breakdown at both ends. Therefore, the on-resistance of the drift region will be very high.
[0004] To obtain a better electric field distribution in the depletion region, researchers in this field have proposed methods such as gradient doping of drift regions, slope-side oxygen, and multi-step side oxygen to improve the electric field distribution in the depletion region. However, these methods have high requirements for the process and are correspondingly difficult to manufacture. Summary of the Invention
[0005] This application provides a shielded gate trench MOSFET device and its fabrication method, which can solve the problem that the electric field distribution at certain locations in the drift region of the current shielded gate trench MOSFET device is too concentrated, resulting in a large on-resistance in the drift region and even device breakdown.
[0006] On one hand, embodiments of this application provide a method for fabricating a shielded gate trench MOSFET device, including: A substrate is provided on which an epitaxial layer and a hard mask layer are sequentially formed, and an opening is formed in the hard mask layer; Using the hard mask layer as a mask, the epitaxial layer of a first thickness is etched to form a first trench in the epitaxial layer; A first oxide layer is formed, which covers the sidewalls and bottom wall of the first trench; Using the hard mask layer as a mask, the first oxide layer and the second epitaxial layer of the second thickness at the bottom of the first trench are etched downwards to form the second trench; Ion implantation is performed on the bottom wall of the second trench and the sidewall of the second trench not covered by the first oxide layer to form an ion implantation region; A thermal annealing process is performed on the semiconductor structure after ion implantation. During this process, the ion implantation region diffuses to a certain depth into the epitaxial layer outside the second trench to form an ion diffusion region. Using the hard mask layer as a mask, the epitaxial layer of a third thickness is etched downwards to the bottom of the second trench to form the third trench; A second oxide layer is formed, which covers the first oxide layer on the sidewall of the third trench, as well as the bottom wall and the remaining sidewall of the third trench.
[0007] Optionally, in the method for fabricating the shielded gate trench MOSFET device, the third thickness of the etched epitaxial layer is greater than the diffusion depth of the ion diffusion region at the bottom of the second trench.
[0008] Optionally, in the fabrication method of the shielded gate trench MOSFET device, the ratio of the lateral dimension of the ion diffusion region on the outer sidewall of the second trench to the lateral dimension of the second trench is (1:5) to (5:1).
[0009] Optionally, in the method for fabricating the shielded gate trench MOSFET device, the ratio of the first thickness, the second thickness, and the third thickness of the etched epitaxial layer is 1:3:1.
[0010] Optionally, in the method for fabricating the shielded gate trench MOSFET device, the thickness of the first oxide layer is one-quarter of the thickness of the second oxide layer.
[0011] Optionally, in the method for fabricating the shielded gate trench MOSFET device, the step of ion implantation of the bottom wall of the second trench and the sidewalls of the second trench not covered by the first oxide layer to form an ion implantation region includes: N-type ion implantation is performed on the bottom wall of the second trench and the sidewall of the second trench not covered by the first oxide layer to form an N-type ion implantation region.
[0012] Optionally, in the method for fabricating the shielded gate trench MOSFET device, the hard mask layer is made of silicon nitride.
[0013] Optionally, in the fabrication method of the shielded gate trench MOSFET device, the doping type of the conductive ions in the substrate is N-type.
[0014] Optionally, in the fabrication method of the shielded gate trench MOSFET device, the doping type of the conductive ions in the epitaxial layer is N-type.
[0015] On the other hand, embodiments of this application also provide a shielded gate trench MOSFET device, comprising: A substrate on which an epitaxial layer and a hard mask layer are sequentially formed, wherein an opening is formed in the hard mask layer; The third trench is located in the epitaxial layer; A first oxide layer covers a portion of the sidewall of the third trench near the top of the third trench; An ion diffusion region is located in the epitaxial layer outside the sidewall of the third trench, and the vertical dimension of the ion diffusion region is smaller than the depth of the third trench. A second oxide layer covers the first oxide layer on the sidewall of the third trench, as well as the bottom wall and remaining sidewalls of the third trench.
[0016] The technical solution of this application has at least the following advantages: The method for fabricating a shielded gate trench MOSFET device provided in this application involves first etching an epitaxial layer of a first thickness to form a first trench, then forming a first oxide layer on the sidewall of the first trench, followed by etching an epitaxial layer of a second thickness to form a second trench, then ion implantation on the bottom wall and part of the sidewall of the second trench to form an ion implantation region, followed by a thermal annealing process to transform the ion implantation region into an ion diffusion region, and finally etching an epitaxial layer of a third thickness to form a third trench, with a second oxide layer formed on the sidewall and bottom wall of the third trench. This application, through a three-step trench etching process plus an ion implantation process, dops impurities from the channel sidewall to the middle section of the drift region (the middle section of the third trench sidewall), which optimizes the electric field distribution within the depletion layer of the device and increases the electric field strength in the middle of the MESA region. This not only reduces the on-resistance of the drift region (epitaxy layer) but also reduces the thickness of the depletion layer, decreases the electric field strength at the bottom of the third trench, and improves the breakdown voltage of the device. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0018] Figure 1 This is a flowchart of a method for fabricating a shielded gate trench MOSFET device according to an embodiment of the present invention; Figures 2-9This is a schematic diagram of the semiconductor structure in each process step of fabricating a shielded gate trench MOSFET device according to an embodiment of the present invention; 10-Substrate, 20-Epipolar layer, 21-First trench, 22-Second trench, 23-Third trench, 30-Hard mask layer, 31-Opening, 41-First oxide layer, 42-Second oxide layer, 51-Ion implantation region, 52-Ion diffusion region. Detailed Implementation
[0019] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0020] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0021] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0022] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0023] This application provides a method for fabricating a shielded gate trench MOSFET device, referring to... Figure 1 , Figure 1 This is a flowchart illustrating a method for fabricating a shielded gate trench MOSFET device according to an embodiment of the present invention. The method for fabricating the shielded gate trench MOSFET device includes: First, perform step S1: Refer to Figure 2 , Figure 2This is a schematic diagram of the semiconductor structure after the opening is formed according to an embodiment of the present invention. A substrate 10 is provided, on which an epitaxial layer 20 and a hard mask layer 30 are sequentially formed. An opening 31 is formed in the hard mask layer 30, and the opening 31 is used to define the position of the first trench / second trench / third trench in the subsequent epitaxial layer.
[0024] In this embodiment, the hard mask layer 30 is made of silicon nitride.
[0025] Preferably, the conductive ions in the substrate are doped with N-type (N+); the conductive ions in the epitaxial layer are doped with N-type (N-).
[0026] Then, proceed to step S2: (Refer to...) Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after the formation of the first trench in an embodiment of the present invention. Using the hard mask layer 30 as a mask, the epitaxial layer 20 of the first thickness is etched by a dry etching process to form the first trench 21 in the epitaxial layer 20.
[0027] Next, proceed to step S3: (Refer to...) Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the formation of the first oxide layer according to an embodiment of the present invention. The first oxide layer 41 is formed, and the first oxide layer 41 covers the sidewalls and bottom wall of the first trench 21.
[0028] In this embodiment, a dry oxygen oxidation process is used with a furnace tube to grow a dense first oxide layer 41 on the surface of the first trench 21, wherein the first oxide layer 41 serves as a barrier layer for subsequent N-type doping implantation.
[0029] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the formation of the second trench in an embodiment of the present invention. Using the hard mask layer 30 as a mask, the first oxide layer 41 at the bottom of the first trench 21 and the epitaxial layer 20 of the second thickness are etched downwards using a dry etching process to form the second trench 22.
[0030] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after the formation of the ion implantation region according to an embodiment of the present invention. Ion implantation is performed on the bottom wall of the second trench 22 and the sidewalls of the second trench 22 not covered by the first oxide layer 41 to form the ion implantation region 51. The first oxide layer 41 is a barrier layer that prevents ion implantation on a portion of the sidewalls of the second trench 22 near the top.
[0031] In this embodiment, N-type ion implantation is performed on the bottom wall of the second trench 22 and the sidewall of the second trench 22 that is not covered by the first oxide layer 41 to form an N-type ion implantation region 51.
[0032] Preferably, during ion implantation of the bottom wall of the second trench 22 and the sidewalls of the second trench 22 not covered by the first oxide layer 41, the ion implantation energy is 35 keV and the ion implantation dose is 2E14 / cm². 2 The ion implantation angle (the angle between the ion implantation beam and the horizontal plane) is 90°.
[0033] Further, proceed to step S6: Refer to Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the formation of the ion diffusion region according to an embodiment of the present invention. After the ion implantation process, the semiconductor structure is subjected to a thermal annealing process. At this time, the ion implantation region 51 diffuses into the epitaxial layer 20 outside the second trench 22 to a certain depth to form the ion diffusion region 52.
[0034] In this embodiment, the ion diffusion region 52 can be relatively arc-shaped. It is worth noting that this application does not impose any limitation on the shape of the ion diffusion region 52. Furthermore, the diffusion range of the ion diffusion region 52 is concentrated near the middle section of the sidewall of the third trench, the lower edge of the ion diffusion region 52 is a certain distance from the bottom wall of the third trench, and the upper edge of the ion diffusion region 52 is also a certain distance from the top of the third trench.
[0035] Preferably, during the hot annealing process, the process temperature is 1150°C and the process duration is 110 minutes. This hot annealing process can transform the ion implantation region 51 into the ion diffusion region 52.
[0036] In this embodiment, the ratio of the lateral dimension of the ion diffusion region 52 on the outer sidewall of the second trench 22 to the lateral dimension of the second trench 22 is (1:5) to (5:1).
[0037] Next, proceed to step S7: (Refer to...) Figure 8 , Figure 8 This is a schematic diagram of the semiconductor structure after the formation of the third trench in an embodiment of the present invention. Using the hard mask layer 30 as a mask, the epitaxial layer 20 of the third thickness at the bottom of the second trench 22 is etched downward to form the third trench 23.
[0038] In this embodiment, the third thickness of the etched epitaxial layer 20 is greater than the diffusion depth of the ion diffusion region 52 at the bottom of the second trench 23. This application utilizes the aforementioned three etching processes to prevent an increase in the doping concentration at the bottom of the third trench 23.
[0039] Preferably, the ratio of the first thickness, the second thickness, and the third thickness of the etched epitaxial layer 20 is 1:3:1.
[0040] Finally, proceed to step S8: (Refer to...) Figure 9 , Figure 9 This is a schematic diagram of the semiconductor structure after the formation of the second oxide layer according to an embodiment of the present invention. The second oxide layer 42 is formed, which covers the first oxide layer 41 on the sidewall of the third trench 23, as well as the bottom wall and the remaining sidewall of the third trench 23.
[0041] Preferably, the thickness of the first oxide layer 41 is one-quarter of the thickness of the second oxide layer 42.
[0042] In this embodiment, a wet oxygen oxidation process is used to grow a dense second oxide layer 42 on the surface of the third trench 23.
[0043] In this embodiment, after forming the second oxide layer 42, the method for fabricating the shielded gate trench MOSFET device provided in this application may further include conventional steps for fabricating the shielded gate trench MOSFET device, such as depositing gate polysilicon in the third trench 23, forming a third oxide layer covering the shielded gate polysilicon, and forming a gate covering the third oxide layer.
[0044] In this application, by using a three-step trench etching process followed by an ion implantation process, impurities are doped from the sidewall of the trench to the middle section of the drift region (the middle section of the third trench sidewall). This optimizes the electric field distribution within the depletion layer of the device and increases the electric field strength in the middle of the MESA region. Consequently, it not only reduces the on-resistance of the drift region (epitaxy layer) but also reduces the thickness of the depletion layer, decreases the electric field strength at the bottom of the third trench, and improves the breakdown voltage of the device.
[0045] Based on the same inventive concept, embodiments of this application also provide a shielded gate trench MOSFET device, such as... Figure 9 As shown, the shielded gate trench MOSFET device includes: Substrate 10, on which an epitaxial layer 20 and a hard mask layer 30 are sequentially formed, and an opening 31 is formed in the hard mask layer 30; The third trench 23 is located in the epitaxial layer 20; A first oxide layer 41 covers a portion of the sidewall of the third trench 23 near the top of the third trench 23; Ion diffusion region 52, which is located in the epitaxial layer 20 outside the sidewall of the third trench 23, and the vertical dimension of the ion diffusion region 52 is smaller than the depth of the third trench 23. The second oxide layer 42 covers the first oxide layer 41 on the sidewall of the third trench 23, as well as the bottom wall and the remaining sidewall of the third trench 23.
[0046] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a shielded gate trench MOSFET device, characterized in that, include: A substrate is provided on which an epitaxial layer and a hard mask layer are sequentially formed, and an opening is formed in the hard mask layer; Using the hard mask layer as a mask, the epitaxial layer of a first thickness is etched to form a first trench in the epitaxial layer; A first oxide layer is formed, which covers the sidewalls and bottom wall of the first trench; Using the hard mask layer as a mask, the first oxide layer and the second epitaxial layer of the second thickness at the bottom of the first trench are etched downwards to form the second trench; Ion implantation is performed on the bottom wall of the second trench and the sidewall of the second trench not covered by the first oxide layer to form an ion implantation region; A thermal annealing process is performed on the semiconductor structure after ion implantation. During this process, the ion implantation region diffuses to a certain depth into the epitaxial layer outside the second trench to form an ion diffusion region. Using the hard mask layer as a mask, the epitaxial layer of a third thickness is etched downwards to the bottom of the second trench to form the third trench; A second oxide layer is formed, which covers the first oxide layer on the sidewall of the third trench, as well as the bottom wall and the remaining sidewall of the third trench.
2. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that, The third thickness of the etched epitaxial layer is greater than the diffusion depth of the ion diffusion region at the bottom of the second trench.
3. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that, The ratio of the lateral dimension of the ion diffusion region on the outer sidewall of the second trench to the lateral dimension of the second trench is (1:5) to (5:1).
4. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that, The ratio of the first thickness, the second thickness, and the third thickness of the etched epitaxial layer is 1:3:
1.
5. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that, The thickness of the first oxide layer is one-quarter of the thickness of the second oxide layer.
6. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that, The step of ion implanting the bottom wall of the second trench and the sidewalls of the second trench not covered by the first oxide layer to form an ion implantation region includes: N-type ion implantation is performed on the bottom wall of the second trench and the sidewall of the second trench not covered by the first oxide layer to form an N-type ion implantation region.
7. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that, The hard mask layer is made of silicon nitride.
8. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that, The substrate is doped with N-type conductive ions.
9. The method for fabricating a shielded gate trench MOSFET device according to claim 1, characterized in that, The conductive ions in the epitaxial layer are N-type doped.
10. A shielded gate trench MOSFET device prepared by the method described in any one of claims 1-9, characterized in that, include: A substrate on which an epitaxial layer and a hard mask layer are sequentially formed, wherein an opening is formed in the hard mask layer; The third trench is located in the epitaxial layer; A first oxide layer covers a portion of the sidewall of the third trench near the top of the third trench; An ion diffusion region is located in the epitaxial layer outside the sidewall of the third trench, and the vertical dimension of the ion diffusion region is smaller than the depth of the third trench. A second oxide layer covers the first oxide layer on the sidewall of the third trench, as well as the bottom wall and remaining sidewalls of the third trench.