LED chip assembly and manufacturing method thereof

Abstract

This invention relates to an LED chip assembly and its fabrication method. The method includes: providing an epitaxial assembly; depositing a plurality of metal electrodes on a functional layer; patterning the functional layer to form a plurality of LED epitaxial structures; depositing a passivation layer on the epitaxial wafer, such that the passivation layer at least covers the metal electrodes on the LED epitaxial structures; etching the passivation layer to expose a driving substrate; forming a fill layer on the driving substrate after etching the passivation layer; forming a protective layer on the fill layer; creating openings in the protective layer on the LED epitaxial structures to expose the metal electrodes; and depositing a common electrode metal layer on the driving substrate with exposed metal electrodes. This application, by simultaneously etching grooves around the core region during Mesa etching and metal etching, transfers areas of uneven resist application to locations away from the core region, resulting in more uniform PV thinning and trench filling processes.

Description

Technical Field

[0001] This invention relates to the field of LED chip technology, and in particular to an LED chip assembly and its manufacturing method. Background Technology

[0002] Micro LED refers to LEDs, which are smaller than traditional LEDs, reducing their size from millimeters to micro-nanoscale. When integrated into high-density, small-sized arrays and applied in the display field, they have advantages such as high brightness, high resolution, high contrast, low energy consumption, and long lifespan. They also have excellent performance in terms of response speed and thermal stability.

[0003] The current process flow for red vertical Micro-LEDs includes: transparent electrode evaporation, metal bonding, N-metal evaporation, Mesa etching, metal etching, protective layer (PV) thinning, channel filling, PV opening, and common N-electrode evaporation.

[0004] For typical Micro-LED products, the chip size is generally greater than 10μm, and the effect of uneven coating is almost negligible. Therefore, no coating buffer zone is reserved around the chip area.

[0005] However, for AR vertical chips, the die size is approximately 3μm with a center-to-center spacing of 3.75μm. Even slight unevenness in the photoresist coating can significantly impact the chip's process uniformity. After metal etching, the PV layer on top of the die is relatively thick and needs to be thinned to facilitate subsequent PV apertures. During PV thinning, the photoresist on top of the die must be etched away first before PV layer thinning can proceed. Due to the unevenness in the photoresist coating, the photoresist on top of the outer die in the light-emitting area is thicker than that on the inner die. Therefore, after PV thinning, the PV layer on top of the outer die will be thicker than that in the middle.

[0006] Similarly, since the channel filler material is a binder, uneven coating can also occur. Therefore, after the channel filler is thinned, the thickness difference between the PV layer at the top of the outer core and the PV layer of the middle core further increases. This results in the PV holes of the outer core not being fully etched, while the PV holes of the middle core are over-etched. Simultaneously, the remaining channel filler material on the periphery of the core region will be thicker than in the middle, affecting the uniformity of the subsequent common N electrode coverage. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the purpose of this application is to provide an LED chip component and a method for manufacturing the same, in order to overcome the above problems.

[0008] In a first aspect, this application provides a method for manufacturing an LED chip assembly, comprising:

[0009] An epitaxial assembly is provided, the epitaxial assembly including a driving substrate and an epitaxial wafer, the epitaxial wafer including a bonding metal layer and a functional layer disposed on the bonding metal layer, the epitaxial wafer being bonded to the driving substrate through the bonding metal layer;

[0010] Multiple metal electrodes are deposited on the functional layer by vapor deposition;

[0011] The functional layer is patterned to form a plurality of LED epitaxial structures and buffer trenches on the driving substrate, such that the channel between adjacent LED epitaxial structures exposes the bonding metal layer, the buffer trenches are located on the periphery of the region where the plurality of LED epitaxial structures are located, and each LED epitaxial structure is connected to a metal electrode.

[0012] A passivation layer is deposited on the epitaxial wafer such that the passivation layer at least covers the metal electrode on the LED epitaxial structure;

[0013] The passivation layer is etched to expose the driving substrate;

[0014] A filling layer is formed on the driving substrate after etching the passivation layer, and the filling layer covers the LED epitaxial structure;

[0015] A protective layer is formed on the filler layer;

[0016] An opening is made in the protective layer on the LED epitaxial structure to expose the metal electrode;

[0017] A common electrode metal layer is deposited on the driving substrate that exposes the metal electrodes, the common electrode metal layer being connected to each of the metal electrodes.

[0018] In one possible embodiment, the width of the buffer groove is greater than the width between adjacent LED epitaxial structures.

[0019] In one possible embodiment, the width of the buffer groove is 40 μm.

[0020] In one possible embodiment, the provision of an epitaxial component includes:

[0021] An epitaxial wafer is provided, the epitaxial wafer including a substrate and a functional layer disposed on the substrate;

[0022] A bonding metal layer is deposited on the surface of the functional layer on the side away from the substrate;

[0023] A driving substrate is provided, wherein a metal bonding layer is disposed on the driving substrate;

[0024] The bonding metal layers are bonded to each other, and the substrate is removed to obtain an epitaxial assembly.

[0025] In one possible embodiment, etching the passivation layer to expose the driving substrate includes:

[0026] The passivation layer is subjected to a first ICP etching to expose the bonding metal layer between the LED epitaxial structures and a portion of the bonding metal layer within the buffer trench;

[0027] A second ICP etching is performed on the driving substrate using the unetched passivation layer as a mask to expose the driving substrate.

[0028] In one possible embodiment, the width of the bonding metal layer exposed within the buffer groove is greater than the width between adjacent LED epitaxial structures.

[0029] In one possible embodiment, the distance between the bonded metal layer exposed in the buffer trench and the LED epitaxial structure near the buffer trench is greater than three times the spacing between adjacent LED epitaxial structures.

[0030] In one possible embodiment, a fill layer is formed on the driving substrate after etching the passivation layer, comprising:

[0031] Photoresist is spin-coated onto the driving substrate after the passivation layer has been etched;

[0032] The photoresist and the passivation layer are thinned by ICP etching, and the photoresist is removed.

[0033] A channel-filling adhesive is spin-coated onto the drive substrate to form a filler layer.

[0034] In one possible embodiment, the spin-coating of the channel-filling adhesive onto the driving substrate to form a filling layer includes:

[0035] A channel-filling adhesive is spin-coated onto the driving substrate to form a preliminary filling layer;

[0036] The initial filler layer is thinned by ICP etching to form the filler layer.

[0037] Secondly, this application also provides an LED chip assembly, which is prepared using the LED chip assembly manufacturing method described in any one of the first aspects.

[0038] Beneficial effects:

[0039] This application provides an LED chip assembly and its manufacturing method. By simultaneously etching buffer trenches around the LED epitaxial structure area during Mesa etching, areas with uneven resist coating are transferred to locations away from the LED epitaxial structure area, making the passivation layer thinning and trench filling processes more uniform. In addition, by etching the buffer trenches with metal, electrical isolation is formed between the peripheral metal and the LED epitaxial structure, preventing short circuits in the LED epitaxial structure when the peripheral metal is not etched. Attached Figure Description

[0040] Figure 1 A flowchart illustrating the manufacturing process of traditional LED chip components;

[0041] Figure 2 This is a schematic diagram of an LED chip assembly manufacturing method provided in an embodiment of this application;

[0042] Figure 3 for Figure 2 The diagram shows the structure of the epitaxial component formation process in the LED chip component manufacturing method.

[0043] Figure 4 for Figure 2 A schematic diagram of the structure after metal electrode deposition in the LED chip assembly fabrication method shown;

[0044] Figure 5 for Figure 2 A schematic diagram of the patterned structure of the functional layer in a method for manufacturing an LED chip component is shown.

[0045] Figure 6 for Figure 2 The diagram shows the structure after the passivation layer is deposited in a method for manufacturing an LED chip assembly.

[0046] Figure 7 for Figure 2 The diagram shows a structural schematic of the etching and deposition of a passivation layer in a method for manufacturing an LED chip assembly.

[0047] Figure 8 for Figure 2 The diagram shows a structural schematic of the process of forming a filler layer in a method for manufacturing an LED chip assembly.

[0048] Figure 9 for Figure 2 The diagram shows the structure of the protective layer after opening holes in a method for manufacturing an LED chip assembly.

[0049] Figure 10 for Figure 2 The diagram shows the structure after the common electrode metal layer is deposited in a method for manufacturing an LED chip component.

[0050] Figure 11 A schematic diagram of the structure of an LED chip assembly manufactured using traditional LED chip assembly methods;

[0051] Figure 12 To adopt such Figure 2 The diagram shows the structure of an LED chip assembly manufactured using a method for producing an LED chip assembly.

[0052] Explanation of reference numerals in the attached figures:

[0053] 1-Substrate; 2-Functional layer; 21-LED epitaxial structure; 23-Buffer trench; 231-Metal groove; 3-Bonding metal layer; 4-Drive substrate; 41-Metal bonding layer; 5-Metal electrode; 6-Passivation layer; 7-Filling layer; 8-Protective layer; 9-Common electrode metal layer. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0055] This invention discloses many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described herein. These are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0056] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. Generally, terms can be understood at least in part according to their usage in accordance with the invention. For example, the term "one or more" as used herein, depending at least in part on the invention, can be used to describe any component, structure, or feature in the singular or in the plural form to describe a combination of components, structures, or features. Similarly, terms such as "a," "an," or "the" can also be understood, depending at least in part on the invention, to convey either a singular or a plural usage. Furthermore, the term "based on..." can be understood not necessarily to convey an exclusive set of factors, but rather, depending at least in part on the invention, can alternatively allow for additional factors that do not necessarily have to be explicitly described.

[0057] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this invention should be interpreted in the broadest sense, such that “on” means not only “directly on something,” but also “on something” including the presence of an intermediate component or layer between the two, and “on something” or “above something” means not only “on something” or “above something,” but also “on something” or “above something” where no intermediate component or layer between the two exists.

[0058] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used in this invention to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways, rotated 90°, or otherwise oriented, and the spatial relative descriptive terms used in this invention can be interpreted accordingly.

[0059] As used in this invention, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entire lower or upper layer structure, or may have a extent smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0060] refer to Figure 1 This diagram illustrates the process flow of a traditional red vertical Micro-LED chip. As shown, a transparent electrode is first deposited on an epitaxial layer (EIP) of a gallium arsenide (GaAs) substrate and then bonded to a CMOS substrate. The GaAs substrate is then removed, followed by N-metal deposition and Mesa etching to form multiple LED epitaxial structures. Next, a passivation layer is deposited and etched to separate the metal beneath the LED epitaxial structures, allowing them to exist independently. Subsequently, the passivation layer (PV) is thinned, and channels on the CMOS are filled. Finally, PV openings are made to expose the N-metal. However, during PV thinning, the photoresist on top of the LED epitaxial structure must be etched away before the PV layer can be thinned. Due to uneven photoresist coating, the photoresist on top of the outermost LED epitaxial structure is thicker than that on the innermost structure. Therefore, after PV thinning, the PV layer on top of the outermost LED epitaxial structure is thicker than that in the middle.

[0061] Similarly, since the channel filler material is a binder, uneven coating can also occur. Therefore, after the channel filler is thinned, the thickness difference between the PV layer at the top of the outer core and the PV layer of the middle core further increases. This may result in the PV holes of the outer core not being fully etched, while the PV holes of the middle core being over-etched. Simultaneously, the remaining channel filler material on the periphery of the core region will be thicker than in the middle, affecting the uniformity of the subsequent common N electrode coverage.

[0062] Therefore, this application aims to provide a solution that can solve the above-mentioned technical problems, the details of which will be described in subsequent embodiments.

[0063] refer to Figure 2 This is a schematic flowchart of an LED chip assembly manufacturing method provided in an embodiment of this application. The method includes:

[0064] 101: Provide an extension component.

[0065] The aforementioned epitaxial assembly includes a driving substrate and an epitaxial wafer. The epitaxial wafer includes a bonding metal layer and a functional layer disposed on the bonding metal layer. The epitaxial wafer is bonded to the driving substrate through the bonding metal layer.

[0066] In one embodiment, step 101 includes: providing an epitaxial assembly, which includes: providing an epitaxial wafer, the epitaxial wafer including a substrate and a functional layer disposed on the substrate; depositing a bonding metal layer on the surface of the functional layer on the side away from the substrate; providing a driving substrate, the driving substrate having a metal bonding layer disposed thereon; bonding the bonding metal layer to the metal bonding layer, and removing the substrate to obtain the epitaxial assembly.

[0067] Optionally, the bonding metal layer is a transparent conductive layer, and the material can be a transparent material with low sheet resistance such as ITO, IGO, or IZO, and it forms an ohmic contact with the epitaxial layer.

[0068] In this embodiment, the functional layer constitutes the main epitaxial layer structure of the LED. The functional layer may include a first semiconductor layer, an active layer, and a second semiconductor layer stacked sequentially on the substrate, wherein the first semiconductor layer and the second semiconductor layer are different types of doped semiconductor layers.

[0069] The first semiconductor layer can be an N-doped semiconductor layer or a P-doped semiconductor layer, and the second semiconductor layer can be a P-doped semiconductor layer or an N-doped semiconductor layer. The active layer can be a multiple quantum well (MQW) structure. Specifically, the semiconductor layer can be a III-V group compound semiconductor material such as GaN, AlGaN, InGaN, AlInP, GaInP, or AlGaInP; the quantum well or quantum layer can be InGaN, AlGaN, InN, InAlN, or AlInGaN; and the quantum barrier alternately stacked with the quantum well layer can be GaN, AlN, AlGaN, AlInGaN, or InAlN; the multiple quantum well structure can include one, two, three, four, five, six, seven, or eight quantum wells (or at least one quantum hole); the wavelength emitted by the active layer can be a wavelength in the blue light band, a wavelength in the green light band, or a wavelength in the red light band. In this embodiment, red light is used as an example.

[0070] In the embodiments of this application, the substrate can be a growth substrate or a temporary substrate. For example, the epitaxial wafer is a red-light-emitting epitaxial wafer based on aluminum indium gallium phosphate, the substrate is a temporary sapphire substrate, and the functional layer includes a P-type AlInP (or AlGaInP) layer, an active layer, and an N-type AlInP (or AlGaInP) layer stacked sequentially.

[0071] For example, such as Figure 3 As shown, an epitaxial wafer is first provided, which includes a substrate 1 and a functional layer 2 disposed on the substrate 1. A bonding metal layer 3 is deposited on the functional layer 2. Then, the metal bonding layer 41 on the driving substrate (CMOS substrate) 4 is bonded to the bonding metal layer 3 by gold bonding. After bonding, the substrate 1 is peeled off by a peeling process.

[0072] 102: A plurality of metal electrodes are deposited on the functional layer by vapor deposition.

[0073] In this embodiment, the metal electrode 5 is one or more metals that can form an ohmic contact with the semiconductor layer (such as an N-type semiconductor layer) in the functional layer to conduct current. For example, the metal electrode 5 can be Au, Al, Ag, Cu, Ni, AuZn, AuBe, AuGe, AuGeNi, etc. (similar conductive metals).

[0074] For example, such as Figure 4 As shown, a metal electrode 5 is deposited on the epitaxial surface by vapor deposition, and then annealed at a temperature of 300-500℃ for 10-60s to allow the metal electrode 5 and the epitaxial layer to form an ohmic contact.

[0075] 103: Pattern the functional layer to form a plurality of LED epitaxial structures and buffer trenches on the driving substrate, such that the bonding metal layer is exposed in the channel between adjacent LED epitaxial structures.

[0076] The buffer groove is located on the periphery of the area where the multiple LED epitaxial structures are located, and each LED epitaxial structure is connected to a metal electrode.

[0077] The aforementioned patterning refers to forming a predetermined pattern shape into the layer structure through multiple photolithography and etching processes. After patterning the functional layer 2, multiple independent LED epitaxial structures 21 are formed. Each LED epitaxial structure 21 is separated from the others. The original functional layers between adjacent LED epitaxial structures 21 are removed to form channels, exposing the bonding metal layer 3 on the channels. Buffer trenches 23 are formed around the area where the LED epitaxial structure 21 is located. Figure 5 As shown.

[0078] The layer structure of the LED epitaxial structure is the same as that of the functional layer, both including the main epitaxial layer structure of the LED: the first semiconductor layer, the active layer, and the second semiconductor layer.

[0079] Optionally, the width of the buffer groove 23 is greater than the width between adjacent LED epitaxial structures 21.

[0080] Optionally, the width of the buffer groove 23 is 40 μm.

[0081] 104: Deposit a passivation layer on the epitaxial wafer such that the passivation layer at least covers the metal electrode on the LED epitaxial structure.

[0082] In this embodiment, the passivation layer covers the surface of the LED epitaxial structure to protect the LED epitaxial structure and the metal electrodes thereon. The passivation layer can be one or more of Al2O3, AlN, SiN, SiO2, and AlON thin films.

[0083] In an alternative embodiment, the passivation layer 6 covers the surface of the LED epitaxial structure and the exposed bonding metal layer 41 and buffer trench 23 on the channel, such as... Figure 6 As shown.

[0084] 105: Etch the passivation layer to expose the drive substrate.

[0085] In one implementation, step 105 includes: performing a first ICP etching on the passivation layer to expose the bonding metal layer between the LED epitaxial structures and a portion of the bonding metal layer within the buffer trench; and performing a second ICP etching on the driving substrate using the unetched passivation layer as a mask to expose the driving substrate.

[0086] For example, such as Figure 7 As shown, the passivation layer 6 is first etched into an independent island structure using ICP etching, which serves as a mask for metal etching; then, the metal between the LED epitaxial structures 21 is etched away using ICP etching, and a metal groove 231 is simultaneously etched into the buffer groove 23 from the previous step.

[0087] Optionally, the width of the bonding metal layer (or metal groove 231) exposed in the buffer groove 23 is greater than the width between adjacent LED epitaxial structures 21.

[0088] Optionally, the distance between the bonded metal layer exposed in the buffer groove 23 and the LED epitaxial structure 21 near the buffer groove 23 is greater than 3 times the spacing between adjacent LED epitaxial structures 21.

[0089] 106: A filling layer is formed on the driving substrate after etching the passivation layer, the filling layer covering the LED epitaxial structure.

[0090] In one embodiment, step 106 includes: spin-coating photoresist onto the driving substrate after etching the passivation layer; thinning the photoresist and the passivation layer using ICP etching, and removing the photoresist; and spin-coating a channel-filling adhesive onto the driving substrate to form a filling layer.

[0091] Optionally, the step of spin-coating a channel filler adhesive on the driving substrate to form a filler layer includes: spin-coating a channel filler adhesive on the driving substrate to form a preliminary filler layer; and thinning the preliminary filler layer using ICP etching to form a filler layer.

[0092] For example, such as Figure 8 As shown, photoresist is spin-coated onto the surface of the epitaxial wafer, and then ICP etching is used to simultaneously thin the photoresist and passivation layer 6 (PV layer). Finally, the photoresist on the surface of the epitaxial wafer is removed. Next, a channel filling material, such as BCB or SOG, is spin-coated onto the surface of the epitaxial wafer, and then ICP etching is used to thin the filling layer 7 as a whole.

[0093] 107: A protective layer is formed on the filling layer.

[0094] 108: An opening is made in the protective layer on the LED epitaxial structure to expose the metal electrode.

[0095] For example, such as Figure 9 As shown, PECVD is first used in... Figure 8 Based on the schematic diagram shown, a protective layer 8 is deposited, and then an opening is made in the protective layer 8 on the surface of the LED epitaxial structure 21 by ICP etching.

[0096] It should be noted that the material of the protective layer can be the same as that of the passivation layer; no specific limitation is made here.

[0097] 109: A common electrode metal layer is deposited on the driving substrate that exposes the metal electrodes, the common electrode metal layer being connected to each of the metal electrodes.

[0098] Optionally, the common electrode metal layer can be a transparent conductive layer, and its material can be a transparent material with low sheet resistance such as ITO, IGO, or IZO.

[0099] For example, such as Figure 10 As shown, a common electrode metal layer 9 is deposited on the driving substrate that exposes the metal electrodes. The metal electrodes 5 of the LED epitaxial structure 21 are interconnected using the common electrode metal layer 9. Finally, the excess common electrode metal layer 9 is removed by wet etching.

[0100] For example, such as Figure 11 The LED chip assembly shown is manufactured using a conventional process and Figure 12 The LED chip assembly fabricated using the LED chip assembly fabrication method provided in the embodiments of this application shown has a basically uniform remaining PV layer thickness on the surface of its core (LED epitaxial structure), and the filling layer is more uniformly filled.

[0101] Based on the same inventive concept, this application also provides an LED chip assembly, which is prepared using the method described in the above-described embodiments.

[0102] In summary, the LED chip assembly and its manufacturing method provided in this application embodiment, by simultaneously etching buffer trenches around the LED epitaxial structure area during Mesa etching, transfers areas with uneven resist coating to locations away from the LED epitaxial structure area, making the passivation layer thinning and trench filling processes more uniform; in addition, by etching the buffer trenches with metal, electrical isolation is formed between the peripheral metal and the LED epitaxial structure, preventing short circuits in the LED epitaxial structure when the peripheral metal is not etched.

[0103] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A method for manufacturing an LED chip assembly, characterized in that, include: An epitaxial assembly is provided, the epitaxial assembly including a driving substrate and an epitaxial wafer, the epitaxial wafer including a bonding metal layer and a functional layer disposed on the bonding metal layer, the epitaxial wafer being bonded to the driving substrate through the bonding metal layer; Multiple metal electrodes are deposited on the functional layer by vapor deposition; The functional layer is patterned to form a plurality of LED epitaxial structures and buffer trenches on the driving substrate, such that the channel between adjacent LED epitaxial structures exposes the bonding metal layer, the buffer trenches are located on the periphery of the region where the plurality of LED epitaxial structures are located, and each LED epitaxial structure is connected to a metal electrode. A passivation layer is deposited on the epitaxial wafer such that the passivation layer at least covers the metal electrode on the LED epitaxial structure; The passivation layer is etched to expose the driving substrate; A filling layer is formed on the driving substrate after etching the passivation layer, and the filling layer covers the LED epitaxial structure; A protective layer is formed on the filler layer; An opening is made in the protective layer on the LED epitaxial structure to expose the metal electrode; A common electrode metal layer is deposited on the driving substrate that exposes the metal electrodes, the common electrode metal layer being connected to each of the metal electrodes.

2. The method for manufacturing an LED chip assembly as described in claim 1, characterized in that, The width of the buffer groove is greater than the width between adjacent LED epitaxial structures.

3. The method for manufacturing an LED chip assembly as described in claim 2, characterized in that, The width of the buffer groove is 40µm.

4. The method for manufacturing an LED chip assembly as described in claim 1, characterized in that, The provision of an epitaxial component includes: An epitaxial wafer is provided, the epitaxial wafer including a substrate and a functional layer disposed on the substrate; A bonding metal layer is deposited on the surface of the functional layer on the side away from the substrate; A driving substrate is provided, wherein a metal bonding layer is disposed on the driving substrate; The bonding metal layers are bonded to each other, and the substrate is removed to obtain an epitaxial assembly.

5. The method for manufacturing an LED chip assembly as described in claim 4, characterized in that, Etching the passivation layer to expose the driving substrate includes: The passivation layer is subjected to a first ICP etching to expose the bonding metal layer between the LED epitaxial structures and a portion of the bonding metal layer within the buffer trench; A second ICP etching is performed on the driving substrate using the unetched passivation layer as a mask to expose the driving substrate.

6. The method for manufacturing an LED chip assembly as described in claim 5, characterized in that, The width of the bonded metal layer exposed within the buffer groove is greater than the width between adjacent LED epitaxial structures.

7. The method for manufacturing an LED chip assembly as described in claim 5, characterized in that, The distance between the bonded metal layer exposed in the buffer groove and the LED epitaxial structure near the buffer groove is greater than three times the spacing between adjacent LED epitaxial structures.

8. The method for manufacturing an LED chip assembly as described in any one of claims 1-7, characterized in that, A filling layer is formed on the driving substrate after etching the passivation layer, comprising: Photoresist is spin-coated onto the driving substrate after the passivation layer has been etched; The photoresist and the passivation layer are thinned by ICP etching, and the photoresist is removed. A channel-filling adhesive is spin-coated onto the drive substrate to form a filler layer.

9. The method for manufacturing an LED chip assembly as described in claim 8, characterized in that, The process of spin-coating a channel-filling adhesive onto the driving substrate to form a filling layer includes: A channel-filling adhesive is spin-coated onto the driving substrate to form a preliminary filling layer; The initial filler layer is thinned by ICP etching to form the filler layer.

10. An LED chip assembly, characterized in that, Prepared using the LED chip assembly fabrication method as described in any one of claims 1-9.

Images