A GaN HEMT structure with an air cavity and its preparation method
By constructing an air cavity structure in GaN HEMT devices, the parasitic capacitance and heat dissipation path problems caused by traditional passivation layers are solved, thereby improving the high-frequency characteristics and thermal stability of the devices, making them suitable for semiconductor power devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUJIAN FULIAN INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2026-03-18
- Publication Date
- 2026-06-26
AI Technical Summary
In existing GaN HEMT devices, the excessive parasitic capacitance and excessively long heat dissipation path caused by traditional passivation layers limit the high-frequency characteristics and long-term operational reliability of the devices.
An air cavity structure is constructed in the global active region between the gate and source, and between the gate and drain. The high-dielectric-constant SiO2 dielectric is removed by wet etching and replaced with low-dielectric-constant air, thus reconstructing the heat dissipation path.
It significantly reduces parasitic capacitance, improves high-frequency characteristics and thermal stability, expands the application potential of devices in the high-frequency band, and improves the long-term operational reliability of devices.
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Figure CN122294524A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a GaN HEMT structure with an air cavity and its fabrication method. Background Technology
[0002] With the rapid development of 5G / 6G communication, satellite communication, radar detection and other fields, GaN HEMT has become the core choice for high-frequency and high-power semiconductor devices due to its excellent characteristics such as wide bandgap, high breakdown electric field, high electron saturation drift velocity and high temperature resistance.
[0003] Existing conventional GaN HEMT devices generally use inorganic dielectric materials such as SiN and SiO2 as passivation layers, which also serve as the support structure between the metal interconnect layers. This structure suffers from two core technical drawbacks: First, SiN and SiO2 materials have high dielectric constants, introducing large parasitic capacitances between the gate and source, and between the gate and drain, severely deteriorating the device's high-frequency characteristics and limiting its application in millimeter-wave and higher frequency bands. Second, the full-coverage passivation layer lengthens the device's heat dissipation path; heat generated in the device channel must pass through multiple dielectric layers to be conducted outwards, causing a rapid rise in junction temperature during operation. This leads to problems such as decreased carrier mobility, threshold voltage drift, and thermal stress concentration, significantly reducing the device's long-term operational reliability.
[0004] To reduce parasitic capacitance, existing technologies have introduced GaN HEMT solutions with cavity structures. These solutions often use special gate structure designs to form a locally enclosed cavity between the gate metal and the passivation layer. This can only reduce the parasitic capacitance in the local area of the gate, while still retaining the passivation thin layer covering the entire active region. It cannot solve the problem of global parasitic capacitance caused by the passivation layer, nor can it improve the industry pain point of low heat dissipation efficiency caused by the passivation layer. The improvement in the high-frequency characteristics and heat dissipation performance of the device is very limited. Summary of the Invention
[0005] To address the dual technical problems of excessive parasitic capacitance and excessively long heat dissipation paths caused by traditional passivation layers in existing high-frequency, high-power semiconductor devices and fabrication schemes, this invention provides a GaN HEMT structure with an air cavity structure and its fabrication method. By constructing an air cavity structure in the entire active region between the gate and source, and between the gate and drain, the dual technical problems of excessive parasitic capacitance and excessively long heat dissipation paths caused by traditional passivation layers are solved simultaneously. This significantly improves the high-frequency characteristics, thermal stability, and operational reliability of GaN HEMT devices. Moreover, the fabrication process is fully compatible with conventional GaN HEMT processes, requires no special gate structure design, and is easy to industrialize and promote.
[0006] The technical solution of the present invention is as follows: A method for fabricating a GaN HEMT structure with an air cavity includes the following steps: Step 1: Grow an epitaxial layer on the substrate, wherein the epitaxial layer comprises, from bottom to top, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a cap layer; Step 2: Define the active region of the device and achieve electrical isolation between devices through dry etching or ion implantation processes; Step 3: Define the source and drain patterns on the cap layer surface, evaporate the source and drain metals and perform high-temperature tempering to form ohmic contacts between the source and drain. Step 4: Deposit a layer of SiO2 as a gate passivation layer, define the gate pattern on the gate passivation layer and etch it, then define the gate cap pattern by photolithography, and evaporate the gate metal to form the gate; Step 5: Deposit a composite passivation layer on the surface of the device after the gate fabrication is completed. The composite passivation layer consists of a SiO2 sacrificial layer and a SiN passivation layer from bottom to top. Step 6: Define a metal interconnect via pattern on the composite passivation layer above the source and drain, and etch the metal interconnect via through the composite passivation layer using a dry etching process. Step 7: A photoresist protective layer is formed on the outer region of the metal interconnect via using photolithography. Using the metal interconnect via as an etching window, a wet etching process is used to remove all the SiO2 sacrificial layer below the SiN passivation layer, forming an air cavity in the region between the gate and the source, and between the gate and the drain. Step 8: Define the metal interconnect pattern on the composite passivation layer, evaporate metal to form the metal interconnect, and complete the device fabrication.
[0007] Furthermore, in step 2, the dry etching process uses BCl3+Cl2 etching gas, and the etching depth at least penetrates the epitaxial layer to form an isolation platform; the ion implantation process uses Ar... + Ion implantation enables device isolation.
[0008] Furthermore, in step 3, the source / drain metal adopts a Ti / Al / Ni / Au stacked structure, and the high-temperature tempering temperature is 850~930℃.
[0009] Furthermore, in step 4, the gate metal is a Ni / Au stack or a Ti / Pt / Au stack, and the total thickness of the gate metal is 4500~6000 Å.
[0010] Furthermore, when the gate metal uses a Ni / Au stack, the Ni layer thickness is 500 Å and the Au layer thickness is 4500 Å; when the gate metal uses a Ti / Pt / Au stack, the Ti layer thickness is 300 Å, the Pt layer thickness is 400 Å, and the Au layer thickness is 4300 Å.
[0011] Furthermore, in step 7, the wet etching process uses HF solution or BOE solution, and the etching temperature is 25°C (room temperature).
[0012] Furthermore, in step 1, the substrate is any one of a Si substrate, a GaN substrate, a SiC substrate, an Al2O3 substrate, or a diamond substrate.
[0013] Furthermore, in step 1, the thickness of the buffer layer is 3~5μm, the thickness of the GaN channel layer is 200~300μm, the thickness of the AlGaN barrier layer is 15~25μm, and the thickness of the cap layer is 3~5μm.
[0014] A GaN HEMT structure with an air cavity is prepared by the above method, including a substrate, an epitaxial layer, a source, a drain, a gate, a composite passivation layer, and an air cavity; The epitaxial layers are stacked sequentially from bottom to top on the upper surface of the substrate, and the epitaxial layers include a buffer layer, a GaN channel layer, an AlGaN barrier layer, and a cap layer. The source, drain, and gate are all disposed on the upper surface of the cap layer, and the gate is located between the source and the drain; The composite passivation layer covers the active region surfaces of the source, drain, gate, and cap layer, and the composite passivation layer includes a bottom SiO2 sacrificial layer and a top SiN passivation layer. Both the source and the drain are provided with metal interconnect vias that penetrate the composite passivation layer, and the metal interconnect vias are electrically connected to the source and the drain, respectively. In the active region between the gate and the source, and between the gate and the drain, the bottom SiO2 sacrificial layer of the composite passivation layer is completely removed to form the air cavity; The air cavity has the SiN passivation layer as the top cover and the upper surface of the cap layer as the bottom wall. The bottom SiO2 sacrificial layer of the composite passivation layer is only retained on the outside of the active region, forming the lateral support structure of the air cavity. The interior of the air cavity is filled with air medium.
[0015] Furthermore, the composite passivation layer also includes a gate passivation layer deposited after the gate is fabricated. The gate passivation layer is a SiO2 dielectric layer. The gate passivation layer covers the gate and the surface of the active region. The bottom SiO2 sacrificial layer and the top SiN passivation layer are deposited sequentially on top of the gate passivation layer.
[0016] Compared with the prior art, the present invention has the following beneficial effects: (1) Significantly reduce global parasitic capacitance and significantly improve high-frequency characteristics: This invention removes all SiO2 dielectric between the gate and source, and between the gate and drain by wet etching to form a global air cavity filled with air. The dielectric constant of air is close to 1, which is much lower than that of SiN (dielectric constant 7~8) and SiO2 (dielectric constant 3.9). This fundamentally eliminates the gate-source and gate-drain parasitic capacitance caused by the passivation layer dielectric, significantly reduces the parasitic parameters of the device, significantly improves the cutoff frequency and maximum oscillation frequency of the device, and expands the application potential of the device in the high-frequency band.
[0017] (2) Reconstructing the heat dissipation path and significantly improving the thermal stability and reliability of the device: This invention breaks the heat dissipation limitation of the traditional full-coverage passivation layer. The heat generated by the device channel can be directly conducted upward through the air cavity without passing through multiple layers of medium, which greatly shortens the heat dissipation path and effectively reduces the junction temperature of the device during operation. At the same time, the air cavity structure can release the thermal stress inside the device, significantly reduce the threshold voltage drift phenomenon under high temperature operation, and improve the long-term working reliability and service life of the device.
[0018] (3) Strong process compatibility and easy to implement in industry: The air cavity preparation process of the present invention is based on the conventional GaN HEMT process. It can be achieved by adding sacrificial layer deposition and wet lateral etching steps. There is no need to design special M-type gate, temporary gate control layer and other complex structures. No special process equipment is required. It is fully compatible with the existing semiconductor production line process. The process complexity is low and the yield is controllable. It has great value for industrialization and promotion.
[0019] (4) Flexible structural design and wide adaptability: The air cavity structure of the present invention can be adapted to various substrates and GaN HEMT devices of various structures, not limited to depletion-type devices. The size and etching range of the air cavity can be adjusted according to the device performance requirements, so as to achieve comprehensive optimization of device performance without changing the core structure of the device. Attached Figure Description
[0020] Figure 1 This is a cross-sectional schematic diagram of the epitaxial layer stacking structure of the GaN HEMT structure in an embodiment of the present invention; Figure 2 This is a schematic cross-sectional view of the device after active region isolation is completed in an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the device after the source and drain electrodes have been fabricated in an embodiment of the present invention. Figure 4 This is a schematic cross-sectional view of the device after gate fabrication in an embodiment of the present invention; Figure 5 This is a schematic cross-sectional view of the device after the composite passivation layer deposition is completed in an embodiment of the present invention; Figure 6This is a schematic cross-sectional view of the device after etching of the metal interconnect vias in an embodiment of the present invention; Figure 7 This is a schematic cross-sectional view of the device after a photoresist protective layer is formed on the outside of the metal interconnect via in an embodiment of the present invention; Figure 8 This is a schematic cross-sectional view of the final device after the air cavity and metal interconnection are fabricated in an embodiment of the present invention.
[0021] In the figure: 1-substrate, 2-buffer layer, 3-GaN channel layer, 4-AlGaN barrier layer, 5-cap layer, 6-source, 7-drain, 8-gate passivation layer, 9-gate metal, 10-composite passivation layer, 101-SiO2 sacrificial layer, 102-SiN passivation layer, 11-metal interconnect via, 12-photoresist protection layer, 13-air cavity, 14-metal interconnect line. Detailed Implementation
[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0023] See Figure 1-8 This invention provides a method for fabricating a GaN HEMT structure with an air cavity, comprising the following steps: Step 1: Grow an epitaxial layer on substrate 1, wherein the epitaxial layer comprises, from bottom to top, a buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, and a cap layer 5; Step 2: Define the active region of the device and achieve electrical isolation between devices through dry etching or ion implantation processes; Step 3: Define source and drain patterns on the surface of the cap layer 5, evaporate source and drain metals and perform high-temperature tempering to form ohmic contacts between the source and drain. Step 4: Deposit a layer of SiO2 as a gate passivation layer 8, define the gate pattern on the gate passivation layer 8 and etch it, then define the gate cap pattern by photolithography, and evaporate the gate metal 9 to form the gate. Step 5: Deposit a composite passivation layer 10 on the surface of the device after the gate fabrication is completed. The composite passivation layer 10 consists of a SiO2 sacrificial layer 101 and a SiN passivation layer 102 from bottom to top. Step 6: Define a metal interconnect via 11 pattern on the composite passivation layer 10 above the source and drain, and form a metal interconnect via 11 through the composite passivation layer 10 by dry etching process. Step 7: A photoresist protection layer 12 is formed on the outer region of the metal interconnect via 11 by photolithography. Using the metal interconnect via 11 as an etching window, a wet etching process is used to remove all the SiO2 sacrificial layer 101 below the SiN passivation layer 102, and an air cavity 13 is formed in the region between the gate and the source, and between the gate and the drain. Step 8: Define the pattern of metal interconnect 14 on the composite passivation layer 10, and deposit metal to form metal interconnect 14 to complete device fabrication.
[0024] In the field of semiconductor devices, the active region is the core area in the device that realizes the core electrical functions such as electrical signal amplification, current regulation, and charge carrier transport. It is the key area for the generation, transport, recombination and other electrical behaviors of charge carriers (electrons or holes), which is different from the passive region that only serves the functions of support, wiring and electrical isolation. In this invention, the active region of the GaN HEMT device refers to a specific functional region of the epitaxial layer on the substrate. The core covers the corresponding region of the GaN channel layer, the AlGaN barrier layer and the cap layer above it. The three core electrodes of the active electrode, drain electrode and gate electrode are fabricated in this region. It is the only region where two-dimensional electron gas (2DEG) is generated and transported and the current between the source and drain electrodes is controlled through the gate electrode. It is also the core region for the fabrication of the air cavity and the core layout of the composite passivation layer in this invention.
[0025] In one embodiment of the present invention, the dry etching process uses BCl3+Cl2 etching gas, and the etching depth at least penetrates the epitaxial layer to form an isolation platform; the ion implantation process uses Ar + Ion implantation enables device isolation.
[0026] In one embodiment of the present invention, the source / drain metal adopts a Ti / Al / Ni / Au stacked structure, and the high-temperature tempering temperature is 850~930℃.
[0027] In one embodiment of the present invention, the gate metal 9 is a Ni / Au stack or a Ti / Pt / Au stack, and the total thickness of the gate metal 9 is 4500~6000 Å.
[0028] Specifically, when the gate metal 9 adopts a Ni / Au stack, the Ni layer thickness is 500 Å and the Au layer thickness is 4500 Å; when the gate metal 9 adopts a Ti / Pt / Au stack, the Ti layer thickness is 300 Å, the Pt layer thickness is 400 Å and the Au layer thickness is 4300 Å.
[0029] In one embodiment of the present invention, the wet etching process uses HF solution or buffered oxide etchant (BOE) and the etching temperature is room temperature 25°C.
[0030] In one embodiment of the present invention, the substrate 1 is any one of a Si substrate, a GaN substrate, a SiC substrate, an Al2O3 substrate, or a diamond substrate.
[0031] In one embodiment of the present invention, the thickness of the buffer layer 2 is 3~5μm, the thickness of the GaN channel layer 3 is 200~300μm, the thickness of the AlGaN barrier layer 4 is 15~25μm, and the thickness of the cap layer 5 is 3~5μm.
[0032] In one embodiment of the present invention, the GaN HEMT structure is a depletion-mode (D-Mode) GaN HEMT structure.
[0033] On the other hand, see Figure 8 The present invention provides a GaN HEMT structure with an air cavity, including a substrate 1, an epitaxial layer, a source, a drain, a gate, a composite passivation layer 10, and an air cavity 13.
[0034] The epitaxial layers are stacked sequentially from bottom to top on the upper surface of the substrate 1. The epitaxial layers include a buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, and a cap layer 5. The source, drain, and gate are all disposed on the upper surface of the cap layer 5, and the gate is located between the source and the drain. The composite passivation layer 10 covers the active region surfaces of the source, drain, gate, and the cap layer 5. The composite passivation layer 10 includes a bottom SiO2 sacrificial layer 101 and a top SiN passivation layer 102.
[0035] Both the source and the drain are provided with metal interconnect vias 11 that penetrate the composite passivation layer 10. The metal interconnect vias 11 are electrically connected to the source and the drain, respectively. In the active region between the gate and the source, and between the gate and the drain, the bottom SiO2 sacrificial layer 101 of the composite passivation layer 10 is completely removed to form the air cavity 13.
[0036] The air cavity 13 has the SiN passivation layer 102 as the top cover and the upper surface of the cap layer 5 as the bottom wall. The bottom SiO2 sacrificial layer 101 of the composite passivation layer 10 is only retained on the outside of the active region, forming the lateral support structure of the air cavity 13. The interior of the air cavity 13 is filled with air medium.
[0037] In one embodiment of the present invention, the composite passivation layer 10 further includes a gate passivation layer 8 deposited after the gate is fabricated. The gate passivation layer 8 is a SiO2 dielectric layer. The gate passivation layer 8 covers the gate and the surface of the active region. The bottom SiO2 sacrificial layer 101 and the top SiN passivation layer 102 are sequentially deposited above the gate passivation layer 8.
[0038] The core design of the GaN HEMT structure with air cavity provided by this invention is as follows: an air cavity 13 is formed by etching the sacrificial layer 101 throughout the active region between the gate and the source, and between the gate and the drain. This replaces the traditional high-dielectric-constant passivation medium with low-dielectric-constant air, while reconstructing the device heat dissipation path, thereby achieving a simultaneous improvement in the device's high-frequency characteristics and thermal reliability. Example 1:
[0039] This embodiment provides a D-ModeGaN HEMT structure with an air cavity, the specific structure of which is as follows: like Figure 8 As shown, the device comprises, from bottom to top, a substrate 1, an epitaxial layer, a source, a drain, a gate, a composite passivation layer 10, and an air cavity 13.
[0040] In this embodiment, substrate 1 is a SiC substrate, which has excellent thermal conductivity and is suitable for high-power device applications; in other alternative embodiments, substrate 1 may also be a Si substrate, GaN substrate, Al2O3 substrate or diamond substrate.
[0041] Epitaxial layers are stacked sequentially from bottom to top on the upper surface of substrate 1, including a buffer layer 2, a GaN channel layer 3, an AlGaN barrier layer 4, and a cap layer 5. The buffer layer 2 has a thickness of 4 μm and is used to match the lattice mismatch between substrate 1 and the channel layer, reducing defect density. The GaN channel layer 3 has a thickness of 250 μm and serves as the conductive channel for the device. The AlGaN barrier layer 4 has a thickness of 20 μm and forms a heterojunction with the GaN channel layer 3, generating a two-dimensional electron gas (2DEG). The cap layer 5 has a thickness of 4 μm and is used to protect the barrier layer and reduce the surface states of the device. In other optional embodiments, the thickness of each epitaxial layer can be adjusted within a corresponding range according to the device performance requirements.
[0042] The source, drain, and gate are all disposed on the upper surface of the cap layer 5, with the gate located between the source and drain. The source and drain employ a Ti / Al / Ni / Au stacked metal structure, forming an ohmic contact with the cap layer 5; the gate employs a Ni / Au stacked structure with a total thickness of 5000 Å, wherein the Ni layer is 500 Å thick and the Au layer is 4500 Å thick, forming a Schottky contact with the cap layer 5. In other optional embodiments, the gate may also employ a Ti / Pt / Au stacked structure with a total thickness of 5000 Å, wherein the Ti layer is 300 Å thick, the Pt layer is 400 Å thick, and the Au layer is 4300 Å thick.
[0043] The composite passivation layer 10 covers the active region surfaces of the source, drain, gate, and cap layer 5, and from bottom to top includes a gate passivation layer 8 (SiO2 dielectric layer), a bottom SiO2 sacrificial layer 101, and a top SiN passivation layer 102. Metal interconnect vias 11 are provided above the source and drain, penetrating the entire composite passivation layer 10. The metal interconnect vias 11 are filled with metal and form electrical connections with the source and drain, respectively.
[0044] In the active region between the gate and source, and between the gate and drain, the bottom SiO2 sacrificial layer 101 of the composite passivation layer 10 is completely removed to form an air cavity 13. The air cavity 13 has the SiN passivation layer 102 as the top cover and the upper surface of the cap layer 5 as the bottom wall. The SiO2 sacrificial layer 101 is only retained on the outside of the active region, forming a lateral support structure for the air cavity 13 to ensure the structural stability of the SiN passivation layer 102. The air cavity 13 is filled with air and no solid dielectric is used. Example 2:
[0045] This embodiment provides a method for fabricating a GaN HEMT structure with an air cavity, used to prepare the device structure described in Embodiment 1. The specific steps are as follows: Epitaxial wafer fabrication: Metal-organic chemical vapor deposition (MOCVD) was used to grow an epitaxial layer on a SiC substrate. From bottom to top, the epitaxial layer consisted of a 4 μm thick buffer layer 2, a 250 μm thick GaN channel layer 3, a 20 μm thick AlGaN barrier layer 4, and a 4 μm thick cap layer 5, completing the epitaxial wafer fabrication. The resulting structure is shown in the figure. Figure 1 As shown.
[0046] Active region isolation: The active region of the device is defined by photolithography. An inductively coupled plasma (ICP) dry etching process is used with a BCl3+Cl2 mixed etching gas. The etching depth penetrates the entire epitaxial layer, forming an independent device isolation platform to achieve electrical isolation between adjacent devices. The resulting structure is shown below. Figure 2 As shown. In other alternative embodiments, Ar⁺ ion implantation can also be used to achieve device isolation.
[0047] Source and drain electrode fabrication: Source and drain electrode patterns were defined on the surface of cap layer 5 using photolithography, evaporation, and lift-off processes. A Ti / Al / Ni / Au multilayer metal was then deposited, followed by high-temperature tempering at 890℃ under a nitrogen atmosphere to form ohmic contacts between the source and drain electrodes. The resulting structure is shown below. Figure 3 As shown.
[0048] Gate fabrication: A SiO2 layer 8 as the gate passivation layer was deposited on the device surface using plasma-enhanced chemical vapor deposition (PECVD). The gate pattern was defined using photolithography, and the SiO2 and cap layer 5 in the gate region were etched using dry etching to expose the gate trench. Photoresist was then spin-coated, and the gate cap pattern was defined using photolithography. Ni / Au gate metal 9 was deposited using electron beam evaporation, and the gate was formed after a lift-off process. The resulting structure is shown below. Figure 4 As shown.
[0049] Deposition of composite passivation layer 10: Using PECVD process, a SiO2 sacrificial layer 101 and a SiN passivation layer 102 are sequentially deposited on the surface of the device after gate fabrication to form a composite passivation layer 10, the resulting structure as shown in the figure. Figure 5 As shown.
[0050] Fabrication of metal interconnect vias 11: Metal interconnect vias 11 are patterned on the composite passivation layer 10 above the source and drain electrodes using photolithography. ICP dry etching is then used to etch metal interconnect vias 11 that penetrate the entire composite passivation layer 10, exposing the underlying source and drain metals. The resulting structure is shown below. Figure 6 As shown.
[0051] Etching of sacrificial layer 101 and formation of air cavity 13: Spin-coating photoresist, and forming a photoresist protection layer 12 on the edge region of the active area outside the metal interconnect via 11 using photolithography. This protects the SiO2 sacrificial layer 101 surrounding the device from etching, exposing only the area of the metal interconnect via 11. The resulting structure is as follows: Figure 7 As shown; using the metal interconnect via 11 as the etching window, room temperature wet etching is performed using BOE solution to remove all SiO2 sacrificial layers 101 below the SiN passivation layer 102 by lateral etching. After etching, the photoresist protection layer 12 is removed, and an air cavity 13 is formed in the region between the gate and the source, and between the gate and the drain.
[0052] Metal interconnect fabrication: Metal interconnect lines 14 are patterned on the composite passivation layer 10 using photolithography. Metal is then deposited using electron beam evaporation, followed by a lift-off process to form the metal interconnect lines 14. These metal interconnect lines 14 are electrically connected to the source and drain electrodes through metal interconnect vias 11, completing the device fabrication. The final structure is shown below. Figure 8 As shown.
[0053] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A method for fabricating a GaN HEMT structure with an air cavity, characterized in that, The preparation method includes the following steps: Step 1: Grow an epitaxial layer on the substrate, wherein the epitaxial layer comprises, from bottom to top, a buffer layer, a GaN channel layer, an AlGaN barrier layer and a cap layer; Step 2: Define the active region of the device and achieve electrical isolation between devices through dry etching or ion implantation processes; Step 3: Define the source and drain patterns on the cap layer surface, evaporate the source and drain metals and perform high-temperature tempering to form ohmic contacts between the source and drain. Step 4: Deposit a layer of SiO2 as a gate passivation layer, define the gate pattern on the gate passivation layer and etch it, then define the gate cap pattern by photolithography, and evaporate the gate metal to form the gate; Step 5: Deposit a composite passivation layer on the surface of the device after the gate fabrication is completed. The composite passivation layer consists of a SiO2 sacrificial layer and a SiN passivation layer from bottom to top. Step 6: Define a metal interconnect via pattern on the composite passivation layer above the source and drain, and etch the metal interconnect via through the composite passivation layer using a dry etching process. Step 7: A photoresist protective layer is formed on the outer region of the metal interconnect via using photolithography. Using the metal interconnect via as an etching window, a wet etching process is used to remove all the SiO2 sacrificial layer below the SiN passivation layer, forming an air cavity in the region between the gate and the source, and between the gate and the drain. Step 8: Define the metal interconnect pattern on the composite passivation layer, evaporate metal to form the metal interconnect, and complete the device fabrication.
2. The method for fabricating a GaN HEMT structure with an air cavity according to claim 1, characterized in that, In step 2, the dry etching process uses BCl3+Cl2 etching gas, and the etching depth at least penetrates the epitaxial layer to form an isolation platform; the ion implantation process uses Ar... + Ion implantation enables device isolation.
3. The method for fabricating a GaN HEMT structure with an air cavity according to claim 1, characterized in that, In step 3, the source / drain metal adopts a Ti / Al / Ni / Au stacked structure, and the high-temperature tempering temperature is 850~930℃.
4. The method for fabricating a GaN HEMT structure with an air cavity according to claim 1, characterized in that, In step 4, the gate metal is a Ni / Au stack or a Ti / Pt / Au stack, and the total thickness of the gate metal is 4500~6000 Å.
5. The method for fabricating a GaN HEMT structure with an air cavity according to claim 4, characterized in that, When the gate metal uses a Ni / Au stack, the Ni layer thickness is 500 Å and the Au layer thickness is 4500 Å; when the gate metal uses a Ti / Pt / Au stack, the Ti layer thickness is 300 Å, the Pt layer thickness is 400 Å and the Au layer thickness is 4300 Å.
6. The method for fabricating a GaN HEMT structure with an air cavity according to claim 1, characterized in that, In step 7, the wet etching process uses HF solution or BOE solution, and the etching temperature is 25°C (room temperature).
7. The method for fabricating a GaN HEMT structure with an air cavity according to claim 1, characterized in that, In step 1, the substrate is any one of Si substrate, GaN substrate, SiC substrate, Al2O3 substrate or diamond substrate.
8. The method for fabricating a GaN HEMT structure with an air cavity according to claim 1, characterized in that, In step 1, the thickness of the buffer layer is 3~5μm, the thickness of the GaN channel layer is 200~300μm, the thickness of the AlGaN barrier layer is 15~25μm, and the thickness of the cap layer is 3~5μm.
9. A GaN HEMT structure with an air cavity, prepared by the method according to any one of claims 1-8, characterized in that, It includes a substrate, epitaxial layer, source, drain, gate, composite passivation layer, and air cavity; The epitaxial layers are stacked sequentially from bottom to top on the upper surface of the substrate, and the epitaxial layers include a buffer layer, a GaN channel layer, an AlGaN barrier layer, and a cap layer. The source, drain, and gate are all disposed on the upper surface of the cap layer, and the gate is located between the source and the drain; The composite passivation layer covers the active region surfaces of the source, drain, gate, and cap layer, and the composite passivation layer includes a bottom SiO2 sacrificial layer and a top SiN passivation layer. Both the source and the drain are provided with metal interconnect vias that penetrate the composite passivation layer, and the metal interconnect vias are electrically connected to the source and the drain, respectively. In the active region between the gate and the source, and between the gate and the drain, the bottom SiO2 sacrificial layer of the composite passivation layer is completely removed to form the air cavity; The air cavity has the SiN passivation layer as the top cover and the upper surface of the cap layer as the bottom wall. The bottom SiO2 sacrificial layer of the composite passivation layer is only retained on the outside of the active region, forming the lateral support structure of the air cavity. The interior of the air cavity is filled with air medium.
10. A GaN HEMT structure with an air cavity according to claim 1, characterized in that, The composite passivation layer also includes a gate passivation layer deposited after the gate is fabricated. The gate passivation layer is a SiO2 dielectric layer. The gate passivation layer covers the gate and the surface of the active region. The bottom SiO2 sacrificial layer and the top SiN passivation layer are deposited sequentially on top of the gate passivation layer.