Trench mosfet device with low on-resistance and method of making the same
By employing heavily doped substrates and epitaxial layer structures in trench MOSFET devices, combined with high-energy ion implantation and high-temperature annealing techniques, a wrapped buried layer structure is formed, solving the trade-off between on-resistance and breakdown voltage. This achieves MOSFET devices with low on-resistance and high breakdown voltage, reducing manufacturing complexity and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI SHANGJIA SEMICON CO LTD
- Filing Date
- 2025-09-09
- Publication Date
- 2026-05-12
AI Technical Summary
Existing technologies reduce the on-resistance of trench MOSFET devices while simultaneously reducing the breakdown voltage, but the manufacturing process is complex and costly.
A trench MOSFET device with low on-resistance is formed by using a heavily doped first conductivity type substrate and epitaxial layer structure, combined with a three-stage high-energy ion implantation process to form a wrapped first and second conductivity type buried layer, optimizing the connection structure of the gate and source, and activating the doped atoms through high-temperature annealing.
While reducing on-resistance, the breakdown voltage is maintained, and costs are controlled. This improves the device's withstand voltage reliability and on-resistance, and simplifies the manufacturing process.
Smart Images
Figure CN121078772B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor power devices, specifically a trench MOSFET device with low on-resistance and its fabrication method. Background Technology
[0002] With the development of new energy vehicles, industrial robots, and artificial intelligence, China's power semiconductor devices are also experiencing rapid development in various application fields. MOSFET devices are one type of power semiconductor device.
[0003] With increasingly higher integration levels in devices, power consumption has become a key focus in power semiconductor devices, and the most effective way to reduce power consumption is to reduce the on-resistance of the device. Researchers have made many efforts to reduce the on-resistance of trench MOSFET devices. The first approach is to optimize device parameters, thereby optimizing on-resistance. For example, Zhang Li et al. studied the optimal on-resistance values for devices under different voltage ratings, focusing on the impact of trench width and trench spacing on on-resistance. Experimental results show that the on-resistance of high-voltage trench MOSFETs is much closer to the ideal value than that of low-voltage MOSFETs. The second approach is to optimize the device structure, thereby optimizing on-resistance. For example, Zhang Yue et al. proposed an improved superjunction UMOS, which reduces on-resistance by introducing P-pillars with varying doping concentrations. Other researchers have proposed a UMOS structure with a floating P-type region, which can effectively reduce the on-resistance of the device. Both of these structures sacrifice some breakdown voltage.
[0004] These methods can effectively reduce the on-resistance of the device, but the breakdown voltage also decreases simultaneously, ultimately requiring a compromise between the two. Currently, there are also products such as superjunction MOSFETs and split-gate MOSFETs, which reduce the on-resistance and power consumption of the device. However, superjunction MOSFETs and split-gate MOSFETs are more expensive than UMOS because their manufacturing processes are more complex. Summary of the Invention
[0005] To address at least one technical problem in the prior art, embodiments of the present invention provide a trench MOSFET device with low on-resistance and its fabrication method, which reduces on-resistance without decreasing breakdown voltage and without significantly increasing cost. To achieve the above technical objectives, the technical solution adopted by embodiments of the present invention is as follows:
[0006] In a first aspect, embodiments of the present invention provide a trench MOSFET device with low on-resistance, including an active region and a termination protection zone disposed around the active region; the trench MOSFET device with low on-resistance includes a heavily doped first conductivity type substrate, and a first conductivity type epitaxial layer is disposed on the first conductivity type substrate; the surface of the first conductivity type epitaxial layer facing away from the first conductivity type substrate is a first main surface, and the surface of the first conductivity type substrate facing away from the first conductivity type epitaxial layer is a second main surface;
[0007] In the active region, a single-cell trench is provided in the first conductivity type epitaxial layer; the single-cell trenches are arranged in parallel with each other at intervals, and a second conductivity type well region and a first conductivity type injection layer are provided from bottom to top on the top of the first conductivity type epitaxial layer between adjacent single-cell trenches; the single-cell trenches extend from the first main surface into the second conductivity type well region; a gate oxide layer is provided on the inner wall of the single-cell trench; a gate polysilicon is provided in the single-cell trench, and the gate polysilicon is insulated from the first conductivity type injection layer, the second conductivity type well region and the first conductivity type epitaxial layer through the gate oxide layer;
[0008] A first conductive type buried layer in the shape of a bowl, which encloses the U-shaped bottom of the unit cell trench, is formed below the bottom of the unit cell trench; a second conductive type buried layer in the shape of a bowl, which encloses the U-shaped bottom of the unit cell trench, is formed in the first conductive type buried layer below the bottom of the unit cell trench.
[0009] The injection dose of the second conductivity type impurity used to form the second conductivity type buried layer is higher than the injection dose of the first conductivity type impurity used to form the first conductivity type buried layer.
[0010] An insulating dielectric layer is provided above the first main surface, and a source metal and a gate metal are provided above the insulating dielectric layer; the source metal is connected to the first conductivity type injection layer and the second conductivity type well region between adjacent unit cell trenches through a source contact hole that penetrates the insulating dielectric layer and the first conductivity type injection layer; the gate metal is connected to the gate polysilicon in the unit cell trench through a gate contact hole that penetrates the insulating dielectric layer.
[0011] A drain metal is provided on the second main surface.
[0012] Furthermore, the first conductivity type impurity used to form the first conductivity type buried layer is phosphorus, and the injection dosage is: 4E14cm-2 to 7E14cm-2.
[0013] Furthermore, the width of the buried layer of the first conductivity type is 1.3 to 1.8 times the width of the unit cell trench.
[0014] Furthermore, the second conductivity type impurity used to form the second conductivity type buried layer is boron, and the implantation dose is: 8E15cm-2~9E15cm-2.
[0015] Furthermore, the width of the buried layer of the second conductive type is 1 to 1.2 times the width of the unit cell trench.
[0016] Secondly, embodiments of the present invention provide a method for fabricating a trench MOSFET device with low on-resistance, used to fabricate the trench MOSFET device with low on-resistance as described above, comprising the following steps:
[0017] Step S1: Provide a heavily doped first conductivity type substrate, and grow a first conductivity type epitaxial layer on the first conductivity type substrate; the surface of the first conductivity type epitaxial layer facing away from the first conductivity type substrate is the first main surface, and the surface of the first conductivity type substrate facing away from the first conductivity type epitaxial layer is the second main surface;
[0018] Step S2: Deposit a hard mask layer on the first main surface, apply photoresist on the hard mask layer, form a photoresist trench pattern by photolithography, then etch the hard mask layer to form a hard mask; then use the hard mask as a barrier layer to etch a first conductivity type epitaxial layer to form a single cell trench; deposit or grow a sacrificial oxide layer on the inner wall of the single cell trench.
[0019] Step S3: Using a hard mask as a barrier layer, a first type of conductive impurity is injected into the bottom of the unit cell trench through a three-stage high-energy ion implantation process, forming a bowl-shaped first type of conductive buried layer that wraps around the U-shaped bottom of the unit cell trench.
[0020] The first high-energy ion implantation process had an implantation angle of -14° to -16°, forming the upper left portion of the first conductivity type buried layer.
[0021] The second high-energy ion implantation process has an implantation angle of 0°, forming the middle part of the first conductivity type buried layer.
[0022] The implantation angle of the third high-energy ion implantation process is 14° to 16°, forming the upper right part of the first conductivity type buried layer;
[0023] Step S4: Using a hard mask as a barrier layer, a second type of conductive impurity is injected into the bottom of the unit cell trench, forming a bowl-shaped second type of conductive buried layer that encloses the U-shaped bottom of the unit cell trench in the first type of conductive buried layer below the bottom of the unit cell trench; then high-temperature annealing is performed.
[0024] Step S5: Remove the hard mask by etching, and then remove the sacrificial oxide layer by wet etching; deposit or grow the gate oxide layer on the inner wall of the single-cell trench;
[0025] Step S6: Conductive polysilicon is deposited on the first main surface, and polysilicon is etched back using dry etching and chemical mechanical polishing processes to form gate polysilicon in the unit cell trench.
[0026] Step S7: Inject a second type of conductivity impurity into the first main surface and push it into a well to form a second type of conductivity well region on top of the first type of conductivity epitaxial layer; then selectively inject a first type of conductivity impurity and anneal to form a first type of conductivity implantation layer on top of the first type of conductivity epitaxial layer between adjacent unit cell trenches.
[0027] Step S8: Deposit an insulating dielectric layer on the first main surface and reflow it to flatten the surface;
[0028] Step S9: Selectively etch the insulating dielectric layer and the epitaxial layer of the first conductivity type to form gate contact holes and source contact holes;
[0029] Step S10: Inject impurities of a second conductivity type into the bottom of the gate contact hole and the source contact hole and perform high-temperature rapid annealing;
[0030] A thin film of titanium metal and titanium nitride is deposited on the inner wall of the gate contact hole and the source contact hole, and reacted with silicon to generate low-resistivity titanium silicide. Then, each contact hole is filled with tungsten metal.
[0031] Step S11: Deposit metal on the first main surface and selectively etch it to form source metal and gate metal;
[0032] The source metal is connected to the first conductivity type injection layer and the second conductivity type well region between adjacent unit cell trenches through a source contact hole that penetrates the insulating dielectric layer and the first conductivity type injection layer.
[0033] The gate metal is connected to the gate polysilicon in the unit cell trench through a gate contact hole that penetrates the insulating dielectric layer.
[0034] Step S12: Perform back-side thinning process on the second main surface, and then deposit drain metal.
[0035] Further, in step S3, the first conductivity type impurity used to form the first conductivity type buried layer is phosphorus, and the injection dose is: 4E14cm-2 to 7E14cm-2.
[0036] Furthermore, in step S3, the width of the first conductive type buried layer is 1.3 to 1.8 times the width of the unit cell trench.
[0037] Further, in step S4, the second conductivity type impurity used to form the second conductivity type buried layer is boron, and the implantation dose is: 8E15cm-2~9E15cm-2.
[0038] Furthermore, in step S4, the width of the second conductive type buried layer is 1 to 1.2 times the width of the unit cell trench.
[0039] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows:
[0040] 1) It can reduce the on-resistance without decreasing the breakdown voltage.
[0041] 2) While controlling costs, it can improve the withstand voltage reliability of devices and reduce the on-resistance of devices. Attached Figure Description
[0042] Figure 1 This is a schematic diagram of the growth of an epitaxial layer of the first conductivity type in an embodiment of the present invention.
[0043] Figure 2 This is a schematic diagram of etching a first conductivity type epitaxial layer to form a single-cell trench in an embodiment of the present invention.
[0044] Figure 3 This is a schematic diagram of the injection formation of a first conductive type buried layer in an embodiment of the present invention.
[0045] Figure 4 This is a schematic diagram of the implantation to form a second conductive type buried layer in an embodiment of the present invention.
[0046] Figure 5 This is a schematic diagram of the deposition or growth of the gate oxide layer in an embodiment of the present invention.
[0047] Figure 6 This is a schematic diagram of forming a gate polysilicon in an embodiment of the present invention.
[0048] Figure 7 This is a schematic diagram of the injection formation of a second conductivity type well region and a first conductivity type injection layer in an embodiment of the present invention.
[0049] Figure 8 This is a schematic diagram of the deposited insulating dielectric layer in an embodiment of the present invention.
[0050] Figure 9 This is a schematic diagram of etching to form gate contact holes and source contact holes in an embodiment of the present invention.
[0051] Figure 10 This is a schematic diagram illustrating the fabrication of the source metal and gate metal in an embodiment of the present invention. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0053] In the description of the embodiments of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0054] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.
[0055] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0056] In the following embodiments, the first conductivity type is N-type and the second conductivity type is P-type;
[0057] Embodiment 1 of the present invention proposes a trench MOSFET device with low on-resistance, including an active region and a termination protection zone surrounding the active region; the trench MOSFET device with low on-resistance includes a heavily doped first conductivity type substrate 1, on which a first conductivity type epitaxial layer 2 is provided; the surface of the first conductivity type epitaxial layer 2 facing away from the first conductivity type substrate 1 is a first main surface, and the surface of the first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2 is a second main surface;
[0058] In the active region, a unit cell trench 4 is provided in the first conductivity type epitaxial layer 2; each unit cell trench 4 is arranged in parallel at intervals, and a second conductivity type well region 9 and a first conductivity type injection layer 10 are provided from bottom to top on the top of the first conductivity type epitaxial layer 2 between adjacent unit cell trenches 4; the unit cell trench 4 extends from the first main surface into the second conductivity type well region 9; a gate oxide layer 7 is provided on the inner wall of the unit cell trench 4; a gate polysilicon 801 is provided in the unit cell trench 4, and the gate polysilicon 801 is insulated from the first conductivity type injection layer 10, the second conductivity type well region 9 and the first conductivity type epitaxial layer 2 through the gate oxide layer 7;
[0059] A first conductive type buried layer 5, which is bowl-shaped and encloses the U-shaped bottom of the unit cell trench 4, is formed below the bottom of the unit cell trench 4; a second conductive type buried layer 6, which is bowl-shaped and encloses the U-shaped bottom of the unit cell trench, is formed in the first conductive type buried layer 5 below the bottom of the unit cell trench 4.
[0060] The injection dose of the second conductivity type impurity used to form the second conductivity type buried layer 6 is higher than the injection dose of the first conductivity type impurity used to form the first conductivity type buried layer 5.
[0061] An insulating dielectric layer 11 is provided above the first main surface, and a source metal 13 and a gate metal are provided above the insulating dielectric layer 11. The source metal 13 is connected to the first conductivity type injection layer 10 and the second conductivity type well region 9 between adjacent unit cell trenches 4 through a source contact hole 1201 that penetrates the insulating dielectric layer 11 and the first conductivity type injection layer 10. The gate metal is connected to the gate polysilicon 801 in the unit cell trench 4 through a gate contact hole that penetrates the insulating dielectric layer 11.
[0062] Specifically, the first conductivity type impurity used to form the first conductivity type buried layer 5 is phosphorus, and the injection dosage is: 4E14cm-2 to 7E14cm-2.
[0063] Specifically, the width of the first conductive type buried layer 5 is 1.3 to 1.8 times the width of the unit cell trench 4.
[0064] Specifically, the second conductivity type impurity used to form the second conductivity type buried layer 6 is boron, and the implantation dose is: 8E15cm-2 to 9E15cm-2.
[0065] The second conductive buried layer 6 can reduce the breakdown voltage drop and hot electron instability caused by the enhanced electric field at the bottom corner of the unit cell trench, effectively protecting the bottom of the unit cell trench. The first conductive buried layer 5 is used to increase the current density when the device is turned on, thereby reducing the on-resistance of the device. It can improve the withstand voltage reliability of the device and reduce the on-resistance of the device while controlling the cost. The first conductive buried layer 5 formed below the bottom of the unit cell trench 4 wraps the buried layer structure of the second conductive buried layer 6, which reduces the on-resistance and ensures that the breakdown voltage does not drop, and the cost does not increase significantly.
[0066] Specifically, the width of the second conductive type buried layer 6 is 1 to 1.2 times the width of the unit cell trench 4.
[0067] Embodiment 2 of the present invention proposes a method for fabricating a trench MOSFET device with low on-resistance, comprising the following steps:
[0068] Step S1, as follows Figure 1As shown, a heavily doped first conductivity type substrate 1 is provided, and a first conductivity type epitaxial layer 2 is grown on the first conductivity type substrate 1; the surface of the first conductivity type epitaxial layer 2 facing away from the first conductivity type substrate 1 is a first main surface, and the surface of the first conductivity type substrate 1 facing away from the first conductivity type epitaxial layer 2 is a second main surface;
[0069] The first conductivity type substrate 1 is a silicon substrate;
[0070] Step S2, as follows Figure 2 As shown, a hard mask layer is deposited on the first main surface, photoresist is coated on the hard mask layer, and a photoresist trench pattern is formed by photolithography using a photomask. Then, the hard mask layer is etched to form a hard mask 3. The hard mask 3 is then used as a barrier layer to etch a first conductivity type epitaxial layer 2 to form a unit cell trench 4. A sacrificial oxide layer (not shown in the figure) is deposited or grown on the inner wall of the unit cell trench 4.
[0071] Sacrificial oxide layers can repair damage during trench etching and protect the silicon substrate from contamination or damage during ion implantation.
[0072] Step S3, as follows Figure 3 As shown, a hard mask 3 is used as a barrier layer. A first type of conductive impurity is injected into the bottom of the unit cell trench 4 through a three-stage high-energy ion implantation process. A bowl-shaped first type of conductive buried layer 5 is formed below the bottom of the unit cell trench 4, which encloses the U-shaped bottom of the unit cell trench.
[0073] The implantation angle of the first high-energy ion implantation process is -14° to -16°, preferably -15°; forming the upper left portion of the first conductivity type buried layer 5;
[0074] The second high-energy ion implantation process has an implantation angle of 0°, forming the middle part of the first conductivity type buried layer 5.
[0075] The implantation angle of the third high-energy ion implantation process is 14° to 16°, preferably 15°; forming the upper right part of the first conductivity type buried layer 5;
[0076] To form a bowl-shaped buried layer 5 of the first conductive type that encloses the U-shaped bottom of the unit cell trench, conventional ion implantation cannot achieve the required bowl-shaped enclosed region, and the ion implantation well depth is also insufficient. In this embodiment, the bowl-shaped buried layer 5 of the first conductive type is formed by three high-energy ion implantations at different angles. Figure 3 The arrows in the image indicate the implantation angles of the three high-energy ion implantation processes;
[0077] The first type of conductive impurity uses phosphorus. Phosphorus is relatively light and can achieve a larger average projected range, forming a deep trap.
[0078] The implantation dose of impurities of the first conductivity type is: 4E14cm-2 to 7E14cm-2;
[0079] The width of the first conductive type buried layer 5 is 1.3 to 1.8 times the width of the unit cell trench 4; for example, 1.6 times.
[0080] Step S4, as follows Figure 4 As shown, a hard mask 3 is used as a barrier layer, and a second type of conductive impurity is injected into the bottom of the unit cell trench 4. A bowl-shaped second type of conductive buried layer 6 is formed in the first type of conductive buried layer 5 below the bottom of the unit cell trench 4, which encloses the U-shaped bottom of the unit cell trench. Then, high-temperature annealing is performed.
[0081] The second type of conductivity impurity is boron; high-temperature annealing can repair lattice damage caused by ion implantation and activate doped atoms to become electroactive charge carriers.
[0082] The implantation dose of the second type of conductivity impurity is 8E15cm-2 to 9E15cm-2; the implantation dose of the second type of conductivity impurity is much higher than that of the first type of conductivity impurity, so as to achieve the inversion of the conductive material.
[0083] The width of the second conductive type buried layer 6 is 1 to 1.2 times the width of the unit cell trench 4; for example, 1.1 times.
[0084] Step S5, as follows Figure 5 As shown, the hard mask 4 is removed by etching, and the sacrificial oxide layer is removed by wet etching; the gate oxide layer 7 is deposited or grown on the inner wall of the unit cell trench 4.
[0085] Step S6, as follows Figure 6 As shown, conductive polysilicon 8 is deposited on the first main surface, and polysilicon is etched back using dry etching and chemical mechanical polishing processes to form gate polysilicon 801 in the unit cell trench 4.
[0086] Step S7, as follows Figure 7 As shown, a second conductivity type impurity is implanted into the first main surface and pushed into a well, forming a second conductivity type well region 9 on the top of the first conductivity type epitaxial layer 2; then, a first conductivity type impurity is selectively implanted and annealed, forming a first conductivity type implantation layer 10 on the top of the first conductivity type epitaxial layer 2 between adjacent unit cell trenches 4.
[0087] Before implanting impurities of the first conductivity type, photoresist needs to be applied to the first main surface, and a photoresist pattern is formed by photomask etching to achieve selective implantation.
[0088] Step S8, as follows Figure 8 As shown, an insulating dielectric layer 11 is deposited on the first main surface and reflowed to make the surface flat;
[0089] Step S9, as follows Figure 9As shown, the insulating dielectric layer 11 and the first conductivity type epitaxial layer 2 are selectively etched to form gate contact holes and source contact holes 1201;
[0090] This step requires first coating the insulating dielectric layer 11 with photoresist, and then forming the photoresist contact hole pattern by photomask etching to achieve selective etching;
[0091] Figure 9 The gate contact hole is not shown in the drawing.
[0092] Step S10: Impurities of a second conductivity type are injected into the bottom of the gate contact hole and the source contact hole 1201 and subjected to high-temperature rapid annealing.
[0093] A thin film of titanium metal and titanium nitride is deposited on the inner wall of the gate contact hole and the source contact hole 1201 and reacted with silicon to generate low-resistance titanium silicide. Then, each contact hole is filled with tungsten metal to improve the contact resistance.
[0094] Step S11, as follows Figure 10 As shown, metal is deposited on the first main surface and selectively etched to form source metal 13 and gate metal;
[0095] The source metal 13 is connected to the first conductive type injection layer 10 and the second conductive type well region 9 between adjacent unit cell trenches 4 through the source contact hole 1201 that penetrates the insulating dielectric layer 11 and the first conductive type injection layer 10.
[0096] The gate metal is connected to the gate polysilicon 801 in the unit cell trench 4 through a gate contact hole that penetrates the insulating dielectric layer 11.
[0097] The connection method between the gate metal and the gate polysilicon is relatively mature. For example, a gate lead-out trench is set around the unit cell trench 4, and a gate polysilicon is also set in the gate lead-out trench. The gate polysilicon in the gate lead-out trench is connected to the gate polysilicon in the unit cell trench. The gate metal is connected to the gate polysilicon in the gate lead-out trench through the gate contact hole that penetrates the insulating dielectric layer 11, thereby connecting the gate polysilicon in the unit cell trench 4.
[0098] Step S12: Perform back-side thinning process on the second main surface, and then deposit drain metal.
[0099] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A trench MOSFET device with low on-resistance, comprising an active region and a termination protection zone surrounding the active region; the trench MOSFET device with low on-resistance includes a heavily doped first conductivity type substrate (1), on which a first conductivity type epitaxial layer (2) is disposed; the surface of the first conductivity type epitaxial layer (2) facing away from the first conductivity type substrate (1) is a first main surface, and the surface of the first conductivity type substrate (1) facing away from the first conductivity type epitaxial layer (2) is a second main surface; characterized in that, In the active region, a single-cell trench (4) is provided in the first conductivity type epitaxial layer (2); each single-cell trench (4) is arranged in parallel at intervals, and a second conductivity type well region (9) and a first conductivity type injection layer (10) are provided from bottom to top on the top of the first conductivity type epitaxial layer (2) between adjacent single-cell trenches (4); the single-cell trench (4) extends from the first main surface into the second conductivity type well region (9); a gate oxide layer (7) is provided on the inner wall of the single-cell trench (4); a gate polysilicon (801) is provided in the single-cell trench (4), and the gate polysilicon (801) is insulated from the first conductivity type injection layer (10), the second conductivity type well region (9) and the first conductivity type epitaxial layer (2) through the gate oxide layer (7); A first conductive type buried layer (5) in the shape of a bowl covering the U-shaped bottom of the unit cell trench (4) is formed below the bottom of the unit cell trench (4); a second conductive type buried layer (6) in the shape of a bowl covering the U-shaped bottom of the unit cell trench is formed in the first conductive type buried layer (5) below the bottom of the unit cell trench (4); The injection dose of the second conductive type impurity used to form the second conductive type buried layer (6) is higher than the injection dose of the first conductive type impurity used to form the first conductive type buried layer (5); An insulating dielectric layer (11) is provided above the first main surface, and a source metal (13) and a gate metal are provided above the insulating dielectric layer (11); the source metal (13) is connected to the first conductivity type injection layer (10) and the second conductivity type well region (9) between adjacent unit cell trenches (4) through a source contact hole (1201) penetrating the insulating dielectric layer (11) and the first conductivity type injection layer (10); the gate metal is connected to the gate polysilicon (801) in the unit cell trench (4) through a gate contact hole penetrating the insulating dielectric layer (11); A drain metal is provided on the second main surface; The first conductivity type impurity used to form the first conductivity type buried layer (5) is phosphorus, and the injection dose is: 4E14cm-2~7E14cm-2; The second conductivity type impurity used to form the second conductivity type buried layer (6) is boron, and the implantation dose is: 8E15cm-2~9E15cm-2.
2. The trench MOSFET device with low on-resistance as described in claim 1, characterized in that, The width of the first conductive type buried layer (5) is 1.3 to 1.8 times the width of the unit cell trench (4).
3. The trench MOSFET device with low on-resistance as described in claim 1, characterized in that, The width of the second conductive type buried layer (6) is 1 to 1.2 times the width of the unit cell trench (4).
4. A method for fabricating a trench MOSFET device with low on-resistance, used to fabricate a trench MOSFET device with low on-resistance as described in any one of claims 1 to 3, characterized in that, Includes the following steps: Step S1: Provide a heavily doped first conductivity type substrate (1), and grow a first conductivity type epitaxial layer (2) on the first conductivity type substrate (1); the surface of the first conductivity type epitaxial layer (2) facing away from the first conductivity type substrate (1) is the first main surface, and the surface of the first conductivity type substrate (1) facing away from the first conductivity type epitaxial layer (2) is the second main surface; Step S2: Deposit a hard mask layer on the first main surface, apply photoresist on the hard mask layer, form a photoresist trench pattern by photolithography, and then etch the hard mask layer to form a hard mask (3); then use the hard mask (3) as a barrier layer to etch the first conductivity type epitaxial layer (2) to form a single cell trench (4); deposit or grow a sacrificial oxide layer on the inner wall of the single cell trench (4); Step S3: Using a hard mask (3) as a barrier layer, a first type of conductive impurity is injected into the bottom of the unit cell trench (4) through a three-stage high-energy ion implantation process, forming a bowl-shaped first type of conductive buried layer (5) that wraps around the U-shaped bottom of the unit cell trench (4) below the bottom of the unit cell trench (4). The implantation angle of the first high-energy ion implantation process is -14° to -16°; forming the upper left part of the first conductivity type buried layer (5); The implantation angle of the second high-energy ion implantation process is 0°; forming the middle part of the first conductive type buried layer (5); The implantation angle of the third high-energy ion implantation process is 14° to 16°; forming the upper right part of the first conductivity type buried layer (5); Step S4: Using a hard mask (3) as a barrier layer, a second type of conductive impurity is injected into the bottom of the unit cell trench (4), and a bowl-shaped second type of conductive buried layer (6) is formed in the first type of conductive buried layer (5) below the bottom of the unit cell trench (4) to enclose the U-shaped bottom of the unit cell trench; then high-temperature annealing is performed. Step S5: Remove the hard mask by etching process, and then remove the sacrificial oxide layer by wet etching; deposit or grow the gate oxide layer (7) on the inner wall of the single cell trench (4); Step S6: Conductive polysilicon is deposited on the first main surface, and polysilicon is etched back using dry etching and chemical mechanical polishing processes to form gate polysilicon (801) in the unit cell trench (4); Step S7: Inject a second type of conductivity impurity into the first main surface and push it into a well, forming a second type of conductivity well region (9) on top of the first type of conductivity epitaxial layer (2); Then, a first conductivity type impurity is selectively implanted and annealed to form a first conductivity type implanted layer (10) on top of the first conductivity type epitaxial layer (2) between adjacent unit cell trenches (4); Step S8: Deposit an insulating dielectric layer (11) on the first main surface and reflow to flatten the surface; Step S9: Selectively etch the insulating dielectric layer (11) and the first conductivity type epitaxial layer (2) to form gate contact holes and source contact holes (1201); Step S10: Impurities of a second conductivity type are implanted at the bottom of the gate contact hole and the source contact hole (1201) and subjected to high-temperature rapid annealing; A thin film of titanium metal and titanium nitride is deposited on the inner wall of the gate contact hole and the source contact hole (1201) and reacted with silicon to generate low-resistivity titanium silicide. Then, each contact hole is filled with tungsten metal. Step S11: Deposit metal on the first main surface and selectively etch it to form source metal (13) and gate metal; The source metal (13) is connected to the first conductive type injection layer (10) and the second conductive type well region (9) between adjacent unit cell trenches (4) through a source contact hole (1201) that penetrates the insulating dielectric layer (11) and the first conductive type injection layer (10); The gate metal is connected to the gate polysilicon (801) in the unit cell trench (4) through a gate contact hole that penetrates the insulating dielectric layer (11); Step S12: Perform back-side thinning process on the second main surface, and then deposit drain metal; In step S3, the first conductive type impurity used to form the first conductive type buried layer (5) is phosphorus, and the injection dose is: 4E14cm-2~7E14cm-2; In step S4, the second conductive type impurity used to form the second conductive type buried layer (6) is boron, and the implantation dose is: 8E15cm-2~9E15cm-2.
5. The method for fabricating a trench MOSFET device with low on-resistance as described in claim 4, characterized in that, In step S3, the width of the first conductive type buried layer (5) is 1.3 to 1.8 times the width of the unit cell trench (4).
6. The method for fabricating a trench MOSFET device with low on-resistance as described in claim 4, characterized in that, In step S4, the width of the second conductive type buried layer (6) is 1 to 1.2 times the width of the unit cell trench (4).