A memory and electronic device

Abstract

A memory and an electronic device, the memory comprising a first memory chip (1) and a logic chip (2) stacked and electrically connected, the first memory chip (1) comprising a first memory cell array. The memory cell array comprises a plurality of transistors (111), a plurality of bit lines (113) and a plurality of word lines (112), the word lines (112) being coupled to the bit lines (113) and the transistors (111). The logic chip (2) comprises a differential amplifier (21), a word line driver and a reference voltage source (25), all of which are electrically connected to the first memory cell array. The differential amplifier (21) comprises a first differential input terminal (211), a second differential input terminal (212) and an output terminal (213). The first differential input terminal (211) is electrically connected to the bit line (113) of the first memory cell array, and the second differential input terminal (212) is electrically connected to the reference voltage source (25). Then the differential amplifier (21) performs differential processing on the reference voltage of the reference voltage source (25) and the signal of the bit line (113).

Description

Technical Field

[0001] This application relates to the field of information technology, and more particularly to a memory and electronic device. Background Technology

[0002] In existing computing systems, Dynamic Random Access Memory (DRAM) serves as main memory, used to temporarily store data processed by the Central Processing Unit (CPU) and data exchanged with external storage devices such as hard drives. Memory performance is typically described using sequential read / write bandwidth and read / write operations per second (IOPS). While DRAM interface performance has gradually improved with technological advancements, the performance of the internal memory array has progressed slowly. Currently, the bottleneck in memory performance lies in the internal memory array, and a significant issue with this array is high latency, which is the shortest time interval between two consecutive activations.

[0003] The high latency of existing memory is mainly due to two factors. First, memory chips consist of a memory cell array and logic circuits. To increase the storage capacity, the area of ​​the memory cell array needs to be increased while the area of ​​the logic circuits needs to be reduced. Therefore, the size of the memory cell array is designed to be relatively large, typically reaching 512 rows x 1024 columns, which includes 512 word lines and 1024 bit lines. Both word lines and bit lines are relatively long, connecting a large number of transistors. Each word line activates multiple transistors, the data transmission path via bit lines is long, and the parasitic capacitance of the bit lines is large, all contributing to the high latency of the memory. Summary of the Invention

[0004] This application provides a memory and an electronic device to expand the storage capacity of the memory, reduce the latency of the memory, simplify the memory structure, and reduce the cost.

[0005] In a first aspect, this application provides a memory comprising a first memory chip and a logic chip stacked and electrically connected, wherein the first memory chip includes a plurality of first memory cell arrays. The memory cell array includes a plurality of transistors, a plurality of bit lines, and a plurality of word lines, each transistor being connected to both a bit line and a word line. Specifically, in a first memory cell array, a plurality of transistor arrays are arranged, with one of the aforementioned transistors connected between any word line and any bit line. The logic chip includes a differential amplifier and an interface control circuit, both of which are electrically connected to the first memory cell array. The differential amplifier includes a first differential input terminal, a second differential input terminal, and an output terminal. The first differential input terminal and the second differential input terminal form a set of differential input terminals, meaning the differential amplifier differentially amplifies the signal input from the first differential input terminal and the signal input from the second differential input terminal. The interface control circuit also includes a reference voltage source. The first differential input terminal of the differential amplifier is electrically connected to the first memory cell array, specifically to the bit line of the first memory cell array. The second differential input terminal is electrically connected to the reference voltage source of the logic chip. The differential amplifier differentially amplifies the reference voltage of the reference voltage source and the signal of the bit line.

[0006] In this application's technical solution, the differential amplifier is located on the logic chip, thus not occupying the area of ​​the first memory chip and expanding the memory capacity. Stacking the first memory chip and the logic chip shortens the connection line length between the first memory cell array and the differential amplifier, thereby reducing latency. With the peripheral control circuitry located on the logic chip and the storage section on the first memory chip, more advanced technologies can be used to fabricate the logic chip and the first memory chip separately, improving the transistor density and speed of the memory. This solution also utilizes a reference voltage source to input a reference voltage to the differential amplifier, simplifying the memory structure, reducing the area occupied by the connection line between the differential amplifier and the first memory chip, and lowering costs.

[0007] To reduce costs and shrink the area of ​​the logic chip, the memory in this application may further include a bit line multiplexer (BML). This BML has multiple input ports and one output port. One end of the input port is connected to the bit lines of the first memory cell array, and the other end of the output port is connected to the differential amplifier. This BML can connect to multiple bit lines. In practical applications, the BML selects one bit line from the multiple bit lines and outputs it to the differential amplifier from the output port, according to requirements. This solution can reduce the number of differential amplifiers in the memory, reduce the area occupied by the differential amplifiers, and also reduce costs.

[0008] When specifically configuring the bit line multiplexer, it can be located on the first memory chip. Since the number of connections between the multiplexer and the bit lines on the first memory chip is relatively large, while the number of connections to the differential amplifier on the logic chip is relatively small, this approach can reduce the number of connection lines between the first memory chip and the logic chip, thereby reducing the area occupied by the connection lines, simplifying the manufacturing process, and improving the reliability of the connection between the first memory chip and the logic chip.

[0009] In a further technical solution, the logic chip further includes a word line driver, which is connected to the word lines of the first memory chip. The word line driver provides gate voltage to the transistors on the word lines, controlling the opening and closing of the memory cells on the word lines. In this solution, the word line driver of the memory is located on the logic chip and does not occupy the area of ​​the first memory chip, which is beneficial to increasing the number of first memory cell arrays of the first memory chip and expanding the storage capacity of the memory.

[0010] To reduce costs and shrink the area of ​​the logic chip, the memory in this application may further include a word line multiplexer (BLL). This BLL has multiple output ports and one input port. One end of the output port of the BLL is connected to a word line of the first memory cell array, and the input port is connected to a word line driver. This BLL can connect multiple word lines. In practical applications, the BLL selects one word line from the multiple word lines to connect to the word line driver, depending on the requirements. This solution can reduce the number of word line drivers in the memory, reduce the area occupied by the word line drivers, and also reduce costs.

[0011] When specifically configuring the aforementioned word line multiplexer, it can be located on the first memory chip. Since the multiplexer has a large number of connections to the word lines on the first memory chip and a small number of connections to the word line drivers on the logic chip, this approach reduces the number of connection lines between the first memory chip and the logic chip, thereby reducing the area occupied by the connection lines, simplifying the manufacturing process, and improving the reliability of the connection between the first memory chip and the logic chip.

[0012] In a specific embodiment of this application, the memory may further include a second memory chip stacked on top of the first memory chip. The second memory chip has a plurality of second memory cell arrays, and the second memory cells are also electrically connected to the differential amplifier of the logic chip. Both the first and second memory chips are connected to the logic chip. In this embodiment, the number of memory chips included in the memory is not limited and can be selected according to actual needs.

[0013] The aforementioned second memory chip also includes a local differential amplifier. The bit lines of the second memory cell array are connected to the input of this local differential amplifier, and the output of this local differential amplifier is connected to a differential amplifier on the logic chip. In practical applications, the signal can first be amplified by the local differential amplifier, and then amplified by the differential amplifier located on the logic chip.

[0014] When connecting the first memory chip and the logic chip, a suitable connection method can be selected according to requirements. Specifically, hybrid bonding can be used to connect the wiring layer of the first memory chip to the wiring layer of the logic chip. When using hybrid bonding technology, the first memory chip and the logic chip can be fabricated in batches separately, and then the first memory chip and the logic chip can be connected together.

[0015] Secondly, the technical solution of this application also provides an electronic device that includes the memory described in any of the above-mentioned technical solutions. This electronic device has a short data read / write latency, a high storage capacity for a given memory volume, and a low cost. Attached Figure Description

[0016] Figure 1 This is a schematic cross-sectional view of a memory in an embodiment of this application;

[0017] Figure 2 This is a schematic diagram of a memory layout in an embodiment of this application;

[0018] Figure 3 This is a schematic diagram of the structure of the first storage cell array in the embodiments of this application;

[0019] Figure 4 This is a schematic diagram of another memory layout in an embodiment of this application;

[0020] Figure 5 This is a schematic diagram of another cross-sectional structure of the memory in an embodiment of this application;

[0021] Figure 6 This is a schematic diagram of another cross-sectional structure of the memory in an embodiment of this application.

[0022] Explanation of reference numerals in the attached figures:

[0023] 1-First memory chip; 11-First memory cell array;

[0024] 111 - Transistor; 112 - Word line;

[0025] 113 - Bit line; 12 - First semiconductor substrate;

[0026] 13 - First wiring layer; 2 - Logic chip;

[0027] 21-Differential amplifier; 211-First differential input terminal;

[0028] 212 - Second differential input terminal; 213 - Output terminal;

[0029] 22 - Interface control circuit; 23 - Second semiconductor substrate;

[0030] 231 - Through-hole; 24 - Second wiring layer;

[0031] 25 - Reference voltage source; 26 - Word line driver;

[0032] 3-Interconnect layer; 4-Bit line multiplexer;

[0033] 5 - Word line multiplexer; 6 - Second memory chip;

[0034] 61 - Second memory cell array; 62 - Local differential amplifier. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0036] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise.

[0037] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0038] The memory provided in this application can be applied to electronic devices, such as computer systems, servers, desktop computers, and laptops. Specifically, the memory in this application can be applied to the last cache closest to the Central Processing Unit (CPU) of the aforementioned computer system. Furthermore, the aforementioned electronic devices can also be mobile terminal products such as mobile phones. This application does not specifically limit the type of electronic device. Specifically, the memory in this application can be Dynamic Random Access Memory (DRAM). The memory in this application can be specifically used to store data and can perform data writing and reading.

[0039] Figure 1 This is a schematic cross-sectional view of a memory in an embodiment of this application. Figure 2 This is a schematic diagram of a memory layout in an embodiment of this application. Please refer to it. Figure 1 and Figure 2 The memory in this embodiment includes a stacked first memory chip 1 and a logic chip 2, which are stacked, fixedly connected, and electrically connected. The first memory chip 1 includes a plurality of first memory cell arrays 11 (sub arrays), and the logic chip 2 includes a plurality of differential amplifiers 21 and an interface control circuit 22. Figure 3 This is a schematic diagram of the structure of the first storage cell array 11 in the embodiments of this application. Please refer to it. Figure 3The aforementioned first memory cell array 11 may include multiple memory cells arranged in an array. Each memory cell includes a transistor 111 and bit lines 113 and word lines 112 connected to the transistor 111. Transistors 111 in each row are connected to the same word line 112, and transistors 111 in each column are connected to the same bit line 113. The extension directions of word lines 112 and bit lines 113 intersect, and a transistor 111 is connected between any word line 112 and any bit line 113. The differential amplifier 21 of the logic chip 2 is electrically connected to the bit lines 113 of the aforementioned first memory cell array 11. Specifically, each differential amplifier 21 is connected to at least one bit line 113 of the first memory cell array 11. Each time the differential amplifier 21 operates, it connects to one bit line 113 to amplify the signal corresponding to that bit line 113, thereby realizing data transmission. In this application's technical solution, the differential amplifier 21 is located on the logic chip 2, allowing the first memory chip 1 to have a larger area for the first memory cell array 11, thus expanding the memory capacity. Furthermore, in the prior art, both the differential amplifier 21 and the first memory array cell 11 are located on the first memory chip 1, meaning they are both on the same plane as the first memory chip 1. This means the connection line between the differential amplifier 21 and the bit line 113 needs to span a considerable distance within the first logic chip 1. In this embodiment, the first memory chip 1 and the logic chip 2 are stacked, allowing the differential amplifier 21 and the connected bit line 113 to be positioned opposite each other. Therefore, the connection line between the first memory cell array 11 and the differential amplifier 21 spans from the first memory chip 1 to the logic chip 2, shortening the length of the connection line and thus reducing latency. In this scheme, the differential amplifier 21 and the interface control circuit 22 are both located in the logic chip 2, while the storage section is located in the first memory chip 1. Therefore, different processes can be used to fabricate the first memory chip 1 and the logic chip 2. For the first memory chip 1, which mainly includes the storage structure, the transistor density of the memory can be increased. For the logic chip 2, which only includes the circuit structure, it is advantageous to use more advanced technologies for processing, thereby increasing the density of the circuit structure and the operation speed. The differential amplifier 21 includes at least one set of differential input terminals, each set including a first differential input terminal 211 and a second differential input terminal 212. The differential amplifier 21 can perform differential calculations on the data input from the first differential input terminal 211 and the data input from the second differential input terminal 212.In the technical solution of this application, the interface control circuit 22 further includes a reference voltage source 25. The first differential input terminal 211 of the differential amplifier 21 is electrically connected to the first memory cell array 11, specifically to the bit line 113 of the first memory cell array 11. The second differential input terminal 212 is electrically connected to the reference voltage source 25. The reference voltage source 25 inputs a reference voltage to the differential amplifier 21. The differential amplifier 21 uses the reference voltage and the voltage of the bit line 113 input from the first input terminal to perform differential calculation to obtain the memory cell data information.

[0040] In the prior art, the differential amplifier 21 is located in the memory chip. In each differential amplifier 21, the first differential input terminal 211 and the second differential input terminal 212 are both connected to the bit line 113, resulting in a large number of connection lines between the differential amplifier 21 and the memory cell array. In this embodiment, the first memory chip 1 and the logic chip 2 are stacked and electrically connected. Using the technical solution of this application, only the first differential input terminal 211 of the differential amplifier 21 is electrically connected to the bit line 113 of the first memory chip 1. Therefore, the number of connection lines between the first memory chip 1 and the logic chip 2 used to connect the bit line 113 and the differential amplifier 21 is significantly reduced, almost by half. This solution simplifies the memory structure and reduces the area occupied by the connection lines between the differential amplifier 21 and the first memory chip 1. By sharing the resources of the reference voltage source 25, costs can also be reduced, and the calculation program can be simplified.

[0041] It is worth noting that in this embodiment, the first memory chip 1 and the logic chip 2 are stacked, which only illustrates the positional relationship between the first memory chip and the logic chip. Specifically, as shown... Figure 2 As shown, the first memory chip 1 and the logic chip 2 are not located on the same plane. Both the first memory chip 1 and the logic chip 2 can be considered as sheet structures, and the two sheet structures are stacked. The first memory chip 1 and the logic chip 2 can be in contact with each other, and other structures can also be arranged between the first memory chip 1 and the logic chip 2.

[0042] In a specific embodiment, the differential amplifier 21 is a single-channel differential amplifier 21, comprising only one set of differential input terminals and output terminals 213, that is, the input terminals only include a first differential input terminal 211 and a second differential input terminal 212. In the technical solution of this application, each set of differential amplifiers 21 includes one first differential input terminal 211 and one second differential input terminal 212 in this embodiment. Each differential amplifier 21 performs differential operations only on the data obtained from the corresponding two differential input terminals, and outputs the operation result from the output terminal 213 of that differential amplifier 21.

[0043] The aforementioned interface control circuit 22 may include a data bus, an address bus, a command enable terminal, a command register, a data / address latch, a global differential amplifier, a refresh counter and refresh control logic, a data buffer, a power supply circuit, a reference power supply, etc.

[0044] In implementing the embodiments of this application, the specific method by which the first memory chip 1 and the logic chip 2 are stacked and electrically connected is not limited. It can be considered that there is an interconnect layer 3 between the first memory chip 1 and the logic chip 2, and the fixed connection and electrical connection between the first memory chip 1 and the logic chip 2 are achieved by using the interconnect layer 3. Please refer to Figure 1 The first memory chip 1 includes a first semiconductor substrate 12, a plurality of first memory cell arrays 11 formed on the first semiconductor substrate 12, and a first wiring layer 13 connected to the first memory cell arrays 11. The logic chip 2 includes a second semiconductor substrate 23, a differential amplifier 21 and an interface control circuit 22 formed on the second semiconductor substrate 23, and a second wiring layer 24 connected to the differential amplifier 21 and the interface control circuit 22. In one connection method between the first memory chip 1 and the logic chip 2, the first memory chip 1 and the logic chip 2 are connected face to face. Specifically, this can be a hybrid bonding connection between the first wiring layer 13 (the top wiring layer of the first memory chip) of the first memory chip 1 and the second wiring layer 24 (the top wiring layer of the logic chip) of the logic chip 2. Figure 1 As shown. When using a hybrid bonding connection process, the first memory chip 1 and the logic chip 2 can be fabricated in batches separately, and then the first memory chip 1 and the logic chip 2 can be connected. When using hybrid bonding connection, since the top wiring layer 13 of the first chip and the top wiring layer 24 of the second chip are opposite each other and located inside the memory, it is necessary to provide vias 231 on the first semiconductor substrate 12 or the second semiconductor substrate 23 so that the memory can be connected to external circuits.

[0045] In one embodiment of this application, to reduce memory latency, the number of bit lines 113 in the first memory cell array 11 can be less than 1024, and the number of word lines 112 can be less than 512, i.e., the memory is fine-grained. Specifically, in one embodiment, the number of bit lines 113 in the first memory cell array 11 can be 8 to 512; in another embodiment, the number of word lines 112 in the first memory cell array 11 can be 8 to 256; in yet another embodiment, the number of bit lines 113 in the first memory cell array 11 can be 8 to 256, and the number of word lines 112 can be 8 to 512. The fewer the number of word lines 112 and bit lines 113 in the first memory cell array 11, the higher the degree of memory fine-grainedness and the shorter the memory latency. In existing technologies, to reduce memory latency, the memory cell array is refined, which increases the number of memory cell arrays in each memory chip and the number of differential amplifiers 21 connected to the bit line 113, resulting in the differential amplifiers 21 occupying a larger area of ​​the memory chip. Therefore, in a memory chip of the same area, the area occupied by the memory cell array decreases, the storage capacity decreases, and the cost per byte of storage increases. However, using the technical solution of this application, the differential amplifiers 21 are located in the logic chip 2, so the first memory chip 1 can have more area for the first memory cell array 11, which can increase the storage capacity of the memory.

[0046] Figure 4 This is a schematic diagram of another memory layout in an embodiment of this application. For example... Figure 4As shown, to reduce costs, in this embodiment, the memory further includes a bit line multiplexer 4. One end of the bit line multiplexer 4 has multiple input ports, and the other end has an output port. The output port can be connected to any one of the multiple input ports. Each input port of the bit line multiplexer 4 can be connected to a bit line 113 of the first memory cell array 11. However, in practical applications, only some of the input ports of the bit line multiplexer 4 can be connected to the bit line 113; this application does not impose any restrictions. The output port of the bit line multiplexer 4 is connected to a differential amplifier 21. The bit line multiplexer 4 can selectively connect one bit line 113 connected to an input port to the output port. In application, multiple bit lines 113 can share a single differential amplifier 21. The bit line multiplexer 4 allows one bit line 113 connected to the bit line multiplexer 4 to be connected to the differential amplifier 21. In existing technologies, each bit line 113 is typically connected to a differential amplifier 21. When the number of bit lines 113 in each first memory cell array 11 of the memory decreases, i.e., when the first memory cell array 11 is made more granular, the number of first memory cell arrays 11 increases, the total number of bit lines 113 in the first memory chip 1 also increases, the number of differential amplifiers 21 that need to be connected also increases, the area occupied is larger, and the cost of the first memory chip 1 also increases. In this solution, the number of differential amplifiers 21 used can be reduced, the area occupied by the differential amplifiers 21 in the logic chip 2 can be reduced, and the cost can be reduced.

[0047] like Figure 4 As shown, when specifically configuring the bit line multiplexer 4, it can be placed within the first memory chip 1, thereby reducing the number of connection lines between the first memory chip 1 and the logic chip 2, simplifying the manufacturing process. Furthermore, a smaller number of connection lines between the first memory chip 1 and the logic chip 2 results in higher reliability and less susceptibility to damage. Specifically, if the bit line multiplexer 4 is located in the logic chip 2, all bit lines 113 of the first memory chip 1 need to be connected from the first memory chip 1 to the input ports of the bit line multiplexer 4 located in the logic chip 2, resulting in a large number of lines. However, if the bit line multiplexer 4 is located in the first memory chip 1, the bit lines 113 are directly connected to the bit line multiplexer 4 within the first memory chip 1, and the output ports of the bit line multiplexer 4 are connected to the logic chip 2. Since multiple input ports of the bit line multiplexer 4 correspond to one output port, the number of output ports is much smaller than the number of input ports, thus reducing the number of connection lines between the first memory chip 1 and the logic chip 2.

[0048] Please continue to refer to this. Figure 4Based on any of the above embodiments, the logic chip 2 further includes a word line driver 26, which is connected to the word line 112 of the first memory chip 1. The word line driver 26 is electrically connected to the word line 112 of the first memory cell array 11 to enable the opening and closing of memory cells on the word line 112. In this scheme, the word line driver 26 of the memory is located in the logic chip 2, therefore it does not occupy the area of ​​the first memory chip 1, which is beneficial for increasing the number of first memory cell arrays 11 of the first memory chip 1 and increasing the storage capacity of the memory.

[0049] Please continue to refer to this. Figure 4 The memory also includes a word line multiplexer 5, which has multiple output ports at one end and an input port at the other end. The input port can be connected to any one of the multiple output ports. Each output port of the word line multiplexer 5 can be connected to a word line 112 of the first memory cell array 11. Of course, in practical applications, only some of the multiple output ports of the word line multiplexer 5 can be connected to the word line 112, and this application does not impose any restrictions. The input port of the word line multiplexer 5 is connected to a word line driver 26, and the word line multiplexer 5 can select one word line 112 connected to the output port to connect to the input port. In application, multiple word lines 112 can share a single word line driver 26. Using the word line multiplexer 5, one of the multiple word lines 112 connected to the word line multiplexer 5 is connected to the word line driver 26. In the prior art, each word line 112 is usually connected to one word line driver 26. When the number of word lines 112 in each first memory cell array 11 of the memory decreases, that is, when the first memory cell array 11 is refined, the number of first memory cell arrays 11 increases, the total number of word lines 112 in the first memory chip 1 also increases, the number of word line drivers 26 that need to be connected also increases, the area occupied by word line drivers 26 is larger, and the cost of the first memory chip 1 also increases. In this solution, the number of word line drivers 26 used can be reduced, the area of ​​logic chip 2 occupied by word line drivers 26 can be reduced, and the cost can be reduced.

[0050] When specifically configuring the word line multiplexer 5, it can be placed within the first memory chip 1, thereby reducing the number of connection lines between the first memory chip 1 and the logic chip 2, simplifying the manufacturing process. Furthermore, a smaller number of connection lines between the first memory chip 1 and the logic chip 2 results in higher reliability and less susceptibility to damage. Specifically, if the word line multiplexer 5 is located in the logic chip 2, all word lines 112 of the first memory chip 1 need to be connected from the first memory chip to the output port of the word line multiplexer 5 located in the logic chip 2, resulting in a large number of lines. However, if the word line multiplexer 5 is located in the first memory chip 1, the word lines 112 are directly connected to the word line multiplexer 5 within the first memory chip 1, the input port of the word line multiplexer 5 is connected to the logic chip 2, and multiple output ports of the word line multiplexer 5 correspond to one input port. Therefore, the number of input ports is less than the number of output ports, resulting in fewer connection lines between the first memory chip 1 and the logic chip 2.

[0051] Figure 5 This is a schematic diagram of another cross-sectional structure of the memory in an embodiment of this application. Please refer to... Figure 5 In other embodiments of this application, the memory further includes a second memory chip 6, which is stacked on top of the first memory chip 1, and the second memory chip 6 and the first memory chip 1 share a logic chip 2. In a specific embodiment, the second memory chip 6 includes a plurality of second memory cell arrays 61, which are electrically connected to the differential amplifier 21. The second memory chip 6 may have the structural features of the first memory chip 1, the connection relationship between the second memory chip 6 and the logic chip 2, or it may have the connection relationship features between the first memory chip 1 and the logic chip 2.

[0052] In specific embodiments, the memory may include one second memory chip 6, or two or more second memory chips 6, and this application does not impose any restrictions.

[0053] Figure 6 This is a schematic diagram of another cross-sectional structure of the memory in an embodiment of this application, as shown below. Figure 6 As shown, in one embodiment, the second memory chip 6 further includes a local differential amplifier 62. The bit lines of the second memory cell array 61 are connected to the input terminal of the local differential amplifier 62, and the output terminal of the local differential amplifier 62 is connected to the differential amplifier 21 on the logic chip 2. In practical applications, the signal can first be amplified by the local differential amplifier 62, and then amplified by the differential amplifier 21 located on the logic chip 2.

[0054] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A memory, characterized in that, The memory is a dynamic random access memory, and the memory includes: A first memory chip includes a first memory cell array, the first memory cell array including a plurality of transistors, and word lines and bit lines coupled to the plurality of transistors; A logic chip, stacked and electrically connected to the first memory chip, includes a differential amplifier and a reference voltage source; The differential amplifier has a first differential input terminal and a second differential input terminal. The first input terminal is electrically connected to the first memory cell array, and the second input terminal is electrically connected to the reference voltage source. The first differential input terminal and the second differential input terminal are a pair of differential input terminals.

2. The memory according to claim 1, characterized in that, It also includes a bit line multiplexer, one end of which is connected to multiple bit lines of the first memory cell array, and the other end is connected to the differential amplifier.

3. The memory according to claim 2, characterized in that, The bit line multiplexer is located on the first memory chip.

4. The memory according to any one of claims 1 to 3, characterized in that, The logic chip also includes a word line driver, which is connected to the word line of the first memory chip.

5. The memory according to claim 4, characterized in that, It also includes a word line multiplexer, one end of which is connected to a plurality of word lines and the other end of which is connected to the word line driver.

6. The memory according to claim 5, characterized in that, The word line multiplexer is located on the first memory chip.

7. The memory according to any one of claims 1 to 6, characterized in that, It also includes a second memory chip, which is stacked on top of the first memory chip. The second memory chip includes a plurality of second memory cell arrays, which are electrically connected to the differential amplifier.

8. The memory according to claim 7, characterized in that, The second memory chip further includes a local differential amplifier, the second memory cell array is electrically connected to the local differential amplifier, and the local differential amplifier is electrically connected to the differential amplifier on the logic chip.

9. The memory according to any one of claims 1 to 8, characterized in that, The first memory chip and the logic chip are hybrid bonded together.

10. An electronic device, characterized in that, Includes the memory as described in any one of claims 1 to 9.

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