Solid-state imaging device and imaging device

Abstract

The solid-state imaging device (200) comprises: a plurality of pixels (101) arranged in a matrix; a control line (114) provided for each pixel row or each pixel column and connected to the pixels belonging to the corresponding pixel row or pixel column; a driving circuit (111) provided for each control signal, having at least two stages of buffer elements (112a to 112c) connected in series and outputting the control signal to the control line (114); and a first wiring (113) for short-circuiting the output lines of the corresponding buffer elements (112) of a certain stage in at least two driving circuits (111).

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging device and an imaging device represented by a CCD (Charge Coupled Device) or a CMOS (Complementary Metal Oxide Semiconductor) image sensor. Background Art

[0002] Among the various methods for detecting objects, the TOF (Time of Flight) method is well known, which uses the time it takes for light to travel back and forth to a target object (subject) for distance measurement. In the TOF method, at least two exposure signals are acquired for light reflected from the object. The time difference or phase difference between light emission and light reception (the time it takes for light to travel back and forth to the object) is calculated based on the acquired exposure signals to perform distance measurement.

[0003] In solid-state imaging devices performing distance measurement, all pixels are exposed simultaneously. Therefore, using a solid-state imaging device that supports a global shutter allows all pixels to be shuttered simultaneously. Variation in shutter timing for each pixel manifests as variation in the distance measured for each pixel. Therefore, to improve distance measurement accuracy, it is necessary to reduce this variation in shutter timing.

[0004] To solve this problem, Patent Document 1 discloses a technology that includes a column skew correction circuit that adjusts the delay time of a drive signal for controlling shutters for each column, thereby reducing the temporal deviation.

[0005] Prior art literature

[0006] Patent Literature

[0007] Patent Document 1: International Publication No. 2015 / 119243 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] However, Patent Document 1 requires adjusting the delay time of the drive signal for each column, necessitating calibration for each solid-state imaging device. Calibration requires actually performing distance calculations and feeding the results back to the delay adjustment unit, which is time-consuming and labor-intensive. Furthermore, the circuit scale increases. Changes in temperature or voltage also change the delay time, necessitating calibration each time. If calibration is not performed, the delay time will vary for each column, reducing ranging accuracy.

[0010] The present disclosure has been made in view of the above-mentioned problems, and its object is to provide a solid-state imaging device and an imaging device that do not require calibration for adjusting the delay time of a driving signal for each column, reduce the delay difference of the driving signal for each column, and achieve high ranging accuracy.

[0011] Means for solving problems

[0012] In order to solve the above-mentioned problems, a solid-state imaging device involved in one embodiment of the present invention comprises: a plurality of pixels arranged in a matrix; a control line provided for each pixel row or each pixel column and connected to the pixels belonging to the corresponding pixel row or pixel column; a driving circuit provided for each of the control lines, having at least two levels of buffer elements connected in series and outputting control signals to the control lines; and a first wiring for short-circuiting the output lines of the corresponding buffer elements of a certain level in at least two of the driving circuits.

[0013] Furthermore, an imaging device according to one embodiment of the present disclosure includes: the solid-state imaging device; and a signal processing circuit configured to generate a distance image or a luminance image based on a signal received by the solid-state imaging device.

[0014] Effects of the Invention

[0015] According to the present disclosure, it is possible to reduce the delay difference of each column of the driving signal without calibration and achieve high ranging accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a block diagram showing a configuration example of an imaging device according to the first embodiment.

[0017] Figure 2 This is a block diagram showing a detailed configuration example of the solid-state imaging device according to the first embodiment.

[0018] Figure 3 A diagram showing a configuration example of a pixel and a configuration example of an electrode driving line according to the first embodiment.

[0019] Figure 4A This is a diagram showing a detailed configuration example of a pixel array and a driver circuit array according to the first embodiment.

[0020] Figure 4B This is a diagram showing another configuration example of the driving circuit array according to the first embodiment.

[0021] Figure 4C A diagram showing a modified example of the pixel array and the driver circuit array according to the first embodiment.

[0022] Figure 5 This is a flowchart showing the exposure operation in the first embodiment.

[0023] Figure 6 This is a timing chart showing the drive pulses during the exposure operation.

[0024] Figure 7 This is a diagram showing details of a driving circuit array according to the second embodiment.

[0025] Figure 8 This is a diagram showing details of a driving circuit array according to the third embodiment.

[0026] Figure 9 This is a flowchart showing the exposure operation in the third embodiment. DETAILED DESCRIPTION

[0027] The following embodiments are described with reference to the accompanying drawings. The following embodiments are merely illustrative in nature and are not intended to limit the scope of the present disclosure, its applicable objects, or its uses. In the embodiments, components with the same reference numerals perform the same operations, and therefore repeated descriptions are omitted.

[0028] (Implementation 1)

[0029] [1. Configuration of Imaging Device 1000]

[0030] Figure 1 1 is a block diagram showing a configuration example of the imaging device 1000 according to the first embodiment. Figure 1 An object 190 to be measured is also shown in FIG.

[0031] As shown in the figure, the imaging device 1000 includes a light source driver 150, a light source unit 160, an optical lens 170, a signal processing circuit 180, and a solid-state imaging device 200. The solid-state imaging device 200 also includes a pixel array 100, a drive circuit array 110, a timing generation circuit 120, an AD conversion unit 130, and a vertical scanning circuit 140.

[0032] The light source driver 150 supplies a driving signal to the light source unit 160 in accordance with a signal instructing emission of light from the timing generation circuit 120 .

[0033] The light source unit 160 generates pulse light for distance measurement according to the driving signal of the light source driver 150 .

[0034] The lens 170 is a lens for focusing the pulse light reflected from the object 190 in response to the pulse light from the light source unit 160 .

[0035] The signal processing circuit 180 calculates the distance to the object 190 based on the signal received from the solid-state imaging device 200 .

[0036] The pixel array 100 includes a plurality of pixels arranged in a matrix on a semiconductor substrate. Hereinafter, pixels arranged in a row direction among the plurality of pixels are referred to as pixel rows. Furthermore, pixels arranged in a column direction are referred to as pixel columns.

[0037] The driving circuit array 110 includes an arrangement of driving circuits provided for each pixel column, and supplies a control signal for controlling signal charges generated in each pixel to the pixel array 100 .

[0038] The timing generation circuit 120 generates a light emission signal that instructs the object 190 to be irradiated with light (here, near-infrared light, for example). The light emission signal drives the light source unit 160 via the light source driver 150. At this time, the timing generation circuit 120 generates an exposure signal that instructs the pixel array 100 to expose the pixel array 100 to the light reflected from the object 190. For example, the timing generation circuit 120 generates the exposure signal multiple times within a single frame period, and accumulates a pixel signal corresponding to the sum of the exposure light amounts from these multiple times in each pixel.

[0039] The AD converter 130 converts analog pixel signals output from the pixel array 100 in units of pixel rows into digital pixel signals.

[0040] The vertical scanning circuit 140 sequentially scans the pixel rows of the pixel array 100 and outputs pixel signals to the AD converter 130 in units of pixel rows.

[0041] The solid-state imaging device 200 is as follows Figure 1 As shown, near-infrared light is irradiated from light source unit 160 toward object 190 under background light. Light reflected from object 190 enters pixel array 100 via optical lens 170. The reflected light incident on pixel array 100 forms an image, and the resulting optical image is converted into pixel signals. The output of solid-state imaging device 200 is converted into distance data by signal processing circuit 180, and then into a visible distance image or brightness image depending on the intended use.

[0042] Furthermore, the signal processing circuit 180 does not necessarily need to be provided outside the solid-state imaging device 200 , and a part or all of the function of calculating the distance may be built into the solid-state imaging device 200 .

[0043] As the solid-state imaging device 200 , a so-called CMOS image sensor is exemplified.

[0044] [1.1 Configuration of the Solid-State Imaging Device 200]

[0045] Figure 2This is a block diagram showing a detailed configuration example of the solid-state imaging device 200 according to Embodiment 1. The solid-state imaging device 200 includes a pixel array 100 , a drive circuit array 110 , a timing generation circuit 120 , and an AD converter 130 .

[0046] In pixel array 100, a plurality of pixels 101 are arranged in a matrix. Pixels 101 are unit elements that are configured, as needed, with a light-sensing element such as a photodiode or photogate, or a device structure for reading signals generated by photoelectric conversion, such as an amorphous silicon photoelectric conversion film or an organic photoelectric conversion film, or a structure capable of performing initialization. These pixels are an example of a sensor element, and pixel array 100 is an example of a sensor element array.

[0047] The driving circuit array 110 includes one or more driving circuits 111 provided for each pixel column, and first wirings 113. The driving circuit array 110 controls charge accumulation and discharge of the plurality of pixels 101.

[0048] Multiple drive circuits 111 output control signals with the same phase to achieve a global shutter. Each drive circuit 111 applies a drive pulse as a control signal to the electrode of the pixel 101 via an electrode drive line 114, which serves as a control line for controlling the pixel. The electrode drive line 114 includes one or more control lines. More specifically, the drive circuit 111 supplies a control signal to the pixel array 100 for controlling the reset and readout of the signal charge generated in the pixels 101 of the corresponding pixel column. This control signal controls the simultaneous operation of all pixels 101 to achieve a global shutter. Hereinafter, the wiring that transmits the control signal or drive pulse output from the drive circuit array 110 is referred to as the electrode drive line 114. In addition, at least one drive circuit 111 is provided for each pixel column. The number of drive circuits 111 corresponding to one pixel column depends on the configuration of the pixel 101. In addition, "readout" based on the above-mentioned control signal means the transfer of signal charge within the pixel 101, for example, the transfer (or readout) of signal charge from the photodiode to the floating diffusion layer.

[0049] First wiring 113 short-circuits signal lines carrying control signals of the same phase in two or more of the multiple driver circuits 111. The delay times of the signal lines short-circuited by first wiring 113 are averaged compared to a non-short-circuited signal line. This eliminates the need for calibration, as described in the prior art, and reduces the difference in delay time between the short-circuited driver circuits 111. Furthermore, since calibration circuitry is unnecessary, circuit size can be reduced.

[0050] In addition, the two or more driving circuits 111 may be, for example, a set of driving circuits 111 corresponding to even-numbered pixel columns, a set of driving circuits 111 corresponding to odd-numbered pixel columns, a set of driving circuits 111 operating in a culling operation mode, etc.

[0051] The timing generation circuit 120 generates the already described emission signal and exposure signal based on instructions from the signal processing circuit 180 .

[0052] The AD conversion section 130 includes a column ADC 131 provided for each pixel column, a memory array 132 , and an output circuit 133 .

[0053] The column ADC 131 is provided for each column or each of a plurality of columns of pixels 101 and converts analog pixel signals output from the pixels 101 via the vertical signal lines 102 into digital pixel signals. Figure 2 , an example in which the column ADC 131 is provided for each column is shown. The converted digital pixel signals are transferred to the memory array 132 and sequentially output as pixel signals to the signal processing circuit 180 via the output circuit 133.

[0054] The vertical scanning circuit 140 sequentially scans pixel rows of the pixel array 100 to read out or initialize pixel signals. The read pixel signals are sent to the column ADC 131 via the vertical signal lines 102 provided for each column and converted into digital signals.

[0055] [1.2 Pixel 101 Configuration]

[0056] Figure 3 101 and 114 .

[0057] The pixel 101 includes a photoelectric conversion unit 300 , a reset electrode 310 , a first readout electrode 330 , a second readout electrode 350 , a first charge accumulation unit 340 , a second charge accumulation unit 360 , a first selection transistor 370 , a second selection transistor 380 , a floating diffusion layer 390 , a reset transistor 400 , and a source follower 410 .

[0058] The photoelectric conversion unit 300 converts light into electric charges and accumulates the electric charges.

[0059] The reset electrode 310 is a gate electrode of a reset transistor that connects the charge discharge unit 320 and the photoelectric conversion unit 300 .

[0060] The first readout electrode 330 is a gate electrode of a first transfer transistor that reads out charges from the photoelectric conversion unit 300 to the first charge accumulation unit 340 .

[0061] The second readout electrode 350 is a gate electrode of a second transfer transistor that reads out charges from the photoelectric conversion unit 300 to the second charge accumulation unit 360 .

[0062] The first charge storage unit 340 is a capacitor or a diffusion layer that stores the charge read out from the photoelectric conversion unit 300 .

[0063] The second charge storage unit 360 is a capacitor or a diffusion layer that stores the charge read out from the photoelectric conversion unit 300 .

[0064] The first selection transistor 370 is controlled by a first selection signal to connect the first charge accumulation unit 340 to the gate electrode of the source follower 410 . The first selection signal is supplied from the vertical scanning circuit 140 to the gate electrode of the first selection transistor 370 .

[0065] The second selection transistor 380 is controlled by a second selection signal to connect the second charge accumulation unit 360 to the gate electrode of the source follower 410. The second selection signal is supplied from the vertical scanning circuit 140 to the gate electrode of the second selection transistor 380.

[0066] The floating diffusion layer 390 holds the charge transferred from the first charge accumulation section 340 via the first selection transistor 370 , and holds the charge transferred from the second charge accumulation section 360 via the second selection transistor 380 .

[0067] The reset transistor 400 resets the floating diffusion layer 390 in accordance with a reset signal. The reset signal is supplied from the vertical scanning circuit 140 to the gate electrode of the reset transistor 400.

[0068] The source follower 410 converts the charge held in the floating diffusion layer 390 into a voltage and outputs the voltage to the vertical signal line 102 .

[0069] Furthermore, the electrode driving lines 114 include a reset control line 114A, a first readout control line 114B, and a second readout control line 114C.

[0070] When a driving pulse is applied to the reset electrode 310 via the reset control line 114A, the charges accumulated in the photoelectric conversion portion 300 are discharged to the charge discharge portion 320 .

[0071] When a drive pulse is applied to the first readout electrode 330 via the first readout control line 114B, the charges accumulated in the photoelectric conversion unit 300 are transferred to the second charge accumulation unit 360 .

[0072] When a drive pulse is applied to the second readout electrode 350 via the second readout control line 114C, the charges accumulated in the photoelectric conversion unit 300 are transferred to the second charge accumulation unit 360 .

[0073] [1.3 Configuration of the Driving Circuit Array 110]

[0074] Figure 4A 1 is a diagram showing a detailed configuration example of the driving circuit array 110 .

[0075] The pixel 101 of the figure is set to Figure 3 The configuration example shown is the same as that shown in FIG. It is assumed that a reset control line 114A, a first readout control line 114B, and a second readout control line 114C are connected to each pixel 101 as electrode drive lines 114 from the drive circuit array 110 .

[0076] The driver circuit array 110 includes three driver circuits 111A to 111C for each pixel column. These three driver circuits 111A to 111C correspond to the reset control line 114A, the first readout control line 114B, and the second readout control line 114C, respectively. Unless otherwise specified, the driver circuits 111A to 111C are simply referred to as driver circuits 111.

[0077] A reset control signal having a drive pulse φODG is input to the driver circuit 111A of each pixel column from the timing generation circuit 120. Each driver circuit 111A outputs a reset control signal to the reset electrode 310 via the reset control line 114A for each pixel 101 in the corresponding pixel column.

[0078] A first readout control signal having a drive pulse ΦTG1 is input to the driver circuit 111B of each pixel column from the timing generation circuit 120. Each driver circuit 111B outputs the first readout control signal to the first readout electrode 330 via the first readout control line 114B for each pixel 101 in the corresponding pixel column.

[0079] A second readout control signal having a drive pulse ΦTG2 is input to the driver circuit 111C of each pixel column from the timing generation circuit 120. Each driver circuit 111C outputs the second readout control signal to the second readout electrode 350 via the second readout control line 114C for each pixel 101 in the corresponding pixel column.

[0080] Each driver circuit 111 includes at least two stages of buffer elements 112. The driver circuit 111 shown in this figure includes three stages of buffer elements 112a through 112c. The driving capability of buffer elements 112a through 112c is configured to increase in the order of buffer elements 112a, 112b, and 112c. Furthermore, the driving capability of buffer element 112 can be increased by increasing the size of the output transistors within buffer element 112. Furthermore, the driving capability of buffer element 112 can be increased by including multiple output transistors in parallel within buffer element 112.

[0081] In addition, when there is no particular distinction between the buffer elements 112a to 112c, they are simply referred to as the buffer element 112. Here, the buffer element 112 may be an inverter circuit with reversed polarity or a buffer circuit with constant polarity.

[0082] First wiring 113 is at least one wiring that short-circuits signal lines transmitting signals of the same phase within two or more driver circuits 111. In the figure, first wiring 113 includes three types of first wirings: 113A, 113B, and 113C, corresponding to reset control line 114A, first readout control line 114B, and second readout control line 114C. Furthermore, first wiring 113 includes three types of first wirings: 113D, 113E, and 113F, corresponding to reset control line 114A, first readout control line 114B, and second readout control line 114C.

[0083] Regardless of the delay time difference, each driver circuit 111A drives the reset control signal with the same phase as the driver circuits 111A in other columns. Similarly, regardless of the column to which the driver circuit 111B corresponds, each driver circuit 111B drives the first readout control signal with the same phase as the driver circuits 111B in other columns. The same applies to the driver circuit 111C.

[0084] First wiring 113A short-circuits wirings for signals with the same phase within two or more driver circuits 111A. In this figure, first wiring 113A short-circuits the output lines of the second-stage buffer elements 112b within each driver circuit 111A. This allows for averaging of delay time differences in the output lines of the buffer elements 112b within each driver circuit 111A.

[0085] The first wiring 113B short-circuits the output lines of the second-stage buffer elements 112b in each driver circuit 111B. Similarly, the first wiring 113C short-circuits the output lines of the second-stage buffer elements 112b in each driver circuit 111C.

[0086] The first wiring 113D short-circuits the output lines of the first-stage buffer elements 112a in each driver circuit 111A, thereby averaging the delay time differences in the output lines of the buffer elements 112a in the driver circuit 111A.

[0087] First wiring 113E short-circuits the output lines of the first-stage buffer elements 112a within each driver circuit 111B. Similarly, first wiring 113F short-circuits the output lines of the first-stage buffer elements 112a within each driver circuit 111C. The impedance of first wirings 113A to 113C is configured to be lower than that of first wirings 113D to 113D. For example, the line width of first wirings 113A to 113C may be larger than that of first wirings 113D to 113D. Alternatively, first wirings 113D to 113F may each consist of a single wire, while first wirings 113A to 113C may each consist of multiple wires connected in parallel.

[0088] The load driven by each driver circuit 111 becomes a gate load and wiring load equal to the number of pixels to be driven, so the load is large. Therefore, the buffer element 112 of the final stage of the driver circuit 111 is required to have a high driving capability. If the driving pulse generated by the timing generation circuit 120 is used to directly drive the buffer element 112 of the final stage, the load is too large, the rise time or fall time of the voltage becomes longer, and the timing deviation of the driving pulse between columns becomes larger. Therefore, the driver circuit 111 needs to gradually increase the driving capability from the primary stage of the buffer element 112 connected in multiple stages to the final stage. For example, the size of the transistors constituting the buffer element 112 also gradually increases from the primary buffer element 112a to the final buffer element 112c.

[0089] The first wiring 113 short-circuits the outputs of the buffer elements 112 driving signals of the same phase, reducing the timing deviation between columns of the drive pulses. In other words, the first wiring 113 is a wiring that averages the delay. In addition, the timing deviation between columns is caused by manufacturing deviations of the transistors that constitute the drive circuit 111, differences in wiring resistance and capacitance caused by layout differences, or differences in power supply voltage drops. Through the first wiring 113, the nodes within the drive circuit are short-circuited with low impedance, and the potential of the nodes changes in a consistent manner. Therefore, even if there is a timing deviation between the columns of the drive circuit 111, the first wiring 113 acts to reduce the timing deviation. In addition, the first wiring 113 is wired in the horizontal direction of the drive circuit array 110, so the timing deviation is reduced in the entire drive circuit array area.

[0090] However, if there is a timing mismatch between columns, a potential difference will occur between the columns, causing a through-current to flow through the first wiring 113. In particular, the greater the timing mismatch, the greater the potential difference, and the greater the through-current. If a large current flows due to the through-current, it may cause wiring to melt or transistor damage. Furthermore, as the number of buffer elements 112 in the driver circuit 111 increases, the timing mismatch between columns accumulates. Therefore, the timing mismatch in the preceding stages of the driver circuit 111 is relatively small. Therefore, when a short circuit is created between columns from the preceding stage of the driver circuit 111 via the first wiring 113, the timing mismatch is small, and the through-current flowing through the first wiring 113 can be suppressed to a low level.

[0091] The first wiring 113 can be composed of multiple wirings, not just one. Even a single first wiring 113 can reduce timing variations. However, as the number of buffer elements 112 increases, timing variations accumulate. Therefore, short-circuiting the columns of each buffer element 112 can further reduce timing variations. Furthermore, the closer to the subsequent stage of the driver circuit 111, the higher the driving capability. Therefore, the impedance of the first wiring 113 should be lowered as the subsequent stage approaches. By increasing the thickness of the first wiring 113 in the subsequent stage, where more through-current flows, the impedance can be reduced, thereby preventing wiring burnout.

[0092] The final-stage buffer element 112c connected to the electrode drive line 114 has high drive capability. If a short circuit occurs between columns, a large amount of through-current will flow, potentially causing wiring to melt or transistor damage. Therefore, the electrode drive line 114 is independent for each column without short circuiting between columns.

[0093] Next, another configuration example of the driving circuit array 110 will be described.

[0094] Figure 4B This figure shows another configuration example of the drive circuit array 110 according to the first embodiment. Figure 4A The difference between the drive circuit array 110 and the drive circuit array 111A is that each of the multiple drive circuits 111A to 111C includes M drive circuit groups divided into M parts (M is an integer greater than or equal to 2), and each first wiring 113A to 113C is provided for each of the M drive circuit groups to short-circuit the output lines of the buffer elements belonging to each drive circuit group. The following description focuses on these differences.

[0095] Each of the plurality of driving circuits 111A to 111C includes two driving circuit groups divided into two parts. Figure 4BWhere M = 2. Specifically, the plurality of drive circuits 111A are divided into a drive circuit group consisting of drive circuits 111 corresponding to odd-numbered columns and a drive circuit group consisting of drive circuits 111 corresponding to even-numbered columns. The plurality of drive circuits 111B are also divided into a drive circuit group corresponding to odd-numbered columns and a drive circuit group corresponding to even-numbered columns. The same applies to the plurality of drive circuits 111C.

[0096] Figure 4A The first wiring 113A is Figure 4B 113Ao and 113Ae. First wiring 113Ao short-circuits the output lines of buffer elements 112b belonging to the driver circuit group corresponding to odd columns. First wiring 113Ae connects the output lines of buffer elements 112b belonging to the driver circuit group corresponding to even columns.

[0097] The first wiring 113B corresponds to the first wiring 113Bo corresponding to the odd-numbered columns and the first wiring 113Ae corresponding to the even-numbered columns.

[0098] The first wiring 113C also corresponds to the first wiring 113Co and the first wiring 113Ce.

[0099] Figure 4A The first wiring 113D is Figure 4B 113Do and 113De. First wiring 113Do short-circuits the output lines of buffer elements 112a belonging to the drive circuit group corresponding to odd columns. First wiring 113De connects the output lines of buffer elements 112a belonging to the drive circuit group corresponding to even columns.

[0100] The first wiring 113E corresponds to the first wiring 113Eo corresponding to the odd-numbered columns and the first wiring 113Ee corresponding to the even-numbered columns.

[0101] The first wiring 113F also corresponds to the first wiring 113Fo and the first wiring 113Fe.

[0102] exist Figure 4B In this case, in the thinning operation mode for generating an image with half the number of pixels in the row direction, the load on the first wiring 113 applied to the drive circuit array 110 can be reduced.

[0103] Furthermore, the division into M parts does not need to be equal, and M may be greater than 3. For example, when generating an image in which the number of pixels in the row direction is reduced to 1 / 4, all pixel columns may be divided into two parts in a 1:3 ratio, or may be divided into three parts in a 1:2:1 ratio.

[0104] [1.4 Operation of the Solid-State Imaging Device 200]

[0105] Next, use Figure 5 、 Figure 6 The operation during the exposure period in the solid-state imaging device 200 will be described.

[0106] Figure 5 Flowchart showing the exposure operation in Embodiment 1. Figure 6 This is a timing chart showing drive pulses during the exposure operation in the first embodiment.

[0107] First, as an initialization operation immediately before time t1, a reset step ST00 is performed. The drive pulse ΦODG applied to the reset electrode 310 is set to the High state, placing the photoelectric converter 300 in the reset state. Furthermore, the drive pulse ΦTG1 applied to the first readout electrode 330 and the drive pulse ΦTG2 applied to the second readout electrode 350 are set to the Low state, electrically disconnecting the photoelectric converter 300 from the first charge accumulation unit 340 and the second charge accumulation unit 360. In this state, the signal charge generated by the photoelectric converter 300 is discharged to the charge discharge unit 320 via the reset electrode 310 and is not stored in the photoelectric converter 300.

[0108] Next, at time t1, the process proceeds to step ST01 for starting light emission accumulation. Reset electrode 310 is set to a low state, stopping the discharge of charge from photoelectric converter 300 to charge discharge unit 320. Photoelectric converter 300 then accumulates the generated signal charge. At the same time, timing generator circuit 120 applies a light emission trigger signal to light source driver 150, causing light source unit 160 to emit infrared pulse light. After the infrared pulse light is emitted, the reflected light enters pixel array 100 with a time difference corresponding to the distance from object 190.

[0109] Next, at time t2, the process proceeds to the first readout step ST03. The first readout electrode 330 becomes High, electrically connecting the photoelectric converter 300 and the first charge storage unit 340. The signal charges stored in the photoelectric converter 300 are transferred to the first charge storage unit 340.

[0110] Next, at time t3, the first readout electrode 330 enters a low state, electrically disconnecting the photoelectric conversion unit 300 from the first charge accumulation unit 340, and the readout of the signal charge S0 is completed. At the same time, the timing generation circuit 120 applies a trigger signal to the light source driver 150, stopping the irradiation of the infrared pulse light from the light source unit 160. The signal charge S0 has a charge amount proportional to the time (Tp - Tf) obtained by subtracting the arrival time Tf from the irradiation of the infrared pulse light until the reflected light reaches the pixel array 100 from the irradiation time Tp of the infrared pulse light.

[0111] Next, at time t4, the process proceeds to the second readout step ST03. The second readout electrode 350 becomes High, electrically connecting the photoelectric converter 300 and the second charge storage unit 360. The signal charges stored in the photoelectric converter 300 are transferred to the second charge storage unit 360.

[0112] Next, at time t5, the second readout electrode 350 is in a low state, the photoelectric converter 300 and the second charge storage unit 360 are electrically disconnected, and the readout of the signal charge S1 is completed. The signal charge S1 has a charge amount proportional to the arrival time Tf.

[0113] Next, at time t6, the process proceeds to reset step ST04. Reset electrode 310 goes high, electrically connecting photoelectric converter 300 and charge discharge unit 320. Photoelectric converter 300 enters a reset state, where no charge is stored.

[0114] In the case of repeated exposure, the process proceeds to the light accumulation start step ST01 again, and the operations from the light accumulation start step ST01 to the reset step ST04 are repeated. The operations from the light accumulation step ST01 to the reset step ST04 are repeated multiple times within a single frame period, and signal charges S0 and S1 corresponding to the sum of the multiple exposure light amounts are accumulated in the first charge accumulation section 340 and the second charge accumulation section 360, respectively. When the repeated exposure is completed, the exposure is complete.

[0115] After the exposure period ends, the first select transistor 370 is set to a high state to begin reading out the signal charge S0. The signal charge S0 is transferred to the floating diffusion layer 390 and converted into a voltage by the source follower 410. The converted signal charge S0 is then converted into a digital signal by the column ADC 131 via the vertical signal line 102. Once the readout of the signal charge S0 is complete, the reset transistor 400 is set to a high state, resetting the floating diffusion layer 390 to its initial state. The pixel array 100 is sequentially scanned in the vertical direction, and the signal charge S0 of all pixels 101 is converted into a digital signal.

[0116] Next, after returning the first select transistor 370 to a low state, the second select transistor 380 is set to a high state, and the readout of signal charge S1 begins. Similar to signal charge S0, signal charge S1 is transferred to the floating diffusion layer 390 and converted into a voltage by the source follower 410. The converted signal charge S1 is then converted into a digital signal by the column ADC 131 via the vertical signal line 102. Once the readout of signal charge S1 is complete, the reset transistor 400 is set to a high state, resetting the floating diffusion layer 390 to its initial state. The pixel array 100 is sequentially scanned in the vertical direction, and the signal charge S1 of all pixels 101 is converted into a digital signal.

[0117] Here, when the speed of light is defined as c, the distance Z from the imaging device 1000 to the object 190 can be obtained based on the arrival time Tf by the following equation (1).

[0118] [Number 1]

[0119]

[0120] Signal charge S0 is proportional to Tp-Tf, which is obtained by subtracting arrival time Tf from irradiation time Tp. Signal charge S1 is proportional to arrival time Tf. Therefore, the signal charge ratio S1 / S0 is equal to the ratio of arrival time to irradiation time, Tf / (Tp-Tf). Arrival time Tf is expressed as shown in the following equations (2a) and (2b) based on irradiation time Tp and signal charges S1 and S0.

[0121] [Number 2]

[0122]

[0123]

[0124] Therefore, the distance Z from the object 190 is expressed by the following equation (3) based on the signal charges S0 and S1 and the irradiation time Tp.

[0125] [Number 3]

[0126]

[0127] In the absence of the first wiring 113, temporal deviation occurs between columns. When there is a temporal deviation Δt, the signal charge S1 is proportional to Tf-Δt, which is obtained by subtracting the temporal deviation Δt from the arrival time Tf. The signal charge S0 is proportional to Tp-Tf+Δt, which is obtained by adding the temporal deviation Δt to Tp-Tf, which is obtained by subtracting the arrival time Tf from the irradiation time Tf. Therefore, the signal charge ratio S1 / S0 is expressed as follows: Equations (4a) and (4b).

[0128] [Number 4]

[0129]

[0130]

[0131] A temporal deviation Δt is added to the actual arrival time Tf, and a measured distance difference ΔZ is generated in the distance Z from the object 190 as shown in the following equation (5).

[0132] [Number 5]

[0133]

[0134] For example, when the speed of light is set to c = 299,792,458 m / s and the temporal variation Δt = 100 ps, ​​the measured distance difference ΔZ is approximately 15 mm. By using first wiring 113, the temporal variation Δt between columns can be reduced, thereby reducing the measured distance difference ΔZ. Consequently, high distance measurement accuracy can be achieved without requiring calibration or increasing circuit size.

[0135] [1.5 Modification of the Solid-State Imaging Device 200]

[0136] Next, a modification of the solid-state imaging device 200 will be described.

[0137] Figure 4C A diagram showing a modified example of the pixel array and the driver circuit array according to the first embodiment. Figure 4C The driving circuit array 110 and Figure 4A The differences are that a reset control line 14A is provided for each pixel row instead of the reset control line 114A for each pixel column; a driver circuit 11A is provided for each pixel row instead of the driver circuit 111A for each pixel column; a first wiring 13A is provided instead of the first wiring 113A; and a first wiring 13D is provided instead of the first wiring 113D. The following description will avoid duplication of similarities and focus on the differences.

[0138] The reset control line 14A is provided for each pixel row and transmits a reset control signal having a drive pulse ΦODG output from the vertical scanning circuit 140 via the drive circuit 11A to the pixels 101 belonging to the corresponding pixel row.

[0139] The driver circuit 11A is provided for each pixel row and is provided at the final stage within the vertical scanning circuit 140. Each driver circuit 11A outputs a reset control signal to the reset electrode 310 via the reset control line 14A for each pixel 101 belonging to the corresponding pixel row. Alternatively, the driver circuit 11A may be provided between the vertical scanning circuit 140 and the pixel array 100.

[0140] Each driver circuit 11A includes at least two stages of buffer elements 11. The driver circuit 11A shown in this figure includes three stages of buffer elements 11a through 11c. The driving capabilities of the buffer elements 11a through 11c are configured to increase in the order of buffer elements 11a, 11b, and 11c. Unless otherwise specified, the buffer elements 11a through 11c are simply referred to as buffer elements 11. The buffer elements 11 can be either inverter circuits with polarity reversal or buffer circuits without polarity reversal.

[0141] The first wiring 13A is a type of first wiring and is at least one wiring that short-circuits signal lines transmitting signals of the same phase in two or more drive circuits 11 .

[0142] The first wiring 13D is a type of first wiring and is at least one wiring that short-circuits signal lines transmitting signals of the same phase within two or more drive circuits 11. When not specifically distinguishing between the first wiring 13A and the first wiring 13D, they are simply referred to as first wiring 13.

[0143] Ignoring the delay time difference, any driver circuit 11A drives the reset control signal with the same phase as the driver circuits 11A of other columns.

[0144] First wiring 13A short-circuits wirings for signals with the same phase within two or more driver circuits 11A. In this figure, first wiring 13A short-circuits the output lines of the second-stage buffer elements 11b within each driver circuit 11A. This allows for averaging of delay time differences in the output lines of the buffer elements 11b within each driver circuit 11A.

[0145] The first wiring 13D short-circuits the output lines of the first-stage buffer elements 11a in each driver circuit 11A, thereby averaging the delay time differences in the output lines of the buffer elements 11a in the driver circuit 11A.

[0146] The impedance of first wiring 13A is configured to be smaller than the impedance of first wiring 13D. For example, the line width of first wiring 13A may be larger than that of first wiring 13D. Alternatively, first wiring 13D may be composed of a single wire, while first wiring 13A may be composed of multiple wires connected in parallel.

[0147] The load driven by each driver circuit 11A becomes a gate load and wiring load equal to the number of pixels to be driven, resulting in a large load. Therefore, the final-stage buffer element 11c of the driver circuit 11A is required to have a high drive capability. If the final-stage buffer element 11c is driven directly using the drive pulse generated by the timing generation circuit 120, the load is too large, and the rise and fall times of the voltage become longer, resulting in a larger timing deviation of the drive pulses between columns. Therefore, the driver circuit 11A needs to gradually increase its drive capability from the initial stage of the multi-stage buffer element 11 toward the final stage. For example, the size of the transistors that make up the buffer element 11 also gradually increases from the initial buffer element 11a toward the final buffer element 11c.

[0148] The first wiring 13 short-circuits the outputs of the buffer elements 11 driving signals of the same phase, reducing the timing variation between columns of the drive pulses. In other words, the first wiring 13 is a wiring that averages the delay. Furthermore, timing variation between columns can occur due to manufacturing variations in the transistors that make up the drive circuit 11, differences in wiring resistance and capacitance due to layout differences, or differences in power supply voltage drops. Through the first wiring 13, the nodes within the drive circuit are short-circuited with low impedance, causing the potentials of the nodes to fluctuate in a consistent manner. Therefore, even if there is timing variation between columns of the drive circuit 111, the timing variation is reduced via the first wiring 13A. Furthermore, the first wiring 13 is routed in a direction perpendicular to the drive circuit array 110, thereby reducing timing variation across the entire drive circuit array 110 region.

[0149] As described above, the solid-state imaging device 200 involved in this embodiment includes: a plurality of pixels 101 arranged in a matrix; a control line 114 provided for each pixel row or each pixel column and connected to the pixels 101 belonging to the corresponding pixel column; a driving circuit 111 provided for each control signal, having at least two stages of buffer elements 112a to 112c connected in series and outputting the control signal to the control line 114; and a first wiring 113 for short-circuiting the output lines of the corresponding buffer elements 112 of a certain stage in at least two driving circuits 111.

[0150] Thus, the short-circuiting of the first wiring 113 can reduce the delay difference, which is the temporal variation of the control signal for each control line 114. This reduces the delay difference of the control signal for each column without calibration, achieving high ranging accuracy.

[0151] Here, the first wiring 113 is a wiring for averaging the delay of the control line 114 for each row or column.

[0152] Here, the plurality of pixels 101 may include optical black pixels and normal pixels other than the optical black pixels, and the wiring length of the first wiring may be longer than one side parallel to the first wiring among the four sides of the effective area formed by the normal pixels.

[0153] Thus, the first wiring can be provided as an output line connectable to the buffer element 112 corresponding to any pixel column among all pixel columns.

[0154] Here, the plurality of driving circuits 111 may include M driving circuit groups divided into M parts (M is an integer greater than or equal to 2), and the first wiring 113 may be provided for each of the M driving circuit groups to short-circuit the output lines of the buffer elements belonging to the driving circuit group.

[0155] This is suitable for generating an image having a smaller number of pixels than the total number of pixels, for example, using the pixel columns corresponding to the drive circuit group.

[0156] Here, one of the M drive circuit groups may be formed of a drive circuit 111 driven in a pixel thinning operation mode.

[0157] Thus, for example, when generating a low-resolution image, a thinning operation mode can be used to use 1 / m (m is an integer greater than or equal to 2) of all pixel columns and not use the remaining pixel columns, allowing only the necessary driver circuits 111 to be short-circuited via the first wiring. This reduces the parasitic capacitance of the first wiring and allows for faster execution of the thinning operation mode.

[0158] Here, the first wiring may be provided in each of two or more stages and less than all stages among the at least two stages of buffer elements 112 .

[0159] Here, the impedance of the first wiring 113 may be lower than the impedance of the first wiring corresponding to the buffer element 112 on the previous stage.

[0160] This can further reduce the occurrence of the above-mentioned delay time difference.

[0161] Here, the wiring width of the first wiring 113 may be wider than the wiring width of the corresponding first wiring 113 on the previous stage side.

[0162] This can further reduce the occurrence of the above-mentioned delay time difference.

[0163] Here, the driving capability of the buffer element 112 may be higher than the driving capability of the buffer element 112 on the preceding stage.

[0164] This can further reduce the occurrence of the above-mentioned delay time difference.

[0165] Here, the pixel 101 may include a photoelectric converter 300 that converts light into electric charge, and readout electrodes 330 / 350 for reading out electric charge from the photoelectric converter 300 , and the control line 114 may be connected to the readout electrodes 330 / 350 .

[0166] Here, the pixel 101 may include a reset electrode 310 for resetting the charge in the pixel, and the control line may be connected to the reset electrode 310 .

[0167] Here, the pixel 101 may be configured to include a photoelectric conversion portion 300 that converts light into electric charges, a first readout electrode 330 for reading out electric charges from the photoelectric conversion portion 300, and a reset electrode 310 for resetting the electric charges within the pixel, the control line 114 may include a first readout control line 114B connected to the first readout electrode 330 and a reset control line 114A connected to the reset electrode 310 for each pixel column, and the solid-state imaging device 200 may include a drive circuit 111B connected to the first readout control line 114B and a drive circuit 111A connected to the reset control line 114A for each pixel column.

[0168] Here, the pixel 101 may further include a second readout electrode 350 for reading out charge from the photoelectric conversion unit 300, the control line 114 may further include a second readout control line 114C connected to the second readout electrode 350 for each pixel column, and the solid-state imaging device 200 may further include a driving circuit 111C connected to the second readout control line 114C for each pixel column.

[0169] Furthermore, the imaging device according to the first embodiment includes the solid-state imaging device 200 described above, and a signal processing circuit 180 that generates a distance image or a luminance image based on a signal received by the solid-state imaging device 200 .

[0170] Furthermore, the first wiring that short-circuits the output lines of corresponding buffer elements 112 of a certain stage is not limited to one, and two or more first wirings 113 connected in parallel may be provided. The two or more first wirings 113 connected in parallel may be formed in one wiring layer or in multiple wiring layers.

[0171] (Implementation Method 2)

[0172] [2. Configuration of the Driving Circuit Array 110]

[0173] Figure 7 : shows the structure of the driving circuit array 110 involved in the second embodiment. Figure 7 As shown, the driving circuit array 110 of the second embodiment is Figure 4AThe difference between the drive circuit array 110 and the drive circuit array 110 is that the wiring switching sections 510a to 510c are added. The following description will focus on the difference. In addition, when there is no particular distinction between the wiring switching sections 510a to 510c, they are simply referred to as the wiring switching section 510.

[0174] Each of the wiring switching sections 510a-510c switches the output wiring of a buffer element 112 in a driver circuit 111 with a wiring of a driver circuit 111 in a different column in order to connect the output wiring of the buffer element 112 to a buffer element 112 in the same level but not in the same column. In other words, each of the wiring switching sections 510a-510c crosses the wiring between driver circuits 111, thereby essentially switching a buffer element 112 in a driver circuit 111 with a corresponding buffer element 112 in the same level in another driver circuit 111.

[0175] exist Figure 7 , the example in which the wiring switching portions 510a to 510c are located at three locations is shown, but the number may be two or four or more. Furthermore, the example in which the wiring is switched between adjacent drive circuits 111 corresponding to the same pixel column is shown, but the wiring may also be switched between non-adjacent drive circuits 111.

[0176] The exposure operation of the second embodiment is similar to that of the first embodiment. Figure 5 Each step is carried out.

[0177] As described above, the solid-state imaging device of this embodiment can reduce inter-column differences in driver circuit 111 caused by layout variations or manufacturing variations by reversing the path of the drive signal. This averages the delay times of the drive signals that differ for each column, thereby reducing inter-column differences in delay time. This is particularly effective in reducing inter-column differences in delay time when the drive signals differ in phase, making it impossible to short-circuit the columns via first wiring 113. As a result, delay differences between drive signals with different phases can be reduced, improving distance measurement accuracy.

[0178] As described above, the solid-state imaging device 200 according to the second embodiment may also include a wiring exchange section 510 that crosses wiring between driver circuits 111 to substantially exchange the buffer element 112 in a driver circuit 111 with a corresponding buffer element 112 of the same level in another driver circuit 111 .

[0179] Here, two or more wiring switching portions 510 may be provided, and the wiring switching portion 510 may be inserted into the input lines or output lines of at least two buffer elements 112 of the plurality of driving circuits 111 .

[0180] (Implementation 3)

[0181] [3. Configuration of the Driving Circuit Array 110]

[0182] Figure 8 : shows the structure of the driving circuit array 110 involved in the third embodiment. Figure 8 As shown, the wiring replacement unit 510 of the third embodiment is Figure 7 The difference is that the wiring exchange parts 510d and 510e are provided instead of the wiring exchange parts 510a to 510c. The following description will focus on the difference. In addition, when there is no particular distinction between the wiring exchange parts 510d and 510e, they are simply referred to as the wiring exchange part 510.

[0183] The wiring switching unit 510d includes three selection circuits 530 for each pixel column. Each selection circuit 530 has one input terminal and three output terminals, selects one of the output terminals, and connects the input terminal to the selected output terminal. The three selection circuits 530 corresponding to one pixel column switch the input wiring of the buffer elements 112a of the corresponding three driver circuits 111.

[0184] The selection circuit 530 to which the driving pulse ΦODG is input selects one of the input lines of the buffer elements 112 a of the three driving circuits 111 corresponding to the pixel column, and transmits the driving pulse ΦODG to the selected input line.

[0185] The selection circuit 530 to which the driving pulse ΦTG1 is input selects one of the input lines of the buffer elements 112 a of the three driving circuits 111 corresponding to the pixel column, and transmits the driving pulse ΦTG1 to the selected input line.

[0186] Similarly, the selection circuit 530 to which the driving pulse ΦTG2 is input selects one of the input lines of the buffer elements 112 a of the three driving circuits 111 corresponding to the pixel column, and transmits the driving pulse ΦTG3 to the selected input line.

[0187] The three selection circuits 530 corresponding to one pixel column exclusively select the buffer element 112 a of the transfer destination.

[0188] The wiring switching unit 510e includes three selection circuits 531 for each pixel column. Each selection circuit 531 has three input terminals and one output terminal, selects one of the input terminals, and connects the selected input terminal to the output terminal. The three selection circuits 531 corresponding to one pixel column switch the output wiring of the buffer elements 112c of the corresponding three drive circuits 111. Figure 8 In the configuration example of , each selection circuit 531 performs a selection operation to restore the wiring swap performed by the corresponding selection circuit 530 .

[0189] Thus, the three selection circuits 530 and 531 corresponding to the pixel columns function to switch the driving circuit 111 with the driving circuit 111 of a different column in response to the selection switching signal 540 .

[0190] For example, when the selection switching signal 540 is "0," the driver circuit 111 is connected to the control line 114 in the same column. In this case, the reset control line 114A is connected to the driver circuit 111A, the first read control line 114B is connected to the driver circuit 111B, and the second read control line 114C is connected to the driver circuit 111C.

[0191] When the selection switching signal 540 is "1," the driver circuit 111 is connected to control lines that are not in the same column. In this case, the reset control line 114A is connected to the driver circuit 111B, the first read control line 114B is connected to the driver circuit 111C, and the second read control line 114C is connected to the driver circuit 111A.

[0192] When selection switching signal 540 is "2," driver circuit 111 is connected to other control lines that are not in the same column. In this case, reset control line 114A is connected to driver circuit 111C, first read control line 114B is connected to driver circuit 111A, and second read control line 114C is connected to driver circuit 111B.

[0193] The selection switching signal 540 shows an example of three values, but may also have two values, or may have four or more values.

[0194] Next, use Figure 9 The flowchart illustrates the exposure action of embodiment 3. Figure 9 Flowchart to Figure 5 The flowchart of Embodiment 1 adds a drive circuit switching step ST05; the remaining steps are the same as those of Embodiment 1. Typically, when measuring the distance to object 190, multiple exposures are performed within a single frame. In Embodiment 3, when repeated exposures are performed after resetting step ST04, the process proceeds to drive circuit switching step ST05. In drive circuit switching step ST05, a selection switching signal 540 is switched to change the buffer element 112 through which the drive signal passes. After drive circuit switching step ST05 is completed, the process proceeds again to light accumulation start step ST01. The drive circuit 111 through which the drive signal passes is switched with each repeated exposure.

[0195] Here, it is assumed that the electrode driving lines 114 include three types of control lines: a reset control line 114A, a first readout control line 114B, and a second readout control line 114C.

[0196] The wiring switching unit 510 switches the three types of control lines for each exposure. A total of (1+m+n) exposures are performed within one frame. The drive signal applied to the reset control line 114A is set to pass through the driver circuit 111A during the first exposure, through the driver circuit 111B during the mth exposure, and through the driver circuit 111C during the nth exposure. The drive signal applied to the first readout control line 114B is set to pass through the driver circuit 111B during the first exposure, through the driver circuit 111C during the mth exposure, and through the driver circuit 111A during the nth exposure. The drive signal applied to the second readout control line 114C is set to pass through the driver circuit 111C during the first exposure, through the driver circuit 111A during the mth exposure, and through the driver circuit 111B during the nth exposure. When the temporal deviation of the driving circuit 111A is set to Δta, the temporal deviation of the driving circuit 111B is set to Δtb, and the temporal deviation of the driving circuit 111C is set to Δtc, the measured distance difference ΔZ1 of the pixel driven by the reset control line 114A, the measured distance difference ΔZ2 of the pixel driven by the first readout control line 114B, and the measured distance difference ΔZ3 of the pixel driven by the second readout control line 114C are as shown in the following equations (6) to (8).

[0197] [Number 6]

[0198]

[0199]

[0200]

[0201] When the number of exposures of the drive signal through the drive circuit 111A, the number of exposures of the drive signal through the drive circuit 111B, and the number of exposures of the drive signal through the drive circuit 111C are the same in the reset control line 114A, the first readout control line 114B, and the second readout control line 114C, l=m=n, and the measured distance differences ΔZ1, ΔZ2, and ΔZ3 are as shown in the following formula (9).

[0202] [Number 7]

[0203]

[0204] Therefore, the measured distance difference ΔZ1 of the pixel 101 driven by the reset control line 114A, the measured distance difference ΔZ2 of the pixel 101 driven by the first readout control line 114B, and the measured distance difference ΔZ3 of the pixel 101 driven by the second readout control line 114C are proportional to (Δta + Δtb + Δtc) / 3, which is the average of the temporal deviation Δta of all drive circuits 111A, the temporal deviation Δtb of drive circuit 111B, and the temporal deviation Δtc of drive circuit 111C. As a result, the temporal deviations of the reset control line 114A, the first readout control line 114B, and the second readout control line 114C are offset, achieving high distance measurement accuracy.

[0205] In addition, Figure 8 In FIG. 1 , a wiring replacement section 510d and 510e are inserted into the input side and the output side of the driver circuit array 110, and all the driver circuits 111 are replaced with other driver circuits 111. The present invention is not limited to this, and a configuration can also be made in which a part of the buffer elements 112 of the driver circuit 111 or a part of the wiring is replaced. For example, Figure 8 The wiring exchange portion 510d is inserted into the output line of the buffer element 112b instead of being inserted into the input line of the buffer element 112a.

[0206] exist Figure 8 In the embodiment, the wiring replacement section 510d may be replaced with the same circuit as the wiring replacement section 510e. In addition, the wiring replacement section 510e may be replaced with the same circuit as the wiring replacement section 510d.

[0207] In addition, Figure 7 and Figure 8 , an example is shown in which three electrode driving lines 114 are exchanged in each column, but the same effect can be obtained when two or four or more electrode driving lines 114 are exchanged.

[0208] As described above, in the solid-state imaging device 200 according to the third embodiment, the wiring replacement section 510 may include the selection circuit 530 or 531 for selecting a drive circuit to be replaced in response to a selection switching signal.

[0209] (Summarize)

[0210] As described above using the accompanying drawings, the solid-state imaging device 200 according to the embodiment includes: a photoelectric conversion unit 300 that converts received light into electric charges; a readout electrode (a first readout electrode 330 and a second readout electrode 350) that controls the readout of the electric charges generated by the photoelectric conversion unit 300; a reset electrode 310 that controls the discharge of the electric charges generated by the photoelectric conversion unit 300; a pixel array 100 that is formed by arranging a plurality of photoelectric conversion units 300, the readout electrodes, and the reset electrodes 310; and a readout control electrode. The control lines (the first readout control line 114B and the second readout control line 114C) drive the above-mentioned readout electrodes; the reset control line 114A drives the reset electrode 310; the driving circuit 111, in which at least two levels of buffer elements 112 are connected in multiple levels, applies driving pulses to the above-mentioned readout control lines and reset control line 114A; and the first wiring 113, in which the driving circuits 111 are arranged in columns, and the first wiring 113 short-circuits the outputs of at least two different columns of buffer elements 112.

[0211] In this configuration, a drive circuit 111 applies drive pulses to the electrodes of a plurality of pixels 101 arranged in a matrix via a readout control line and a reset control line 114A, thereby controlling the transfer of charge accumulated in the photoelectric converter 300. In the drive circuit 111, buffer elements 112 are connected in multiple stages, and the outputs of the buffer elements 112 between columns are electrically connected at low impedance via first wiring 113. As a result, the potentials between columns fluctuate in a uniform manner, minimizing delay differences.

[0212] Furthermore, the length of first wiring 113 is longer than the length of one of the four sides of the active area of ​​pixel 101 that is parallel to the first wiring. The further downstream the first wiring 113 is, the lower its impedance becomes. Furthermore, the further downstream the buffer element 112 is, the higher its driving capability becomes. Electrode drive lines 114 are independent for each column.

[0213] By short-circuiting two or more stages of the buffer element through first wiring 113, even if a potential difference occurs due to a delay difference between columns, the delay difference is minimal, thus shortening the period over which the potential difference occurs. Furthermore, the driving capability of the preceding buffer element 112 is low, resulting in less through-current. This reduces the risk of wiring burnout or damage to the buffer element 112. Furthermore, the impedance of the short-circuited first wiring 113 decreases as the stage approaches the buffer element 112, further reducing the risk of wiring burnout. As a result, first wiring 113 reduces the delay difference between each column of the drive signal caused by differences in the characteristics of the drive buffer or differences in parasitic components due to layout, without requiring calibration.

[0214] The driving circuit array 110 includes one or more wiring switching sections 510 that switch wiring of the driving circuit 111 with wiring of a driving circuit 111 in a different column. The wiring switching section 510 includes selection circuits 530 and 531 that can select a column to switch wiring in response to a selection switching signal.

[0215] By connecting two or more buffer elements 112 in different columns in multiple stages, delay differences can be reduced even when the drive signal phases differ, preventing short-circuiting the buffer elements 112 between columns. Delay differences between columns caused by layout variations or manufacturing variations in the drive circuit 111 are addressed by rerouting the drive signal paths, averaging the delay times between different drive signals. The selection circuit 530 can utilize multiple TOF exposures to average delay times by rerouting the drive signal paths during the exposure period, thus reducing delay differences between columns or between drive signals with different phases.

[0216] Industrial Applicability

[0217] As described above, the imaging device according to the present disclosure is useful as an imaging device that can suppress an increase in circuit scale, reduce the delay difference between each column of a drive signal without calibration, and achieve high ranging accuracy.

[0218] Description of reference numerals:

[0219] 100-pixel array

[0220] 101 pixels

[0221] 102 vertical signal lines

[0222] 110 driving circuit array

[0223] 111 drive circuit

[0224] 112, 112a, 112b, 112c buffer elements

[0225] 113, 113A~113F 1st wiring

[0226] 114 electrode drive line (control line)

[0227] 114A reset control line

[0228] 114B 1st readout control line

[0229] 114C 2nd readout control line

[0230] 120 Timing Generation Circuit

[0231] 130 AD conversion unit

[0232] 131 columns ADC

[0233] 132 memory array

[0234] 133 Output Circuit

[0235] 140 vertical scanning circuit

[0236] 150 light source driver

[0237] 160 Light Source

[0238] 170 lens

[0239] 180 signal processing circuit

[0240] 190 objects

[0241] 200 Solid-state imaging device

[0242] 300 Photoelectric Conversion Unit

[0243] 310 reset electrode

[0244] 320 Charge discharge unit

[0245] 330 1st readout electrode

[0246] 340 First charge storage unit

[0247] 350 Second readout electrode

[0248] 360 Second charge storage unit

[0249] 370 1st selection transistor

[0250] 380 Second selection transistor

[0251] 390 floating diffusion layer

[0252] 400 Reset transistor

[0253] 410 Source Follower

[0254] 510, 510a~510e wiring replacement unit

[0255] 530 selection circuit

[0256] 540 Select switching signal

[0257] 1000 Camera Device

Claims

1. A solid-state imaging device comprising: Multiple pixels are arranged in a matrix; A control line is provided for each pixel row or each pixel column and is connected to the pixels belonging to the corresponding pixel row or pixel column; a drive circuit provided for each of the control lines, including at least two stages of buffer elements connected in series, and outputting a control signal to the control line; and The first wiring short-circuits output lines of the buffer elements included in the corresponding different drive circuits at a certain stage in at least two of the drive circuits.

2. The solid-state imaging device according to claim 1, The first wiring is a wiring for averaging the delay of the control line for each row or column.

3. The solid-state imaging device according to claim 1 or 2, The plurality of pixels include optical black pixels and normal pixels other than the optical black pixels. The wiring length of the first wiring is longer than one side parallel to the first wiring among four sides of the effective area formed by the normal pixels.

4. The solid-state imaging device according to claim 1 or 2, The plurality of driving circuits include M driving circuit groups divided into M parts, where M is an integer greater than 2, The first wiring is provided for each of the M drive circuit groups and short-circuits output lines of the buffer elements included in the different drive circuits belonging to the drive circuit group.

5. The solid-state imaging device according to claim 4, One of the M drive circuit groups is composed of a drive circuit driven in a pixel thinning operation mode.

6. The solid-state imaging device according to claim 1 or 2, The first wiring is provided in two or more stages of the at least two stages of the buffer elements.

7. The solid-state imaging device according to claim 6, The impedance of the first wiring is lower than the impedance of the first wiring corresponding to the buffer element on the previous stage.

8. The solid-state imaging device according to claim 6, The wiring width of the first wiring is wider than the wiring width of the corresponding first wiring on the previous stage side.

9. The solid-state imaging device according to claim 1 or 2, The driving capability of the buffer element is higher than that of the buffer element on the preceding stage.

10. The solid-state imaging device according to claim 1 or 2, The pixel includes a photoelectric converter that converts light into electric charge, and a readout electrode for reading out the electric charge from the photoelectric converter. The control line is connected to the readout electrode.

11. The solid-state imaging device according to claim 1 or 2, The pixel has a reset electrode for resetting the charge in the pixel. The control line is connected to the reset electrode.

12. The solid-state imaging device according to claim 1 or 2, The pixel includes a photoelectric conversion portion for converting light into electric charge, a first readout electrode for reading out the electric charge from the photoelectric conversion portion, and a reset electrode for resetting the electric charge in the pixel. The control line includes, for each pixel column, a first readout control line connected to the first readout electrode and a reset control line connected to the reset electrode. The solid-state imaging device includes, for each pixel column, the drive circuit connected to the first readout control line and the drive circuit connected to the reset control line.

13. The solid-state imaging device according to claim 12, The pixel further includes a second readout electrode for reading out charges from the photoelectric conversion portion. The control line further includes a second readout control line connected to the second readout electrode for each pixel column. The solid-state imaging device further includes the driving circuit connected to the second readout control line for each pixel column.

14. The solid-state imaging device according to claim 1 or 2, comprising: The wiring switching unit crosses wirings between the driving circuits to substantially switch the buffer elements in the driving circuits with corresponding buffer elements of the same level in other driving circuits.

15. The solid-state imaging device according to claim 14, The wiring replacement section includes a selection circuit that selects a drive circuit to be replaced in response to a selection switching signal.

16. The solid-state imaging device according to claim 15, The solid-state imaging device includes two or more wiring replacement sections. The wiring switching portion is inserted into the input line or the output line of the at least two buffer elements of the plurality of driving circuits.

17. A camera device comprising: The solid-state imaging device according to any one of claims 1 to 16; and The signal processing circuit generates a distance image or a brightness image based on the signal received by the solid-state imaging device.

Images