Chip testing equipment and control method of chip testing equipment

Abstract

The embodiment of the present application discloses a chip testing device and a control method for the chip testing device. The chip testing device includes a power supply, a first testing device, a second testing device and a third testing device. The power supply is connected to the first testing device and the second testing device. The third testing device includes a temperature testing circuit. The third testing device is used to set the target audio chip. The temperature testing circuit is used to connect the target audio chip and provide a high-temperature operating environment and a normal-temperature operating environment for the target audio chip. The third testing device is also used to connect the first testing device or the second testing device through the target audio chip. When the first testing device is connected to the target audio chip, a high-temperature performance test of the target audio chip is performed. When the second testing device is connected to the target audio chip, a normal-temperature performance test of the target audio chip is performed. During the test process, interference from devices used to test other performances is avoided, thereby improving the reliability of the test results of the target audio chip.

Description

Technical Field

[0001] The present invention relates to the field of hardware testing, and in particular to a chip testing device and a control method for the chip testing device. Background Art

[0002] With the rapid development of chip technology, the performance requirements for audio chips are becoming increasingly stringent. Before an audio chip is put into use, it must undergo HTOL (High Temperature Operating Life) testing. Because EVBs (Evaluation Boards) are highly environmentally compatible, they are commonly used to perform HTOL testing on audio chips.

[0003] HTOL testing using a built-in EVB makes it difficult to fully test all functions of an audio chip. This typically requires the addition of third-party devices to provide a test environment that closely resembles the audio chip's actual application scenario. However, the inclusion of too many other devices increases the uncertainty of the audio chip's testing process, further impacting the reliability of the test results. Furthermore, there may be incompatibilities between the audio chip and other devices, further impacting the reliability of the test results. Summary of the Invention

[0004] In view of the defects of the prior art, the embodiment of the present application aims to provide a chip testing device and a control method for the chip testing device to solve the problem of how to improve the reliability of the test results of the audio chip.

[0005] In a first aspect, an embodiment of the present application provides a chip testing device, the chip testing device comprising a power supply, a first testing device, a second testing device, and a third testing device, wherein the power supply is connected to both the first testing device and the second testing device;

[0006] The third test device includes a temperature test circuit, the third test device is used to set the target audio chip, the temperature test circuit is used to connect to the target audio chip and provide a high temperature operating environment and a normal temperature operating environment for the target audio chip;

[0007] The third test device is further configured to connect to the first test device or the second test device via the target audio chip;

[0008] When the first testing device is connected to the target audio chip, a high-temperature performance test of the target audio chip is performed. When the second testing device is connected to the target audio chip, a normal-temperature performance test of the target audio chip is performed.

[0009] With reference to the first aspect, in a first possible implementation manner, the first testing device includes a first number of power managers, each of the power managers being connected to the power supply;

[0010] Each of the power managers is configured to connect to a second number of target audio chips and control the power states of the target audio chips.

[0011] In combination with the first aspect, in a second possible implementation manner, the first testing device includes an indicator;

[0012] The indicator is used to connect to the target audio chip and indicate whether the target audio chip is in an abnormal state.

[0013] With reference to the first aspect, in a third possible implementation manner, the second test device includes a chip configuration device and an audio analyzer, and the chip configuration device is connected to the audio analyzer;

[0014] The chip configuration device is used to connect to the target audio chip, configure the working mode of the target audio chip, and store the test audio data of the audio analyzer;

[0015] The audio analyzer is used to connect to the target audio chip and obtain test audio data of the target audio chip.

[0016] With reference to the first aspect, in a fourth possible implementation manner, the third testing device includes a connection identifier;

[0017] One end of the connection identifier is used to connect to the first test device or the second test device, and the other end of the connection identifier is used to connect to the target audio chip;

[0018] The connection identifier is used to identify the first test device or the second test device connected to the target audio chip.

[0019] In combination with the first aspect, in a fifth possible implementation, the temperature testing circuit includes a high temperature testing circuit and a normal temperature testing circuit;

[0020] The high temperature test circuit is used to connect to the target audio chip and provide a high temperature operating environment for the target audio chip;

[0021] The normal temperature test circuit is used to connect to the target audio chip and provide a normal temperature operating environment for the target audio chip.

[0022] In combination with the fifth possible implementation manner of the first aspect, in a sixth possible manner, the high temperature test circuit includes a DAC circuit and an ADC circuit;

[0023] One end of the DAC circuit is used to connect to the target audio chip, and the other end of the DAC circuit is used to connect to the target audio chip through the ADC circuit.

[0024] In combination with the fifth possible implementation manner of the first aspect, in a seventh possible manner, the high-temperature test circuit includes a DLP circuit and a SARADC circuit;

[0025] One end of the DLP circuit is used to connect to the target audio chip, and the other end of the DLP circuit is used to connect to the target audio chip through the SARADC circuit.

[0026] In a second aspect, an embodiment of the present application provides a method for controlling a chip testing device, wherein the chip testing device is the chip testing device according to the first aspect, the method comprising:

[0027] placing the target audio chip in the third testing device;

[0028] Connecting the first test device to a target audio chip provided in the third test device, performing a high temperature performance test on the target audio chip, and obtaining high temperature performance data of the target audio chip;

[0029] The second test device is connected to the target audio chip provided in the third test device, and a normal temperature performance test of the target audio chip is performed to obtain normal temperature performance data of the target audio chip.

[0030] In conjunction with the second aspect, in a first possible implementation manner, the method further includes:

[0031] The high temperature performance data or the normal temperature performance data of the target audio chip is stored based on a preset time interval.

[0032] The present application provides a chip testing device, which includes a power supply, a first test device, a second test device, and a third test device. The power supply is connected to both the first test device and the second test device. The third test device includes a temperature test circuit. The third test device is used to set a target audio chip. The temperature test circuit is used to connect to the target audio chip and provide a high-temperature operating environment and a normal-temperature operating environment for the target audio chip. The third test device is also used to connect to the first test device or the second test device through the target audio chip. When the first test device is connected to the target audio chip, a high-temperature performance test of the target audio chip is performed. When the second test device is connected to the target audio chip, a normal-temperature performance test of the target audio chip is performed. The third test device chooses to connect to the first test device or the second test device through the target audio chip, thereby avoiding interference from devices used to test other performance during the test process. At the same time, the power and signal required by the temperature test circuit are provided by the target audio chip, further avoiding interference factors from other devices and improving the reliability of the test results of the target audio chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solution of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope of protection of the present invention. In each of the drawings, similar components are numbered similarly.

[0034] Figure 1 A first structural diagram of a chip testing device provided in an embodiment of the present application is shown;

[0035] Figure 2 A schematic structural diagram of a first testing device provided in an embodiment of the present application is shown;

[0036] Figure 3 A schematic structural diagram of a second testing device provided in an embodiment of the present application is shown;

[0037] Figure 4 A second structural diagram of a chip testing device provided in an embodiment of the present application is shown;

[0038] Figure 5 A schematic structural diagram of a third testing device provided in an embodiment of the present application is shown;

[0039] Figure 6 A flow chart of a method for controlling a chip testing device provided by an embodiment of the present invention is shown.

[0040] Description of main component symbols:

[0041] 10-Chip testing equipment; 100-Power supply, 200-First test device, 300-Second test device, 400-Third test device, 500-Target audio chip; 210-Power manager, 220-Indicator; 310-Chip configuration device, 320-Audio analyzer; 410-Temperature test circuit, 420-Connection identifier; 4111-DAC circuit, 4112-ADC circuit, 4113-DLP circuit, 4114-SARADC circuit. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0043] The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the figures is not intended to limit the scope of the claimed invention, but rather merely represents selected embodiments of the present invention. All other embodiments derived by those skilled in the art based on the embodiments of the present invention without inventive effort are intended to be within the scope of protection of the present invention.

[0044] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present invention, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0045] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present invention pertain. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present invention.

[0047] Example 1

[0048] See also Figure 1 , Figure 1The first structural diagram of the chip testing device provided in the embodiment of the present application is shown. Figure 1 The chip testing device 10 includes a power supply 100, a first testing device 200, a second testing device 300 and a third testing device 400, wherein the power supply 100 is connected to the first testing device 200 and the second testing device 300;

[0049] The third test device 400 includes a temperature test circuit 410. The third test device 400 is used to set the target audio chip 500. The temperature test circuit 410 is used to connect to the target audio chip 500 and provide a high-temperature operating environment and a normal-temperature operating environment for the target audio chip 500.

[0050] The third testing device 400 is further configured to connect to the first testing device 200 or the second testing device 300 via the target audio chip 500;

[0051] When the first testing device 200 is connected to the target audio chip 500 , a high temperature performance test of the target audio chip 500 is performed. When the second testing device 300 is connected to the target audio chip 500 , a normal temperature performance test of the target audio chip 500 is performed.

[0052] The temperature test circuit 410 is used to provide a temperature operating environment for the target audio chip 500, wherein the target audio chip 500 is any audio chip that needs to be tested and is not limited here. When a high-temperature performance test of the target audio chip 500 is required, the temperature test circuit 410 provides a high-temperature operating environment. When a normal-temperature performance test of the audio chip is required, the temperature test circuit 410 provides a normal-temperature operating environment. By providing a temperature environment that meets the actual operation requirements of the target audio chip 500, it is easier to determine whether the target audio chip 500 has any abnormalities.

[0053] The first test device 200 provides a device for testing the high-temperature performance of the target audio chip 500. When the first test device 200 is connected to the target audio chip 500, it constitutes a high-temperature test circuit for the target audio chip 500. The second test device 300 provides a device for testing the normal-temperature performance of the target audio chip 500. When the second test device 300 is connected to the target audio chip 500, it constitutes a normal-temperature test circuit for the target audio chip 500. When the high-temperature performance test of the target audio chip 500 is performed, it complies with the high-temperature operating environment of the target audio chip 500, avoiding the influence of other devices such as the second test device 300. When the normal-temperature performance test of the target audio chip 500 is performed, it complies with the normal-temperature operating environment of the target audio chip 500, avoiding the influence of other devices such as the first test device 200. By reducing the interference factors of other devices, the reliability of the test results of the target audio chip 500 is improved.

[0054] The target audio chip 500 is placed in the third test apparatus 400 and connected to the power supply 100 via the first test apparatus 200 or the second test apparatus 300. The target audio chip 500 is then powered on. The power and signals required by the temperature test circuit 410 are both provided by the target audio chip 500, reducing interference from other factors and further improving the reliability of the test results for the target audio chip 500.

[0055] Please also refer to Figure 2 , Figure 2 The first test device 200 includes a first number of power managers 210, each of which is connected to the power supply 100;

[0056] Each of the power managers 210 is configured to connect to a second number of target audio chips 500 and control the power supply 100 status of the target audio chips 500 .

[0057] The target audio chip 500 undergoes a high-temperature performance test, and the first test device 200 supplies power to the target audio chip 500 via the power manager 210. The first test device 200 does not include any other devices for detecting specific performance of the target audio chip 500, thereby reducing interference factors during the test.

[0058] The first test device 200 can be connected to multiple target audio chips 500 at the same time to improve the test efficiency of the target audio chip 500. Multiple third test devices 400 can be set in the first test device 200 to provide accommodation space for the target audio chip 500, which will not be described in detail here. In the present application, the first test device 200 includes a first number of power managers 210, and each of the power managers 210 is used to connect a second number of target audio chips 500. When some of the target audio chips 500 are abnormal, the power manager 210 connected to the abnormal target audio chip 500 is determined, and the abnormal target audio chip 500 is disconnected from the power supply 100 through the power manager 210, and the other power managers 210 continue to supply power. It should be understood that the first quantity and the second quantity are set according to actual needs and are not limited here.

[0059] In this embodiment, the first testing device 200 includes an indicator 220;

[0060] The indicator 220 is used to connect to the target audio chip 500 and indicate whether the target audio chip 500 is in an abnormal state.

[0061] The indicator 220 is used to indicate whether the target audio chip 500 is in an abnormal state. When the target audio chip 500 is in an abnormal state, the power supply to the target audio chip 500 is cut off to avoid electrical accidents. It should be understood that the indicator 220 can be any device that can indicate the status of the target audio chip 500, and can be an indicator light, a display screen, etc., which is not limited here. In this embodiment, the indicator 220 is an indicator light, and whether the target audio chip 500 is in an abnormal state can be determined by the color of the light emitted by the indicator 220, the on and off state, the flashing state, etc., which will not be elaborated here.

[0062] Please also refer to Figure 3 , Figure 3 The second test device 300 includes a chip configuration device 310 and an audio analyzer 320, wherein the chip configuration device 310 is connected to the audio analyzer 320;

[0063] The chip configuration device 310 is used to connect to the target audio chip 500, configure the working mode of the target audio chip 500, and store the test audio data of the audio analyzer 320;

[0064] The audio analyzer 320 is used to connect to the target audio chip 500 and obtain test audio data of the target audio chip 500 .

[0065] When the second test device 300 is connected to the third test device 400, the audio analyzer 320 and chip configuration device 310 are both connected to the target audio chip 500. The power supply 100, chip configuration device 310, audio analyzer 320, and temperature test circuit 410 form a normal-temperature test circuit for the target audio chip 500, eliminating interference from other components and improving the reliability of the test results for the target audio chip 500.

[0066] It should be understood that the type of chip configuration device 310 is selected based on actual needs and can be a host computer, etc., and is not limited here. The type of audio analyzer 320 is also selected based on actual needs and is not limited here. The chip configuration device 310 is used to control the target audio chip 500 to perform a specific operating mode, control the audio analyzer 320 to obtain test audio data from the target audio chip 500, and store the test audio data.

[0067] Please also refer to Figure 4 , Figure 4 A second structural diagram of a chip testing device provided in an embodiment of the present application is shown. The third testing device 400 includes a connection identifier 420;

[0068] One end of the connection identifier 420 is used to connect to the first test device 200 or the second test device 300, and the other end of the connection identifier 420 is used to connect to the target audio chip 500;

[0069] The connection identifier 420 is configured to identify the first test device 200 or the second test device 300 connected to the target audio chip 500 .

[0070] It should be understood that the connection identifier 420 is compatible with connecting to either the first test device 200 or the second test device 300, but not both simultaneously. The connection identifier 420 is used to identify the first test device 200 or the second test device 300 connected to the target audio chip 500. When the first test device 200 is connected to the connection identifier 420, the connection identification information is fed back to the target audio chip 500 to perform a high-temperature performance test on the target audio chip 500. When the second test device 300 is connected to the connection identifier 420, the connection identification information is fed back to the target audio chip 500 to perform a room-temperature performance test on the target audio chip 500.

[0071] The temperature testing circuit 410 includes a high temperature testing circuit and a normal temperature testing circuit;

[0072] The high temperature test circuit is used to connect to the target audio chip 500 and provide a high temperature operating environment for the target audio chip 500;

[0073] The normal temperature test circuit is used to connect to the target audio chip 500 and provide a normal temperature operating environment for the target audio chip 500 .

[0074] The third test device 400 includes a high-temperature test circuit for providing a high-temperature operating environment and a high-temperature test circuit for providing a normal-temperature operating environment. By connecting the first test device 200 with the third test device 400, a high-temperature performance test of the target audio chip 500 can be performed. By connecting the second test device 300 with the third test device 400, a normal-temperature performance test of the target audio chip 500 can be performed. Since the third test device 400 provides circuits for both high-temperature and normal-temperature test environments, there is no need to change the circuit configuration when switching between high-temperature and normal-temperature tests, which simplifies the test operation process and improves the test efficiency of the target audio chip 500.

[0075] The high temperature test circuit includes a DAC circuit 4111 and an ADC circuit 4112;

[0076] One end of the DAC circuit 4111 is used to connect to the target audio chip 500 , and the other end of the DAC circuit 4111 is used to connect to the target audio chip 500 through the ADC circuit 4112 .

[0077] The DAC (Digital to analog converter) circuit 4111, the ADC (analog to digital converter) circuit 4112 and the target audio chip 500 constitute a loopback test circuit of the target audio chip 500. The DAC circuit 4111 is used to obtain an audio signal and output the audio signal to the ADC circuit 4112. The ADC circuit 4112 is used to parse and verify the audio signal output by the DAC circuit 4111. It should be understood that the number of channels of the DAC circuit 4111 and the ADC circuit 4112 is set according to actual needs and is not limited here. The parsing of the data can be completed through time-sharing operation, and the operating mode of the DAC circuit 4111 and the ADC circuit 4112 is also set according to actual needs, which can be a single-ended mode or a differential mode, which is not limited here.

[0078] Please also refer to Figure 5 , Figure 5 The schematic diagram of the structure of the third test device provided in the embodiment of the present application is shown. The high temperature test circuit includes a DLP circuit 4113 and a SARADC circuit 4114;

[0079] One end of the DLP circuit 4113 is used to connect to the target audio chip 500 , and the other end of the DLP circuit 4113 is used to connect to the target audio chip 500 through the SARADC circuit 4114 .

[0080] The DLP (Digital Light Porsessor) circuit 4113, the SARADC (Successive Approximation Analog to Digital Converter) circuit 4114, and the target audio chip 500 constitute the voltage test circuit of the target audio chip 500. The DLP circuit 4113 can receive digital signals or analog signals. After the signal output by the target audio chip 500 is divided by the DLP circuit 4113, the DLP circuit 4113 inputs the voltage signal to the SARADC circuit 4114. The SARADC circuit 4114 collects and identifies the voltage signal input by the DLP circuit 4113, identifies the preset voltage value, and reports it to the target audio chip 500. Based on the voltage value reported to the target audio chip 500, it is determined whether the voltage is abnormal.

[0081] Example 2

[0082] See also Figure 6 , Figure 6 FIG1 is a flow chart showing a control method of a chip test device according to an embodiment of the present invention. In this embodiment, the chip test device 10 is the chip test device 10 described in embodiment 1. Figure 6 The control method of the chip testing device 10 includes the following steps:

[0083] Step 610 : Place the target audio chip 500 in the third testing device 400 .

[0084] Because the temperature test circuit 410 provides both high-temperature and normal-temperature operating environments for the target audio chip 500, the target audio chip 500 can be tested by simply placing the target audio chip 500 in the third test apparatus 400 and connecting the third test apparatus 400 to the first test apparatus 200 or the second test apparatus 300. Switching between high-temperature and normal-temperature testing eliminates the need to change circuit configuration, simplifying the test process and improving testing efficiency for the target audio chip 500.

[0085] The target audio chip 500 can burn and store two sets of test programs, one set of test programs is used for high temperature performance testing, and the other set of test programs is used for normal temperature performance testing. The target audio chip 500 can also burn and store only one set of test programs to reduce the time spent on burning the test programs. It should be understood that the test program is written according to actual needs and will not be elaborated here. In this embodiment, the test program is the HTOL test code. When performing high temperature performance testing of the target audio chip 500, the test program is to keep the modules in the chip running at high intensity, and the chip and the temperature test circuit 410 are looped together to verify and cooperate with each other. When performing normal temperature performance testing of the target audio chip 500, the test program is compatible with ATE (Automatic Test Equipment) code, and can efficiently complete the normal temperature performance testing of the target audio chip 500.

[0086] Step 620 , connecting the first test device 200 to the target audio chip 500 provided in the third test device 400 , performing a high temperature performance test on the target audio chip 500 , and obtaining high temperature performance data of the target audio chip 500 .

[0087] The target audio chip 500 can automatically switch between high-temperature and normal-temperature test modes. When the first test device 200 is connected to the target audio chip 500 located in the third test device 400, the target audio chip 500 switches to high-temperature test mode to perform a high-temperature performance test on the target audio chip 500. During this high-temperature performance test, the target audio chip 500 is not connected to the second test device 300 performing normal-temperature testing, thus avoiding interference from other devices and improving the reliability of the test results for the target audio chip 500.

[0088] Step 630 , connecting the second test device 300 to the target audio chip 500 provided in the third test device 400 , performing a normal temperature performance test of the target audio, and obtaining normal temperature performance data of the target audio chip 500 .

[0089] When the second test device 300 is connected to the target audio chip 500 located in the third test device 400, the target audio chip 500 switches to a normal temperature test mode and performs a normal temperature performance test on the target audio chip 500. During the normal temperature performance test of the target audio chip 500, the target audio chip 500 is not connected to the first test device 200 performing a high temperature test, thereby avoiding interference from other devices and improving the reliability of the test results of the target audio chip 500.

[0090] When testing the target audio chip 500, the first test device 200 or the second test device 300 acts as the host device, and the third test device 400 acts as the device device. After the host device connects to the device, the device actively powers on to initiate the test. After receiving the correct descriptor, the host device sends a feedback signal to the device. Based on the received feedback signal, the device completes a valid communication. The device actively disconnects from the host device and waits until the next test time to start a new test round.

[0091] As an example, the method further includes:

[0092] The high temperature performance data or the normal temperature performance data of the target audio chip 500 is stored based on a preset time interval.

[0093] The target audio chip 500's built-in memory can store high-temperature or room-temperature performance data in real time. This data, such as the number of runs and abnormal interruptions of the target audio chip 500, is recorded at preset intervals. By storing high-temperature or room-temperature performance data, data during the testing of the target audio chip 500 is traceable, allowing for quick identification of abnormal conditions in the target audio chip 500.

[0094] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or flowchart, and the combination of boxes in the structure diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0095] In addition, the functional modules or units in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0096] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0097] The above description is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be covered by the scope of protection of the present invention.

Claims

1. A chip testing device, characterized in that: The chip testing device includes a power supply, a first testing device, a second testing device and a third testing device, wherein the power supply is connected to the first testing device and the second testing device; The third test device includes a temperature test circuit, the third test device is used to set the target audio chip, the temperature test circuit is used to connect to the target audio chip and provide a high temperature operating environment and a normal temperature operating environment for the target audio chip; The third test device is further configured to connect to the first test device or the second test device via the target audio chip; When the first testing device is connected to the target audio chip, a high-temperature performance test of the target audio chip is performed; when the second testing device is connected to the target audio chip, a normal-temperature performance test of the target audio chip is performed; The third test device also includes a connection identifier; one end of the connection identifier is used to connect to the first test device or the second test device, and the other end of the connection identifier is used to connect to the target audio chip; the connection identifier is used to identify the first test device or the second test device connected to the target audio chip.

2. The chip testing device according to claim 1, characterized in that: The first test device includes a first number of power managers, each of the power managers being connected to the power supply; Each of the power managers is configured to connect to a second number of target audio chips and control the power states of the target audio chips.

3. The chip testing device according to claim 1, characterized in that: The first testing device includes an indicator; The indicator is used to connect to the target audio chip and indicate whether the target audio chip is in an abnormal state.

4. The chip testing device according to claim 1, characterized in that: The second test device includes a chip configuration device and an audio analyzer, wherein the chip configuration device is connected to the audio analyzer; The chip configuration device is used to connect to the target audio chip, configure the working mode of the target audio chip, and store the test audio data of the audio analyzer; The audio analyzer is used to connect to the target audio chip and obtain test audio data of the target audio chip.

5. The chip testing device according to claim 1, characterized in that: The temperature testing circuit includes a high temperature testing circuit and a normal temperature testing circuit; The high temperature test circuit is used to connect to the target audio chip and provide a high temperature operating environment for the target audio chip; The normal temperature test circuit is used to connect to the target audio chip and provide a normal temperature operating environment for the target audio chip.

6. The chip testing device according to claim 5, characterized in that: The high temperature test circuit includes a DAC circuit and an ADC circuit; One end of the DAC circuit is used to connect to the target audio chip, and the other end of the DAC circuit is used to connect to the target audio chip through the ADC circuit.

7. The chip testing device according to claim 5, characterized in that: The high temperature test circuit includes a DLP circuit and a SARADC circuit; One end of the DLP circuit is used to connect to the target audio chip, and the other end of the DLP circuit is used to connect to the target audio chip through the SARADC circuit.

8. A control method for a chip testing device, characterized in that: The chip testing device is a chip testing device according to any one of claims 1 to 7, and the method includes: placing the target audio chip in the third testing device; Connecting the first test device to a target audio chip provided in the third test device, performing a high temperature performance test on the target audio chip, and obtaining high temperature performance data of the target audio chip; The second test device is connected to the target audio chip provided in the third test device, and a normal temperature performance test of the target audio chip is performed to obtain normal temperature performance data of the target audio chip.

9. The control method of chip testing equipment according to claim 8, characterized in that: The method further comprises: The high temperature performance data or the normal temperature performance data of the target audio chip is stored based on a preset time interval.

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