Wafer bonding alignment method and apparatus

Abstract

The application discloses a wafer bonding alignment method and device, and the method comprises the following steps: providing a first wafer carrier and a second wafer carrier, the first wafer carrier carries a first wafer, the second wafer carrier carries a second wafer, the second wafer and the first wafer are arranged in parallel, a laser emitter on the first wafer carrier emits laser towards the second wafer carrier; a photodetector on the second wafer carrier obtains light flux; according to the light flux, the first wafer carrier or the second wafer carrier is controlled to move to a set position in the horizontal direction, so that the first wafer and the second wafer are aligned. The method can improve the alignment accuracy of wafer bonding.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and in particular to a wafer bonding alignment method and device thereof. BACKGROUND

[0002] Three-Dimensional Integrated Circuit (3D-IC) refers to a three-dimensional integrated circuit structure with interconnections in the vertical direction formed by chip stacking. With the continuous improvement of chip integration, simply reducing the critical dimension (CD) of semiconductor devices has approached the physical limit. In order to achieve higher integration and device capacity, three-dimensional integrated circuit technology is increasingly applied in the field of chip manufacturing. Compared with two-dimensional integrated circuits, three-dimensional integrated circuits greatly shorten the interconnection length, have higher bandwidth, lower parasitic capacitance and interconnection delay, and lower power consumption, etc.

[0003] In the field of three-dimensional integrated circuit manufacturing, wafer-level direct bonding interconnection is a key technology for multi-layer chip stacking. Among them, the bonding alignment accuracy is an important indicator, which has a direct impact on yield and reliability. In addition, higher precision alignment means that higher density bonding interconnection can be achieved, which can be used for interconnection of smaller critical dimension devices.

[0004] At present, the existing technology determines the wafer relative offset by image recognition, and the alignment accuracy is limited by the optical resolution and depth of field of the imaging system. In addition, due to the limitation of the imaging light path, i.e. the upper and lower lenses need to be aligned, the existing technology cannot detect the alignment marks of the upper and lower wafers at the same time, and needs to move the stage to move the upper and lower wafers to the detection position respectively, resulting in that the wafer alignment accuracy is affected by the return error of the mechanical moving parts, and the alignment deviation cannot be dynamically adjusted in real time during the bonding process. Therefore, the alignment accuracy of the traditional alignment mark alignment method is usually above 0.2 μm, it is difficult to achieve sub-micron to nanometer level high-precision alignment, and it cannot meet the manufacturing requirements of ultra-fine pitch interconnection three-dimensional integrated circuits.

[0005] Therefore, it is urgent to provide a new bonding alignment scheme to improve the above problems. SUMMARY

[0006] The embodiments of the present application provide a wafer bonding alignment method and device thereof to improve the alignment accuracy of wafer bonding.

[0007] In a first aspect, the present application provides a wafer bonding alignment method, which comprises: providing a first wafer carrier and a second wafer carrier, the first wafer carrier carrying a first wafer, the second wafer carrier carrying a second wafer, the second wafer and the first wafer being arranged in parallel to each other; controlling a laser emitter located on the first wafer carrier to emit laser towards the second wafer carrier; obtaining light flux from a photodetector located on the second wafer carrier; and controlling the first wafer carrier or the second wafer carrier to move to a set position in a horizontal direction so that the first wafer and the second wafer are aligned, according to the light flux; wherein the first wafer and the second wafer are each provided with a light-transmitting structure, the light-transmitting structure having a light-transmitting region allowing the laser to pass through the first wafer and the second wafer to reach the photodetector, the size of the light-transmitting region being determined by the amount of horizontal displacement between the first wafer carrier and the second wafer carrier.

[0008] The wafer bonding alignment method provided by the present application has the advantages that: the degree of wafer alignment deviation can be determined by reading the size of the light flux received by the photodetector, the alignment precision of wafer bonding can be improved, high-precision alignment can be achieved, the alignment precision can reach 20 nm, and nanometer-level high-precision alignment is achieved. In addition, the light-transmitting structure is arranged on the wafer, no through hole needs to be made on the wafer carrier, and no precise imaging system is needed, so the requirements for equipment manufacturing are low and the method is easy to implement.

[0009] In a possible implementation, the first wafer and the second wafer are controlled to be coarsely aligned by image recognition; and the first wafer carrier or the second wafer carrier is controlled to move vertically to a target position so that the distance between the first wafer and the second wafer meets a set threshold. In this implementation, coarse alignment is performed before high-precision alignment, and the purpose of coarse alignment is to prevent misjudgment. Because of the characteristics of the alignment mark array arrangement, there is more than one extreme value of light flux change with displacement, and too large initial alignment deviation may lead to misjudgment of the degree of deviation.

[0010] In another possible implementation, after the first wafer carrier or the second wafer carrier is controlled to move to a set position in a horizontal direction, the method further comprises: controlling the first wafer and the second wafer to be bonded. This alignment method is intuitive and easy to implement, and has no requirements for wafer substrates, so it is widely used in wafer-level alignment and bonding processes.

[0011] In other possible embodiments, the step of controlling the first wafer stage or the second wafer stage to move to a set position in a horizontal direction according to the light flux includes: controlling the first wafer stage or the second wafer stage to displace multiple times in a horizontal direction, recording the displacement amount between the first wafer stage and the second wafer stage after each displacement, and obtaining the light flux from the photodetector after each displacement; determining the displacement amount corresponding to the minimum light flux as the minimum displacement amount according to the multiple displacement amounts and the multiple light fluxes corresponding to the multiple displacement amounts; and controlling the first wafer stage or the second wafer stage to move to a set position in a horizontal direction such that the displacement amount between the first wafer stage and the second wafer stage is the minimum displacement amount.

[0012] In another possible embodiment, the step of obtaining the light flux from the photodetector located on the second wafer stage includes:

[0013] The first alignment mark is arranged on the first wafer, the second alignment mark is arranged on the second wafer, and the light-transmitting region formed by the first alignment mark and the second alignment mark. The light flux is obtained from the photodetector located on the second wafer stage. The position of the laser emitter satisfies that the emitted laser falls on the first alignment mark. The first alignment mark and the second alignment mark are configured such that when the first wafer and the second wafer are aligned, the first alignment mark and the second alignment mark form an opaque pattern, the transmittance of the opaque pattern to laser is minimum, and the light flux detected by the photodetector is minimum.

[0014] In a second aspect, the present application further provides a wafer bonding alignment device, which comprises a first wafer stage and a second wafer stage, the first wafer stage carries a first wafer, the second wafer stage carries a second wafer, the second wafer and the first wafer are arranged in parallel to each other; a laser emitter located on the first wafer stage and a photodetector located on the second wafer stage; a driving part, a memory and a control part; the laser emitter of the first wafer stage is used for emitting laser; the photodetector is used for detecting light flux;

[0015] The control part is used for performing the following processing:

[0016] The laser emitter located on the first wafer stage is controlled to emit laser towards the second wafer stage;

[0017] The light flux is obtained from the photodetector located on the second wafer stage;

[0018] The driving part is controlled to drive the first wafer stage or the second wafer stage to move to a set position in a horizontal direction according to the light flux, so that the first wafer and the second wafer are aligned.

[0019] The first wafer and the second wafer are provided with light-transmitting structures, and the light-transmitting structures have light-transmitting areas that allow the laser to pass through the first wafer and the second wafer to reach the photodetector, and the size of the light-transmitting areas is determined by the amount of horizontal displacement between the first wafer stage and the second wafer stage.

[0020] In a possible implementation, the control unit is further configured to control a mechanical movement component of the second wafer stage and a corresponding optical imaging module that performs coarse alignment of the first wafer and the second wafer.

[0021] Before the laser emitter located on the first wafer stage emits the laser, the control unit is further configured to control the optical imaging module to perform coarse alignment of the first wafer and the second wafer by image recognition.

[0022] The control unit controls vertical movement of the first wafer stage or the second wafer stage to a target position, so that the distance between the first wafer and the second wafer meets a set threshold.

[0023] In another possible implementation, after the control unit controls the driving unit to drive the first wafer stage or the second wafer stage to move to a set position in the horizontal direction, the control unit is further configured to control wafer bonding of the first wafer and the second wafer.

[0024] In a possible implementation, the control unit controls the driving unit to drive the first wafer stage or the second wafer stage to move to a set position in the horizontal direction according to the light flux, and specifically controls:

[0025] The control unit controls the driving unit to drive the first wafer stage or the second wafer stage to move multiple times in the horizontal direction, controls the memory to record the displacement amount between the first wafer stage and the second wafer stage after each displacement, and controls the photodetector to obtain the light flux after each displacement. The control unit obtains the minimum displacement amount corresponding to the minimum light flux from multiple displacement amounts and corresponding light fluxes, and controls the driving unit to drive the first wafer stage or the second wafer stage to move to the position where the displacement amount between the first wafer stage and the second wafer stage is the minimum displacement amount.

[0026] In other possible embodiments, the control unit acquires the light flux from the photodetector located on the second wafer stage by: the first wafer being provided with first alignment marks, the second wafer being provided with second alignment marks, and the light flux being acquired from the photodetector located on the second wafer stage through a light-transmissive region formed by the first and second alignment marks; wherein the position of the laser emitter satisfies that the emitted laser light falls on the first alignment marks, and the first and second alignment marks are configured such that when the first and second wafers are aligned, the first and second alignment marks form an opaque pattern, and the opaque pattern has a minimum transmittance to the light emitted by the light source, so that the light flux detected by the photodetector is minimum.

[0027] In another possible embodiment, the first alignment marks are located in the metal interconnection layer of the first wafer, the second alignment marks are located in the metal interconnection layer of the second wafer, and when the first and second wafers are misaligned, the first and second alignment marks are transparent to the laser light emitted by the laser emitter in the direction perpendicular to the substrate of the first wafer.

[0028] The first and second alignment marks are a set of mutually nested patterns; when the first and second wafers are aligned, the projections of the first and second alignment marks in the direction perpendicular to the substrate form an opaque region without gaps; and when the first and second wafers are misaligned, the projections of the first and second alignment marks in the direction perpendicular to the substrate are not completely nested, forming a partially light-transmissive region.

[0029] In another possible embodiment, the first alignment marks are a dot-matrix arranged rectangular pattern, and the second alignment marks are an interlaced line pattern, wherein the size and spacing of the hollow regions enclosed by each line in the line pattern and each rectangular pattern of the first alignment marks are consistent, and the two sets of marks overlap to form a complete large rectangle.

[0030] In a possible embodiment, the size of the rectangle is 5 μm x 5 μm, the spacing in the X and Y directions is 10 μm, and the dot matrix has a size of 25 mm x 30 mm.

[0031] In other possible embodiments, the first alignment marks are placed in the non-patterned region of the edge of the first wafer, and the second alignment marks are placed in the non-patterned region of the same position of the edge of the second wafer, and the first and second alignment marks occupy the area of a chip.

[0032] In other possible implementations, the first alignment mark and the second alignment mark are a set of gratings that satisfy the linear polarization extinction condition. Grating-type alignment marks are more sensitive to rotational misalignment.

[0033] In other possible implementations, the first alignment mark and the second alignment mark are gratings composed of dense metal lines, the grating constant of which satisfies the near-infrared light diffraction condition.

[0034] For the beneficial effects of the device provided in the second aspect, please refer to the beneficial effects described in the first aspect. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 A schematic diagram of an alignment structure including two wafers is provided for an embodiment of the present invention;

[0037] Figure 2 A set of alignment marks is provided as an embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of another set of alignment marks of grating type provided in an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of a wafer alignment structure based on grating-type alignment marks provided in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of a wafer bonding alignment device provided in an embodiment of the present invention;

[0041] Figure 6 This is a schematic flowchart of a wafer bonding alignment method provided in an embodiment of the present invention;

[0042] Figure 7 Based on Figure 6 The diagram shows a wafer bonding alignment method flow chart that includes two processes: coarse alignment and fine alignment.

[0043] Figure 8 This is a schematic diagram of the X-direction wafer alignment process provided in an embodiment of the present invention;

[0044] Figure 9 This is a schematic diagram illustrating the relationship between luminous flux and X-direction offset between wafers, provided as an embodiment of the present invention.

[0045] Figure label explanation:

[0046] 101 First wafer; 102 Second wafer; 103 Metal interconnect layer; 104 First alignment mark; 105 Second alignment mark; 106 Laser emitter; 107 Photodetector;

[0047] 501 First wafer stage; 502 Second wafer stage; 503 Driving unit; 504 Control unit;

[0048] 5041 Control Unit; 5042 Processor; 5043 Memory Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be described below with reference to the accompanying drawings. In the description of the embodiments of the present invention, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to limit the present invention. As used in the specification and appended claims of the present invention, the singular expressions “a,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of the present invention, “at least one” and “one or more” refer to one or more (including two). The term “and / or” is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character “ / ” generally indicates that the preceding and following related objects are in an “or” relationship.

[0050] References to "one embodiment" or "some embodiments" as used in this specification mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in one or more embodiments of the invention. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically emphasized. The term "connection" includes both direct and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0051] In embodiments of the present invention, the terms "exemplarily" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplarily" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the terms "exemplarily" or "for example" is intended to present the relevant concepts in a specific manner.

[0052] like Figure 1 As shown, Figure 1 A schematic diagram illustrating an alignment structure comprising two wafers is provided, wherein the second wafer 102 and the first wafer 101 are arranged parallel to each other. Both the first wafer 101 and the second wafer 102 have light-transmitting structures, which have light-transmitting areas that allow the laser to pass through the first wafer 101 and the second wafer 102 to reach the photodetector 107. Figure 1 As shown, the light-transmitting structure can be a set of alignment marks. Alignment marks are formed in specific areas on the substrates of the first wafer 101 and the second wafer 102. Specifically, a first alignment mark 104 is formed in a specific area on the substrate of the first wafer 101, and a second alignment mark 105 is formed in a specific area on the substrate of the second wafer 102. The first alignment mark 104 is located within the metal interconnect layer 103 of the first wafer 101, and the second alignment mark 105 is located within the metal interconnect layer 103 of the second wafer 102. The first alignment mark 104 has no obstructing pattern in the direction perpendicular to the substrate of the first wafer 101 and is transparent to infrared light. The second alignment mark 105 has no obstructing pattern in the direction perpendicular to the substrate of the second wafer 102 and is transparent to infrared light.

[0053] In one possible implementation, the first alignment mark 104 on the first wafer 101 and the second alignment mark 105 on the second wafer 102 can be a set of nested patterns. When the first wafer 101 and the second wafer 102 are perfectly aligned, the projections of the first alignment mark 104 and the second alignment mark 105 in the direction perpendicular to the substrate form a gapless opaque region; when the first wafer 101 and the second wafer 102 are misaligned, the projections of the first alignment mark 104 and the second alignment mark 105 in the direction perpendicular to the substrate are not completely nested, forming a partially infrared transparent region.

[0054] in addition, Figure 1A laser emitter 106, which can be a near-infrared laser source, is disposed on the back side of the first wafer 101. A photodetector 107 is disposed at a corresponding position on the back side of the second wafer 102, so that the laser beam emitted by the laser emitter 106 can be received by the photodetector 107. The position of the laser emitter 106 should ensure that its emitted laser beam falls on the first alignment mark 104. Therefore, when the first wafer 101 and the second wafer 102 are misaligned, some light passes through the infrared transparent area to reach the photodetector 107. Furthermore, as the relative misalignment of the wafers increases, the area of ​​the infrared transparent area increases, and the light flux passing through the two wafers to the photodetector 107 also increases. Thus, the degree of wafer alignment deviation can be determined by reading the amount of light flux received by the photodetector 107. It is evident that the size of the transparent area is determined by the horizontal displacement between the first wafer stage and the second wafer stage.

[0055] Figure 2 Another preferred implementation of the first alignment mark 104 and the second alignment mark 105 is illustrated. The first alignment mark 104 is a rectangular pattern arranged in a dot matrix, and the second alignment mark 105 is an interlaced line pattern. The cutout areas enclosed by the lines in the line pattern and the rectangles of the first alignment mark 104 have the same pattern size and spacing. When the first alignment mark 104 and the cutout areas overlap, they can form a complete large rectangle. Optionally, this set of alignment marks can be placed in a non-patterned area at the edge of the wafer and can fill the area of ​​a single chip (shot). For example, the rectangles are 5μm × 5μm in size, with a spacing of 10μm in both the X and Y directions, orthogonally arranged, and the dot matrix size is 25mm × 30mm.

[0056] In another embodiment, the first alignment mark 104 and the second alignment mark 105 may both be gratings composed of densely packed metallic lines, whose grating constants satisfy the near-infrared diffraction conditions. See also Figure 3 The incident light beam becomes linearly polarized after passing through the first alignment mark 104 on the first wafer 101. The polarization direction of the second alignment mark 105 on the second wafer 102 is perpendicular to the polarization direction of the linearly polarized light incident on the second grating 502. This scheme takes into account the optical rotation of the medium. When the two wafers are perfectly aligned, the first alignment mark 104 and the second alignment mark 105 satisfy the linear polarization extinction condition. The linearly polarized light transmitted through the first alignment mark 104 is completely blocked by the second alignment mark 105, and the photodetector 107 cannot detect the light signal, thus minimizing the light flux detected by the photodetector 107. Specifically, see... Figure 4When the two wafers are translated and misaligned, a portion of the linearly polarized light transmitted through the first alignment mark 104 falls outside the second alignment mark 105, and the photodetector 107 detects the light signal. When the two wafers are rotated and misaligned, the polarization directions of the first alignment mark 104 and the second alignment mark 105 are not completely perpendicular, failing to meet the extinction condition for linearly polarized light, and the photodetector 107 can still detect the light signal. Therefore, in this embodiment, by translating and rotating the first wafer 101, the first alignment mark 104 and the second alignment mark 105 can satisfy the extinction condition, and wafer alignment is achieved when the light intensity detected by the photodetector 107 is at its minimum. Compared to completely opaque alignment marks, when rotational misalignment occurs, light also passes through the grating-type alignment marks, except in the non-overlapping areas. Therefore, the grating-type alignment marks are more sensitive to rotational misalignment.

[0057] Based on the above schematic diagram of the bonding and calibration of the two wafers, Figure 5 A schematic diagram of a wafer bonding alignment apparatus is shown. The apparatus includes: a first wafer stage 501, a second wafer stage 502, a laser emitter 106 located on the first wafer stage 501 for emitting near-infrared light, a photodetector 107 located on the second wafer stage 502, a drive unit 503 for adjusting the position of the first wafer stage 501 (which may be a piezoelectric drive module), and a control unit 504 connected to the drive unit 503. The control unit 504 may include a control unit 5041, a processor 5042, and a memory 5043. Figure 5 As can be seen, the first wafer carrier 501 is used to support the first wafer 101, and the second wafer carrier 502 is used to support the second wafer 102. The control unit 504 is electrically connected to the drive unit 503, which is used to drive the first wafer carrier 501 to move back and forth or left and right relative to the second wafer carrier 502 in the horizontal direction.

[0058] Understandably, the device may also include mechanical motion components for controlling the movement of the first wafer stage 501, and corresponding optical imaging modules for coarse alignment of the two wafers.

[0059] like Figure 6 As shown, the present invention provides a wafer bonding alignment method, which can be executed by the control unit 504 in the above-mentioned wafer bonding alignment device, and includes the following steps:

[0060] S601, control the laser emitter 106 located on the first wafer stage 501 to emit a laser toward the second wafer stage 502.

[0061] In this step, the laser emitted by laser emitter 106 can be near-infrared light. The laser emitted by laser emitter 106 falls on the first alignment mark 104.

[0062] S602, light flux is obtained from the photodetector 107 located on the second wafer stage 502.

[0063] The first wafer stage 501 carries the first wafer 101, and the second wafer stage 502 carries the second wafer 102. The second wafer 102 is disposed parallel to and below the first wafer 101.

[0064] In this step, when the positions of the first wafer 101 and the second wafer 102 are not perfectly aligned, the projections of the first alignment mark 104 and the second alignment mark 105 in the direction perpendicular to the substrate are not completely nested, forming a partially infrared-transparent area. Thus, some light will pass through the infrared-transparent area and reach the photodetector 107. The control unit 504 can determine the degree of wafer alignment deviation by reading the magnitude of the light flux received by the photodetector 107.

[0065] S603, according to the light flux, control the first wafer stage or the second wafer stage to move to a set position in the horizontal direction, so that the first wafer and the second wafer are aligned.

[0066] In this step, the first wafer stage 501 or the second wafer stage 502 can be controlled to move multiple times in the horizontal direction. The displacement between the first wafer stage 501 and the second wafer stage 502 after each displacement is recorded, and the luminous flux after each displacement is obtained from the photodetector 107. Based on the multiple displacements and their corresponding luminous fluxes, the displacement corresponding to the minimum luminous flux is determined as the minimum displacement. The first wafer stage or the second wafer stage is controlled to move in the horizontal direction until the displacement between the first wafer stage and the second wafer stage is determined as the minimum displacement, so that the first wafer and the second wafer are aligned.

[0067] Combination Figure 5Specifically, the control unit 504 controls the drive unit 503 to drive the first wafer stage 501 to move relative to the second wafer stage 502. As the relative offset between the two wafers increases, the area of ​​the infrared light transparent region increases, and the light flux passing through the two wafers to the photodetector 107 also increases. As a result, the amount of light flux received by the photodetector 107 changes. The control unit 504 can read the amount of light flux received by the photodetector 107 and then compare the amount of light flux. Based on the change in the amount of light flux, the control unit 504 can determine the degree of alignment deviation between the two wafers. When the first wafer 101 and the second wafer 102 are fully aligned, the projections of the first alignment mark 104 and the second alignment mark 105 in the direction perpendicular to the substrate form a gapless opaque region, or the first alignment mark 104 and the second alignment mark 105 satisfy the extinction condition. At this time, the light intensity detected by the photodetector 107 is the minimum. Therefore, the displacement between the first wafer stage 501 and the second wafer stage 502 at this time can be recorded as the minimum displacement. The first wafer stage or the second wafer stage is controlled to move in the horizontal direction until the displacement between the first wafer stage and the second wafer stage is the minimum displacement, so that the two wafers are aligned.

[0068] In one possible implementation, before controlling the laser emitter 106 located on the first wafer stage 501 to emit laser light, the method further includes: controlling the first wafer 101 and the second wafer 102 to perform coarse alignment via image recognition; and controlling the second wafer stage 502 to move vertically to the target position, such that the distance between the first wafer 101 and the second wafer 102 meets a set threshold. In this implementation, coarse alignment is performed before high-precision alignment. The purpose of coarse alignment is to prevent misjudgment because, due to the characteristics of the alignment mark array arrangement, the light flux changes with displacement with more than one extreme value. A large initial alignment deviation may lead to misjudgment of the degree of deviation.

[0069] In another possible implementation, after controlling the first wafer stage 501 to move to a set position in the horizontal direction, the method further includes controlling the first wafer 101 and the second wafer 102 to undergo wafer bonding. This alignment method is intuitive, easy to implement, and has no requirements for the wafer substrate, and is therefore widely used in wafer-level alignment and bonding processes.

[0070] To further describe the wafer bonding alignment process systematically, the following section uses the control of the first wafer stage movement as an example. Figure 7 The specific process of bonding and aligning the two wafers shown is described, including the following steps:

[0071] S701: First, define the XYZ rectangular coordinate system. The bonding surfaces of the first wafer 101 and the second wafer 102 are parallel and perpendicular to the Z-axis. The first wafer 101 and the second wafer 102 are coarsely aligned by optical imaging and image recognition. The second wafer stage 502 is raised to reduce the distance between the first wafer 101 and the second wafer 102.

[0072] In this step, the coarse alignment error can be ±500nm, for example, the spacing is reduced to 60μm.

[0073] S702: The laser emitter 106 located on the first wafer stage 501 emits near-infrared light. At the same time, the processor 5042 reads the detected light flux data from the photodetector 107 located on the second wafer stage 502 and records the light flux data in the memory 5043.

[0074] S703: The processor 5042 outputs the movement command to the control unit 5041. The control unit 5041 outputs a drive signal to control the piezoelectric drive module 503 to drive the first wafer stage 501 to produce a small displacement in the X direction.

[0075] S704, the processor 5042 reads and records the light flux data detected by the photodetector 107 to the memory 5043, and the processor 5042 calculates the direction and distance to be moved in the X direction based on the comparison result of the two light fluxes and the displacement of the stage.

[0076] The detailed calculation process for this step can be found below. Figure 8 The process described in the corresponding embodiment.

[0077] S705, repeat S703 to S704 until processor 5042 determines the amount of displacement of the stage in the X direction corresponding to the minimum wafer alignment deviation based on the data of light flux and stage displacement.

[0078] In this step, the processor 5042, based on the luminous flux and stage displacement data obtained from the memory 5043, can determine that the luminous flux changes linearly with the displacement in the X direction, and the relationship curve is as follows: Figure 9 The serrated shape shown, based on the pattern reflected by this relationship curve, represents the displacement of the stage in the X direction when the wafer alignment deviation is minimized.

[0079] S706, processor 5042 outputs movement commands to control unit 5041. Control unit 5041 outputs drive signals to control piezoelectric drive module 503 to drive the first wafer stage 501 to produce a small displacement in the Y direction.

[0080] S707, the processor 5042 reads and records the light flux data detected by the photodetector 107 to the memory 5043, and the processor 5042 calculates the direction and distance to be moved in the Y direction based on the comparison result of the two light fluxes and the displacement of the stage.

[0081] The specific calculation process for this step is similar to that for the X-direction; please refer to the following text for details. Figure 8 The process described in the corresponding embodiments can be extrapolated.

[0082] S708: Repeat S706 to S707 until the processor 5042 determines the amount of displacement of the stage in the Y direction corresponding to the minimum wafer alignment deviation based on the data of light flux and stage displacement.

[0083] In this step, processor 5042, based on the luminous flux and stage displacement data obtained from memory 5043, can determine that the luminous flux changes linearly with the displacement in the Y direction, and the relationship curve is as follows: Figure 9 The serrated shape shown, based on the pattern reflected by this relationship curve, represents the displacement of the stage in the Y direction when the wafer alignment deviation is minimized.

[0084] S709, the processor 5042 controls the first wafer stage to rotate along the Z-axis, repeating the above action in steps of one rotation angle, for example, 0.01 μrad, until the light flux data detected by the photodetector 107 reaches the minimum, completing the wafer alignment in the Z-axis direction, and recording the offset in the Z-axis direction corresponding to the minimum light flux.

[0085] The S710 processor 5042 controls the first wafer stage to move to the corresponding position, and the wafer is bonded and aligned.

[0086] Specifically, the bonding process of the two wafers is as follows: The centers of the first wafer 101 and the second wafer 102 are bulged outwards by the first wafer stage 501 and the second wafer stage 502, respectively. The sum of the deformation on both sides is greater than the wafer pitch, thus bringing the centers of the first wafer 101 and the second wafer 102 into place. Then, the first wafer stage 501 releases the first wafer 101, and the deformation of the second wafer 102 is removed, causing the bonding area of ​​the first wafer 101 and the second wafer 102 to spontaneously expand outwards from the wafer center, thereby achieving bonding of the entire wafer. Optionally, during the bonding process, the first wafer 101 and the second wafer 102 can be partially deformed before bonding, and then the above alignment steps can be performed, thereby eliminating alignment deviations caused by wafer deformation.

[0087] In summary, through the above process, the horizontal X and Y direction deviations and rotational deviations of the first wafer 101 and the second wafer 102 can be minimized, thereby achieving wafer alignment. Optionally, the above process is based onFigure 9 The relationship curve shown indicates that the displacement of the stage in the Y direction corresponding to the minimum wafer alignment deviation can be determined using algorithms such as least squares method and gradient descent method to determine the alignment position.

[0088] Figure 8 The following is a detailed explanation using wafer alignment along the X-axis as an example.

[0089] S801: The laser emitter 106 located on the first wafer stage 501 emits near-infrared light. At the same time, the processor 5042 reads the detected light flux data Φ1 from the photodetector 107 located on the second wafer stage 502 and records the light flux data Φ1 in the memory 5043.

[0090] S802: The processor 5042 outputs the movement command to the control unit 5041. The control unit 5041 outputs the drive signal to control the piezoelectric drive module 503 to drive the first wafer stage 501 to generate a small displacement of one step in the X-axis direction. Then the processor 5042 reads and records the light flux data Φ2 detected by the photodetector 107 located on the second wafer stage 502.

[0091] For example, the control unit 5041 outputs a drive signal to control the piezoelectric drive module 503 to drive the first wafer stage 501 to translate one step in the positive X-axis direction, for example, the step size is 20nm, X' = X + 20nm.

[0092] In S803, the processor 5042 compares the magnitudes of the luminous flux data Φ2 and luminous flux data Φ1 to determine the direction and distance to be moved in the next step. If Φ2 is greater than Φ1, then S804 is executed; otherwise, S805 is executed.

[0093] S804, if Φ2 is greater than Φ1, then shift two steps in the opposite direction of the X-axis, for example, a step size of 20nm, X” = X-40nm, and then execute S806.

[0094] S805, if Φ2 is less than or equal to Φ1, then continue to translate one step in the positive X-axis direction, and then return to execute S803.

[0095] In step S806, processor 5042 continues to compare the magnitudes of luminous flux data Φ2 and luminous flux data Φ1. If Φ2 is greater than Φ1, then step S807 is executed; otherwise, step S803 is executed.

[0096] The S807 and processor 5042 complete the wafer alignment in the X direction. Since the luminous flux does not decrease after the stage is displaced in the opposite direction, it means that the position before the stage displacement in the opposite direction was the position with the minimum luminous flux, that is, the alignment deviation of the wafer in the X direction is the minimum.

[0097] The wafer alignment process in the Y direction can be referred to the wafer alignment process in the X direction, and will not be repeated here.

[0098] Furthermore, although this method uses a transmission wafer to observe the alignment mark, it does not require through-holes on the wafer stage or a sophisticated imaging system, thus having low equipment manufacturing requirements and being easy to implement.

[0099] As can be seen from the above description, the wafer bonding alignment method provided by the present invention can improve the alignment accuracy of wafer bonding and achieve high-precision alignment. Figure 2 The preferred alignment mark shown is an example.

[0100] (1) The luminous flux changes linearly with the X-direction offset, and the relationship curve is as follows: Figure 9 The zigzag shape is shown. Assuming the output light flux of the near-infrared laser emitter 106 is 100 lm and the detection limit (sensitivity) of the photodetector is 0.1 lm, then the corresponding relative offset in the X direction is 20 nm, that is, the alignment accuracy is 20 nm.

[0101] (2) When the first alignment mark 104 and the second alignment mark 105 have a relative offset of aμm (|a|<5μm) in both the X and Y directions, the area of ​​their transparent region accounts for (a / 10-a^2 / 100) of the total area, and the light flux passing through the second alignment mark 105 is (a / 10-a^2 / 100) of the incident light flux. Therefore, its light flux is a quadratic function of the offset in the X and Y directions. When the alignment deviation is small, the rate of decrease in light flux is faster than when the X direction is offset. The calculated alignment accuracy is 10nm.

[0102] (3) When there is a rotational deviation between the first alignment mark 104 and the second alignment mark 105 along the Z-axis, assuming that the distance between their rotation center and the alignment mark is 100mm, since the size of the detection area is much smaller than this distance, the local offset at the alignment mark can be approximated as the offset caused by the translational deviation, and the alignment accuracy is between the two cases mentioned above. Therefore, in the above embodiment, the alignment accuracy reaches 20nm, realizing high-precision alignment at the nanometer level.

[0103] It is worth noting that the drive unit 503 in the above-mentioned wafer bonding device may not be connected to the first wafer stage 501, but to the second wafer stage 502. That is, the drive unit 503 can drive the second wafer stage 502 to move relative to the first wafer stage 501 in the horizontal direction. The specific alignment method is the same as the above method, and will not be elaborated here.

[0104] This invention also provides a readable medium storing a program that, when executed by a chip, implements the method described in any of the above method embodiments.

[0105] This invention also provides a program product that, when executed by a chip, implements the method described in any of the above method embodiments.

[0106] The above description is merely a preferred embodiment of the present invention. The embodiments are not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural changes made based on the description and drawings of the present invention should also be included within the scope of protection of the present invention.

[0107] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.

[0108] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A wafer bonding alignment method, characterized in that, include: A first wafer stage and a second wafer stage are provided. The first wafer stage carries a first wafer, and the second wafer stage carries a second wafer. The second wafer and the first wafer are arranged in parallel and opposite to each other. Control the laser emitter located on the first wafer stage to emit a laser toward the second wafer stage; Light flux is obtained from a photodetector located on the second wafer stage; The first wafer stage or the second wafer stage is controlled to move horizontally to a set position according to the light flux, so that the first wafer and the second wafer are aligned. Both the first wafer and the second wafer are provided with a light-transmitting structure. The light-transmitting structure has a light-transmitting area that allows the laser to pass through the first wafer and the second wafer to reach the photodetector. The size of the light-transmitting area is determined by the horizontal displacement between the first wafer stage and the second wafer stage. The steps for obtaining light flux from the photodetector located on the second wafer stage include: A first alignment mark is set on the first wafer, and a second alignment mark is set on the second wafer. Light flux is obtained from a photodetector located on the second wafer stage through the light-transmitting area formed by the first alignment mark and the second alignment mark. The laser emitter is positioned such that the emitted laser falls on the first alignment mark. The first and second alignment marks are configured such that when the first wafer and the second wafer are aligned, the first and second alignment marks form an opaque pattern. The opaque pattern has the lowest transmittance for the laser, thus minimizing the light flux detected by the photodetector.

2. The method according to claim 1, characterized in that, Before controlling the laser emitter located on the first wafer stage to emit laser light, the process also includes: The first wafer and the second wafer are coarsely aligned using image recognition. Control the first wafer stage or the second wafer stage to move vertically to the target position, so that the distance between the first wafer and the second wafer meets the set threshold.

3. The method according to claim 1, characterized in that, After controlling the first wafer stage or the second wafer stage to move to a set position in the horizontal direction, the method further includes: Control the first wafer and the second wafer to undergo wafer bonding.

4. The method according to claim 1, characterized in that, The steps of controlling the first wafer stage or the second wafer stage to move to a set position in the horizontal direction according to the light flux include: The first wafer stage or the second wafer stage is controlled to move multiple times in the horizontal direction. The displacement between the first wafer stage and the second wafer stage is recorded after each displacement, and the light flux after each displacement is obtained from the photodetector. Based on multiple displacements and their corresponding luminous fluxes, the displacement corresponding to the minimum luminous flux is determined as the minimum displacement. The minimum displacement is defined as the amount by which the first wafer stage or the second wafer stage moves horizontally to a position between the first wafer stage and the second wafer stage.

5. A wafer bonding alignment apparatus, characterized in that, include: A first wafer stage and a second wafer stage, the first wafer stage carrying a first wafer, the second wafer stage carrying a second wafer, the second wafer and the first wafer being arranged parallel to each other; a laser emitter located on the first wafer stage, a photodetector located on the second wafer stage; a driving unit, a memory, and a control unit; the laser emitter on the first wafer stage is used to emit laser light; the photodetector is used to detect luminous flux; The control unit is used to perform the following processing: Control the laser emitter located on the first wafer stage to emit a laser toward the second wafer stage; Light flux is obtained from a photodetector located on the second wafer stage; According to the light flux, the driving unit controls the first wafer stage or the second wafer stage to move horizontally to a set position, so that the first wafer and the second wafer are aligned; Both the first wafer and the second wafer are provided with a light-transmitting structure. The light-transmitting structure has a light-transmitting area that allows the laser to pass through the first wafer and the second wafer to reach the photodetector. The size of the light-transmitting area is determined by the horizontal displacement between the first wafer stage and the second wafer stage. The step of the control unit acquiring light flux from the photodetector located on the second wafer stage is specifically used as follows: the first wafer is provided with a first alignment mark, the second wafer is provided with a second alignment mark, and the light flux is acquired from the photodetector located on the second wafer stage through the light-transmitting area formed by the first alignment mark and the second alignment mark; The laser emitter is positioned such that the emitted laser falls on the first alignment mark. The first and second alignment marks are configured such that when the first wafer and the second wafer are aligned, the first and second alignment marks form an opaque pattern. The opaque pattern has the lowest transmittance for the laser, thus minimizing the luminous flux detected by the photodetector.

6. The apparatus according to claim 5, characterized in that, The control unit is also used for mechanical motion components that control the movement of the second wafer stage, and corresponding optical imaging modules for coarse alignment of the first wafer and the second wafer. Before controlling the laser emitter located on the first wafer stage to emit laser light, the control unit is also used to control the optical imaging module to enable the first wafer and the second wafer to be coarsely aligned by image recognition. Control the first wafer stage or the second wafer stage to move vertically to the target position, so that the distance between the first wafer and the second wafer meets the set threshold.

7. The apparatus according to claim 5, characterized in that, After the control unit controls the driving unit to drive the first wafer stage or the second wafer stage to move in the horizontal direction to a set position, it is further configured to: Control the first wafer and the second wafer to undergo wafer bonding.

8. The apparatus according to claim 5, characterized in that, The control unit controls the driving unit to drive the first wafer stage or the second wafer stage to a set position in the horizontal direction according to the light flux, specifically for: The driving unit is controlled to drive the first wafer stage or the second wafer stage to move multiple times in the horizontal direction, and the memory is controlled to record the displacement between the first wafer stage and the second wafer stage after each displacement, and the light flux after each displacement is obtained from the photodetector. The minimum displacement is obtained by taking the displacement corresponding to the minimum luminous flux from multiple displacements and their corresponding luminous fluxes. The driving unit controls the first wafer stage or the second wafer stage to move horizontally until the displacement between the first wafer stage and the second wafer stage is the minimum displacement.

9. The apparatus according to claim 5, characterized in that, The first alignment mark is located within the metal interconnect layer of the first wafer, and the second alignment mark is located within the metal interconnect layer of the second wafer. When the first wafer and the second wafer are not aligned, the first alignment mark and the second alignment mark are transparent to the laser emitted by the laser emitter in a direction perpendicular to the first wafer substrate.

10. The apparatus according to claim 5, characterized in that, The first alignment mark and the second alignment mark are a set of nested patterns; when the first wafer and the second wafer are aligned, the projections of the first alignment mark and the second alignment mark in the direction perpendicular to the substrate form a gapless opaque area; when the first wafer and the second wafer are not aligned, the projections of the first alignment mark and the second alignment mark in the direction perpendicular to the substrate are not completely nested, forming a partially light-transparent area.

11. The apparatus according to claim 5, characterized in that, The first alignment mark is a rectangular pattern arranged in a dot matrix, and the second alignment mark is an interlaced line pattern. The hollow area enclosed by each line in the line pattern has the same size and spacing as the rectangular patterns of the first alignment mark. The two sets of marks overlap to form a complete large rectangle.

12. The apparatus according to claim 11, characterized in that, The rectangle has dimensions of 5μm × 5μm, with a spacing of 10μm in both the X and Y directions, and is orthogonally arranged. The size of the dot matrix is ​​25mm × 30mm.

13. The apparatus according to claim 11, characterized in that, The first alignment mark is placed in a non-patterned area at the edge of the first wafer, and the second alignment mark is placed in a non-patterned area at the same position at the edge of the second wafer, and the first alignment mark and the second alignment mark occupy the area of ​​a chip.

14. The apparatus according to claim 5, characterized in that, The first alignment mark and the second alignment mark are a set of gratings that satisfy the linear polarization extinction condition.

15. The apparatus according to claim 14, characterized in that, The first alignment mark and the second alignment mark are gratings composed of dense metal lines.

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