A trench gate structure and double heterojunction structure gallium nitride high electron mobility transistor and a preparation method thereof

Abstract

The application discloses a gallium nitride high electron mobility transistor with a slot gate structure and a double heterojunction structure and a preparation method thereof, wherein annealing treatment is performed on the interface formed by the insulating dielectric layer and each layer under supercritical fluid, meanwhile, a low-temperature annealing process is adopted, high-temperature re-oxidation and material decomposition are avoided, the interface is treated by using the characteristics of high permeability, high solubility and no surface tension of SCF state, interface defects formed between HfO2 and GaN layer, Al 0.2 Ga 0.8 N barrier layer, GaN channel layer in the slot gate process are reduced, the interface quality is improved, defects are reduced, new damage is not caused, the influence of traps between the insulating dielectric layer and each layer is reduced, high-quality slot gate is realized, energy loss is improved, and the reliability of the gate dielectric layer is remarkably improved. Defects are further reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a gallium nitride high electron mobility transistor with trench gate structure and double heterojunction structure and its fabrication method. Background Technology

[0002] GaN semiconductor materials possess numerous advantages, including a large bandgap and high breakdown field strength, making them widely applicable in the field of semiconductor integrated circuits. With third-generation semiconductors becoming a major area of ​​research and development in my country, the development of GaN HEMTs has attracted widespread attention, particularly in fields such as communications, radar, fast charging, and new energy vehicles, where it holds immense promise.

[0003] However, the piezoelectric polarization and spontaneous polarization mechanism of GaN HEMTs dictate that they are in an on-state at zero gate voltage, which is detrimental to the control of device switching and leads to adverse effects such as high power consumption. To address this issue, the trench gate structure thins the AlGaN barrier layer, making the voltage generated by the polarization electric field less than the voltage drop required for the formation of a two-dimensional electron gas, thus enabling the device to exhibit normally-off characteristics. However, the trench gate structure has drawbacks: the etching process damages the interface between the channel layer and the oxide layer, creating defects at the gate-oxide interface. This leads to reduced channel mobility, increased channel specific resistance, and worsened energy loss. Furthermore, the high annealing temperature causes re-oxidation and material decomposition, reducing device quality. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure, and a method for fabricating the same. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] A first aspect of this invention provides a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure, comprising: a substrate, a first AlN nucleation layer, a second AlN nucleation layer, and an Al..., sequentially disposed from bottom to top. x Ga 1-x N-buffer layer and GaN channel layer;

[0006] An Al layer is disposed above the GaN channel layer. 0.2 Ga 0.8 N-barrier layer, source electrode, and drain electrode;

[0007] The source electrode and the drain electrode are respectively located in the Al 0.2 Ga 0.8 Both sides of the N-barrier layer;

[0008] The Al 0.2 Ga 0.8A GaN layer is disposed above the N-barrier layer, and a first HfO2 insulating dielectric layer is disposed above the GaN layer;

[0009] The GaN channel layer, the Al 0.2 Ga 0.8 Grooves are provided in the N-barrier layer, the GaN layer, and the first HfO2 insulating dielectric layer;

[0010] The inner wall of the groove has a second HfO2 insulating dielectric layer, which extends above the first HfO2 insulating dielectric layer; a gate electrode is disposed in the gate groove formed by the second HfO2 insulating dielectric layer.

[0011] Among them, for the GaN layer, the Al 0.2 Ga 0.8 The interfaces of the N barrier layer and the GaN channel layer with the first HfO2 insulating dielectric layer and the second HfO2 insulating dielectric layer are annealed under supercritical fluid conditions.

[0012] A second aspect of this invention provides a method for fabricating a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure, comprising the following steps:

[0013] Step 1: Grow a first AlN nucleation layer on the substrate, and then grow a second AlN nucleation layer on the first AlN nucleation layer;

[0014] Step 2: Growing Al on the second AlN nucleation layer x Ga 1-x N buffer layer, in Al x Ga 1-x A GaN channel layer is deposited on the N-buffer layer, and Al is deposited on the GaN channel layer. 0.2 Ga 0.8 N-barrier layer, in the Al 0.2 Ga 0.8 GaN layers are deposited on the N-barrier layer;

[0015] Step 3: Deposit a SiN passivation layer on the GaN layer;

[0016] Step 4: Etch the SiN passivation layer and the GaN / Al layer. 0.2 Ga 0.8 N-barrier layer / GaN channel layer, forming etching trenches;

[0017] Step 5: Wet etching of the SiN passivation layer to completely etch the SiN passivation layer and form a groove;

[0018] Step six: Grow an HfO2 dielectric layer on the GaN layer and within the groove, and then apply the following to the GaN layer and the Al...0.2 Ga 0.8 The interfaces between the N-barrier layer and the GaN channel layer and the HfO2 dielectric layer are annealed under supercritical fluid conditions.

[0019] Step 7: Etch the HfO2 layer at the location corresponding to the groove to form a gate trench, and grow the gate electrode in the gate trench using magnetron sputtering technology;

[0020] Step 8: Partial etching of the HfO2 dielectric layer to form a first HfO2 insulating dielectric layer and a second HfO2 insulating dielectric layer;

[0021] Step 9: Etch the first HfO2 insulating dielectric layer / the GaN layer / Al 0.2 Ga 0.8 On both sides of the N-barrier layer, source and drain regions are formed, and source and drain electrodes are deposited using electron beam evaporation to obtain a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure as described in the first aspect of the present invention.

[0022] In one embodiment of the present invention, the Al x Ga 1-x The Al composition of the N buffer layer gradually decreases from the second AlN nucleation layer to the GaN channel layer.

[0023] In one embodiment of the present invention, in step six, the supercritical fluid is supercritical carbon dioxide or supercritical nitrous oxide, and the annealing temperature is 100-200°C.

[0024] In one embodiment of the present invention, the Al 0.2 Ga 0.8 The N-barrier layer forms a double heterojunction structure with the GaN layer and the GaN channel layer, respectively.

[0025] The beneficial effects of this invention are:

[0026] This invention relates to GaN layers, Al 0.2 Ga 0.8 The interfaces of the N-barrier layer, GaN channel layer, and HfO2 insulating dielectric layer are annealed under supercritical fluid conditions. Simultaneously, a low-temperature annealing process is employed to avoid high-temperature re-oxidation and material decomposition. The high permeability, high solubility, and zero surface tension of the SCF state are utilized to treat the interfaces, thereby mitigating the interaction between HfO2 and the GaN and Al layers during the trench gate process. 0.2 Ga 0.8The interface defects formed between the N barrier layer and the GaN channel layer improve interface quality, reduce defects, and do not cause new damage. They also reduce the influence of traps between the HfO2 insulating dielectric layer and each layer, achieving a high-quality trench gate, improving energy loss, significantly improving the reliability of the gate dielectric layer, and further mitigating defects.

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0028] Figure 1 This is a schematic cross-sectional view of a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure provided in an embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram of the structure of an intermediate product prepared by a method for fabricating a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure according to an embodiment of the present invention.

[0030] Figures 3a-3f This is a schematic diagram of the process for fabricating a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure, provided by an embodiment of the present invention.

[0031] Explanation of reference numerals in the attached figures:

[0032] 10 - Substrate; 20 - First AlN nucleation layer; 30 - Second AlN nucleation layer; 40 - Al x Ga 1-x N-buffer layer; 50-GaN channel layer; 60-Al 0.2 Ga 0.8 N-Barrier layer; 70-Source electrode; 80-Drain electrode; 90-GaN layer; 91-First insulating dielectric layer; 92-Second insulating dielectric layer; 93-Groove; 94-Gate electrode. Detailed Implementation

[0033] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0034] Example 1

[0035] like Figure 1 As shown, a first aspect of the present invention provides a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure, comprising: a substrate 10, a first AlN nucleation layer 20, a second AlN nucleation layer 30, and an AlN nucleation layer 4, which are sequentially disposed from bottom to top. x Ga 1-x An N-type buffer layer 40 and a GaN channel layer 50 are present. An Al layer is disposed above the GaN channel layer 50. 0.2 Ga0.8 The N-type barrier layer 60, source electrode 70, and drain electrode 80 are located on Al. The source electrode 70 and drain electrode 80 are respectively located on Al. 0.2 Ga 0.8 The N-barrier layer 60 extends to both sides. The source electrode 70 and drain electrode 80 extend to the GaN layer 90.

[0036] Al 0.2 Ga 0.8 A GaN layer 90 is disposed above the N-barrier layer 60, and a first HfO2 insulating dielectric layer 91 is disposed above the GaN layer 90.

[0037] GaN channel layer 50, Al 0.2 Ga 0.8 A groove 93 is formed within the N-barrier layer 60, GaN layer 90, and first HfO2 insulating dielectric layer 91. The source electrode 70 and drain electrode 80 are located on opposite sides of the groove 93. A second HfO2 insulating dielectric layer 92 is formed on the inner wall of the groove 93, extending above the first HfO2 insulating dielectric layer 91; a gate electrode 94 is disposed within the gate trench formed by the second HfO2 insulating dielectric layer 92. The interface between the GaN layer 90 and the first HfO2 insulating dielectric layer 91 and the second HfO2 insulating dielectric layer 92, and the Al... 0.2 Ga 0.8 The interfaces between the N barrier layer 60 and the second HfO2 insulating dielectric layer 92, and between the GaN channel layer 50 and the second HfO2 insulating dielectric layer 92, are annealed under supercritical fluid conditions, wherein the annealing is performed at low temperature.

[0038] In this embodiment, Al 0.2 Ga 0.8 Above the N-barrier layer 60 is the GaN layer 90, and below it is the GaN channel layer 50, forming a double heterojunction structure. The gate electrode 94 extends into the channel layer 50, and an HfO2 insulating dielectric layer is formed around the gate electrode 94 to form a MIS structure. The first AlN nucleation layer 20 is close to the substrate 10. The first AlN nucleation layer 20 is a low-temperature AlN nucleation layer, the purpose of which is to obtain an epitaxial layer with high crystallinity. The second AlN nucleation layer 30 is above the first AlN nucleation layer 20. The second AlN nucleation layer 30 is a high-temperature AlN nucleation layer, the purpose of which is to ensure the quality of the nucleation layer and effectively suppress the buried charge layer, that is, to suppress the diffusion of impurities in the substrate 10 into the buffer layer.

[0039] Al x Ga 1-x The purpose of the N-buffer layer 40 is to reduce the stress between the AlN and GaN layers, thereby reducing device leakage and power consumption. The GaN channel layer 50 is used to provide an undoped conductive channel for the device.

[0040] Al0.2 Ga 0.8 The N-type barrier layer 60 provides a heterojunction barrier, allowing the two-dimensional electron gas density to reach saturation and exhibiting good mobility. The GaN layer 90 and Al... 0.2 Ga 0.8 The N-barrier layer 60 forms a two-dimensional hole gas, reducing the electric field strength and increasing the breakdown voltage. The drain electrode 80 and the source electrode 70 are fabricated using an electron beam evaporation process, and then rapidly thermally annealed at 800°C to form an ohmic contact.

[0041] For trench gate technology, by increasing pressure, carbon dioxide or nitrous oxide gas is introduced into the supercritical fluid (SCF) state at near room temperature. The high permeability, high solubility, and zero surface tension of the SCF state are utilized to treat the interface, improving interface quality, reducing defects, and preventing new damage. This mitigates the interaction between HfO2 and the GaN and Al layers during trench gate technology. 0.2 Ga 0.8 Interface defects formed between the N barrier layer and the GaN channel layer. Meanwhile, a low-temperature annealing process was employed to avoid high-temperature re-oxidation and material decomposition, further mitigating the defects.

[0042] Example 2

[0043] A second aspect of this invention provides a method for fabricating a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure, comprising the following steps:

[0044] Step 101: Deposit an AlN nucleation layer.

[0045] A first AlN nucleation layer 20 is grown on substrate 10, and a second AlN nucleation layer 30 is grown on the first AlN nucleation layer 20. Specifically, a silicon substrate 10 is selected and placed in the equipment growth chamber. Using MOCVD technology, the first AlN nucleation layer 20 with a thickness of 20 nm is deposited at a temperature of 600 °C. Then, the temperature is further increased to 1000 °C, and the V / III ratio is controlled to be relatively high, to grow a second AlN nucleation layer 30 with a thickness of 120 nm.

[0046] Step 102, depositing gradient Al x Ga 1-x N-buffer layer.

[0047] Al is grown on the second AlN nucleation layer 30 x Ga 1-x The N buffer layer 40, specifically, can use trimethylaluminum (TMAL) as the aluminum source, trimethylgallium (TMGA) as the gallium source, and NH3 as the nitrogen source, to grow an Al composition with a thickness of 2 μm that gradually decreases from 80% to 20% from the second AlN nucleation layer 30 to the GaN channel layer 50. x Ga1-x N buffer layer 40.

[0048] Step 103: Deposit GaN channel layer.

[0049] In Al x Ga 1-x GaN channel layer 50 is deposited on N buffer layer 40. Specifically, MOCVD process is continued on Al. x Ga 1-x A GaN channel layer 50 with a thickness of 700 nm is deposited on the N buffer layer 40.

[0050] Step 104: Deposit the barrier layer.

[0051] Al was deposited on the GaN channel layer 50. 0.2 Ga 0.8 N-barrier layer 60, specifically, continues to use MOCVD process to deposit an Al layer with a thickness of 30 nm above the GaN channel layer 50. 0.2 Ga 0.8 N-barrier layer 60.

[0052] Step 105: Deposit a GaN layer.

[0053] In Al 0.2 Ga 0.8 A GaN layer 90 is deposited on an N-barrier layer 60.

[0054] Specifically, continue to use MOCVD process in Al 0.2 Ga 0.8 A GaN layer 90 with a thickness of 500 nm is deposited above the N-barrier layer 60. Steps 101-105 are completed to obtain the desired result. Figure 2 The product shown.

[0055] Step 106, grow SiN.

[0056] A SiN passivation layer is deposited on the GaN layer 90, such as Figure 3a As shown.

[0057] Specifically, first clean the product surface with toluene, acetone, and ethanol using ultrasonic cleaning (10 minutes each time) to remove organic impurities, and then rinse with deionized water.

[0058] Then, SiN with a thickness of 100 nm was deposited on top of the GaN layer 90 using PECVD process. The process conditions were: SiH4 flow rate of 13.5 sccm, NH3 flow rate of 10 sccm, N2 flow rate of 1000 sccm, pressure of 2200 mToor, plasma RF power of 67 W, and temperature of 350 °C.

[0059] Step 107: Etch the SiN / GaN / AlGaN / GaN channel layer.

[0060] Specifically, the etching positions corresponding to the photolithographic groove 93 form etching grooves:

[0061] First, spin-coat the AZ6112 photoresist with the following parameters: 600 rpm for 5 seconds; 4000 rpm for 30 seconds; and bake at 100°C for 2 minutes. Then, expose the photoresist using an MA6 lithography machine with an exposure time of 1.9 seconds, a development time of 42 seconds, and then dry at 110°C for 2 minutes.

[0062] Subsequently, the SiN layer was etched using a RIE device under the following process conditions: CHF3 flow rate of 72 sccm, SF6 flow rate of 10 sccm, Ar flow rate of 10 sccm, plasma RF power of 100W, pressure of 35mToor, and etching depth of 100nm.

[0063] Then, ICP etching was used to etch the GaN layer 90 / Al. 0.2 Ga 0.8 The N-barrier layer is 60 / GaN channel layer is 50, and the process conditions are: BCl3 flow rate of 25 sccm, He flow rate of 15 sccm, plasma RF power of 55 W, pressure of 6 mToor, and etching depth of 550-560 nm. Figure 3b As shown.

[0064] Step 108: Wet etching of the SiN passivation layer to completely etch the SiN passivation layer, forming groove 93, as shown. Figure 3c As shown. Specifically, use a 40%-42% HF acid solution, soak for 180 seconds, then rinse repeatedly with deionized water more than 5 times, and blow dry with N2.

[0065] Step 109, growth medium layer, which can be made of materials such as HfO2, etc. Figure 3d As shown.

[0066] A HfO2 dielectric layer is grown on the GaN layer 90 and within the groove 93. The interface between the GaN layer 90 and the HfO2 dielectric layer, and the Al... 0.2 Ga 0.8 The interfaces between the N barrier layer 60 and the HfO2 dielectric layer, and between the GaN channel layer 50 and the HfO2 dielectric layer, are annealed under supercritical fluid conditions.

[0067] Specifically, a 100nm thick HfO2 dielectric layer was grown under the following process conditions: N2O flow rate of 710 sccm, N2 flow rate of 180 scm, SiH4 flow rate of 4 sccm, pressure of 2000 mToor, RF power of 21W, and temperature of 350℃.

[0068] After growing the dielectric layer, an annealing process is used to improve the interface quality. The annealing step employs a low-temperature annealing process using supercritical carbon dioxide (SCCO2) or supercritical nitrous oxide (SCN2O) fluid to improve the interface between the GaN layer 90 and the HfO2 dielectric layer in the HEMT, as well as the Al... 0.2 Ga 0.8 The interface quality between the N barrier layer 60 and the HfO2 dielectric layer, and between the GaN channel layer 50 and the HfO2 dielectric layer, is improved. By increasing the pressure, some gas enters the supercritical fluid (SCF) state near room temperature. The SCF state is a special phase of matter, possessing high permeability like a gas and high solubility like a liquid, with almost no surface tension. Therefore, a low-temperature annealing process with an annealing temperature of 100–200℃ is used to avoid high-temperature re-oxidation and material decomposition. SCCO2 or (SCN2O) fluid can be introduced into the interface to reduce traps without causing new damage. This reduces the interaction between HfO2 and the GaN layer, Al, and other dielectric layers in the trench gate process. 0.2 Ga 0.8 The interface defects formed between the N barrier layer and the GaN channel layer improve the interface quality, reduce defects, realize a high-quality trench gate, improve energy loss, and significantly improve the reliability of the gate dielectric layer.

[0069] Step 110, fabrication of gate electrode 94, as follows Figure 3e .

[0070] A gate trench is formed by etching an HfO2 dielectric layer at the location corresponding to the groove 93.

[0071] Specifically, a photolithography process is used to select the gate deposition area (the position corresponding to the groove 93), the exposure parameters are the same as those in step 107, the selected area is etched, and the HfO2 dielectric layer at the position corresponding to the groove 93 is etched. The process conditions are: BCl3 flow rate of 25 sccm, He flow rate of 15 sccm, plasma RF power of 55W, pressure of 6mToor, and etching depth of 620nm to form the gate trench.

[0072] Then clean with toluene, acetone, and ethanol using ultrasound (10 minutes each time) to remove organic impurities from the product surface, and then rinse with deionized water.

[0073] Next, the contact area (gate trench area) of the gate electrode 94 was selected using photolithography, with the same exposure parameters as in step 107. TiN / Ti / Al / TiN was grown using magnetron sputtering technology to a thickness of 150 / 150 / 150 / 170 nm. Acetone was then used to peel off the metal until it detached, followed by heating in a positive-resin glass bath at 75°C for 10 min. After rinsing with deionized water, it was dried with N2 to form the gate electrode 94.

[0074] Step 111: Etch away excess HfO2, such as... Figure 3f As shown.

[0075] Partial etching of the HfO2 dielectric layer forms a first HfO2 insulating dielectric layer 91 and a second HfO2 insulating dielectric layer 92. Specifically, a photolithography process is used to select the deposition area excluding the gate, with the same exposure parameters as in step 107. The selected area is etched, and the HfO2 dielectric layer is etched under the following process conditions: BCl3 flow rate of 25 sccm, He flow rate of 15 sccm, plasma RF power of 55 W, pressure of 6 mToor, and etching depth of 50 nm, forming the first HfO2 insulating dielectric layer 91 and the second HfO2 insulating dielectric layer 92.

[0076] Step 112, fabrication of the source electrode 70 and the drain electrode 80, as follows: Figure 1 As shown.

[0077] Etching the first HfO2 insulating dielectric layer 91 / GaN layer 90 / Al 0.2 Ga 0.8 On both sides of the N-barrier layer 60, source and drain regions are formed, and source electrode 70 and drain electrode 80 are deposited using electron beam evaporation, thus completing the fabrication of a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure as described in Example 1. Specifically, the source and drain electrode contact areas are first selected using photolithography, with the same exposure parameters as in step 107, and HfO2 / GaN / Al is etched. 0.2 Ga 0.8 The etching depth is 580nm in the two sides of N.

[0078] Then, Ti / Al metal was deposited using electron beam evaporation to a thickness of 20 / 20 nm. The metal was then ultrasonically peeled off with acetone, heated in a water bath at 75°C for 10 min, and dried with N2. Finally, the source and drain metal electrodes were annealed using rapid thermal annealing at 800°C for 30 s.

[0079] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0081] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0082] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0083] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0084] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure, characterized in that, include: The substrate (10), the first AlN nucleation layer (20), the second AlN nucleation layer (30), the AlxGa1-xN buffer layer (40) and the GaN channel layer (50) are arranged sequentially from bottom to top. An Al0.2Ga0.8N barrier layer (60), a source electrode (70), and a drain electrode (80) are disposed above the GaN channel layer (50); The source electrode (70) and the drain electrode (80) are located on opposite sides of the Al0.2Ga0.8N barrier layer (60); A GaN layer (90) is disposed above the Al0.2Ga0.8N barrier layer (60), and a first HfO2 insulating dielectric layer (91) is disposed above the GaN layer (90). The GaN channel layer (50), the Al0.2Ga0.8N barrier layer (60), the GaN layer (90) and the first HfO2 insulating dielectric layer (91) are provided with grooves (93); The inner wall of the groove (93) has a second HfO2 insulating dielectric layer (92), which extends above the first HfO2 insulating dielectric layer (91); a gate electrode (94) is disposed in the gate groove formed by the second HfO2 insulating dielectric layer (92); Among them, the interfaces of the GaN layer (90), the Al0.2Ga0.8N barrier layer (60) and the GaN channel layer (50) with the first HfO2 insulating dielectric layer (91) and the second HfO2 insulating dielectric layer (92) are annealed in supercritical fluid. The supercritical fluid is supercritical nitrous oxide; the annealing temperature is 100℃~200℃.

2. A method for fabricating a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure, characterized in that, Includes the following steps: Step 1: A first AlN nucleation layer (20) is grown on the substrate (10), and a second AlN nucleation layer (30) is grown on the first AlN nucleation layer (20); Step 2: An AlxGa1-xN buffer layer (40) is grown on the second AlN nucleation layer (30), a GaN channel layer (50) is deposited on the AlxGa1-xN buffer layer (40), an Al0.2Ga0.8N barrier layer (60) is deposited on the GaN channel layer (50), and a GaN layer (90) is deposited on the Al0.2Ga0.8N barrier layer (60). Step 3: Deposit a SiN passivation layer on the GaN layer (90); Step 4: Etch the SiN passivation layer and GaN layer (90) / Al0.2Ga0.8N barrier layer (60) / GaN channel layer (50) to form an etching trench; Step 5: Wet etching of the SiN passivation layer to completely etch the SiN passivation layer to form a groove (93); Step 6: An HfO2 dielectric layer is grown on the GaN layer (90) and in the groove (93), and the interfaces of the GaN layer (90), the Al0.2Ga0.8N barrier layer (60) and the GaN channel layer (50) with the HfO2 dielectric layer are annealed in supercritical fluid. Step 7: Etch HfO2 layer at the position corresponding to the groove (93) to form a gate trench, and grow gate electrode (94) in the gate trench using magnetron sputtering technology; Step 8: Partial etching of the HfO2 dielectric layer to form a first HfO2 insulating dielectric layer (91) and a second HfO2 insulating dielectric layer (92); Step nine: Etch both sides of the first HfO2 insulating dielectric layer (91) / the GaN layer (90) / Al0.2Ga0.8N barrier layer (60) to form the source region and the drain region, and deposit the source electrode (70) and the drain electrode (80) using an electron beam evaporation process to complete the fabrication and obtain a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure as described in claim 1.

3. The method for fabricating a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure according to claim 2, characterized in that, The Al composition of the AlxGa1-xN buffer layer (40) gradually decreases from the second AlN nucleation layer (30) to the GaN channel layer (50).

4. The method for fabricating a gallium nitride high electron mobility transistor with a trench gate structure and a double heterojunction structure according to claim 2, characterized in that, The Al0.2Ga0.8N barrier layer (60) forms a double heterojunction structure with the GaN layer (90) and the GaN channel layer (50), respectively.

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