Semiconductor structure and its fabrication method

Abstract

This disclosure provides a semiconductor structure and its fabrication method, relating to the field of semiconductor technology. The semiconductor structure includes an antifuse unit, which includes a select unit and a memory unit. The semiconductor structure further includes: a substrate; a gate disposed in the substrate, the gate including opposing first and second sidewalls in a cross-section perpendicular to the substrate; a first doped region disposed in the substrate near the first sidewall; a second doped region disposed in the substrate near the second sidewall; and an oxide layer covering a portion of the gate surface. The gate, the first doped region, and the oxide layer constitute the memory unit, and the gate, the first doped region, the second doped region, and the oxide layer constitute the select unit. In this disclosure, the select unit and the memory unit of the antifuse unit share a gate. Applying a voltage to the gate breaks down a portion of the oxide layer, allowing the logic state of the memory unit to be read through the select unit. This reduces the size of the antifuse unit and provides more usable space for the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] Anti-fuse devices are commonly used one-time programmable devices (OTPs) and are widely used in memory chips.

[0003] An antifuse device consists of a memory cell and a select cell. For an antifuse device to be used in a memory chip, at least two semiconductor devices are required as the memory cell and the select cell. Furthermore, the memory cell and the select cell cannot be too close together. If they are too close, the performance of the select cell will degrade during the breakdown of the memory cell, affecting the reliability of the circuit. The structure of the antifuse device results in it occupying a relatively large area of ​​the memory chip, which is detrimental to increasing the storage density of the memory chip and further miniaturizing the memory chip. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a semiconductor structure and a method for fabricating the same.

[0006] A first aspect of this disclosure provides a semiconductor structure including at least one antifuse unit, wherein the antifuse unit includes a selection unit and a memory unit, and the semiconductor structure includes:

[0007] Substrate;

[0008] A gate, disposed in the substrate, wherein in a cross section perpendicular to the substrate, the gate includes opposing first and second sidewalls;

[0009] A first doped region is disposed in the substrate near the first sidewall;

[0010] A second doped region is disposed in the substrate near the second sidewall;

[0011] An oxide layer covers a portion of the surface of the gate.

[0012] The gate, the first doped region, and the oxide layer constitute the memory cell, and the gate, the first doped region, the second doped region, and the oxide layer constitute the selection cell.

[0013] The oxide layer includes a first oxide layer and a second oxide layer, the storage unit includes the first oxide layer, and the selection unit includes the second oxide layer.

[0014] The dielectric constant of the first oxide layer is greater than that of the second oxide layer.

[0015] The thickness of the first oxide layer is less than the thickness of the second oxide layer.

[0016] Wherein, the projection of the first doped region on the first sidewall covers the projection of the first oxide layer on the first sidewall, and the second oxide layer includes the oxide layer other than the first oxide layer.

[0017] In a cross-section perpendicular to the substrate, the bottom surface of the first oxide layer is higher than the bottom surface of the first doped region.

[0018] The selection unit further includes a third doped region, which is disposed in the substrate, located between the first doped region and the second doped region, and surrounds a portion of the oxide layer.

[0019] The conductivity type of the doped ions in the first doped region is the same as that of the doped ions in the second doped region, and the conductivity type of the doped ions in the third doped region is opposite to that of the doped ions in the first and second doped regions.

[0020] In a cross-section perpendicular to the substrate, the top surface of the gate is higher than the bottom surface of the first doped region and the bottom surface of the second doped region.

[0021] The semiconductor structure further includes:

[0022] An insulating layer covers the top surface of the gate and the top surface of the oxide layer, the top surface of the insulating layer being flush with the top surface of the substrate.

[0023] A second aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0024] A substrate is provided, and a first trench is formed in the substrate;

[0025] An oxide layer is formed, which covers the bottom wall and part of the sidewall of the first trench, and the top surface of the oxide layer is lower than the top surface of the substrate;

[0026] A gate is formed, the gate covering the oxide layer and filling a portion of the first trench, the top surface of the gate being flush with the top surface of the oxide layer, and in a cross section perpendicular to the substrate, the gate including opposing first and second sidewalls;

[0027] A first doped region and a second doped region are formed in the substrate, wherein the first doped region is disposed in the substrate near the first sidewall, and the second doped region is disposed in the substrate near the second sidewall;

[0028] The gate, the first doped region, and the oxide layer form a memory cell; the gate, the first doped region, the second doped region, and the oxide layer form a selection cell; and the memory cell and the selection cell together form an antifuse cell.

[0029] The formation of the oxide layer includes:

[0030] A first intermediate oxide layer is formed, which covers the bottom wall and part of the sidewall of the first trench. The top surface of the first intermediate oxide layer is lower than the top surface of the substrate. The first intermediate oxide layer forms a second trench in the first trench.

[0031] A second intermediate oxide layer is formed, which is connected to the first intermediate oxide layer to form an oxide layer that covers a portion of the surface of the gate.

[0032] The gate is formed by:

[0033] A first metal layer is formed in the second trench, and the top surface of the first metal layer is flush with the top surface of the first intermediate oxide layer.

[0034] A second metal layer is formed above the first metal layer, the second metal layer covers the top surface of the first metal layer, the projection of the first metal layer on the substrate and the projection of the second metal layer on the substrate do not coincide, and the first metal layer and the second metal layer form the gate.

[0035] The formation of the second intermediate oxide layer includes:

[0036] A deposition medium material is used to fill the unfilled areas in the first trench;

[0037] The dielectric material is etched back to expose the top surface of the second metal layer, and the retained dielectric material forms a second intermediate oxide layer;

[0038] The second intermediate oxide layer located between the gate and the sidewall of the first trench forms the first oxide layer, and the first intermediate oxide layer and the remaining second intermediate oxide layers together form the second oxide layer, wherein the thickness of the first oxide layer is less than the thickness of the second oxide layer.

[0039] The formation of the oxide layer includes:

[0040] Deposition medium material, forming an initial oxide layer;

[0041] A medium material is deposited through a mask layer to form an intermediate oxide layer, the mask layer shielding a first region of the first trench, the first region being a portion of a sidewall of the first trench, the intermediate oxide layer covering the trench wall, and the thickness of the intermediate oxide layer in the first region being less than the thickness of the intermediate oxide layer in other regions of the first trench.

[0042] The intermediate oxide layer is etched back to a position below the top surface of the substrate. The intermediate oxide layer retained in the first region forms a first oxide layer, and the intermediate oxide layer retained in other regions of the first trench forms a second oxide layer. The thickness of the first oxide layer is less than the thickness of the second oxide layer, and the first oxide layer and the second oxide layer together form the oxide layer.

[0043] The formation of the oxide layer includes:

[0044] A first material is deposited to cover a first region of the first trench, forming a first initial oxide layer, wherein the first region is located in a portion of one sidewall of the first trench;

[0045] A second material is deposited to cover the other areas of the first trench, forming a second initial oxide layer;

[0046] The first initial oxide layer and the second initial oxide layer are etched back to a position below the top surface of the substrate. The retained first initial oxide layer forms the first oxide layer, and the retained second initial oxide layer forms the second oxide layer.

[0047] The dielectric constant of the first oxide layer is greater than that of the second oxide layer, and the first oxide layer and the second oxide layer together form the oxide layer.

[0048] The feature is that forming the first doped region and the second doped region includes:

[0049] The substrate is first doped to form the first doped region, which is adjacent to the first sidewall. The bottom surface of the first doped region is lower than the bottom surface of the first oxide layer and higher than the bottom surface of the gate.

[0050] The substrate is subjected to a second doping to form a second doped region, which is adjacent to the second sidewall. The bottom surface of the second doped region is lower than the top surface of the gate and higher than the bottom surface of the first oxide layer.

[0051] The method for fabricating the semiconductor structure further includes:

[0052] An insulating layer is formed above the gate, the insulating layer covering the top surface of the gate and the top surface of the oxide layer, and the top surface of the insulating layer is flush with the top surface of the substrate.

[0053] In the semiconductor structure and manufacturing method provided in this disclosure, the selection unit and the memory unit of the antifuse unit share a gate. Applying voltage to the gate can break down part of the oxide layer, so that the logic state of the memory unit can be read out through the selection unit. This reduces the size of the antifuse unit and provides more usable space for the semiconductor structure.

[0054] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0056] Figure 1 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0057] Figure 2 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0058] Figure 3 This is a top view of a semiconductor structure according to an exemplary embodiment.

[0059] Figure 4 This is a schematic cross-sectional view of the AA side of a semiconductor structure according to an exemplary embodiment.

[0060] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0061] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0062] Figure 7 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0063] Figure 8 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0064] Figure 9 This is a schematic diagram of a substrate according to an exemplary embodiment.

[0065] Figure 10 This is a schematic diagram illustrating the formation of a first dielectric layer according to an exemplary embodiment.

[0066] Figure 11 This is a schematic diagram illustrating the formation of a first intermediate oxide layer according to an exemplary embodiment.

[0067] Figure 12 This is a schematic diagram illustrating the formation of a first metal layer according to an exemplary embodiment.

[0068] Figure 13 This is a schematic diagram illustrating the formation of a second metal layer according to an exemplary embodiment.

[0069] Figure 14 This is a schematic diagram illustrating the formation of an oxide layer according to an exemplary embodiment.

[0070] Figure 15 This is a schematic diagram illustrating the formation of a first doped region and a second doped region according to an exemplary embodiment.

[0071] Figure 16 This is a schematic diagram illustrating the formation of an insulating layer according to an exemplary embodiment.

[0072] Figure 17 This is a schematic diagram illustrating the formation of a mask layer according to an exemplary embodiment.

[0073] Figure 18 This is a schematic diagram illustrating the formation of an initial oxide layer according to an exemplary embodiment.

[0074] Figure 19 This is a schematic diagram illustrating the formation of an oxide layer according to an exemplary embodiment.

[0075] Figure 20 This is a schematic diagram illustrating a formed semiconductor structure according to an exemplary embodiment.

[0076] Figure 21 This is a schematic diagram illustrating the formation of a first initial oxide layer and a second initial oxide layer according to an exemplary embodiment.

[0077] Figure 22This is a schematic diagram illustrating the formation of an oxide layer according to an exemplary embodiment.

[0078] Figure 23 This is a schematic diagram illustrating a formed semiconductor structure according to an exemplary embodiment.

[0079] Figure label:

[0080] 1. Antifuse cell; 11. Select cell; 12. Memory cell; 13. Third doped region; 14. Insulating layer; 2. Substrate; 21. Isolation structure; 22. Active region; 23. First trench; 231. First region; 24. Word line; 25. Bit line; 26. Second trench; 27. Initial doped region; 29. ​​Mask layer; 3. Gate; 31. First metal layer; 32. Second metal layer; 321. Extension; 4. First doped region; 5. Second doped region; 6. Oxide layer; 61. First oxide layer; 62. Second oxide layer; 63. First dielectric layer; 64. First intermediate oxide layer; 65. Second intermediate oxide layer; 66. Intermediate oxide layer; 67. First initial oxide layer; 68. Second initial oxide layer; 69. Initial oxide layer; 7. First sidewall; 71. First portion; 72. Second portion; 8. Second sidewall;

[0081] V1, first voltage; V2, second voltage; K1, first dielectric constant; K2, second dielectric constant. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0083] Antifuse devices are commonly used one-time programmable devices. They are used in Dynamic Random Access Memory (DRAM) and NAND flash memory. An antifuse device includes an antifuse structure, with a transistor adjacent to the antifuse structure in the memory array serving as the select transistor. The select transistor conducts to apply a programming voltage or current to the antifuse structure. The antifuse structure is a semiconductor device composed of two conductive layers and a dielectric layer between them. When unprogrammed, the conductive layers are separated by the dielectric layer, and the antifuse structure is open-circuited. During programming (with an applied high voltage), the dielectric layer is broken down by the high voltage, forming an electrical connection between the two conductive layers, and the antifuse structure short-circuits (breaks down). This breakdown process is physically one-time, permanent, and irreversible.

[0084] Antifuse devices are relatively large, occupying a large area in memory, which is not conducive to setting more memory cells in memory, nor to further reducing the size of memory.

[0085] This disclosure provides an exemplary embodiment of a semiconductor structure, such as Figure 1 , Figure 2 As shown, it includes at least one antifuse unit 1, which includes a selection unit 11 and a storage unit 12. Figure 1 , Figure 2 As shown, the semiconductor structure includes a substrate 2, a gate 3, a first doped region 4, a second doped region 5, and an oxide layer 6. The oxide layer 6 covers a portion of the surface of the gate 3. The gate 3 is disposed in the substrate 2, and in a cross-section perpendicular to the substrate 2, the gate 3 includes opposing first sidewalls 7 and second sidewalls 8. The first doped region 4 is disposed in the substrate 2 near the first sidewall 7, and the second doped region 5 is disposed in the substrate 2 near the second sidewall 8. The gate 3, the first doped region 4, and the oxide layer 6 constitute a memory cell 12, and the gate 3, the first doped region 4, the second doped region 5, and the oxide layer 6 constitute a selection cell 11.

[0086] like Figure 1 , Figure 2 As shown, in a cross-section perpendicular to the substrate 2, the top surface of the gate 3 is higher than the bottom surface of the first doped region 4 and the bottom surface of the second doped region 5. The oxide layer 6 covers the first sidewall 7, the second sidewall 8, and the bottom surface of the gate 3, separating the gate 3 from the substrate 2. In this embodiment, the antifuse unit 1, the selection unit 11, and the storage unit 12 share the gate 3. Applying a voltage to the gate 3 breaks down part of the oxide layer 6, establishing an electrical connection between the gate 3 and the first doped region 4. This eliminates the need for adjacent transistors as the selection transistors for the antifuse unit 1, reducing its size and freeing up more usable space in the semiconductor structure.

[0087] According to an exemplary embodiment, such as Figure 1 , Figure 2 As shown, oxide layer 6 includes a first oxide layer 61 and a second oxide layer 62, memory cell 12 includes the first oxide layer 61, and selection cell 11 includes the second oxide layer 62. For example, a portion of the region between the first doped region 4 and the first sidewall 7 is separated by the first oxide layer 61, and another portion of the region between the first doped region 4 and the first sidewall 7 is separated by the second oxide layer 62. The second oxide layer 62 also covers the second sidewall 8 and the bottom surface of the gate 3, and the second sidewall 8 and the bottom surface of the gate 3 are separated from the substrate 2 by the second oxide layer 62.

[0088] like Figure 1 , Figure 2 As shown, the projection of the first doped region 4 on the first sidewall 7 overlaps the projection of the first oxide layer 61 on the first sidewall 7, and the second oxide layer 62 includes the oxide layer 6 other than the first oxide layer 61. In this embodiment, as... Figure 1 , Figure 2 As shown, in a cross-section perpendicular to the substrate 2, the bottom surface of the first oxide layer 61 is higher than the bottom surface of the first doped region 4. For example, in the direction from the top surface of the gate 3 to the bottom surface, the first sidewall 7 includes a first portion 71 and a second portion 72 arranged sequentially. The bottom surface of the first portion 71 is higher than the bottom surface of the first doped region 4. The first oxide layer 61 is located between the first portion 71 and the first doped region 4. The second oxide layer 62 is located between the second portion 72 and the first doped region 4. The second oxide layer 62 is also located between the second sidewall 8 and the substrate 2, and between the bottom surface of the gate 3 and the substrate 2.

[0089] In this embodiment, the breakdown voltages of the first oxide layer 61 and the second oxide layer 62 are different. The breakdown voltage of the first oxide layer 61 is lower than that of the second oxide layer 62, meaning the first oxide layer 61 is more easily broken down than the second oxide layer 62. For example, if the breakdown voltage of the first oxide layer 61 is a first voltage V1, and the breakdown voltage of the second oxide layer 62 is greater than the first voltage V1, then applying the first voltage V1 to the gate 3 is sufficient to break down the first oxide layer 61, causing a short circuit between the gate 3 and the first doped region 4.

[0090] like Figure 1 , Figure 2As shown, the selection unit 11 further includes a third doped region 13, which is disposed in the substrate 2, located between the first doped region 4 and the second doped region 5, and surrounds a portion of the oxide layer 6. Furthermore, the conductivity type of the dopant ions in the first doped region 4 is the same as that in the second doped region 5, while the conductivity type of the dopant ions in the third doped region 13 is opposite to that in the first and second doped regions 5. For example, the dopant ions in the first and second doped regions 4 and 5 are both N-type conductive dopant ions, and the dopant ions in the third doped region 13 are P-type conductive dopant ions. Alternatively, the dopant ions in the first and second doped regions 4 and 5 are both P-type conductive dopant ions, and the dopant ions in the third doped region 13 are N-type conductive dopant ions.

[0091] Reference Figure 1 , Figure 2 In this embodiment, during writing, the antifuse unit 1 floats the first doped region 4 and applies a first voltage V1 to the gate 3, which breaks down the first oxide layer 61, forming a conductive path between the gate 3 and the first doped region 4. Since the first voltage V1 does not reach the breakdown voltage of the second oxide layer 62, the second oxide layer 62 will not be mistakenly broken down, and the selection unit 11 continues to operate.

[0092] When the antifuse unit 1 in this embodiment performs a read operation, a second voltage V2 is applied to the gate 3. The second voltage V2 is less than the first voltage V1. The selection unit 11 is turned on under the drive of the second voltage V2. Induced charges are generated in the third doped region 13 below the gate 3 through the edge electric field effect. A conductive channel is formed in the third doped region 13. The charges in the first doped region 4 move to the second doped region 5 through the conductive channel. The logic value of the antifuse unit 1 can be read through the second doped region 5.

[0093] In this embodiment, oxide layer 6 consists of a first oxide layer 61 and a second oxide layer 62 with different breakdown voltages. The breakdown voltage of oxide layer 6 is related to the dielectric constant and thickness of oxide layer 6, where Q = CV, Q is the charge, U is the voltage, and C is the capacitance. The equivalent capacitance C = V Q When the charge is equal, the breakdown voltage of oxide layer 6 is inversely proportional to the equivalent capacitance of oxide layer 6. In this embodiment, the dielectric constant of the first oxide layer 61 is greater than that of the second oxide layer 62; and / or, the thickness of the first oxide layer 61 is less than that of the second oxide layer 62, resulting in a breakdown voltage of the first oxide layer 61 being less than that of the second oxide layer 62, so as to form a region that is easily broken down between the first doped region 4 and the first sidewall 7.

[0094] In some embodiments, such as Figure 2As shown, the thickness of the first oxide layer 61 is the same as the thickness of the second oxide layer 62, the dielectric constant of the first oxide layer 61 is greater than the dielectric constant of the second oxide layer 62, and the breakdown voltage of the first oxide layer 61 is greater than the breakdown voltage of the second oxide layer 62.

[0095] In some embodiments, such as Figure 1 As shown, the dielectric constant of the first oxide layer 61 is the same as that of the second oxide layer 62, the thickness of the first oxide layer 61 is less than the thickness of the second oxide layer 62, and the breakdown voltage of the first oxide layer 61 is less than the breakdown voltage of the second oxide layer 62. It can be understood that, as... Figure 1 As shown, the thickness of the second oxide layer 62 does not have to be uniform; the thickness of the second oxide layer 62 at different locations can be greater than that of the first oxide layer 61.

[0096] In some embodiments, the dielectric constant of the first oxide layer 61 is greater than that of the second oxide layer 62, and the thickness of the first oxide layer 61 is less than that of the second oxide layer 62, so that the critical voltage at which the first oxide layer 61 is broken down is smaller, that is, the first voltage V1 is smaller, thereby reducing the difficulty of breaking down the first oxide layer 61 and shortening the time required for the first oxide layer 61 to be broken down.

[0097] like Figure 1 , Figure 2 As shown, in some embodiments, the top surface of the gate 3 is lower than the top surface of the substrate 2. The semiconductor structure also includes an insulating layer 14 that covers the top surface of the gate 3 and the top surface of the oxide layer 6, and the top surface of the insulating layer 14 is flush with the top surface of the substrate 2.

[0098] According to an exemplary embodiment, a semiconductor structure is provided, which includes all the structures of the semiconductor structures described in the above embodiments. In this embodiment, as... Figure 3 , Figure 4 As shown, the substrate 2 includes an isolation structure 21, which divides the substrate 2 into multiple independently disposed active regions 22. In a cross-section perpendicular to the substrate 2, the bottom surface of the isolation structure 21 is lower than the bottom surface of the gate 3. Each active region 22 has two first doped regions 4 at its two ends and a second doped region 5 in its middle region. The active region 22 also includes a first trench 23, which is disposed between the first doped regions 4 and the second doped regions 5. Each active region 22 includes two first trenches 23.

[0099] like Figure 3 , Figure 4As shown, each first trench 23 is provided with a gate 3. The gate 3, the first doped region 4, and the oxide layer 6 constitute a memory cell 12. The gate 3, the first doped region 4, the second doped region 5, and the oxide layer 6 constitute a selection cell 11. The selection cell 11 and the memory cell 12 together form an antifuse cell 1. Figure 4 As shown, the selection unit 11 also includes a third doped region 13 disposed in the substrate 2. The third doped region 13 surrounds a portion of the oxide layer 6, and the first doped region 4 and the second doped region 5 are connected through the third doped region 13.

[0100] like Figure 3 , Figure 4 As shown, two antifuse units 1 are formed in each active region 22, and the two antifuse units 1 share the same second doped region 5. Two adjacent antifuse units 1 are located in the same active region 22, or are separated by an isolation structure 21.

[0101] In this embodiment, as Figure 3 As shown, the semiconductor structure also includes a word line 24, which extends in the substrate 2. The gate 3 is electrically connected to the word line 24, and a programming voltage can be applied to the gate 3 through the word line 24.

[0102] In this embodiment, as Figure 3 , Figure 4 As shown, the semiconductor structure also includes a bit line 25 extending on the substrate 2, the extension direction of the bit line 25 intersecting the extension direction of the word line 24. The bit line 25 is electrically connected to the second doped region 5, and the logic value of the antifuse unit 1 can be read through the bit line 25.

[0103] The semiconductor structure of this embodiment reduces the number of semiconductor devices constituting the antifuse unit 1, eliminates the need for additional selection transistors for the antifuse unit 1, reduces the area occupied by the antifuse unit 1, and provides more usable space for the semiconductor structure.

[0104] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments, such as... Figure 5 As shown, Figure 5 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 9-23 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 9-23 The methods for fabricating semiconductor structures are introduced.

[0105] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0106] like Figure 5As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0107] Step S110: Provide a substrate and form a first trench in the substrate.

[0108] Reference Figure 9 Substrate 2 can be a semiconductor substrate, which may include silicon substrate, germanium (Ge) substrate, silicon germanide (SiGe) substrate, SOI (Silicon-on-insulator) substrate or GOI (Germanium-on-Insulator) substrate, etc.

[0109] In this embodiment, the substrate 2 includes an initial doped region 27, such as Figure 9 The initial doped region 27 of substrate 2 is shown. It will be understood that substrate 2 may also include other structures. Substrate 2 may include one or more initial doped regions 27, the dopant ions of which have a first conductivity doping type, which may be a P-type or an N-type conductivity doping type. (Refer to...) Figure 9 The initial doped region 27 is partially removed by etching, and a first trench 23 is formed in the substrate 2. The depth of the first trench 23 is less than the doping depth of the initial doped region 27, and the retained initial doped region 27 surrounds the trench wall of the first trench 23.

[0110] Step S120: Form an oxide layer that covers the bottom wall and part of the sidewall of the first trench, with the top surface of the oxide layer being lower than the top surface of the substrate.

[0111] like Figure 14 , Figure 19 , Figure 22 As shown, the oxide layer 6 can be deposited using any of the following deposition processes: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or sputtering. The oxide layer 6 covers the bottom wall and part of the sidewalls of the first trench 23, and the top surface of the oxide layer 6 is lower than the top surface of the substrate 2. The material of the oxide layer 6 may include silicon oxide or silicon oxynitride, etc.

[0112] Step S130: Form a gate, the gate covers an oxide layer and fills part of the first trench, the top surface of the gate is flush with the top surface of the oxide layer, and in a cross section perpendicular to the substrate, the gate includes opposing first sidewalls and second sidewalls.

[0113] like Figure 14 , Figure 20 , Figure 23 As shown, in this embodiment, the gate 3 is deposited using any of the above-described deposition processes. The gate 3 covers the oxide layer 6 and fills a portion of the first trench 23. The gate 3 includes a first sidewall 7 and a second sidewall 8 disposed opposite to each other. The material of the gate 3 may include at least one of titanium or its alloys, tantalum or its alloys, and tungsten or its alloys.

[0114] Step S140: An insulating layer is formed above the gate, the insulating layer covers the top surface of the gate and the top surface of the oxide layer, and the top surface of the insulating layer is flush with the top surface of the substrate.

[0115] like Figure 15 , Figure 20 , Figure 23 As shown, refer to Figure 14 An insulating layer 14 can be deposited using any one of the following deposition processes: chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The insulating layer 14 covers the top surface of the gate 3 and the top surface of the oxide layer 6, and fills the unfilled area of ​​the first trench 23. In this embodiment, the material of the insulating layer 14 may include at least one of silicon nitride or silicon oxynitride. The insulating layer 14 is used to isolate devices in the semiconductor structure, preventing short circuits when the semiconductor structure is powered on. Furthermore, the insulating layer 14 can prevent contamination of the gate 3 by the processes forming the first doped region 4 and the second doped region 5 (described in detail in subsequent steps).

[0116] Step S150: A first doped region and a second doped region are formed in the substrate. The first doped region is disposed in the substrate near the first sidewall, and the second doped region is disposed in the substrate near the second sidewall.

[0117] like Figure 16 , Figure 20 , Figure 23 As shown, in this embodiment, dopant ions of a second conductivity type are implanted into the substrate 2 near the first sidewall 7 using an ion implantation process to form a first doped region 4. Dopant ions of a second conductivity type are implanted into the substrate 2 near the second sidewall 8 to form a second doped region 5. The second conductivity doping type is opposite to the first conductivity doping type; the second conductivity doping type can be either an N-type or a P-type conductivity doping type. In this embodiment, the bottom surface of the first doped region 4 is higher than the bottom surface of the gate 3, and the bottom surface of the second doped region 5 is higher than the bottom surface of the gate 3. Figure 16 , Figure 20 , Figure 23As shown, after the first doped region 4 and the second doped region 5 are formed, the retained initial doped region 27 is formed into the third doped region 13. The third doped region 13 is located between the first doped region 4 and the second doped region 5, and the third doped region 13 surrounds part of the oxide layer 6.

[0118] It is understood that the first doped region 4 and the second doped region 5 can be formed by doping the initial doped region 27 with dopants of the second conductivity type. That is, the first doped region 4 and the second doped region 5 can include dopants of the first conductivity type. The concentration of dopants of the second conductivity type in the first doped region 4 and the second doped region 5 is greater than that of dopants of the first conductivity type. The conductivity type of the first doped region 4 and the second doped region 5 is the second conductivity type.

[0119] like Figure 16 , Figure 20 , Figure 23 As shown, gate 3, first doped region 4, and oxide layer 6 form memory cell 12, and gate 3, first doped region 4, second doped region 5, and oxide layer 6 form selection cell 11. Memory cell 12 and selection cell 11 together form antifuse cell 1. In this embodiment, selection cell 11 further includes third doped region 13.

[0120] In this embodiment, the selection unit and the memory unit share a gate, eliminating the need to use adjacent transistors as the selection transistors in the antifuse structure. This reduces the size of the antifuse unit and frees up more usable space for the semiconductor structure.

[0121] like Figure 6 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0122] Step S210: Provide a substrate and form a first trench in the substrate.

[0123] like Figure 9 As shown, the substrate 2 provided in this embodiment is the same as the substrate 2 provided in step S110 of the above embodiment, and will not be described again here.

[0124] Step S220: Form a first intermediate oxide layer, which covers the bottom wall and part of the sidewall of the first trench. The top surface of the first intermediate oxide layer is lower than the top surface of the substrate. The first intermediate oxide layer forms a second trench in the first trench.

[0125] In this embodiment, the first intermediate oxide layer can be formed using the following implementation method:

[0126] First, such as Figure 10As shown, a first dielectric layer 63 is formed by depositing a dielectric material through any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering. The first dielectric layer 63 covers the bottom wall and sidewalls of the first trench 23.

[0127] Then, as Figure 11 As shown, the first dielectric layer 63 is etched back to a predetermined depth, and the first dielectric layer 63 retained in the first trench 23 forms a first intermediate oxide layer 64, which in turn forms a second trench 26 in the first trench 23.

[0128] Step S230: A first metal layer is formed in the second trench, the top surface of the first metal layer being flush with the top surface of the first intermediate oxide layer.

[0129] In this embodiment, as Figure 12 As shown, refer to Figure 11 The first metal layer 31 is formed in the second trench 26. The following implementation method can be adopted: deposit conductive metal by any of the above deposition processes, the conductive metal covers the first dielectric layer 63 and fills the second trench 26 to form the first metal layer 31.

[0130] Step S240: A second metal layer is formed above the first metal layer, the second metal layer covers the top surface of the first metal layer, the projection of the first metal layer on the substrate and the projection of the second metal layer on the substrate do not coincide, and the first metal layer and the second metal layer form a gate.

[0131] In this embodiment, a second metal layer 32 is formed above the first metal layer 31, which can be achieved through the following implementation:

[0132] Form the first mask (not shown in the figure), refer to Figure 12 The first mask covers the sidewall of the first trench 23 exposed by the first intermediate oxide layer 64, and the width of the first mask covering the sidewalls of the first trench 23 is different. The first mask exposes part of the top surface of the first intermediate oxide layer 64 covering one sidewall of the first trench 23.

[0133] Then, as Figure 13 As shown, refer to Figure 12 Conductive metal is deposited using atomic layer deposition (ALD) to fill the unfilled areas of the first trench 23. Next, the conductive metal is etched back until its top surface is below the top surface of the substrate 2, forming a second metal layer 32 above the first metal layer 31. In this embodiment, as... Figure 13As shown, one side of the second metal layer 32 extends toward the sidewall of the first trench 23 to form an extension 321. The extension 321 covers part of the top surface of the first intermediate oxide layer 64. The projection of the first metal layer 31 on the substrate 2 is within the range of the projection of the second metal layer 32 on the substrate 2. The first metal layer 31 and the second metal layer 32 form the gate 3.

[0134] In this embodiment, after the second metal layer 32 is formed, the first mask is removed by dry or wet etching. For example, the first mask can be removed by dissolving it with an etching solution.

[0135] Step S250: A second intermediate oxide layer is formed, which is connected to the first intermediate oxide layer to form an oxide layer that covers a portion of the gate surface.

[0136] In this embodiment, as Figure 14 As shown, refer to Figure 13 First, a dielectric material is deposited using any of the above-described deposition processes, filling the unfilled areas in the first trench 23. Then, the dielectric material is etched back to expose the top surface of the second metal layer 32, and the retained dielectric material forms the second intermediate oxide layer 64.

[0137] like Figure 13 , Figure 14 , Figure 15 As shown, the second intermediate oxide layer 65 located between the gate 3 and the sidewall of the first trench 23 forms the first oxide layer 61, and the first intermediate oxide layer 64 and the remaining second intermediate oxide layers 65 together form the second oxide layer 62. The thickness of the first oxide layer 61 is less than the thickness of the second oxide layer 62.

[0138] In this embodiment, the materials of the first intermediate oxide layer 64 and the second intermediate oxide layer 65 are the same, therefore the materials of the first oxide layer 61 and the second oxide layer 62 are also the same. That is, the dielectric constants of the first oxide layer 61 and the second oxide layer 62 are the same, but the thickness of the first oxide layer 61 is less than the thickness of the second oxide layer 62, so that the breakdown voltage of the first oxide layer 61 is less than the breakdown voltage of the second oxide layer 62. The breakdown voltage of the first oxide layer 61 is a first voltage V1. Applying the first voltage V1 to the gate will break down the first oxide layer 61, forming a conductive path in the gate 3 and the first doped region 4 (described in detail in subsequent steps) (see reference). Figure 1 or Figure 2 ).

[0139] Step S260: An insulating layer is formed above the gate, the insulating layer covers the top surface of the gate and the top surface of the oxide layer, and the top surface of the insulating layer is flush with the top surface of the substrate.

[0140] The implementation method of step S260 in this embodiment is the same as that of step S140 in the above embodiment, and will not be repeated here.

[0141] Step S270: A first doped region and a second doped region are formed in the substrate. The first doped region is disposed in the substrate near the first sidewall, and the second doped region is disposed in the substrate near the second sidewall.

[0142] like Figure 16 As shown, the substrate 2 is first doped to form a first doped region 4. The first doped region 4 is adjacent to the first sidewall 7. The bottom surface of the first doped region 4 is lower than the bottom surface of the first oxide layer 61 and higher than the bottom surface of the gate 3. The first doped region 4 and the gate 3 are partially separated by the first oxide layer 61 and partially separated by the second oxide layer 62, so that the second oxide layer 62 still has an isolation effect after the first oxide layer 61 is broken down.

[0143] like Figure 16 As shown, the substrate 2 is subjected to a second doping to form a second doped region 5. The second doped region 5 is adjacent to the second sidewall 8. The bottom surface of the second doped region 5 is lower than the top surface of the gate 3 and higher than the bottom surface of the first oxide layer 61.

[0144] like Figure 16 As shown, after the first doped region 4 and the second doped region 5 are formed, the initial doped region 27 retained in the substrate 2 is formed as the third doped region 13.

[0145] The fabrication method of this embodiment forms an oxide layer through two depositions, so that the oxide layer includes a first oxide layer and a second oxide layer with different thicknesses. The thickness of the first oxide layer is thinner than that of the second oxide layer, and the breakdown voltage of the first oxide layer is lower than that of the second oxide layer. The first oxide layer is located between the gate and the first doped region. When a first voltage or a voltage higher than the first voltage is applied to the gate, the first oxide layer can be broken down, completing the writing of the antifuse cell. There is no need to configure a selection transistor for the antifuse cell.

[0146] like Figure 7 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0147] Step S310: Provide a substrate and form a first trench in the substrate.

[0148] like Figure 17 As shown, the substrate 2 provided in this embodiment is the same as the substrate 2 provided in step S110 of the above embodiment, and will not be described again here.

[0149] Step S320: Deposit the medium material to form an initial oxide layer.

[0150] In this embodiment, a dielectric material is deposited using any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering processes. The dielectric material covers the wall of the first trench 23, forming an initial oxide layer 69.

[0151] Step S330: Deposit a medium material through a mask layer to form an intermediate oxide layer. The mask layer covers a first region of the first trench, which is a portion of one sidewall of the first trench.

[0152] like Figure 17 As shown, after the initial oxide layer 69 is formed, a mask layer 29 is formed, which masks the first region 231 of the first trench 23. Figure 18 As shown, dielectric material is deposited based on mask layer 29, covering the initial oxide layer 69 outside the first region 231. Deposition stops after the dielectric material in other regions outside the first region 231 reaches the target thickness. The initial oxide layer 69 and the dielectric material covering the initial oxide layer 69 together form the intermediate oxide layer 66. The thickness of the intermediate oxide layer 66 located in the first region 231 is thinner than the thickness of the intermediate oxide layers 66 located in other regions.

[0153] Step S340: Irradiate the intermediate oxide layer back to a position below the top surface of the substrate. The intermediate oxide layer retained in the first region forms the first oxide layer, and the intermediate oxide layer retained in the other regions of the first trench forms the second oxide layer. The thickness of the first oxide layer is less than the thickness of the second oxide layer, and the first oxide layer and the second oxide layer together form the oxide layer.

[0154] like Figure 19 As shown, refer to Figure 18 The intermediate oxide layer 66 is etched back, and the retained intermediate oxide layer 66 forms oxide layer 6, with the top surface of oxide layer 6 higher than the bottom surface of the first region 231. The retained intermediate oxide layer 66 in the first region 231 forms the first oxide layer 61, and the retained intermediate oxide layers 66 in other regions form the second oxide layer 62. The thickness of the first oxide layer 61 is less than the thickness of the second oxide layer 62, and the first oxide layer 61 and the second oxide layer 62 together form oxide layer 6.

[0155] Step S350: Form a gate, the gate covers an oxide layer and fills a portion of the first trench, the top surface of the gate is flush with the top surface of the oxide layer, and in a cross section perpendicular to the substrate, the gate includes opposing first and second sidewalls.

[0156] In this embodiment, refer to Figure 20 As shown, the gate 3 can be formed in the following manner: First, after forming the initial oxide layer 66, a conductive metal is deposited by any of the above deposition processes. The conductive metal covers the initial oxide layer 66 and fills the unfilled portion of the first trench 23.

[0157] Then, the conductive metal is etched back to a point where its top surface is lower than the top surface of the substrate 2, and the conductive metal retained in the first trench 23 forms the gate 3. In this embodiment, the etch-back of the intermediate oxide layer 66 and the etch-back of the conductive metal are performed in the same etching process, and the etching process has the same etching selectivity for the initial oxide layer 66 and the conductive metal, so the oxide layer 6 and the gate 3 are formed simultaneously.

[0158] Step S360: An insulating layer is formed above the gate, the insulating layer covers the top surface of the gate and the top surface of the oxide layer, and the top surface of the insulating layer is flush with the top surface of the substrate.

[0159] Step S370: A first doped region and a second doped region are formed in the substrate. The first doped region is disposed in the substrate near the first sidewall, and the second doped region is disposed in the substrate near the second sidewall.

[0160] The implementation methods of steps S360 and S370 in this embodiment are the same as those of steps S260 and S270 in the above embodiments, and will not be repeated here.

[0161] In this embodiment, the first oxide layer and the second oxide layer are made of the same material and have the same dielectric constant. The thickness of the first oxide layer is thinner than that of the second oxide layer. Therefore, the breakdown voltage of the first oxide layer is less than that of the second oxide layer.

[0162] In this embodiment, the first oxide layer and the second oxide layer are formed by the same deposition process, which simplifies the process steps, saves process costs and time, and improves production efficiency.

[0163] like Figure 8 As shown, an exemplary embodiment of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0164] Step S410: Provide a substrate and form a first trench in the substrate.

[0165] Reference Figure 21 The substrate 2 provided in this embodiment is the same as the substrate 2 provided in step S110 of the above embodiment, and will not be described again here.

[0166] Step S420: Deposit a first material to cover a first region of the first trench, forming a first initial oxide layer. The first region is located in a portion of one sidewall of the first trench.

[0167] like Figure 21As shown, firstly, a second mask (not shown) is formed, covering the bottom wall and part of the sidewall of the first trench 23. The second mask exposes a first region 231, which is located on one sidewall of the first trench 23. Then, a first material is deposited using any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition, or sputtering to form a first initial oxide layer 67 in the first region 231, wherein the first material has a first dielectric constant K1.

[0168] Step S430: Deposit a second material to cover the other areas of the first trench, forming a second initial oxide layer.

[0169] like Figure 21 As shown, firstly, a third mask is formed, covering the first initial oxide layer 67. The second mask is then removed, exposing the remaining areas of the first trench 23. Next, a second material is deposited using any of the above deposition processes to form a second initial oxide layer 68, covering the bottom wall of the first trench 23 and the exposed sidewalls of the first trench 23. The second material has a second dielectric constant K2, where the first dielectric constant K1 is greater than the second dielectric constant K2.

[0170] Step S440: Irradiate the first initial oxide layer and the second initial oxide layer back to below the top surface of the substrate. The retained first initial oxide layer forms the first oxide layer, and the retained second initial oxide layer forms the second oxide layer.

[0171] like Figure 21 , Figure 22 As shown, the first initial oxide layer 67 and the second initial oxide layer 68 are etched back. The first initial oxide layer 67 that is retained after etching back forms the first oxide layer 61, and the second initial oxide layer 68 that is retained forms the second oxide layer 38. The first oxide layer 61 and the second oxide layer 62 together form the oxide layer 6.

[0172] Step S450: Form a gate, the gate is covered with an oxide layer and partially fills the first trench, the top surface of the gate is flush with the top surface of the oxide layer, and in a cross section perpendicular to the substrate, the gate includes opposing first and second sidewalls.

[0173] Step S460: An insulating layer is formed above the gate, the insulating layer covering the top surface of the gate and the top surface of the oxide layer, and the top surface of the insulating layer is flush with the top surface of the substrate.

[0174] Step S470: A first doped region and a second doped region are formed in the substrate. The first doped region is disposed in the substrate near the first sidewall, and the second doped region is disposed in the substrate near the second sidewall.

[0175] The implementation methods of steps S450-S470 in this embodiment are the same as those of steps S350-S370 in the above embodiment, and will not be repeated here.

[0176] like Figure 23 As shown, in the semiconductor structure formed in this embodiment, the thickness of the first oxide layer 61 is the same as the thickness of the second oxide layer 62. The dielectric constant of the first oxide layer 61 is greater than that of the second oxide layer 62, so that the breakdown voltage of the first oxide layer 61 is less than that of the second oxide layer 62. The first oxide layer 61 is more easily broken down than the second oxide layer 62, forming a conductive path between the gate 3 and the first doped region 4.

[0177] In this embodiment, the breakdown voltage of the partial oxide layer between the first sidewall and the first doped region is different from that of the remaining oxide layer, making the partial oxide layer between the gate and the first doped region easier to break down. Furthermore, when forming the first doped region, the depth of the first doping is defined according to the bottom surface of the first oxide layer and the bottom surface of the gate, so that the bottom surface of the first doped region is higher than the bottom surface of the gate and lower than the bottom surface of the first oxide layer. This allows the gate and the first doped region, as well as the gate, the second oxide layer, the first doped region, and the second doped region, to continue to function as transistors without the need for additional selection transistors for the antifuse unit. The antifuse unit is composed of only one semiconductor device, reducing the size of the antifuse unit and providing more usable space for the semiconductor structure.

[0178] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0179] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0180] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0181] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0182] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0183] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes at least one antifuse unit, wherein the antifuse unit includes a selection unit and a memory unit, and the semiconductor structure includes: Substrate; A gate, disposed in the substrate, wherein in a cross section perpendicular to the substrate, the gate includes opposing first and second sidewalls; A first doped region is disposed in the substrate near the first sidewall; A second doped region is disposed in the substrate near the second sidewall; An oxide layer covers a portion of the surface of the gate. The gate, the first doped region, and the oxide layer constitute the memory cell, and the gate, the first doped region, the second doped region, and the oxide layer constitute the selection cell; The oxide layer includes a first oxide layer and a second oxide layer, the storage cell includes the first oxide layer, and the selection cell includes the second oxide layer; the projection of the first doped region on the first sidewall covers the projection of the first oxide layer on the first sidewall, and the second oxide layer includes the oxide layer other than the first oxide layer.

2. The semiconductor structure according to claim 1, characterized in that, The dielectric constant of the first oxide layer is greater than that of the second oxide layer.

3. The semiconductor structure according to claim 1, characterized in that, The thickness of the first oxide layer is less than the thickness of the second oxide layer.

4. The semiconductor structure according to claim 1, characterized in that, In a cross-section perpendicular to the substrate, the bottom surface of the first oxide layer is higher than the bottom surface of the first doped region.

5. The semiconductor structure according to claim 1, characterized in that, The selection unit further includes a third doped region disposed in the substrate, the third doped region being located between the first doped region and the second doped region, and the third doped region surrounding a portion of the oxide layer; The conductivity type of the doped ions in the first doped region is the same as that of the doped ions in the second doped region, and the conductivity type of the doped ions in the third doped region is opposite to that of the doped ions in the first and second doped regions.

6. The semiconductor structure according to claim 1, characterized in that, In a cross-section perpendicular to the substrate, the top surface of the gate is higher than the bottom surface of the first doped region and the bottom surface of the second doped region.

7. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: An insulating layer covers the top surface of the gate and the top surface of the oxide layer, the top surface of the insulating layer being flush with the top surface of the substrate.

8. A method for fabricating a semiconductor structure, characterized in that, The method for fabricating the semiconductor structure includes: A substrate is provided, and a first trench is formed in the substrate; An oxide layer is formed, which covers the bottom wall and part of the sidewall of the first trench, and the top surface of the oxide layer is lower than the top surface of the substrate; A gate is formed, the gate covering the oxide layer and filling a portion of the first trench, the top surface of the gate being flush with the top surface of the oxide layer, and in a cross section perpendicular to the substrate, the gate including opposing first and second sidewalls; A first doped region and a second doped region are formed in the substrate, wherein the first doped region is disposed in the substrate near the first sidewall, and the second doped region is disposed in the substrate near the second sidewall; The gate, the first doped region, and the oxide layer form a memory cell; the gate, the first doped region, the second doped region, and the oxide layer form a selection cell; and the memory cell and the selection cell together form an antifuse cell.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Forming an oxide layer includes: A first intermediate oxide layer is formed, which covers the bottom wall and part of the sidewall of the first trench. The top surface of the first intermediate oxide layer is lower than the top surface of the substrate. The first intermediate oxide layer forms a second trench in the first trench. A second intermediate oxide layer is formed, which is connected to the first intermediate oxide layer to form an oxide layer that covers a portion of the surface of the gate.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, Forming a gate includes: A first metal layer is formed in the second trench, and the top surface of the first metal layer is flush with the top surface of the first intermediate oxide layer. A second metal layer is formed above the first metal layer, the second metal layer covers the top surface of the first metal layer, the projection of the first metal layer on the substrate and the projection of the second metal layer on the substrate do not coincide, and the first metal layer and the second metal layer form the gate.

11. The method for fabricating a semiconductor structure according to claim 10, characterized in that, Forming a second intermediate oxide layer includes: A deposition medium material is used to fill the unfilled areas in the first trench; The dielectric material is etched back to expose the top surface of the second metal layer, and the retained dielectric material forms a second intermediate oxide layer; The second intermediate oxide layer located between the gate and the sidewall of the first trench forms the first oxide layer, and the first intermediate oxide layer and the remaining second intermediate oxide layers together form the second oxide layer, wherein the thickness of the first oxide layer is less than the thickness of the second oxide layer.

12. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Forming an oxide layer includes: Deposition medium material, forming an initial oxide layer; A medium material is deposited through a mask layer to form an intermediate oxide layer, the mask layer shielding a first region of the first trench, the first region being a portion of a sidewall of the first trench, the intermediate oxide layer covering the trench wall, and the thickness of the intermediate oxide layer in the first region being less than the thickness of the intermediate oxide layer in other regions of the first trench. The intermediate oxide layer is etched back to a position below the top surface of the substrate. The intermediate oxide layer retained in the first region forms a first oxide layer, and the intermediate oxide layer retained in other regions of the first trench forms a second oxide layer. The thickness of the first oxide layer is less than the thickness of the second oxide layer, and the first oxide layer and the second oxide layer together form the oxide layer.

13. The method for fabricating a semiconductor structure according to claim 8, characterized in that, Forming an oxide layer includes: A first material is deposited to cover a first region of the first trench, forming a first initial oxide layer, wherein the first region is located in a portion of one sidewall of the first trench; A second material is deposited to cover the other areas of the first trench, forming a second initial oxide layer; The first initial oxide layer and the second initial oxide layer are etched back to a position below the top surface of the substrate. The retained first initial oxide layer forms the first oxide layer, and the retained second initial oxide layer forms the second oxide layer. The dielectric constant of the first oxide layer is greater than that of the second oxide layer, and the first oxide layer and the second oxide layer together form the oxide layer.

14. The method for fabricating a semiconductor structure according to any one of claims 11, 12, or 13, characterized in that, Forming the first doped region and the second doped region includes: The substrate is first doped to form the first doped region, which is adjacent to the first sidewall. The bottom surface of the first doped region is lower than the bottom surface of the first oxide layer and higher than the bottom surface of the gate. The substrate is subjected to a second doping to form a second doped region, which is adjacent to the second sidewall. The bottom surface of the second doped region is lower than the top surface of the gate and higher than the bottom surface of the first oxide layer.

15. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The method for fabricating the semiconductor structure further includes: An insulating layer is formed above the gate, the insulating layer covering the top surface of the gate and the top surface of the oxide layer, and the top surface of the insulating layer is flush with the top surface of the substrate.

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