A method for communication between a master device and at least one slave device according to the TDMA protocol.

Abstract

According to the TDMA protocol, a method for communication between a master device and at least one slave device is used. During communication, multiple frames are transmitted between the master device and the slave device. Each frame is divided into multiple time slots. At least one time slot includes an analog synchronization signal (S). The analog synchronization signal includes an amplitude setting unit (S1) and an optimized synchronization unit (S2). The amplitude setting unit is in the form of a sine wave with a constant amplitude during a set number of pulses. The optimized synchronization unit is in the form of a triangular amplitude modulation of a sine wave to determine a reference time (TOP).

Description

Technical Field

[0001] This invention relates to the field of synchronization between a master device and at least one slave device communicating according to a Time Division Multiple Access (TDMA) protocol. Background Technology

[0002] As is known, the master device and slave device transmit frames according to the TDMA protocol. Each frame is divided into time slots for communication between the master device or the slave device. The master device includes a master clock for timing data transmission. Similarly, each slave device includes a slave clock for timing data reception.

[0003] For optimal data reception, the master and slave clocks must be perfectly synchronized. In practice, frame time slots comprise analog waveforms modulated by digital signals. Clocks are known to be digitally synchronized via a program clock reference (PCR) defined by digital signals. Clock synchronization depends on the transmission of the program clock reference (PCR).

[0004] In practice, frequency errors (drift, etc.) in the slave clock are detected by comparing the timestamp provided by the Programmed Clock Reference (PCR) with the value of the slave device's time counter. After detection, the slave clock frequency can be corrected. This synchronization method has several drawbacks.

[0005] First, the low timestamp accuracy of data packets within a frame affects synchronization quality. Microsecond-level accuracy is required. Additionally, synchronization solutions based on digital signal correlations impact throughput because dedicated space must be provided in each frame for the analog wave modulated by the digital signal.

[0006] Furthermore, in order to extract the master clock, the slave device must include extraction circuitry, which includes a digital processing chain that must be kept running at all times. In other words, from an energy perspective, the digital processing chain is high-power, which is a disadvantage for embedded slave devices that do not have large-capacity batteries.

[0007] The prior art methods can be obtained through patents EP3444975A1 and WO2014 / 0915592A.

[0008] Therefore, the present invention aims to at least partially eliminate the above-mentioned disadvantages by providing a new communication method based on the TDMA protocol. Summary of the Invention

[0009] The present invention relates to a method for communication between a master device and at least one slave device according to a TDMA protocol, wherein during the communication, multiple frames are transmitted between the master device and the slave device, each frame being divided into multiple time slots, at least one time slot including an analog synchronization signal transmitted from the master device to the slave device, the analog synchronization signal including an amplitude setting part and an optimized synchronization part, the amplitude setting part being in the form of a sine wave having a constant amplitude during a set number of pulses, and the optimized synchronization part being in the form of a triangular amplitude modulation of the sine wave to determine a reference time.

[0010] This advantageously allows the gain of the slave device to be set by analyzing the amplitude setting unit, which includes several constant amplitude pulses and thus forms a reference amplitude. Furthermore, triangular amplitude modulation allows for the definition of a unique shape through increasing and decreasing phases, which can be easily detected through signal analysis. The determination of the reference time, especially at the transition between the two phases, enables very high accuracy. Therefore, the clock of the master device can be precisely synchronized with the clock of the slave device. Finally, the components of the analog synchronization signal are formed by the same sine wave, which controls the technical means required to form this analog synchronization signal.

[0011] Preferably, the triangular amplitude modulation of the sine wave includes an increasing amplitude phase and a decreasing amplitude phase, and the reference time is determined at the transition point between the increasing amplitude phase and the decreasing amplitude phase.

[0012] Preferably, the triangular amplitude modulation of the sine wave comprises an odd number of pulses, and the reference time is determined by the pulse at the center.

[0013] Preferably, the sine wave is a pure sine wave. This allows for very precise measurement of the frequency of the sine wave.

[0014] According to a preferred aspect, the period of the sine wave is between 0.1 microseconds and 10 microseconds, preferably about 1 microsecond. This provides high accuracy.

[0015] Preferably, the number of pulses in the amplitude setting unit is greater than 16 and more preferably less than 40. This number of pulses ensures a good balance between speed and accuracy when setting the gain.

[0016] Preferably, the optimized synchronization unit has 3 pulses, and more preferably less than 7, and more preferably 5. This number of pulses ensures optimal detection within a short period.

[0017] The present invention also relates to a transmission module for transmitting data from a master device to at least one slave device in a frame according to a TDMA protocol, wherein each frame is divided into multiple time slots, and at least one time slot includes an analog synchronization signal, the analog synchronization signal including an amplitude setting part and an optimized synchronization part, the amplitude setting part being in the form of a sine wave having a constant amplitude during a set number of pulses, and the optimized synchronization part being in the form of a triangular amplitude modulation of the sine wave to determine a reference time, the transmission module including a master signal generator, an analog synchronization signal generator, and a master clock connected to the two generators, the master clock controlling the generation rate of the master signal and the analog synchronization signal.

[0018] Preferably, the analog synchronization signal generator includes a pulse generator and a processing unit for processing the pulses to form the different portions of the analog synchronization signal, the processing unit including a weighted adder circuit to perform triangular amplitude modulation of the optimized synchronization portion.

[0019] The present invention also relates to a receiving module for receiving data transmitted from a master device to at least one slave device in a frame according to a TDMA protocol, wherein each frame is divided into multiple time slots, at least one time slot includes an analog synchronization signal, the analog synchronization signal including an amplitude setting part and an optimized synchronization part, the amplitude setting part being in the form of a sine wave having a constant amplitude during a set number of pulses, and the optimized synchronization part being in the form of a triangular amplitude modulation of the sine wave to determine a reference time, the receiving module including an extraction system for extracting the reference time and a setting system for setting a slave clock according to the reference time.

[0020] Preferably, the extraction system includes a programmable gain amplifier and a voltage comparator, the voltage comparator being configured to accurately determine the amplitude of the analog timing signal and thereby derive the setting of the programmable gain amplifier.

[0021] The present invention also relates to a system comprising the aforementioned transmission module for transmitting frames and the aforementioned receiving module for receiving frames. Attached Figure Description

[0022] The invention will be better understood by reading the following description given by way of example only and by referring to the accompanying drawings given by way of non-limiting example, in which the same reference numerals are used to denote similar objects.

[0023] Figure 1 This is a schematic diagram of a master device communicating with multiple slave devices according to an embodiment of the present invention;

[0024] Figure 2 This is a diagram illustrating frames transmitted over a network.

[0025] Figure 3 yes Figure 2 A schematic diagram of the analog synchronization signal for the frame shown;

[0026] Figure 4 This is a schematic diagram showing the transmission of signals M and S between the transmission module of the master device and the receiving module of the slave device.

[0027] Figure 5 This is a schematic diagram of the transmission module;

[0028] Figure 6 yes Figure 5 A schematic diagram of the processing element of the transmission module shown;

[0029] Figure 7 It is a schematic diagram of a digital output and an amplitude setting unit and an optimized synchronization unit that process the digital output to form an analog synchronization signal;

[0030] Figure 8 This is a schematic diagram of the receiving module;

[0031] Figure 9 It is used for extraction Figure 8 A schematic diagram of the reference time extraction system of the receiving module shown;

[0032] Figure 10 It is by means of Figure 9 The diagram shows a voltage comparator in the extraction system determining the reference time.

[0033] Figure 11 yes Figure 8 The diagram shows a clock generation system for the receiving module.

[0034] It should be noted that the figures illustrate the invention in detail for the purpose of implementing the invention, and of course, the figures can be used to better define the invention where appropriate. Detailed Implementation

[0035] This invention relates to a method for communication between a master device and at least one slave device according to a Time Division Multiple Access (TDMA) protocol. In this example, reference is made to... Figure 1 This example illustrates the communication between a single master device D1 and n slave devices D2 (D2-1, D2-2, D2-n). For clarity and simplicity, slave device D2 will be used as a general reference in the following text. This example primarily describes communication from master device DA to slave device D2, but communication from slave device D2 to master device D1 also exists.

[0036] Preferably, the master device D1 and the slave device D2 are electronic devices. In this example, devices D1 and D2 are used in the aerospace field, particularly as a network of sensors and actuators in aircraft.

[0037] As is known, according to the TDMA protocol, frames TR1 and TR2 are transmitted over the network. Each frame TR1 and TR2 includes time slots for transmitting data from the master device D1 and for transmitting data from the designated slave device D2. In this example, the duration of each frame TR1 and TR2 is approximately 1 ms.

[0038] Master device D1 includes a master clock HORL1 for timing data transmission in frames TR1 and TR2. Similarly, each slave device D2 includes a slave clock HORL2 for timing data reception in frames TR1 and TR2.

[0039] like Figure 2 As shown, each frame TR1 and TR2 includes a master signal M and an analog synchronization signal S. The master signal M includes data from the master device D1 and transmitted from the master device D1 to the slave device D2, and the analog synchronization signal S is transmitted from the master device D1 to the slave device D2. Each frame TR1 and TR2 also includes time slots X1-X20 for transmitting data from each slave device D2 to the master device D1.

[0040] In this exemplary implementation, in order to achieve accurate synchronization, the distance between the master device D1 and the slave device D2 does not exceed 30m and the maximum delay is about 150ns.

[0041] According to the present invention, the analog synchronization signal S includes an amplitude setting unit S1 and an optimized synchronization unit S2. The amplitude setting unit S1 is in the form of a sine wave with a constant amplitude during a set number of pulses, and the optimized synchronization unit S2 is in the form of a triangular amplitude modulation of a sine wave, so as to determine the reference time TOP.

[0042] According to the present invention, such as Figure 3 As shown, the analog synchronization signal S includes an amplitude setting unit S1, which will be described in detail, and an optimized synchronization unit S2. Advantageously, this analog synchronization signal S allows for precise setting of the gain of the slave device D2, synchronization of the master clock HORL1 and the slave clock HORL2, and high-precision timestamps on frames TR1 and TR2.

[0043] In this example, such as Figure 3 As shown, the analog synchronization signal S includes a first protection time G1 (e.g., about 3 microseconds), an amplitude setting unit S1, a second protection time G2 (e.g., about 1 microsecond), an optimized synchronization unit S2, and a third protection time G3. In this example, the duration of the analog synchronization signal S is approximately 45 microseconds.

[0044] Still refer to Figure 3 The amplitude setting unit S1 is in the form of a sine wave, preferably a pure sine wave. A pure sine wave means that the sine wave consists only of sine waves. In this example, the duration of the amplitude setting unit S1 is approximately 35 microseconds.

[0045] The sine wave has a constant amplitude over a set number of cycles. In this exemplary embodiment, the amplitude of the sine wave is between -1V and +1V, but it can also be different. Similarly, the sine wave has 35 pulses (also referred to as cycles), each pulse being a sine wave with a period of 1 microsecond. Therefore, each pulse is identical. A number of pulses between 16 and 40 is preferred because this ensures a good balance between speed and accuracy in setting the gain of the slave device D2, which will be explained later.

[0046] The frequency of the sine wave depends on the frequency of the master clock HORL1. In this example, the frequency of the sine wave is equal to the frequency of the master clock HORL1.

[0047] Still refer to Figure 3 The optimized synchronization unit S2 is in the form of a triangular amplitude modulation of a sine wave, which is the form of the amplitude setting unit S1, in order to determine the reference time TOP. In this example, the duration of the optimized synchronization unit S2 is approximately 5 microseconds.

[0048] The optimized synchronization unit S2 has pulses (with a period of 1 microsecond) at the same frequency as the amplitude setting unit S1.

[0049] The optimized synchronization unit S2 does not have a constant amplitude, but rather a variable amplitude. The increasing phase, decreasing phase, and the reference time TOP at the transition between the increasing and decreasing phases are defined by triangular amplitude modulation. During reception, the phase transitions can be detected quickly and accurately, allowing for the determination of a very precise reference time TOP. In this way, clocks HORL1 and HORL2 can be synchronized, and the time slots of frames TR1 and TR2 can be accurately timestamped.

[0050] Preferably, the optimized synchronization unit S2 comprises an odd number of pulses, wherein the central pulse has the highest amplitude to determine the reference time TOP. In this example, the optimized synchronization unit S2 comprises five symmetrical pulses I1 to I5: pulses I1 and I5 have low amplitudes of -0.3V / +0.3V, pulses I2 and I4 have medium amplitudes of -0.7V / +0.7V, and the central pulse I3 has a high amplitude of -1V / +1V. Each pulse I1 to I5 has the same period of 1 microsecond. When the amplitude of the central pulse I3 is +1V, the reference time TOP is defined.

[0051] For each frame TR1 and TR2, the reference time TOP is determined every 1ms, and each frame TR1 and TR2 has extremely high accuracy of less than 1 microsecond (pulse period).

[0052] The reference time TOP is used to define the start of the cycle, at which each slave device D2-1 to D2-20 transmits data X1-X20 to the master device D1, respectively. With the help of this invention, this reference time TOP is known with high precision. Furthermore, this allows for the precise determination of the time period between two reference times TOP, which is approximately 1 ms, so that the frequency of the master clock HORL1 can be derived and the frequency of the slave clock HORL2 can be corrected.

[0053] The following section will explain the transmission and reception of the analog synchronization signal S.

[0054] Reference Figure 4 This diagram schematically illustrates the transmission of the master signal M and the analog synchronization signal S from the master device D1 to the slave device D2. For this purpose, the master device D1 includes a transmission module ME for transmitting signals M and S, while the slave device D2 includes a receiving module MR for receiving signals M and S.

[0055] As previously stated, the communication is bidirectional, and each slave device D2 includes a transmission module (not shown) for transmitting data X1-X20. Similarly, the master device D1 also includes a receiving module (not shown) for receiving data X1-X20.

[0056] Generally speaking, such as Figure 5 As shown, the transmission module ME includes a generator GEN_M for the main signal M and a generator GEN_S for the analog synchronization signal S. The transmission module ME has a master clock HORL1 connected to the generators GEN_M and GEN_S, which controls the generation rate of the main signal M and the analog synchronization signal S. The transmission module ME also includes a low-pass filter F_PB, which filters the signals M and S before they are transmitted to the slave device D2.

[0057] The generator GEN_M of the main signal M includes a digital signal processor 1 and an analog-to-digital converter 2 to form the main signal M. This generation method is prior art and will not be described in detail here.

[0058] Still refer to Figure 5 The generator GEN_S of the analog synchronization signal S includes a pulse generator 3 and a processing unit 4. The processing unit 4 is used to process the pulse to form different parts S1 and S2 of the analog synchronization signal S.

[0059] In detail, such as Figure 7As shown, pulse generator 3 generates two digital outputs SN0 and SN1 that are transmitted to processor 4. The frequencies of digital outputs SN0 and SN1 depend on the master clock HORL1. Digital outputs SN0 and SN1 are binary and encoded in four positions, and are converted into four-level analog voltages by processor 4. Processor 4 executes a weighted adder circuit, especially by means of, Figure 6 The operational amplifier 41 and a set of resistors 42, 43, and 44 are shown. The processing unit 4 enables the triangular amplitude modulation of the optimized synchronization unit S2 to be performed using a low-complexity digital chain.

[0060] Figure 6 Only the generation of the positive portion of the pulse is shown. To generate the negative portion of the pulse in bipolar mode, two additional digital outputs are preferably provided.

[0061] Advantageously, such as Figure 7 As shown, the order of digital outputs SN0 and SN1 enables the generation of all pulses, namely the pulses of amplitude setting unit S1 and the pulses of optimized synchronization unit S2.

[0062] like Figure 7 As shown, after applying the low-pass filter F_PB, an amplitude setting unit S1 with pulses of the same amplitude and an optimized synchronization unit S2 with pulses that increase to the reference time TOP and then decrease are obtained.

[0063] Advantageously, the reference time TOP is digitally generated directly from the master clock HORL1 and then filtered to preserve only the fundamental frequency of the signal. Therefore, the analog synchronization signal S is closely related to the master clock HORL1. Consequently, the master clock HORL1 can be easily determined by the slave device D2.

[0064] The transmission module ME has low structural complexity, which reduces costs and makes it easy to adopt.

[0065] like Figure 8 As shown, the receiving module MR includes an extraction system 5 for extracting the reference time TOP and a setting system 6 for setting the slave clock HORL2 according to the reference time TOP.

[0066] like Figure 9 As shown, the extraction system 5 includes a programmable gain amplifier 51, which is configured to set its gain parameter according to the amplitude of the amplitude setting unit S1 of the analog synchronization signal S. In other words, the function of the programmable gain amplifier 51 is to normalize the amplitude of the amplitude setting unit S1 to a set reference value.

[0067] Still refer to Figure 9The extraction system 5 also includes voltage comparators 52, 53, and 54, which are configured to convert the amplitude of the analog synchronization signal S into digital signals Q1, Q2, and Q3. Of course, the number of comparators can vary. Voltage comparators 52, 53, and 54 are configured to compare the amplitude of the analog synchronization signal S, particularly the amplitude setting unit S1, with set voltages VTH1+, VTH2+, and VTH3+. Figure 10 As shown, the set voltages VTH1+, VTH2+, and VTH3+ are gradually increased (the trigger threshold is set step-by-step from 0% to a maximum value of 100%). This advantageously obtains a digital signal encoded with 2 bits. Therefore, the receiving module MR can accurately determine the amplitude of the analog synchronization signal S to set the programmable gain amplifier 51. Advantageously, the large number of constant amplitude pulses in the amplitude setting unit S1 allows for rapid and accurate gain setting.

[0068] Voltage comparators 52, 53, and 54 are also configured to compare the amplitude of the optimized synchronization unit S2 with the set voltage V. TH1+ V TH2+ V TH3+ The two phases are compared to detect the increasing and decreasing amplitude phases, thereby deriving the reference time TOP located at the transition between the two phases.

[0069] Advantageously, such as Figure 10 As shown, following the comparison step, the optimized synchronization unit S2 is converted into multiple digital signals Q1, Q2, and Q3, which highlights the reference time TOP. Advantageously, even if one of the digital signals Q1, Q2, and Q3 is lost, the reference time TOP can still be determined.

[0070] Preferably, digital signals Q1, Q2, and Q3 are digitally sampled at high frequencies, such as 4 to 16 times the fundamental frequency, to detect small width variations caused by the sinusoidal shape. This allows for very accurate detection of the increasing amplitude phase, the decreasing amplitude phase, and the reference time TOP located at the transition point.

[0071] Reference Figure 9 The extraction system 5 also includes a digital processing unit 55, which is configured to extract the reference time TOP from the digital signals Q1, Q2, and Q3. The continuous reference time TOP, transmitted every 1ms, is transmitted to... Figure 11 The setting system 6 is shown from clock HORL2.

[0072] The setup system 6 itself is known to those skilled in the art. In this example, the setup system 6 includes a servo control and frequency measurement controller 61 that uses a sequence of reference times TOP as a time reference, and a voltage-controlled oscillator (VCO) 63 connected to the servo control and frequency measurement controller 61 via an analog-to-digital converter 62. The VCO 63 is connected to a buffer 64 to form a slave clock HORL2.

[0073] In this example, the system 6 also includes a digital counter 65, which counts the number of pulses of the slave clock HORL2 within a 1ms time slot to determine its frequency. The servo control and frequency measurement controller 61 enables servo control of the slave clock HORL2 relative to the master clock HORL1. Therefore, the master clock HORL1 is determined from the sequence of reference time TOP, and the time is marked every 1ms to correct for possible drift in the frequency of the slave clock HORL2.

[0074] Setting system 6 to operate independently of extraction system 5 advantageously allows for the reduction of overall power consumption by placing unused digital portions outside the time slice allocated to slave device D2 into standby mode. Furthermore, this reduces the variable and random delays associated with the digitization of analog signals.

[0075] Therefore, after receiving the analog synchronization signal S, the receiving module MR advantageously enables the amplitude (gain) to be set and the slave clock HORL2 to be synchronized with the master clock HORL1.

[0076] Now refer to Figure 4 The master device D1 transmits signals M and S to the slave device D2 through its transmission module ME. The slave device D2 sets the amplitude (gain) using its receiving module MR and synchronizes its slave clock HORL2 with the master clock HORL1. Since the slave clock HORL2 is servo-controlled to the master clock HORL1, this improves the data demodulation performance of frames TR1 and TR2. Furthermore, the reference time TOP provides a microsecond time reference, enabling the slave device D2 to perform precise time stamping of data packets X1-X20 relative to this reference time TOP. Therefore, the master device D1 can reconstruct the precise timestamp of the data packets based on the state of its master clock HORL1 at the previous reference time TOP and the relative timestamp provided by the slave device D2.

[0077] Advantageously, high frequency accuracy (approximately + / - 100 ppm) can be achieved even at high temperatures through conventional drift compensation. This is particularly advantageous compared to conventional quartz or surface wave elements.

[0078] Finally, since the synchronization of the present invention is efficient, the conventional synchronization preamble of signals M and X1-X20 can be removed from each digital frame TR1, TR2, thereby increasing the useful bandwidth.

Claims

1. A method for communication between a master device (D1) and at least one slave device (D2) according to a Time Division Multiple Access (TDMA) protocol, characterized in that, During the communication, multiple frames (TR1, TR2) are transmitted between the master device (D1) and the slave device (D2). Each frame (TR1, TR2) is divided into multiple time slots, and at least one time slot includes an analog synchronization signal (S) transmitted from the master device (D1) to the slave device (D2). The analog synchronization signal (S) includes: • Amplitude setting unit (S1), which takes the form of a sine wave with a constant amplitude during a set number of pulses, and • An optimized synchronization unit (S2) is provided, which takes the form of a triangular amplitude modulation of the sine wave in order to determine the reference time (TOP).

2. The communication method as described in claim 1, characterized in that, The triangular amplitude modulation of the sine wave includes an increasing amplitude phase and a decreasing amplitude phase, and the reference time (TOP) is determined at the transition between the increasing amplitude phase and the decreasing amplitude phase.

3. The communication method as described in claim 1, characterized in that, The triangular amplitude modulation of the sine wave comprises an odd number of pulses, with the reference time (TOP) determined at the center of the pulse.

4. The communication method as described in claim 1, characterized in that, The sine wave is a pure sine wave.

5. The communication method as described in claim 1, characterized in that, The period of the sine wave is between 0.1 microseconds and 10 microseconds.

6. The communication method as described in claim 1, characterized in that, The number of pulses in the amplitude setting unit (S1) is greater than 16.

7. A transmission module (ME) for transmitting data from a master device (D1) to at least one slave device (D2) in a frame according to the TDMA protocol, characterized in that, Each frame (TR1, TR2) is divided into multiple time slots, at least one time slot including an analog synchronization signal (S). The analog synchronization signal (S) includes an amplitude setting unit (S1) and an optimized synchronization unit (S2). The amplitude setting unit (S1) is in the form of a sine wave with a constant amplitude during a set number of pulses. The optimized synchronization unit is in the form of a triangular amplitude modulation of the sine wave to determine a reference time (TOP). The transmission module (ME) includes a generator (GEN_M) for the main signal (M), a generator (GEN_S) for the analog synchronization signal (S), and a master clock (HORL1) connected to the two generators (GEN_M, GEN_S). The master clock (HORL1) controls the generation rate of the main signal (M) and the analog synchronization signal (S).

8. The transmission module (ME) as described in claim 7, characterized in that, The generator (GEN_S) of the analog synchronization signal (S) includes a pulse generator (3) and a processing unit (4) for processing the pulse to form an amplitude setting unit (S1) and an optimized synchronization unit (S2) of the analog synchronization signal (S). The processing unit (4) includes a weighted adder circuit to perform triangular amplitude modulation of the optimized synchronization unit (S2).

9. A receiving module (MR) for receiving data transmitted from a master device (D1) to at least one slave device (D2) in a frame according to a TDMA protocol, characterized in that, Each frame (TR1, TR2) is divided into multiple time slots, at least one time slot including an analog synchronization signal (S), the analog synchronization signal (S) including an amplitude setting part (S1) and an optimized synchronization part (S2), the amplitude setting part being in the form of a sine wave with a constant amplitude during a set number of pulses, the optimized synchronization part being in the form of a triangular amplitude modulation of the sine wave in order to determine a reference time (TOP), the receiving module (MR) including an extraction system (5) for extracting the reference time (TOP) and a setting system (6) for setting a slave clock (HORL2) from the reference time (TOP).

10. The receiving module (MR) as claimed in claim 9, characterized in that, The extraction system (5) includes a programmable gain amplifier (51) and voltage comparators (52, 53, 54), which are configured to accurately determine the amplitude of the analog synchronization signal (S) and thereby derive the setting of the programmable gain amplifier (51).

11. A system characterized by, It includes the transmission module (ME) as described in claim 7 or 8 and the receiving module (MR) as described in claim 9 or 10.

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