Apparatuses that perform communications and computing systems that include the apparatuses

Abstract

The present invention relates to an apparatus that can limit the performance of each function capable of controlling a path margin operation in an upstream port. The apparatus includes: an upstream port for receiving or transmitting data from or to one or more external apparatuses located on an upstream path through a link including a plurality of paths; a path margin controller coupled to the upstream port and for transmitting a margin command for requesting a path margin operation to the one or more external apparatuses via the upstream port to acquire margin status information indicating a margin of each of the plurality of paths, and the path margin controller controls the upstream port to receive the margin status information from the external apparatuses; and a port setting controller coupled in communication with the upstream port to receive the margin status information and for determining a setting of the upstream port based on the margin status information.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority and benefit to Korean patent application No. 10-2021-0042642, filed on April 1, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The disclosed technology generally relates to an electronic device, and more particularly, to a device for performing communication and a computing system including the device. Background Technology

[0004] Computer buses such as Peripheral Component Interconnect (PCI) are used to connect peripheral devices to a computer system. High-speed PCI (PCIe) is a high-speed computer bus standard that includes a physical communication layer as a high-speed serial interface while maintaining software compatibility with the PCI standard.

[0005] A data storage device is used to store or provide data in response to a request from a host device such as a computer or smartphone. Such a data storage device may include one or more memory devices for storing data and a memory controller for controlling the one or more memory devices. Memory devices can be classified as volatile memory devices and non-volatile memory devices.

[0006] Volatile memory devices retain their data only while the device is powered on and lose their data when power is lost. Examples of volatile memory devices may include static random access memory (SRAM) or dynamic random access memory (DRAM).

[0007] Non-volatile memory devices retain stored data even when there is no power supply, and therefore do not lose their data when power is lost. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), and flash memory. Summary of the Invention

[0008] The disclosed embodiments relate to a high-speed peripheral component interconnect (PCIe) device capable of controlling the path margin operation in an upstream port and a computing system including the PCIe device.

[0009] According to one aspect of the disclosed technology, an apparatus for performing communication between components in a computing system is provided, the apparatus comprising: an upstream port configured to receive data from or transmit data to one or more external devices located on an upstream path via a link, the link including a plurality of paths configured to include differential signal pairs for receiving and transmitting data; a path margin controller coupled to the upstream port and configured to send a margin command via the upstream port to the one or more external devices for requesting path margin operation to obtain margin status information indicating the margin of each of the plurality of paths, and the path margin controller controlling the upstream port to receive the margin status information from the external devices; and a port setting controller coupled to communicate with the upstream port to receive the margin status information and operable to determine the setting of the upstream port based on the margin status information.

[0010] Based on another aspect of the disclosed technology, a computing system is provided, comprising: a first device configured to include a downstream port and to receive and transmit data via the downstream port according to a High Speed ​​Peripheral Component Interconnect (PCIe) standard; and a second device configured to include an upstream port connected to the downstream port of the first device via a link comprising multiple paths, wherein the second device is configured to: receive and transmit data through the first device via the upstream port according to a High Speed ​​Peripheral Component Interconnect (PCIe) standard; send a margin command to the first device via the upstream port; receive margin status information as a response to the margin command from the first device, the margin status information indicating the margin of each of the multiple paths; and determine the setting of the upstream port based on the margin status information.

[0011] Based on another aspect of the disclosed technology, a computing system is provided, comprising: a downstream port configured to interconnect components of the computing system in a downstream path; and an upstream port configured to interconnect components of the computing system in an upstream path and to connect to the downstream port via a link including a plurality of paths, wherein each of the downstream port and the upstream port is configured to: generate a margin command for requesting margin operation of a path to obtain margin status information indicating the margin of each of the plurality of paths, and send the margin command to or receive a margin command from the downstream port. Attached Figure Description

[0012] Figure 1 This is a diagram illustrating an example of a computing system based on an embodiment of the disclosed technology.

[0013] Figure 2 This is a diagram illustrating a high-speed peripheral component interconnect (PCIe) device based on an embodiment of the disclosed technology.

[0014] Figure 3 This is a diagram illustrating a PCIe interface based on an embodiment of the disclosed technology.

[0015] Figure 4 This is a diagram illustrating a transmitter, receiver, and lane based on an embodiment of the disclosed technology.

[0016] Figure 5 This is a diagram illustrating a port based on an embodiment of the disclosed technology.

[0017] Figure 6 This is a diagram illustrating an interconnect structure including one or more retimers based on an embodiment of the disclosed technology.

[0018] Figure 7 This is a diagram illustrating a computing system including a PCIe device based on an embodiment of the disclosed technology.

[0019] Figure 8 This is a diagram illustrating an operation for determining the settings of a transmitter controlled by an upstream port, based on an embodiment of the disclosed technology.

[0020] Figure 9 This is a diagram illustrating operations for determining the settings of a receiver controlled by an upstream port, based on an embodiment of the disclosed technology.

[0021] Figure 10 This is a diagram illustrating an operation for determining the settings of a transmitter controlled by a downstream port, based on an embodiment of the disclosed technology.

[0022] Figure 11 This is a flowchart illustrating a method for determining the settings of an upstream port based on an embodiment of the disclosed technology.

[0023] Figure 12 This is a flowchart illustrating a method for determining receiver settings based on an embodiment of the disclosed technology.

[0024] Figure 13 This is a flowchart illustrating a method for determining the settings of a downstream port based on an embodiment of the disclosed technology. Detailed Implementation

[0025] The technology disclosed in this patent document can be implemented in several embodiments to provide data storage devices and data storage methods. The specific structural or functional descriptions disclosed herein are merely illustrative for describing embodiments based on the disclosed technology concept. Embodiments based on the disclosed technology concept can be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0026] Figure 1This is a diagram illustrating an example of a computing system based on an embodiment of the disclosed technology.

[0027] Reference Figure 1 The computing system 100 may include a central processing unit (CPU) 110, a root union 120, a memory 130, a switch 140, high-speed peripheral component interconnect (PCIe) endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and a PCIe bridge 170.

[0028] The computing system 100 may be an electronic device that supports communication via a PCIe interface. The computing system 100 may be a PC, a laptop computer, or a mobile computing device, and includes expansion cards, expansion boards, adapter cards, plug-in cards, or accessory cards. Furthermore, the computing system 100 may include a printed circuit board (PCB) that can be inserted into electrical connectors or expansion slots on the motherboard of the computing system 100 to provide additional functionality to the computing system 100 via an expansion bus. Moreover, the computing system 100 may include storage devices such as solid-state drives (SSDs), and may include graphics cards, network cards, USB cards, etc.

[0029] The CPU 110 can be electrically connected to each component of the computing system 100 and control each operation of the computing system 100. Specifically, the CPU 110 can control the hardware or software components connected to the CPU 110 by driving an operating system or application, and perform various data processing and calculations. Moreover, the CPU 110 can run software or applications for controlling the operation of the computing system 100.

[0030] Root union 120 can be a root hub, controller hub, or root controller in a PCIe interconnect architecture. For example, root union 120 may include a chipset, memory controller hub (MCH), northbridge, interconnect controller hub (ICH), southbridge, and root controller / hub. Furthermore, root union 120 can connect CPU 110 and memory 130 to an input / output (I / O) hierarchy. Root union 120 may support peer-to-peer (P2P) routing. Root union 120 may include at least one master bridge and at least one root port. Root union 120 may support one or more PCIe ports. In some embodiments, ports may indicate interfaces between PCIe components and links and include differential transmitters and receivers. In some embodiments, upstream ports are ports pointing towards the root union, while downstream ports are ports pointing away from the root union.

[0031] The memory 130 may store data, commands, or program code required for the operation of the computing system 100. In some embodiments, the memory 130 may store program code for running one or more operating systems (OS) and one or more virtual machines (VMs), as well as program code for running a virtualization middleware (VI) for managing the VMs. Moreover, the memory 130 may be implemented as a volatile memory device such as DRAM or SRAM.

[0032] Switch 140 can route packets or messages upstream or downstream. Specifically, switch 140 can route packets or messages upstream from a PCIe endpoint (e.g., 150_1) to a layer toward the root union 120. Furthermore, switch 140 can route packets or messages downstream from the root union 120 to a layer toward a PCIe endpoint (e.g., 150_2).

[0033] Switch 140 may include logical components of multiple virtual PCI to PCI bridge devices. Devices that can be connected to switch 140 may include internal or external devices or components connected to electronic systems such as: network interface controllers (NICs), expansion cards, audio processors, network processors, hard drives, storage devices, CD / DVD ROMs, monitors, printers, mice, keyboards, routers, mobile storage devices, FireWire devices, Universal Serial Bus (USB), scanners, and other input / output devices. Although not shown in detail, the device may include PCIe to PCI / PCI-X bridges that support legacy or other versions of PCI devices.

[0034] In some implementations, root union 120 may be connected to an endpoint. An endpoint may represent a functional type that can act as a requester or completer for a PCIe transaction. Here, a requester may include a device that initiates a transaction in the PCIe architecture, while a completer may include a device addressed or locked by the requester. Endpoints may be classified as traditional endpoints and PCIe endpoints. In some implementations, an endpoint is a device other than the root union and the switch that acts as a requester or completer for a PCIe transaction.

[0035] PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can act as either requesting or completing ends of a PCIe transaction. Transaction Layer Packets (TLPs) communicated through PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 provide configuration space headers. Furthermore, PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 provide configuration requests as completing ends.

[0036] PCIe endpoints 150_1 to 150_3 and traditional endpoints 160_1 and 160_2 can be classified based on the size of memory transactions. For example, when an endpoint supports memory transactions exceeding 4GB, it can be classified as PCIe endpoints 150_1 to 150_3. When an endpoint does not support memory transactions exceeding 4GB, it can be traditional endpoints 160_1 and 160_2. PCIe endpoints 150_1 to 150_3 do not generate arbitrary I / O requests, while traditional endpoints 160_1 and 160_2 can provide or generate I / O requests. Additionally, PCIe endpoint 150_3 can communicate TPL with root union 120. Furthermore, PCI / PCI-X can communicate TLP with root union 120 via PCIe bridge 170. PCIe endpoints 150_1 and 150_2 or traditional endpoints 160_1 and 160_2 can communicate TLP with switch 140.

[0037] PCIe endpoints 150_1 to 150_3 can be functional endpoints with a type 00h configuration space header. PCIe endpoints 150_1 to 150_3 can support configuration requests as completion endpoints. PCIe-compatible software drivers and applications can be created such that arbitrary locking semantics are not used when PCIe endpoints 150_1 to 150_3 are accessed. PCIe endpoints 150_1 to 150_3 operating as memory transaction requesting endpoints can generate addresses larger than 4GB. When interrupt resources are requested, PCIe endpoints 150_1 to 150_3 may need to support Message Signaled Interrupt (MSI), MSI-X, or both. When implementing MSI, PCIe endpoints 150_1 to 150_3 can support a 64-bit message address version of the MSI functional architecture. The minimum memory address range requested by the base address register can be 128 bytes. PCIe endpoints 150_1 to 150_3 can exist in one of the hierarchical domains starting from root union 120.

[0038] Traditional endpoints 160_1 and 160_2 can be functional endpoints including a type 00h configuration space header. Traditional endpoints 160_1 and 160_2 can support configuration requests as completion endpoints. Traditional endpoints 160_1 and 160_2 can support I / O requests as completion endpoints. Traditional endpoints 160_1 and 160_2 can receive I / O requests for one or both of positions 80h and 84h, regardless of the I / O decoding configuration of the respective endpoint. Traditional endpoints 160_1 and 160_2 can generate I / O requests. Traditional endpoints 160_1 and 160_2 can include scalable configuration space capabilities. Traditional endpoints 160_1 and 160_2, operating as requesting endpoints for memory transactions, do not necessarily need to generate addresses with 4GB or more of space. When interrupt resources are requested, traditional endpoints 160_1 and 160_2 need to support MSI, MSI-X, or both. When implementing MSI, legacy endpoints 160_1 and 160_2 can support either 32-bit or 64-bit message address versions of the MSI functional architecture. Legacy endpoints 160_1 and 160_2 can support a 32-bit address specification for the base address register of the requested memory resource. Legacy endpoints 160_1 and 160_2 can reside in one of the hierarchical domains starting from root union 120.

[0039] Figure 2 This is a diagram illustrating a PCIe device based on an embodiment of the disclosed technology.

[0040] Reference Figure 2 A PCIe device may include a PCIe interface. In some embodiments, the PCIe device may be an electronic device that supports sending / receiving via the PCIe interface. For example, the first PCIe device 200-1 or the second PCIe device 200-2 may be... Figure 1 Any one of the following: root union 120, switch 140, PCIe endpoints 150_1 to 150_3, legacy endpoints 160_1 and 160_2, and PCIe bridge 170.

[0041] Furthermore, the first PCIe device 200-1 or the second PCIe device 200-2 can perform communication using the first PCIe interface 210-1 or the second PCIe interface 210-2. Specifically, the first PCIe device 200-1 can use the first PCIe interface 210-1 to convert data to be sent from the second PCIe device 200-2 into a protocol suitable for communication. Additionally, the first PCIe device 200-1 and the second PCIe device 200-2 can form a link. The first PCIe device 200-1 and the second PCIe device 200-2 can communicate with each other through the formed link. For example, the first PCIe device 200-1 or the second PCIe device 200-2 can send / receive data packets through the link.

[0042] Figure 3 This is a diagram illustrating a PCIe interface based on an embodiment of the disclosed technology.

[0043] Reference Figure 3 The diagram shows a first PCIe interface 210-1 and a second PCIe interface 210-2. The first PCIe interface 210-1 and the second PCIe interface 210-2 can be formed with the same structure; therefore, the first PCIe interface 210-1 will be described primarily.

[0044] The PCIe layer included in the first PCIe interface 210-1 may include three independent logical layers. For example, the first PCIe interface 210-1 may include a transaction layer, a data link layer, and a physical layer. Each layer may include two parts. One part can handle external (or transmitted) information, while the other part can handle internal (or received) information. Moreover, the first PCIe interface 210-1 can use data packets to communicate information between other PCIe interfaces.

[0045] The upper layer in the PCIe interface architecture can be a transaction layer. The transaction layer can aggregate and decompose Transaction Layer Packets (TLPs). Furthermore, the transaction layer can implement split transactions, which allows another flow of traffic to be transmitted over the link while the target system aggregates the data required for a response. In some implementations, the four transaction address spaces can include a configuration address space, a memory address space, an input / output address space, and a message address space. A memory space transaction can include one or more of a write request to transfer data to a memory-mapped location or a read request to transfer data from a memory-mapped location. In one example, a memory space transaction can use two different address formats, such as a short address format like a 32-bit address or a long address format like a 64-bit address. A configuration space transaction can be used to access the configuration space of a PCIe device. A configuration space transaction can include read requests and write requests. Message space transactions (or messages) can be defined to support in-band communication between PCIe devices.

[0046] The transaction layer can store link configuration information or other data. Furthermore, the transaction layer can generate TLPs or convert received TLPs into payloads or status information.

[0047] In a PCIe interface architecture, the middle layer can be the data link layer, which performs the functions of an intermediate stage between the transaction layer and the physical layer. The main functions of the data link layer can include link management and data integrity, including error detection and correction. Specifically, the sending side of the data link layer can receive the Data Protection Token (TLP) gathered at the transaction layer, provide the data protection code, or calculate the TLP sequence number. Furthermore, the sending side of the data link layer can send the data protection code and TLP sequence number to the physical layer, thereby transmitting the data protection code and TLP sequence number over the link. The receiving side of the data link layer can check the data integrity of the TLP received from the physical layer and send the TLP to the transaction layer for further processing.

[0048] The physical layer may include circuitry for interface operation. This circuitry may include drivers, input buffers, series-to-parallel converters, parallel-to-series converters, phase-locked loops (PLLs), and impedance matching circuitry.

[0049] Furthermore, the physical layer may include a logical sub-block and an electrical sub-block that physically transmit data packets to external PCIe devices. The logical sub-block can perform the functions required for the digital functions of the physical layer. In this regard, the logical sub-block may include a transmitting section and a receiving section; the transmitting section prepares and transmits information to be transmitted by the logical sub-block, and the receiving section identifies and prepares information received before transmitting it to the data link layer. The physical layer may include a transmitter and a receiver. When the transmitter is serialized by the logical sub-block, it can receive symbols destined for external devices. Additionally, the receiver can receive serialized symbols from external devices and convert the received symbols into a bit stream. The bit stream can be deserialized to supply the logical sub-block. For example, the physical layer can convert TLPs received from the data link layer into a serialized format and data packets received from external devices into a deserialized format. Moreover, the physical layer may include logical functions associated with interface initialization and maintenance.

[0050] although Figure 3 The structure of the first PCIe interface 210-1 and the second PCIe interface 210-2 is shown as an example, but the structure of the first PCIe interface 210-1 and the second PCIe interface 210-2 may include any form such as a fast path interconnect structure, a next-generation high-performance computing interconnect structure or other hierarchical structure.

[0051] Figure 4 This is a diagram illustrating a transmitter, receiver, and path based on an embodiment of the disclosed technology.

[0052] Reference Figure 4 The diagram illustrates a first transmitter TX1, a second transmitter TX2, a first receiver RX1, and a second receiver RX2. A path may include a path comprising differentially driven signal pairs. In some embodiments, a path may include two differential signal pairs, one pair for receiving data and the other for transmitting data. For example, a path may include a transmit path pair configured to transmit and a receive path pair configured to receive. A PCIe device may include transmit logic for transmitting data to another PCIe device and receive logic for receiving data from another PCIe device. For example, a path may include two transmit paths connected to the first transmitter TX1 and two receive paths connected to the first receiver RX1.

[0053] The transmission path can include any path used for transmitting data, such as a transmission line, copper wire, optical fiber, wireless communication channel, infrared communication link, or other communication path. Additionally, while the receiving path is used for receiving data, it can include paths implemented in the same way as the transmission path.

[0054] The connection between two PCIe devices, such as the first PCIe device 200-1 and the second PCIe device 200-2, can be a link. A link can support one or more paths. For example, a link can include multiple paths. Additionally, each path can include a set of differential signal pairs (one pair for transmitting and one pair for receiving). Differential signals can include signal pairs with the same frequency and amplitude but opposite phases. For example, when the first signal is at the rising edge of the first signal switching from 0 to V+, the second signal can be at the falling edge of the second signal switching from 0 to V-. PCIe devices can utilize differential signals to achieve signal integrity, such as more desirable electrical characteristics like cross-coupling, voltage overshoot / undershoot, and ringing. PCIe devices can adjust the transmission frequency more quickly. Moreover, a link can include multiple paths to adjust bandwidth. For example, a link can include 1 path, 2 paths, 4 paths, 8 paths, 12 paths, 32 paths, 64 paths, etc.

[0055] Figure 5 This is a diagram illustrating a port based on an embodiment of the disclosed technology.

[0056] Reference Figure 5 The diagram shows the downstream port 215-1 and the upstream port 215-2 included in the first PCIe device 200-1 and the second PCIe device 200-2, respectively.

[0057] In some implementations, the first PCIe device 200-1 can be at a higher layer than the second PCIe device 200-2, and data movement and transmission to the upper layer can be referred to as upstream. Conversely, data movement and transmission to the lower layer can be referred to as downstream. For example, refer to... Figure 1 Switch 140 can support upstream and downstream routing. Specifically, upstream can be a layer that routes packets or messages from a PCIe endpoint (e.g., 150_1) upstream toward a layer toward the root union 120, and downstream can be a layer that routes packets or messages from the root union 120 downstream toward a layer toward a PCIe endpoint (e.g., 150_2).

[0058] In some implementations, the first PCIe device 200-1, including the downstream port 215-1, may be referred to as an "upstream component". The upstream component may include... Figure 1 The root union 120 or switch 140 shown. Additionally, the second PCIe device 200-2, including upstream port 215-2, can be referred to as a "downstream component". A downstream component can represent... Figure 1 Any one of the switch 140, PCIe endpoints 150_1 to 150_3, traditional endpoints 160_1 and 160_2, and PCIe bridge 170 shown.

[0059] Each of the downstream port 215-1 and the upstream port 215-2 may include a transmitter Tx, a receiver Rx, and a phase-locked loop (PLL) circuit. The PLL circuit can generate a clock signal to be provided to the transmitter Tx or receiver Rx using a clock signal provided from a clock signal generator CLK GEN. The PLL circuit can generate a clock signal with a changed frequency by multiplying a signal received from the clock signal generator CLK GEN. For example, the PLL circuit can multiply a reference clock signal REFCLK with a frequency of 100MHz with a clock signal with a frequency of 2.5GHz. The transmitter Tx can convert a parallel data signal into a serial data signal using the output signal of the PLL circuit and send the serial data signal to an external device, such as an external PCIe device. The receiver Rx can receive the serial data signal sent from the external device and generate a clock signal for recovering the received serial data signal and a clock signal for converting the recovered serial data signal back into a parallel data signal using the output signal of the PLL circuit. The clock signal generator CLK GEN can generate a reference clock signal REFCLK for the operation of the PCIe interface. The PCIe interface can be used for communication with external PCIe devices.

[0060] Figure 6 This is a diagram illustrating an interconnect structure including one or more retimers based on an embodiment of the disclosed technology.

[0061] Reference Figure 6 The interconnect structure may include downstream ports, upstream ports, and one or more retimers. A downstream port can be a port included in an upstream component, and an upstream port can be a port included in a downstream component. Downstream ports allow components of the computing system to interconnect in a downstream path. For example, a downstream port can represent a port located in an upstream component to provide an interface for transmission from the upstream component to the downstream component. Upstream ports allow components of the computing system to interconnect in an upstream path. For example, an upstream port can represent a port located in a downstream component to provide an interface for transmission from the downstream component to the upstream component. Because the interconnect operates at high speed, one or more retimers can be connected between the downstream ports and the upstream ports.

[0062] A retimer can function as a signal repeater operating at the physical layer to finely tune signals from downstream and upstream ports. Its primary function is signal retiming. A retimer can recover received signals and retransmit the recovered signals by using a local clock and a new transmit equalization circuit.

[0063] In some implementations, the retimer may include two pseudo-ports. Each pseudo-port can be dynamically determined in the downstream / upstream direction. The pseudo-port positioned downstream can be a downstream pseudo-port. The pseudo-port positioned upstream can be an upstream pseudo-port.

[0064] The downstream port may include a transmitter Tx(A) and a receiver Rx(A). The retimer X may include transmitters Tx(B) and Tx(C) and receivers Rx(B) and Rx(C). The retimer Y may include transmitters Tx(D) and Tx(E) and receivers Rx(D) and Rx(E). The upstream port may include a transmitter Tx(F) and a receiver Rx(F).

[0065] In some implementations, the path through which data or signals move from a downstream port to an upstream port can be defined as a downstream path. On the downstream path, receiver Rx(B) can be connected to transmitter Tx(A) and forward data and signals to transmitter Tx(C). Receiver Rx(D) can be connected to transmitter Tx(C) and forward data and signals to transmitter Tx(E). Receiver Rx(F) can be connected to transmitter Tx(E).

[0066] In some implementations, the path through which data or signals move from an upstream port to a downstream port can be defined as the upstream path. On the upstream path, receiver Rx(E) can be connected to transmitter Tx(F) and forward data and signals to transmitter Tx(D). Receiver Rx(C) can be connected to transmitter Tx(D) and forward data and signals to transmitter Tx(B). Receiver Rx(A) can be connected to transmitter Tx(B).

[0067] Downstream ports, upstream ports, and retimers can be connected via a link. In some implementations, the downstream port can obtain margin status information for multiple paths included in the link through path margin operations. For example, the downstream port can send margin commands to retimers X, Y, and the upstream port, and retimers X, Y, and the upstream port can provide margin status information to the downstream port in response to the margin commands. Margin commands and response signals to margin commands can be sent by controlling the skip order set. For example, the downstream port can provide margin commands by controlling the skip order set. Furthermore, retimers X, Y, and the upstream port can provide response signals to margin commands by controlling the skip order set.

[0068] Path margin operations can be performed on all ports. The computing system can obtain margin status information in the corresponding receiver by performing path margin operations on the receiver included in the port that received the margin command. In some implementations, the margin status information may include voltage and time associated with the receiver location. In one example, the margin status information may include margin information regarding the voltage and timing at the current receiver location. Receiver path margin operations can be performed when a margin command is received, when the link is operating at a data rate of 16.0 GT / s or higher, and when the link is in the L0 state.

[0069] Path margin operation may include issuing a command instructing the receiver to move a sampling point to the left or right side of a voltage timing diagram via several steps related to timing, or to move a sampling point to the top or bottom of a voltage timing diagram via several steps related to voltage. The receiver may report margin status information in response to the margin command. Margin commands may include instructions indicating various operations associated with path margin operation.

[0070] The computing system can obtain margin status information about the receiver using the margin path control register and margin path status register in each port. Downstream ports can control the receiver's path margin operation by executing records on appropriate bits of the margin path control register. Furthermore, downstream ports can update the receiver's margin status information through the margin path status register.

[0071] Traditional path margin operations can be controlled solely by the downstream port. Traditional upstream ports cannot control path margin operations and can only provide margin status information obtained through these operations. Furthermore, physical layer characteristics can vary depending on the platform and the presence or absence of retimers. The settings of the physical layer transmitter and receiver can also be modified.

[0072] The disclosed techniques can be implemented in some embodiments to tune the transmitter and receiver settings by controlling the path margin operation in the upstream port.

[0073] Figure 7 This is a diagram illustrating a computing system including a PCIe device based on an embodiment of the disclosed technology.

[0074] The computing system 700 based on the embodiments of the disclosed technology may include an external device 710 and a PCIe device 720.

[0075] External device 710 can use the PCIe interface of PCIe device 720 connected via a link. The link may include multiple pathways. Although Figure 7 Only one external device 710 is shown, but more than one external device 710 may be connected to the PCIe device 720.

[0076] In some implementations, external device 710 may be a device located on an upstream path. For example, external device 710 may be an upstream component or a retimer. External device 710 may be a device belonging to a higher layer than PCIe device 720. Therefore, the direction of a signal moving from external device 710 to PCIe device 720 can be defined as downstream, and the direction of a signal moving from PCIe device 720 to external device 710 can be defined as upstream.

[0077] In some embodiments, external device 710 may include a downstream port. The downstream port may include a transmitter Tx1 and a receiver Rx1. The transmitter Tx1 included in external device 710 may be connected to the receiver Rx2 included in PCIe device 720, and the receiver Rx1 included in external device 710 may be connected to the transmitter Tx2 included in PCIe device 720.

[0078] In some implementations, the PCIe device 720 may be a downstream component located in the downstream path.

[0079] PCIe device 720 may include an upstream port 721, a path margin controller 722, a port setting controller 723, a margin path control register 724, and a margin path status register 725.

[0080] Upstream port 721 can be connected to external device 710 via a link. Specifically, upstream port 721 can communicate data or signals with downstream ports included in external device 710. Upstream port 721 may include transmitter Tx2 and receiver Rx2.

[0081] The path margin controller 722 can control path margin operation. The path margin controller 722 can control the upstream port 721 to send a margin command to the external device 710 to request path margin operation. The upstream port 721 can generate the margin command and send it via a transmitter.

[0082] Path margin operation can be an operation that acquires margin status information for each of multiple paths included in a link. Margin status information may include at least one of eye margin information and error information. Eye margin information may include an indication of the quality of signals transmitted / received through the multiple paths. Error information may include information associated with errors occurring during path margin operation. For example, margin status information may include timing steps, maximum timing offset, voltage steps, maximum voltage offset, voltage sampling rate, timing sampling rate, maximum number of paths (e.g., the maximum number of paths for which path margin operation can be performed simultaneously), individual error samplers (e.g., whether any errors due to path margin operation have occurred), number of errors (e.g., the number of errors that have occurred during path margin operation), number of samples (e.g., the number of margin bits), etc.

[0083] In some implementations, margin commands and margin status information can be sent by controlling the skipping of ordered sets.

[0084] Skip-ordered sets can be used in clock tolerance compensation. Specifically, skip-ordered sets can be used to compensate for frequency differences in bit rates at the two ends of a link. The resilient buffer performing the compensation can be included in the logical sublayer of the physical layer on the receiving side. The transmission interval of the skip-ordered set can be set based on the pre-designed absolute value of the transmit and receive clock frequency difference.

[0085] A flexible buffer can temporarily store data to be sent or data to be received. Specifically, a flexible buffer can be included in each of the sending and receiving sides. A flexible buffer can temporarily store skipped ordered sets and data blocks.

[0086] In some implementations, the path margin controller 722 can increase / decrease the transmission interval of the skipped ordered set based on the transmission history of the skipped ordered set. The transmission history may include the transmission interval of the skipped ordered set, changes in the transmission interval, or the recovery state entry frequency corresponding to the transmission interval. For example, the path margin controller 722 can calculate the recovery state entry frequency corresponding to the transmission interval and increase / decrease the transmission interval of the skipped ordered set based on the recovery state entry frequency. In another example, when no request for recovery state entry is received within a predetermined time, the path margin controller 722 can fix the transmission interval of the skipped ordered set.

[0087] Furthermore, the path margin controller 722 can increase / decrease the transmission interval of skipped ordered sets based on the state of the elastic buffer included in the external device 710. For example, if the transmitting and receiving sides operate at different frequencies, overflow or underflow errors may occur. When an overflow or underflow error occurs, the computing system 700 can enter a recovery state. For example, communication between PCIe devices may be suspended, and significant performance degradation and data loss may occur in the PCIe system. Therefore, the path margin controller 722 can request information indicating the state of the elastic buffer included in the external device 710 via a margin command. Specifically, the path margin controller 722 can request information indicating the state of the elastic buffer from the external device 710 by sending a margin command of a vendor-defined type to the external device 710. The path margin controller 722 can increase / decrease the transmission interval of skipped ordered sets based on the received state of the elastic buffer from the external device 710.

[0088] In some implementations, external device 710 can perform a path margin operation in response to a margin command. External device 710 can acquire and store margin status information through the path margin operation. Additionally, path margin controller 722 can control upstream port 721 to receive margin status information from external device 710. Upstream port 721 can receive margin status information via a receiver.

[0089] The port configuration controller 723 can determine the configuration of the upstream port 721 based on margin status information. The port configuration controller 723 can adjust the characteristics of signals transmitted / received through the link by controlling the configuration of the transmitters and receivers included in the upstream port 721 based on the margin status information. For example, the port configuration controller 723 can control the configuration of the transmitters and receivers connected to each path to improve the quality of signals transmitted / received through the path and meet specific requirements.

[0090] The margin path control register 724 can store information associated with margin commands. For example, the margin path control register 724 may include receiver number, margin type, usage mode, margin payload, etc. The receiver number may be information used to identify the receiver receiving the margin command. The margin type may be information indicating the type of margin. The usage mode may be information indicating whether a path margin operation will be performed. The margin payload may be information indicating the operation to be indicated by the margin command.

[0091] The margin path status register 725 can store margin status information. For example, the margin path status register 725 may include receiver number status, margin type status, usage mode status, margin payload status, etc.

[0092] The path margin controller 722 can control the path margin operation of the computing system 700 using the path margin control register 724 and the path margin status register 725. For example, the path margin controller 722 can record information associated with the margin command in the path margin control register 724. Furthermore, the path margin controller 722 can record margin status information in the path margin status register 725.

[0093] In some embodiments, the path margin controller 722 can control the upstream port 721 to send a transmitter configuration request to the external device 710. The transmitter configuration request can be used to request an operation to determine the configuration of transmitters included in the external device 710. For example, the configuration of receiver Rx2 included in the upstream port 721 can be determined based on the configuration of transmitter Tx1 included in the external device 710. An operation to update the configuration of receiver Rx2 must be performed when errors are frequently detected in receiver Rx2 or when the configuration of receiver Rx2 according to the configuration of transmitter Tx1 does not meet the system's required values. The PCIe device 720 can allow the re-determination of the transmitter Tx1 configuration by sending a transmitter configuration request to the external device 710. For example, the PCIe device 720 can trigger a transmitter configuration operation of the external device 710 via a transmitter configuration request. In some embodiments, upon receiving a transmitter configuration request requesting the external device 710 to provide transmitter configuration information, the external device 710 can perform a transmitter configuration operation to obtain and / or provide transmitter configuration information.

[0094] External device 710 can determine the settings of transmitter Tx1 based on a transmitter setting request. Subsequently, PCIe device 720 can control upstream port 721 to receive transmitter setting information from external device 710. The transmitter setting information may include information associated with the settings of the transmitter included in external device 710. For example, the transmitter setting information may include prompts associated with the transmitter's settings. PCIe device 720 can determine the settings of the receiver included in upstream port 721 based on the transmitter setting information.

[0095] In some implementations, sender setup requests and sender setup information can be sent via margin commands with vendor-defined types.

[0096] Figure 8 This is a diagram illustrating an operation for determining the settings of a transmitter controlled by an upstream port, based on an embodiment of the disclosed technology.

[0097] Reference Figure 8The computing system 800 may include a first PCIe device 810-1, retimers 810-2 and 810-3, and a second PCIe device 820. The first PCIe device 800-1 and the retimers 810-2 and 810-3 can represent... Figure 7 The external device 710 is shown. The second PCIe device 820 can represent... Figure 7 The PCIe device 720 shown is shown.

[0098] In some implementations, the first PCIe device 810-1 may include a downstream port. The downstream port may include a transmitter Tx(A) and a receiver Rx(A). Retimer X 810-2 may include transmitters Tx(B) and Tx(C) and receivers Rx(B) and Rx(C). Retimer Y 810-3 may include transmitters Tx(D) and Tx(E) and receivers Rx(D) and Rx(E). The second PCIe device 820 may include an upstream port. The upstream port can be connected to the downstream port via a link. The upstream port may include a transmitter Tx(F) and a receiver Rx(F).

[0099] In some implementations, retimers 810-2 and 810-3 may be connected between the first PCIe device 810-1 and the second PCIe device 820.

[0100] In some implementations, each of retimers 810-2 and 810-3 may include a downstream pseudo-port. For example, the downstream pseudo-port of retimer X 810-2 may include a transmitter Tx(C) and a receiver Rx(C). The downstream pseudo-port of retimer Y 810-3 may include a transmitter Tx(E) and a receiver Rx(E). Furthermore, each of retimers 810-2 and 810-3 may include an upstream pseudo-port. For example, the upstream pseudo-port of retimer X 810-2 may include a transmitter Tx(B) and a receiver Rx(B). The upstream pseudo-port of retimer Y 810-3 may include a transmitter Tx(D) and a receiver Rx(D).

[0101] In some implementations, the path through which data or signals move from a downstream port to an upstream port can be defined as a downstream path. On the downstream path, receiver Rx(B) can be connected to transmitter Tx(A) and forward data and signals to transmitter TX(C). Receiver Rx(D) can be connected to transmitter Tx(C) and forward data and signals to transmitter Tx(E). Receiver Rx(F) can be connected to transmitter Tx(E).

[0102] The downstream pseudo-ports and upstream pseudo-ports of retimers 810-2 and 810-3 can be connected to the upstream and downstream ports via links.

[0103] In some implementations, the path through which data or signals move from an upstream port to a downstream port can be defined as the upstream path. On the upstream path, receiver Rx(E) can be connected to transmitter Tx(F) and forward data and signals to transmitter Tx(D). Receiver Rx(C) can be connected to transmitter Tx(D) and forward data and signals to transmitter Tx(B). Receiver Rx(A) can be connected to transmitter Tx(B).

[0104] In some implementations, each of the first PCIe device 810-1 and the second PCIe device 820 may include a margin path control register and a margin path status register. Each of the first PCIe device 810-1 and the second PCIe device 820 may record information associated with margin commands in the margin path control register and record margin status information in the margin path status register.

[0105] In some implementations, the second PCIe device 820 can send margin commands to the first PCIe device 810-1 and retimers 810-2 and 810-3 via an upstream port. For example, the upstream port can generate margin commands. Margin commands may include information identifying any one of the receivers included in the first PCIe device 810-1, the second PCIe device 820, and the retimers 810-2 and 810-3. The upstream port can provide margin commands to the first PCIe device 810-1 and the retimers 810-2 and 810-3 via a control skip ordered set.

[0106] The first PCIe device 810-1 and retimers 810-2 and 810-3 can acquire margin status information for each of the multiple paths in response to a margin command. For example, the first PCIe device 810-1 and retimers 810-2 and 810-3 can acquire margin status information by executing a path margin operation corresponding to the margin command. The first PCIe device 810-1 and retimers 810-2 and 810-3 can send margin status information to the second PCIe device 820 by controlling a skip-order set in response to a margin command. For example, a downstream port can send margin status information to an upstream port by controlling a skip-order set in response to a margin command.

[0107] Additionally, the second PCIe device 820 can receive margin status information from the first PCIe device 810-1 and retimers 810-2 and 810-3 as a response to a margin command. For example, the upstream port can receive margin status information from the downstream port as a response to a margin command. The second PCIe device 820 can determine the settings of the transmitter Tx(F) included in the upstream port based on the margin status information. Subsequently, the first PCIe device 810-1 can determine the settings of the receiver Rx(A) included in the downstream port based on the settings of the transmitter Tx(F) determined by the second PCIe device 820. Furthermore, retimers 810-2 and 810-3 can determine the settings of the receiver Rx(C) and receiver Rx(E) based on the settings of the transmitter Tx(F) determined by the second PCIe device 820.

[0108] Therefore, based on the embodiments of the disclosed technology, by controlling the path margin operation through the upstream port, the settings of the transmitter and receiver included in the upstream port can be tuned in real time. Thus, the link status can be optimized.

[0109] Figure 9 This is a diagram illustrating operations for determining the settings of a receiver controlled by an upstream port, based on an embodiment of the disclosed technology.

[0110] Reference Figure 9 The computing system 800 may include a first PCIe device 810-1, retimers 810-2 and 810-3, and a second PCIe device 820. The first PCIe device 800-1 and the retimers 810-2 and 810-3 can represent... Figure 7 The external device 710 is shown. The second PCIe device 820 can represent... Figure 7 The PCIe device 720 shown is shown.

[0111] In some implementations, the first PCIe device 810-1 may include a downstream port. The downstream port may include a transmitter Tx(A) and a receiver Rx(A). Retimer X 810-2 may include transmitters Tx(B) and Tx(C) and receivers Rx(B) and Rx(C). Retimer Y 810-3 may include transmitters Tx(D) and Tx(E) and receivers Rx(D) and Rx(E). The second PCIe device 820 may include an upstream port. The upstream port can be connected to the downstream port via a link. The upstream port may include a transmitter Tx(F) and a receiver Rx(F).

[0112] In some implementations, retimers 810-2 and 810-3 may be connected between the first PCIe device 810-1 and the second PCIe device 820.

[0113] In some implementations, each of retimers 810-2 and 810-3 may include a downstream pseudo-port. For example, the downstream pseudo-port of retimer X 810-2 may include a transmitter Tx(C) and a receiver Rx(C). The downstream pseudo-port of retimer Y 810-3 may include a transmitter Tx(E) and a receiver Rx(E). Furthermore, each of retimers 810-2 and 810-3 may include an upstream pseudo-port. For example, the upstream pseudo-port of retimer X 810-2 may include a transmitter Tx(B) and a receiver Rx(B). The upstream pseudo-port of retimer Y 810-3 may include a transmitter Tx(D) and a receiver Rx(D).

[0114] In some implementations, the path through which data or signals move from a downstream port to an upstream port can be defined as a downstream path. On the downstream path, receiver Rx(B) can be connected to transmitter Tx(A) and forward data and signals to transmitter TX(C). Receiver Rx(D) can be connected to transmitter Tx(C) and forward data and signals to transmitter Tx(E). Receiver Rx(F) can be connected to transmitter Tx(E).

[0115] In some implementations, the path through which data or signals move from an upstream port to a downstream port can be defined as the upstream path. On the upstream path, receiver Rx(E) can be connected to transmitter Tx(F) and forward data and signals to transmitter Tx(D). Receiver Rx(C) can be connected to transmitter Tx(D) and forward data and signals to transmitter Tx(B). Receiver Rx(A) can be connected to Tx(B).

[0116] In some implementations, each of the first PCIe device 810-1 and the second PCIe device 820 may include a margin path control register and a margin path status register. Each of the first PCIe device 810-1 and the second PCIe device 820 may record information associated with margin commands in the margin path control register and record margin status information in the margin path status register.

[0117] The second PCIe device 820 can send a transmitter configuration request to a downstream port via an upstream port. The transmitter configuration request can be used to request the determination of the settings of transmitters included in the upstream port. For example, the settings of receiver Rx(F) included in the upstream port can be determined based on the settings of transmitter Tx(A) included in the downstream port. When the frequency of errors detected in receiver Rx(F) increases, or when the settings of receiver Rx(F) based on transmitter Tx(A) do not meet the system's required values, an operation to update the settings of receiver Rx(F) must be performed. The second PCIe device 820 can allow the re-determination of the transmitter Tx(A) settings by sending a transmitter configuration request to the downstream port. For example, the second PCIe device 820 can trigger a transmitter configuration operation on the downstream port via a transmitter configuration request.

[0118] The first PCIe device 810-1 can determine the settings of the transmitter included in the downstream port based on a transmitter configuration request. Subsequently, the second PCIe device 820 can receive transmitter configuration information from the first PCIe device 810-1 through the upstream port. The transmitter configuration information may include information associated with the settings of the transmitter included in the downstream port. For example, the transmitter configuration information may include prompts associated with the transmitter settings. The second PCIe device 820 can determine the settings of the receiver included in the upstream port based on the transmitter configuration information.

[0119] In some implementations, sender setup requests and sender setup information can be sent via margin commands with vendor-defined types.

[0120] Figure 10 This is a diagram illustrating an operation for determining the settings of a transmitter controlled by a downstream port, based on an embodiment of the disclosed technology.

[0121] Reference Figure 10 The computing system 800 may include a first PCIe device 810-1, retimers 810-2 and 810-3, and a second PCIe device 820. The first PCIe device 800-1 and the retimers 810-2 and 810-3 can represent... Figure 7 The external device 710 is shown. The second PCIe device 820 can represent... Figure 7 The PCIe device 720 shown is shown.

[0122] In some implementations, the first PCIe device 810-1 may include a downstream port. The downstream port may include a transmitter Tx(A) and a receiver Rx(A). Retimer X 810-2 may include transmitters Tx(B) and Tx(C) and receivers Rx(B) and Rx(C). Retimer Y 810-3 may include transmitters Tx(D) and Tx(E) and receivers Rx(D) and Rx(E). The second PCIe device 820 may include an upstream port. The upstream port can be connected to the downstream port via a link. The upstream port may include a transmitter Tx(F) and a receiver Rx(F).

[0123] In some implementations, retimers 810-2 and 810-3 may be connected between the first PCIe device 810-1 and the second PCIe device 820.

[0124] In some implementations, each of retimers 810-2 and 810-3 may include a downstream pseudo-port. For example, the downstream pseudo-port of retimer X 810-2 may include a transmitter Tx(C) and a receiver Rx(C). The downstream pseudo-port of retimer Y 810-3 may include a transmitter Tx(E) and a receiver Rx(E). Furthermore, each of retimers 810-2 and 810-3 may include an upstream pseudo-port. For example, the upstream pseudo-port of retimer X 810-2 may include a transmitter Tx(B) and a receiver Rx(B). The upstream pseudo-port of retimer Y 810-3 may include a transmitter Tx(D) and a receiver Rx(D).

[0125] In some implementations, the path through which data or signals move from a downstream port to an upstream port can be defined as a downstream path. On the downstream path, receiver Rx(B) can be connected to transmitter Tx(A) and forward data and signals to transmitter TX(C). Receiver Rx(D) can be connected to transmitter Tx(C) and forward data and signals to transmitter Tx(E). Receiver Rx(F) can be connected to transmitter Tx(E).

[0126] The downstream pseudo-ports and upstream pseudo-ports of retimers 810-2 and 810-3 can be connected to the upstream and downstream ports via links.

[0127] In some implementations, the path through which data or signals move from an upstream port to a downstream port can be defined as the upstream path. On the upstream path, receiver Rx(E) can be connected to transmitter Tx(F) and forward data and signals to transmitter Tx(D). Receiver Rx(C) can be connected to transmitter Tx(D) and forward data and signals to transmitter Tx(B). Receiver Rx(A) can be connected to transmitter Tx(B).

[0128] In some implementations, each of the first PCIe device 810-1 and the second PCIe device 820 may include a margin path control register and a margin path status register. Each of the first PCIe device 810-1 and the second PCIe device 820 may record information associated with margin commands in the margin path control register and record margin status information in the margin path status register.

[0129] In some implementations, the first PCIe device 810-1 can send a margin command to the second PCIe device 820 and retimers 810-2 and 810-3 via a downstream port. For example, the downstream port can generate the margin command. The margin command may include information identifying any one of the receivers included in the first PCIe device 810-1, the second PCIe device 820, and the retimers 810-2 and 810-3. The downstream port can provide the margin command to the second PCIe device and the retimers 810-2 and 810-3 via a control skip ordered set.

[0130] The second PCIe device 820 and retimers 810-2 and 810-3 can acquire margin status information for each of the multiple paths in response to a margin command. For example, the second PCIe device 820 and retimers 810-2 and 810-3 can acquire margin status information by executing a path margin operation corresponding to the margin command. The second PCIe device 820 and retimers 810-2 and 810-3 can also send margin status information to the first PCIe device 810-1 by controlling a skip-order set in response to a margin command. For example, an upstream port can send margin status information to a downstream port by controlling a skip-order set in response to a margin command.

[0131] Additionally, the first PCIe device 810-1 can receive margin status information from the second PCIe device 820 and retimers 810-2 and 810-3 as a response to a margin command. For example, the downstream port can receive margin status information from the upstream port as a response to a margin command. The first PCIe device 810-1 can determine the settings of the transmitter Tx(A) included in the upstream port based on the margin status information. Subsequently, the second PCIe device 820 can determine the settings of the receiver Rx(F) included in the upstream port based on the settings of the transmitter Tx(A) determined by the first PCIe device 810-1. Furthermore, retimers 810-2 and 810-3 can determine the settings of the receivers Rx(C) and Rx(E) based on the settings of the transmitter Tx(A) determined by the first PCIe device 810-1.

[0132] Therefore, based on the embodiments of the disclosed technology, in addition to the upstream port, the path margin operation is also controlled through the downstream port, thereby enabling a variety of means to optimize the link state.

[0133] Figure 11 This is a flowchart illustrating a method for determining the settings of an upstream port based on an embodiment of the disclosed technology.

[0134] Figure 11 The method shown can be derived from, for example... Figure 7 or Figure 8 The computational system shown will be used to perform this task. In the following text, for ease of description, it will be based on... Figure 8 The method is described using the computing system 800 shown.

[0135] In operation S1101, the computing system 800 can send a margin command for requesting path margin operation to the first PCIe device and the retimer from the second PCIe device.

[0136] Margin status information may include eye diagram margin information, error information, or other information. In some embodiments, eye diagram margin information may include an indication of the quality of signals transmitted / received through multiple paths. In some embodiments, error information may include information associated with errors occurring during path margin operation.

[0137] In operation S1103, the computing system 800 may perform a path margin operation in the first PCIe device and the retimer. In some embodiments, the path margin operation may be performed to obtain margin status information indicating the margin of each of the plurality of paths.

[0138] In operation S1105, the computing system 800 can receive margin status information of each of the multiple paths from the first PCIe device and the retimer in the second PCIe device.

[0139] In operation S1107, the computing system 800 can determine the upstream port settings in the second PCIe device based on margin status information.

[0140] The computing system 800 can determine the settings of the transmitter included in the second PCIe device based on the margin status information.

[0141] Figure 12 This is a flowchart illustrating a method for determining receiver settings based on an embodiment of the disclosed technology.

[0142] Figure 12 The method shown can be derived from, for example... Figure 7 or Figure 8 The computational system shown will be used to perform this task. In the following text, for ease of description, it will be based on... Figure 8 The method is described using the computing system 800 shown.

[0143] In operation S1201, the computing system 800 may send a transmitter setting request from the second PCIe device to the first PCIe device.

[0144] In operation S1203, the computing system 800 may perform a transmitter setup operation in the first PCIe device. In some embodiments, the first PCIe device may perform a transmitter setup operation to obtain transmitter setup information.

[0145] In operation S1205, the computing system 800 may receive transmitter configuration information from the first PCIe device in the second PCIe device. The transmitter configuration information may include information associated with the configuration of the transmitter included in the first PCIe device.

[0146] In operation S1207, the computing system 800 can determine the receiver settings in the second PCIe device based on the transmitter setting information.

[0147] Figure 13 This is a flowchart illustrating a method for determining the settings of a downstream port based on an embodiment of the disclosed technology.

[0148] Figure 13 The method shown can be derived from, for example... Figure 7 or Figure 8 The computational system shown will be used to perform this task. In the following text, for ease of description, it will be based on... Figure 8 The method is described using the computing system 800 shown.

[0149] In operation S1301, the computing system 800 can send a margin command from the first PCIe device to the second PCIe device and the retimer to request a path margin operation.

[0150] The margin status information may include eye diagram margin information, error information, or other information.

[0151] In operation S1303, computing system 800 can perform path margin operation in the second PCIe device and retimer.

[0152] In operation S1305, the computing system 800 can receive margin status information of each of the multiple paths from the second PCIe device and the retimer in the first PCIe device.

[0153] In operation S1307, the computing system 800 can determine the downstream port settings in the first PCIe device based on margin status information.

[0154] The computing system 800 can determine the settings of the transmitters included in the first PCIe device based on the margin status information.

[0155] In some embodiments of the disclosed technology, a PCIe device capable of controlling the path margin operation in an upstream port, and a computing system including the PCIe device, may be provided.

[0156] In some embodiments of the disclosed technology, control path margin operation is performed in the upstream port, thereby allowing real-time adjustment of the settings of the transmitters and receivers included in the upstream port. Therefore, the state of the link connecting PCIe devices can be optimized.

[0157] In some implementations, some of the operations discussed above may be selectively performed or omitted. The order of operations may be modified in each embodiment.

[0158] Only limited examples of implementations or embodiments of the disclosed technology are described or illustrated. Variations and enhancements to the disclosed implementations or embodiments, as well as other implementations or embodiments, are possible based on what is disclosed and illustrated in this patent document.

Claims

1. An apparatus for performing communication between components in a computing system, comprising: An upstream port receives data from or transmits data to one or more external devices located on an upstream path via a link, the link comprising multiple paths including differential signal pairs for receiving and transmitting data; A margin path control register stores information associated with a margin command that requests a path margin operation to obtain margin status information, the margin status information indicating the margin of each of the plurality of paths. A margin path status register stores the margin status information; A path margin controller is connected to the upstream port and records information associated with the margin command in the margin path control register. It controls the upstream port to transmit the margin command recorded in the margin path control register to the one or more external devices, controls the upstream port to receive the margin status information from the external devices, and records the margin status information received through the upstream port in the margin path status register. The port setting controller receives the margin status information from the margin path status register and connects to communicate with the upstream port to determine the setting of the upstream port based on the margin status information.

2. The apparatus of claim 1, wherein the margin status information includes at least one of eye diagram margin information or error information, the eye diagram margin information including an indication of the quality of a signal transmitted or received through each of the plurality of paths, and the error information including information associated with an error occurring from margin operation of the path.

3. The apparatus of claim 1, wherein the margin command and the margin status information are transmitted by controlling the skipping of ordered sets.

4. The apparatus of claim 1, wherein the upstream port comprises: The transmitter sends the margin command; as well as The receiver receives the margin status information.

5. The apparatus of claim 4, wherein the port setting controller determines the settings of the transmitter based on the margin status information.

6. The apparatus of claim 4, wherein the path margin controller: A transmitter setup request is sent to the external device, the transmitter setup request being used to request the external device to provide transmitter setup information by performing a transmitter setup operation; and The upstream port is controlled to receive transmitter setting information associated with the settings of a transmitter included in the external device. in, The port setting controller determines the receiver settings based on the transmitter setting information.

7. The apparatus of claim 6, wherein the transmitter setup request and the transmitter setup information are sent via a margin command having a vendor-defined type.

8. The apparatus of claim 1, wherein the apparatus includes a high-speed peripheral component interconnect device, i.e., a PCIe device, serving as a downstream component located in the downstream path, and The external device is an upstream component or one or more retimers located on the upstream path.

9. A computing system, comprising: The first device includes a downstream port and receives and transmits data via the downstream port in accordance with the high-speed peripheral component interconnect standard, namely the PCIe standard; as well as The second device includes an upstream port connected to the downstream port of the first device via a link, a margin path control register storing information associated with margin commands, and a margin path status register storing margin status information, the link including multiple paths, the margin status information indicating the margin of each of the multiple paths. The second device: Data is received and transmitted via the first device through the upstream port according to the high-speed peripheral component interconnection standard; The information associated with the margin command is recorded in the margin path control register; The margin command recorded in the margin path control register is sent to the first device through the upstream port. The margin status information is received via the upstream port as a response to the margin command from the first device; The margin status information received through the upstream port is recorded in the margin path status register; and The settings of the upstream port are determined based on the margin status information recorded in the margin path control register.

10. The computing system of claim 9, wherein the first device: The margin status information is obtained by executing the path margin operation corresponding to the margin command; and In response to the margin command, the margin status information is sent to the second device via a control skip ordered set.

11. The computing system of claim 9, wherein the margin status information includes at least one of eye diagram margin information or error information, the eye diagram margin information including an indication of the quality of a signal transmitted or received through each of the plurality of paths, and the error information including information associated with an error occurring in a path margin operation corresponding to the margin command.

12. The computing system of claim 9, wherein the second device sends the margin command by controlling the skipping of ordered sets.

13. The computing system of claim 9, further comprising one or more retimers connected to the downstream port and the upstream port via the link.

14. The computing system of claim 13, wherein the margin command includes information for identifying any one of the first device, the second device, and the receiver included in the retimer.

15. The computing system of claim 13, wherein the second device receives the margin status information as a response to the margin command from the retimer.

16. The computing system of claim 15, wherein the second device determines the settings of the transmitter included in the upstream port based on the margin state information, and The first device and the retimer determine the settings of the downstream port and the receiver included in the retimer based on the settings of the transmitter included in the upstream port.

17. The computing system of claim 9, wherein the second device sends a transmitter setting request to the first device via the upstream port for requesting a transmitter setting operation of the downstream port.

18. The computing system of claim 17, wherein the first device determines the settings of the transmitter included in the downstream port based on the transmitter setting request, and The second device: Receive transmitter setting information associated with the settings of the transmitter included in the downstream port from the first device via the upstream port; and The settings of the receivers included in the upstream port are determined based on the transmitter settings information.

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