Display substrate, display panel and display device

Abstract

A display substrate, a display panel and a display device are provided. The display substrate includes a first display area and a second display area, and the transmittance of the first display area is greater than the transmittance of the second display area. A plurality of sub-pixels located in the first display area include a plurality of sub-pixel groups, each sub-pixel group includes a first sub-pixel and a second sub-pixel, the first pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit, the first sub-pixel driving circuit is used to drive a first light-emitting device of the first sub-pixel to emit light, the second sub-pixel driving circuit is used to drive a first light-emitting device of the second sub-pixel to emit light, the first sub-pixel driving circuit includes at least a first reset transistor, the second sub-pixel driving circuit includes at least a second reset transistor, and the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit are at least partially shared.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate, a display panel, and a display device. Background Art

[0002] With the increasing demand for diversified use of display devices by users and the emergence of design requirements for high screen-to-body ratio of display devices, the "under-screen camera" solution has emerged. In the "under-screen camera" solution, the camera and other imaging modules are embedded in the display area to reduce the size of the border area of ​​the display device, thereby increasing the screen-to-body ratio. At present, in the "under-screen camera" solution, on the basis of increasing the screen-to-body ratio of the display device, how to balance the light transmittance and display effect at the position where the imaging module is set in the display substrate has become an important topic of concern for R&D personnel.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore, the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, a display substrate is provided, the display substrate comprising a first display area and a second display area, the transmittance of the first display area being greater than the transmittance of the second display area, the display substrate comprising: a base substrate; a plurality of sub-pixels arranged on the base substrate and located in the first display area, the sub-pixels comprising a first pixel driving circuit and a first light-emitting device, the first pixel driving circuit being electrically connected to the first light-emitting device, and being used to drive the first light-emitting device to emit light; and a plurality of sub-pixels arranged on the base substrate and located in the second display area, the sub-pixels located in the second display area comprising a second pixel driving circuit and a second light-emitting device, the second pixel driving circuit being electrically connected to the second light-emitting device The first display area is connected to a display device for driving the second light-emitting device to emit light, wherein the plurality of sub-pixels located in the first display area include a plurality of sub-pixel groups, each sub-pixel group includes a first sub-pixel and a second sub-pixel, the first pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit, the first sub-pixel driving circuit is used to drive the first light-emitting device of the first sub-pixel to emit light, the second sub-pixel driving circuit is used to drive the first light-emitting device of the second sub-pixel to emit light, the first sub-pixel driving circuit includes at least a first reset transistor, the second sub-pixel driving circuit includes at least a second reset transistor, and the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit are at least partially shared.

[0005] According to some exemplary embodiments, the orthographic projection of each of the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit on the substrate falls within the orthographic projection of the occupied area of ​​the first sub-pixel driving circuit on the substrate.

[0006] According to some exemplary embodiments, the first reset transistor includes a common transistor and a first sub-transistor, the second reset transistor includes the common transistor and the second sub-transistor, each of the common transistor, the first sub-transistor and the second sub-transistor includes a gate, a source and a drain, the gate of each of the common transistor, the first sub-transistor and the second sub-transistor is connected to a reset control signal, one of the source or the drain of the common transistor is connected to an initialization voltage signal, and the other of the source or the drain of the common transistor is electrically connected to the first sub-transistor and the second sub-transistor, respectively.

[0007] According to some exemplary embodiments, the display substrate also includes a semiconductor layer arranged on the base substrate and a first conductive layer located on a side of the semiconductor layer away from the base substrate, the display substrate also includes a reset signal line arranged on the base substrate, the reset signal line is used to transmit a reset control signal, the reset signal line is located in the first conductive layer; and the reset signal line includes a first part, a second part and a third part located in the first display area, the semiconductor layer includes a common channel part, a first channel part and a second channel part located in the first display area, the orthographic projections of the first part, the second part and the third part on the base substrate coincide with the orthographic projections of the common channel part, the first channel part and the second channel part on the base substrate respectively, the gate of the common transistor includes the first part, the gate of the first sub-transistor includes the second part, and the gate of the second sub-transistor includes the third part.

[0008] According to some exemplary embodiments, the common transistor includes a common source portion and a common drain portion located in the semiconductor layer, the first sub-transistor includes a first sub-source portion and a first sub-drain portion located in the semiconductor layer, and the second sub-transistor includes a second sub-source portion and a second sub-drain portion located in the semiconductor layer; and the common source portion and the common drain portion are respectively located on both sides of the common channel portion, the first sub-source portion and the first sub-drain portion are respectively located on both sides of the first channel portion, and the second sub-source portion and the second sub-drain portion are respectively located on both sides of the second channel portion.

[0009] According to some exemplary embodiments, the display substrate also includes an initialization voltage line arranged on the base substrate and a first connection portion arranged on the base substrate; one of the common source portion and the common drain portion is electrically connected to the initialization voltage line through a first via, and the other of the common source portion and the common drain portion extends continuously with one of the first sub-source portion and the first sub-drain portion; and the other of the first sub-source portion and the first sub-drain portion is electrically connected to one end of the first connection portion through a second via.

[0010] According to some exemplary embodiments, the first sub-pixel driving circuit further includes a first driving transistor, the first driving transistor includes a gate, and the other end of the first connecting portion is electrically connected to the gate of the first driving transistor through a third via hole.

[0011] According to some exemplary embodiments, the display substrate also includes a first transparent conductive connection portion arranged on the base substrate; the other of the common source portion and the common drain portion also extends continuously with one of the second sub-source portion and the second sub-drain portion; and the other of the second sub-source portion and the second sub-drain portion is electrically connected to one end of the first transparent conductive connection portion through a third via.

[0012] According to some exemplary embodiments, the second sub-pixel driving circuit further includes a second driving transistor, the second driving transistor includes a gate, and the other end of the first transparent conductive connection portion is electrically connected to the gate of the second driving transistor through a fourth via hole.

[0013] According to some exemplary embodiments, the initialization voltage line is located in the second conductive layer, the first connecting portion is located in the third conductive layer, the second conductive layer is located on a side of the first conductive layer away from the base substrate, and the third conductive layer is located on a side of the second conductive layer away from the base substrate.

[0014] According to some exemplary embodiments, the first transparent conductive connection portion is located in a first transparent conductive layer, and the first transparent conductive layer is located on a side of the third conductive layer away from the base substrate.

[0015] According to some exemplary embodiments, the first sub-pixel driving circuit also includes a first initialization transistor, which includes an active layer located in the semiconductor layer; the second sub-pixel driving circuit also includes a second initialization transistor, which includes an active layer located in the semiconductor layer; and the orthographic projection of the first transparent conductive connection portion on the substrate overlaps with the orthographic projection of the active layer of the first initialization transistor on the substrate, and the orthographic projection of the first transparent conductive connection portion on the substrate overlaps with the orthographic projection of the active layer of the second initialization transistor on the substrate.

[0016] According to some exemplary embodiments, the display substrate also includes a first scan signal line and a second scan signal line arranged on the base substrate, the first scan signal line is used to supply a scan signal to the first sub-pixel driving circuit, and the second scan signal line is used to supply a scan signal to the second sub-pixel driving circuit; and the orthographic projection of the first scan signal line on the base substrate partially overlaps with the orthographic projection of the active layer of the first initialization transistor on the base substrate, and the orthographic projection of the second scan signal line on the base substrate partially overlaps with the orthographic projection of the active layer of the second initialization transistor on the base substrate.

[0017] According to some exemplary embodiments, the first transparent conductive connection portion includes at least a first portion, a second portion and a third portion, the third portion of the first transparent conductive connection portion extends along a first direction, the second portion of the first transparent conductive connection portion extends along a second direction, and the first portion of the first transparent conductive connection portion extends along an inclined direction that is inclined relative to both the first direction and the second direction.

[0018] According to some exemplary embodiments, an orthographic projection of a first portion of the first transparent conductive connection portion on the substrate partially overlaps with an orthographic projection of an active layer of the first initialization transistor on the substrate; and / or an orthographic projection of a third portion of the first transparent conductive connection portion on the substrate partially overlaps with an orthographic projection of an active layer of the second initialization transistor on the substrate; and / or a second portion of the first transparent conductive connection portion is located in a light-transmitting region between a first sub-pixel and a second sub-pixel.

[0019] According to some exemplary embodiments, the active layer of the first initialization transistor is spaced apart from other portions of the first sub-pixel driving circuit located in the semiconductor layer; and / or the active layer of the second initialization transistor is spaced apart from other portions of the second sub-pixel driving circuit located in the semiconductor layer.

[0020] According to some exemplary embodiments, the display substrate also includes a second connecting portion arranged on the base substrate, a first end of the second connecting portion is electrically connected to the initialization voltage line through a fifth via, and a second end of the second connecting portion is electrically connected to the first end of the active layer of the first initialization transistor through a sixth via.

[0021] According to some exemplary embodiments, the display substrate also includes a second transparent conductive connection portion arranged on the base substrate, the first end of the second transparent conductive connection portion is electrically connected to the second end of the second connection portion through a seventh via hole, and the second end of the second transparent conductive connection portion is electrically connected to the first end of the active layer of the second initialization transistor through an eighth via hole.

[0022] According to some exemplary embodiments, the second connection portion is located in the third conductive layer; and / or the second transparent conductive connection portion is located in the first transparent conductive layer.

[0023] According to some exemplary embodiments, an orthographic projection of the sixth via hole on the base substrate at least partially overlaps with an orthographic projection of the seventh via hole on the base substrate.

[0024] According to some exemplary embodiments, the display substrate also includes a third transparent conductive connection portion arranged on the base substrate, one end of the third transparent conductive connection portion is electrically connected to the first scanning signal line through a ninth via hole, and the other end of the third transparent conductive connection portion is electrically connected to the second scanning signal line through a tenth via hole.

[0025] According to some exemplary embodiments, the display substrate also includes a first light-emitting control line and a second light-emitting control line arranged on the base substrate, the first light-emitting control line is used to supply a light-emitting control signal to the first sub-pixel driving circuit, and the second light-emitting control line is used to supply a light-emitting control signal to the second sub-pixel driving circuit; and the display substrate also includes a fourth transparent conductive connection portion arranged on the base substrate, one end of the fourth transparent conductive connection portion is electrically connected to the first light-emitting control line through an eleventh via hole, and the other end of the fourth transparent conductive connection portion is electrically connected to the second light-emitting control line through a twelfth via hole.

[0026] According to some exemplary embodiments, in at least one sub-pixel group, the first sub-pixel and the second sub-pixel share the reset signal line and the initialization voltage line.

[0027] According to some exemplary embodiments, the multiple sub-pixel groups include at least a first sub-pixel group and a second sub-pixel group located in the same row and adjacent to each other; and the display substrate also includes a first conductive lead arranged on the base substrate, one end of the first conductive lead is electrically connected to the reset signal line in the first sub-pixel group through a thirteenth via hole, and the other end of the first conductive lead is electrically connected to the reset signal line in the second sub-pixel group through a fourteenth via hole.

[0028] According to some exemplary embodiments, the display substrate also includes a second conductive lead arranged on the base substrate, one end of the second conductive lead is electrically connected to the initialization voltage line in the first sub-pixel group through a fifteenth via hole, and the other end of the second conductive lead is electrically connected to the initialization voltage line in the second sub-pixel group through a sixteenth via hole.

[0029] According to some exemplary embodiments, the third transparent conductive connection portion and / or the fourth transparent conductive connection portion is located in the first transparent conductive layer; and the first conductive lead and / or the second conductive lead is located in the second transparent conductive layer, wherein the second transparent conductive layer is located on a side of the first transparent conductive layer away from the base substrate.

[0030] According to some exemplary embodiments, the display substrate further includes: a data signal line for transmitting a data signal; and a driving voltage line for transmitting a driving voltage; and both the data signal line and the driving voltage line are located in the first transparent conductive layer.

[0031] According to some exemplary embodiments, the driving voltage line is disconnected at the first sub-pixel driving circuit and the second sub-pixel driving circuit, so that the driving voltage line includes a first driving voltage sub-line and a second driving voltage sub-line, and the first driving voltage sub-line and the second driving voltage sub-line are spaced apart in the extension direction of the driving voltage line; and the display substrate also includes a third connecting portion, one end of the third connecting portion is electrically connected to the first driving voltage sub-line through a seventeenth via hole, and the other end is electrically connected to the second driving voltage sub-line through an eighteenth via hole.

[0032] According to some exemplary embodiments, the display substrate includes a fourth conductive layer disposed on the base substrate, the fourth conductive layer is located between the first transparent conductive layer and the second transparent conductive layer; and the third connecting portion is located in the fourth conductive layer.

[0033] According to some exemplary embodiments, an orthographic projection of at least one of the first conductive lead and the second conductive lead on the base substrate crosses an orthographic projection of at least one of the data line and the driving voltage line on the base substrate.

[0034] According to some exemplary embodiments, the first light-emitting device includes at least a first electrode and a light-emitting material layer, the light-emitting material layer is arranged on a side of the first electrode away from the base substrate; and the area of ​​the orthographic projection of the first electrode of the first sub-pixel on the base substrate is larger than the area of ​​the orthographic projection of the first electrode of the second sub-pixel on the base substrate.

[0035] According to some exemplary embodiments, the orthographic projection of the first electrode of the first sub-pixel on the substrate covers the orthographic projection of the occupied area of ​​the first sub-pixel driving circuit on the substrate; and / or, the orthographic projection of the first electrode of the second sub-pixel on the substrate covers the orthographic projection of the occupied area of ​​the second sub-pixel driving circuit on the substrate.

[0036] According to some exemplary embodiments, the first sub-pixel is a red sub-pixel or a blue sub-pixel, and the second sub-pixel is a green sub-pixel.

[0037] In another aspect, a display panel is provided, comprising the display substrate as described above.

[0038] In yet another aspect, a display device is provided, comprising the display substrate as described above or the display panel as described above.

[0039] According to some exemplary embodiments, the display device further comprises at least one image sensor; and wherein an orthographic projection of the at least one image sensor on the base substrate falls within an orthographic projection of the first display area on the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0041] Figure 1 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure, in which a plan structure of a display substrate included in the display device is schematically shown.

[0042] Figure 2 A display device according to some exemplary embodiments of the present disclosure is provided along Figure 1 Schematic cross-sectional view taken along line AA'.

[0043] Figure 3 According to some exemplary embodiments of the present disclosure, a display substrate is Figure 1 A local enlarged view of part I in FIG.

[0044] Figure 4 According to some exemplary embodiments of the present disclosure, a display substrate is Figure 3A local enlarged view of part II in FIG.

[0045] Figure 5 According to some exemplary embodiments of the present disclosure, a display substrate is Figure 4 A local enlarged view of part III in FIG.

[0046] Fig. 6A is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure.

[0047] Figure 6B is an equivalent circuit diagram of a pixel driving circuit of a sub-pixel located in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0048] Figure 6C is an equivalent circuit diagram of a pixel driving circuit of a sub-pixel located in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0049] Figure 7 1 is a plan view showing an exemplary implementation of a sub-pixel in a second display region of a display substrate according to some exemplary embodiments of the present disclosure, wherein a plan view of one repeating unit in the second display region is schematically shown.

[0050] Figure 8 It is shown Figure 7 A plan view of a semiconductor layer of an exemplary embodiment of a sub-pixel including one repeating unit.

[0051] Fig. 9 It is shown Figure 7 FIG. 1 is a plan view of a combination of a semiconductor layer and a first conductive layer of an exemplary embodiment of a sub-pixel in which one repeating unit includes.

[0052] Fig.10 It is shown Figure 7 1 is a plan view of a combination of a semiconductor layer, a first conductive layer, and a second conductive layer of an exemplary embodiment of a sub-pixel including one repeating unit.

[0053] Fig.11 It is shown Figure 7 FIG. 4 is a plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of an exemplary embodiment of a sub-pixel including one repeating unit.

[0054] Fig. 12A and Fig. 12B They are shown respectively Figure 7 FIG. 1 is a plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer of an exemplary embodiment of a sub-pixel including one repeating unit.

[0055] Fig.13 It is shown Figure 7 1 is a plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer of an exemplary embodiment of a sub-pixel including one repeating unit.

[0056] Fig.14A FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig. 12B Schematic diagram of the cross-sectional structure taken along line BB' in FIG.

[0057] Fig. 14B FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig.13 Schematic diagram of the cross-sectional structure taken along line CC' in FIG.

[0058] Fig.15 1 is a plan view showing an exemplary implementation of a sub-pixel in a first display region of a display substrate according to some exemplary embodiments of the present disclosure, wherein a plan view of one repeating unit in the first display region is schematically shown.

[0059] Fig.16A It is shown Fig.15 A plan view of a semiconductor layer of an exemplary embodiment of a sub-pixel including one repeating unit.

[0060] Fig. 16B It is shown Fig.16A A local enlarged view of the semiconductor layer at the reset transistor shown in FIG.

[0061] Fig.17A is a plan view showing a first conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.

[0062] Fig. 17B is a plan view showing a combination of a semiconductor layer and a first conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.

[0063] Fig.18A is a plan view showing a second conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.

[0064] Fig.18B is a plan view showing a combination of a semiconductor layer, a first conductive layer, and a second conductive layer of a sub-pixel group in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0065] Fig.19Ais a plan view showing a third conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.

[0066] Fig.19B is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of a sub-pixel group in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0067] Fig. 20A is a plan view showing a first transparent conductive layer of a sub-pixel group in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0068] Fig. 20B is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a first transparent conductive layer of a sub-pixel group in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0069] Fig.21A is a plan view showing a fourth conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.

[0070] Fig. 21B is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, and a fourth conductive layer of a sub-pixel group in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0071] Fig.22A is a plan view showing a second transparent conductive layer of a sub-pixel group in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0072] Fig. 22B 1 is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, a fourth conductive layer, and a second transparent conductive layer of a sub-pixel group in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0073] Fig.23A is a plan view showing a fifth conductive layer of a sub-pixel group in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.

[0074] Fig. 23B 1 is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, a fourth conductive layer, a second transparent conductive layer and a fifth conductive layer of a sub-pixel group in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure.

[0075] Fig.24AFIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig. 21B Schematic diagram of the cross-sectional structure taken along line DD' in FIG.

[0076] Fig. 24B FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig.23A Schematic diagram of the cross-sectional structure taken along line EE' in FIG.

[0077] Fig.25A and Fig.25B is a plan view illustrating an exemplary implementation of a plurality of sub-pixel groups in a first display region of a display substrate according to some exemplary embodiments of the present disclosure.

[0078] Fig.26A , Fig.26B and Fig.26C They are shown respectively Fig.15 A plan view of a combination of a blocking layer, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first transparent conductive layer, a fourth conductive layer, a second transparent conductive layer and a fifth conductive layer of an exemplary embodiment of three sub-pixels included in one repeating unit.

[0079] Fig. 27 FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig.26A Schematic diagram of the cross-sectional structure taken along line FF'. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0081] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0082] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, the Y-axis, and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis, and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0083] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various parts, components, elements, regions, layers and / or parts, these parts, components, elements, regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and / or part from another. Thus, for example, the first part, first member, first element, first region, first layer and / or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and / or second part without departing from the teachings of the present disclosure.

[0084] For ease of description, spatial relational terms, such as "upper", "lower", "left", "right", etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that the spatial relational terms are intended to cover other different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the figure is turned upside down, elements described as "below" or "beneath" other elements or features will be oriented "above" or "above" the other elements or features.

[0085] As used herein, the terms "about," "approximately," "substantially," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein include the stated value and indicate that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0086] It should be noted that, in this article, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are made of the same material and are formed through the same composition process. Usually, multiple elements, components, structures and / or parts located in the "same layer" have approximately the same thickness.

[0087] Those skilled in the art should understand that, herein, unless otherwise specified, the expressions "continuous extension", "integrated structure", "monolithic structure" or similar expressions mean that multiple elements, components, structures and / or parts are located on the same layer and are usually formed by the same patterning process during the manufacturing process. There are no gaps or breaks between these elements, components, structures and / or parts, but they are continuously extended structures.

[0088] In this document, the expression "repeating unit" refers to a combination of multiple sub-pixels, for example, a combination of multiple sub-pixels used to display a pixel, and multiple "repeating units" are repeatedly arranged in an array on the substrate. For example, a repeating unit may include at least one pixel, for example, may include 2, 3, 4, or more sub-pixels. In addition, in this document, for the convenience of description, the repeating unit located in the first display area is referred to as the first repeating unit, and the repeating unit located in the second display area is referred to as the second repeating unit.

[0089] In this document, the expression "pixel density" refers to the number of repeating units or sub-pixels per unit area. For example, PPI can be used to represent pixel density, and PPI means the number of pixels per unit area. Similarly, the expression "distribution density" refers to the number of components (such as repeating units, sub-pixels, spacers, etc.) per unit area.

[0090] Figure 1 is a schematic plan view of a display device according to some exemplary embodiments of the present disclosure, in which a plan structure of a display substrate included in the display device is schematically shown. Figure 2 A display device according to some exemplary embodiments of the present disclosure is provided along Figure 1 Schematic cross-sectional view taken along line AA'.

[0091] For example, the display device includes a display substrate. The display substrate may be an electroluminescent display substrate, such as an OLED display substrate.

[0092] like Figure 1 As shown, the display device according to the embodiment of the present disclosure includes a display substrate 100. The display substrate 100 includes a display area, and the display area may include a first display area AA1 and a second display area AA2. For example, the first display area AA1 and the second display area AA2. For example, the second display area AA2 at least partially surrounds (for example, completely surrounds) the first display area AA1.

[0093] like Figure 2 As shown, the display substrate 100 may include a base substrate 1. The sensor 2 may be disposed on the back side of the base substrate 1 located at the first display area AA1 (at Figure 2 The first display area AA1 can meet the imaging requirements of the sensor 2 for light transmittance.

[0094] For example, the transmittance of the first display area AA1 is greater than the transmittance of the second display area AA2. The sensor 2 is, for example, an image sensor or an infrared sensor. The sensor 2 is configured to receive a display side ( Figure 2 The upper side of the display, for example, displays the light in the direction of light emission, or the direction of the human eye when displaying), so that image capture, distance perception, light intensity perception and other operations can be performed. These lights, for example, pass through the first display area AA1 and then shine on the sensor, thereby being sensed by the sensor.

[0095] It should be noted that in the illustrated exemplary embodiment, the second display area AA2 completely surrounds the first display area AA1, but the embodiments of the present disclosure are not limited thereto. For example, in other embodiments, the first display area AA1 may be located at the upper edge of the display substrate, for example, three sides of the first display area AA1 are surrounded by the second display area AA2, and the upper side thereof is flush with the upper side of the display substrate. For another example, the first display area AA1 may be located at the upper edge of the display substrate and arranged along the entire width of the display substrate.

[0096] For example, the shape of the first display area AA1 can be circular, elliptical, polygonal or rectangular, and the shape of the second display area AA2 can be circular, annular, elliptical or rectangular, but the embodiments of the present disclosure are not limited thereto. For another example, the shapes of the first display area AA1 and the second display area AA2 can both be rectangular, rounded rectangular or other suitable shapes.

[0097] exist Figure 1 to Figure 2 In the display substrate shown, OLED display technology can be used. Due to the advantages of OLED display substrates such as wide viewing angle, high contrast, fast response, low power consumption, foldability, and flexibility, they are increasingly widely used in display products. With the development and in-depth application of OLED display technology, the demand for high screen-to-body ratio displays is becoming increasingly strong. Figure 1 to Figure 2 The display substrate shown adopts the solution of under-screen camera. In this way, the notch area can be eliminated, the hole in the display can be avoided, and the screen-to-body ratio can be increased, providing a better visual experience.

[0098] For example, the display substrate may include a base substrate 1 and various film layers arranged on the base substrate 1. For example, the display substrate may also include a driving circuit layer, a light emitting device layer and a packaging layer arranged on the base substrate 1. Figure 2 Schematically shows a driving circuit layer 3, a light-emitting device layer 4 and an encapsulation layer 5. The driving circuit layer 3 includes a driving circuit structure, and the light-emitting device layer 4 includes a light-emitting device such as an OLED. The driving circuit structure controls the light-emitting device of each sub-pixel to emit light to achieve a display function. The driving circuit structure includes a thin film transistor, a storage capacitor and various signal lines. The various signal lines include a gate line, a data line, an ELVDD power line and an ELVSS power line, etc., so as to provide various signals such as a control signal, a data signal, and a power supply voltage to the pixel driving circuit in each sub-pixel.

[0099] For example, the first display area AA1 may correspond to the under-screen camera, that is, the first display area AA1 may be an under-screen camera area. In the embodiment of the present disclosure, the display substrate 100 includes two first display areas AA1 as an example for description. Each of the first display areas AA1 may be circular, substantially circular, elliptical, polygonal, or the like. The two first display areas AA1 are arranged at intervals, and there is an interval area SR between the two first display areas AA1.

[0100] For example, combined with reference Figure 1 and Figure 2In the illustrated embodiment, two sensors 2 may be provided to correspond to two sub-display areas respectively, so as to form a display device having a dual-camera structure. However, the embodiments of the present disclosure are not limited thereto, and in other embodiments, fewer (e.g., one) or more sub-display areas and sensors 2 may be provided. In addition, the shape of the sub-display area may be determined according to the shape of the hardware structure to be installed. For example, the orthographic projection of each sub-display area on the substrate may have one or more of the following shapes: circular, elliptical, rectangular, rounded rectangular, square, rhombus, trapezoidal, polygonal, and various combinations of these shapes.

[0101] In the embodiment of the present disclosure, a display area having a higher light transmittance than a normal display area is provided in the display substrate, and a hardware structure such as a camera is installed in the display area. In this way, functions such as under-screen camera can be realized, thereby increasing the screen-to-body ratio and achieving a full-screen effect.

[0102] In the related art, in order to make the transmittance in the display area where the sensor 2 is provided (i.e., the above-mentioned first display area AA1) higher than the transmittance in the normal display area (i.e., the above-mentioned second display area AA2), the pixel density in the first display area is usually reduced, that is, the PPI in the first display area is less than the PPI in the second display area. For example, the PPI in the first display area is usually set to less than half of the PPI in the second display area. However, this method of reducing the PPI will reduce the display quality in the first display area. Compared with the normal display area, the picture displayed in the first display area will have obvious graininess visually. In addition, in the related art, the pixel driving circuit of the pixels in the first display area is also usually set outside the camera area under the screen. For example, the pixel driving circuit is set in the above-mentioned spacing area SR. In this case, black edges will appear in the display area between the two sensors 2 during display, which will have an adverse effect on the overall display quality. In addition, when the pixel driving circuit is arranged outside the camera area under the screen, the pixel driving circuit arranged outside must be electrically connected to the light-emitting elements (such as OLEDs) of each pixel arranged in the camera area under the screen through conductive leads. Due to the limitations of the spacing between pixels and the line width and line spacing of the conductive leads, the realization of a high PPI in the camera area under the screen will be limited, that is, a high PPI under the screen camera area cannot be achieved.

[0103] Embodiments of the present disclosure at least provide a display substrate, a display panel, and a display device. The display substrate includes a first display area and a second display area, the transmittance of the first display area is greater than the transmittance of the second display area, and the display substrate includes: a base substrate; a plurality of sub-pixels arranged on the base substrate and located in the first display area, the sub-pixels include a first pixel driving circuit and a first light-emitting device, the first pixel driving circuit is electrically connected to the first light-emitting device and is used to drive the first light-emitting device to emit light; and a plurality of sub-pixels arranged on the base substrate and located in the second display area, the sub-pixels located in the second display area include a second pixel driving circuit and a second light-emitting device, the second pixel driving circuit is electrically connected to the second light-emitting device and is used to drive the second light-emitting device to emit light, wherein the plurality of sub-pixels located in the first display area include a plurality of sub-pixel groups, each of which includes a first sub-pixel and a second sub-pixel, the first pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit, the first sub-pixel driving circuit is used to drive the first light-emitting device of the first sub-pixel to emit light, the second sub-pixel driving circuit is used to drive the first light-emitting device of the second sub-pixel to emit light, the first sub-pixel driving circuit includes at least a first reset transistor, the second sub-pixel driving circuit includes at least a second reset transistor, and the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit are at least partially shared. In an embodiment of the present disclosure, in the under-screen camera area, multiple sub-pixels can share at least a portion of the reset transistor. This is helpful in reducing the area occupied by the pixel driving circuit corresponding to a portion of the sub-pixels, thereby achieving a higher PPI in the under-screen camera area while ensuring that the transmittance of the under-screen camera area meets the requirements.

[0104] Figure 3 According to some exemplary embodiments of the present disclosure, a display substrate is Figure 1 A local enlarged view of part I in FIG. Figure 4 According to some exemplary embodiments of the present disclosure, a display substrate is Figure 3 A local enlarged view of part II in FIG. Figure 5 According to some exemplary embodiments of the present disclosure, a display substrate is Figure 4 A local enlarged view of part III in FIG.

[0105] Combined with reference Figures 1 to 5 The display substrate may include a first display area AA1 and a second display area AA2, the transmittance of the first display area AA1 is higher than the transmittance of the second display area AA2, and the first display area AA1 may correspond to the sensor 2, that is, the orthographic projection of the sensor 2 on the base substrate 1 falls within the orthographic projection of the first display area AA1 on the base substrate 1.

[0106] Fig. 6A is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Figure 7 1 is a plan view showing an exemplary embodiment of a sub-pixel in the second display area AA2 of a display substrate according to some exemplary embodiments of the present disclosure, wherein a plan view of one repeating unit in the second display area AA2 is schematically shown. Figure 8 It is shown Figure 7 A plan view of a semiconductor layer of an exemplary embodiment of a sub-pixel including one repeating unit. Fig. 9 It is shown Figure 7 FIG. 1 is a plan view of a combination of a semiconductor layer and a first conductive layer of an exemplary embodiment of a sub-pixel in which one repeating unit includes. Fig.10 It is shown Figure 7 1 is a plan view of a combination of a semiconductor layer, a first conductive layer, and a second conductive layer of an exemplary embodiment of a sub-pixel including one repeating unit. Fig.11 It is shown Figure 7 FIG. 4 is a plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of an exemplary embodiment of a sub-pixel including one repeating unit. Fig. 12A and Fig. 12B They are shown respectively Figure 7 FIG. 1 is a plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer of an exemplary embodiment of a sub-pixel including one repeating unit. Fig.13 It is shown Figure 7 1 is a plan view of a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer of an exemplary embodiment of a sub-pixel including one repeating unit. Fig.14A FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig. 12B Schematic diagram of the cross-sectional structure taken along line BB' in FIG. Fig. 14B FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig.13 Schematic diagram of the cross-sectional structure taken along line CC' in FIG.

[0107] Combined with reference Figures 1 to 7 In an embodiment of the present disclosure, a plurality of pixels may be provided in the first display area AA1. The plurality of pixels may be arranged in an array on the base substrate 1 along the first direction X and the second direction Y. For example, each of the plurality of pixels may include a sub-pixel 11, a sub-pixel 12, and a sub-pixel 13. For ease of understanding, the sub-pixel 11, the sub-pixel 12, and the sub-pixel 13 may be described as a red sub-pixel, a blue sub-pixel, and a green sub-pixel, respectively, but the embodiments of the present disclosure are not limited thereto.

[0108] In the second display area AA2, a plurality of pixels may be provided. The plurality of pixels may be arranged in an array on the base substrate 1 along the first direction X and the second direction Y. For example, each of the plurality of pixels 20 may include a sub-pixel 21, a sub-pixel 22, and a sub-pixel 23. For ease of understanding, the sub-pixel 21, the sub-pixel 22, and the sub-pixel 23 may be described as a red sub-pixel, a blue sub-pixel, and a green sub-pixel, respectively, but the embodiments of the present disclosure are not limited thereto.

[0109] In an embodiment of the present disclosure, a plurality of repeating units arranged in an array may be provided in the second display area AA2. In this document, for the convenience of description, the repeating unit located in the second display area AA2 is referred to as a second repeating unit P2. In some embodiments, a second repeating unit P2 may include at least one pixel, for example, Figure 7 In the illustrated embodiment, one second repeating unit P2 includes two pixels. Accordingly, one second repeating unit P2 may include a plurality of sub-pixels, such as the sub-pixel 21, sub-pixel 22, and sub-pixel 23 described above.

[0110] In an embodiment of the present disclosure, a plurality of repeating units arranged in an array are provided in the first display area AA1. In this document, for the convenience of description, the repeating unit located in the first display area AA1 is referred to as a first repeating unit P1. In some embodiments, a first repeating unit P1 may include at least one pixel. For example, in some embodiments, a first repeating unit P1 includes 2 pixels. Accordingly, a first repeating unit P1 may include a plurality of sub-pixels, such as the above-mentioned sub-pixel 11, sub-pixel 12, and sub-pixel 13.

[0111] It should be noted that the embodiments of the present disclosure are described by taking red, green and blue as examples, but the embodiments of the present disclosure are not limited thereto, that is, each repeating unit may include at least two sub-pixels of different colors, such as a first color sub-pixel, a second color sub-pixel and a third color sub-pixel, and the first color, the second color and the third color are different colors from each other. In some embodiments of the present disclosure, the arrangement of the sub-pixels in each repeating unit may refer to a conventional pixel arrangement, such as GGRB, RGBG, RGB, etc., and the embodiments of the present disclosure are not limited thereto.

[0112] It should be understood that in the embodiments of the present disclosure, the sub-pixels located in the first display area AA1 and the second display area AA2 may include a pixel driving circuit and a light-emitting device. For example, the light-emitting device may be an OLED light-emitting device, including a stacked anode, an organic light-emitting layer, and a cathode. The pixel driving circuit may include a plurality of thin film transistors and at least one storage capacitor.

[0113] It should be noted that, although in the illustrated embodiment, the first direction X and the second direction Y are perpendicular to each other, the embodiments of the present disclosure are not limited thereto.

[0114] Below, taking the 7T1C pixel driving circuit as an example, the structure of the pixel driving circuit of the sub-pixels located in the first display area AA1 and the second display area AA2 is described in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit. In the absence of conflict, other known pixel driving circuit structures can be applied to the embodiments of the present disclosure.

[0115] It should be understood that in the embodiments of the present disclosure, Fig.13 and Fig. 14B , the display substrate 100 also includes a pixel definition layer PDL located on the side of the first electrode (e.g., anode) away from the pixel driving circuit, the pixel definition layer PDL includes a plurality of openings, each sub-pixel corresponds to at least one pixel definition layer opening (e.g., one), and the actual light-emitting area or display area of ​​the sub-pixel is roughly equivalent to the pixel definition layer opening corresponding to the sub-pixel. In some embodiments, the pixel definition layer opening or the actual light-emitting area corresponding to each sub-pixel is smaller than the area of ​​the first electrode (e.g., anode), and the projection on the substrate completely falls within the projection of the first electrode on the substrate. For the convenience of illustration, in the embodiments of the present disclosure, only the approximate position and shape of the first electrode (e.g., anode) of the sub-pixel are shown to indicate the distribution of each sub-pixel.

[0116] Combined with reference Figure 7 , Fig.13 and Fig. 14B , each sub-pixel located in the second display area AA2 may include a light-emitting device (e.g., an OLED). For the convenience of description, the light-emitting device located in the second display area AA2 is referred to as a second light-emitting device 42. For example, the second light-emitting device 42 may include an anode 42A, a light-emitting material layer 42B, and a cathode 42C arranged in a stacked manner. It should be noted that, for the sake of clarity, the anode of the second light-emitting device 42 is used in the plan view to schematically illustrate the second light-emitting device 42, thereby schematically representing the sub-pixel located in the second display area AA2. For example, in the second display area AA2, the anode 42A of the second light-emitting device 42 may include an anode body 421 and an anode connecting portion 422. The positive projection of the anode body 421 on the base substrate 1 may have a regular shape, such as a circle, an ellipse, a rectangle, a hexagon, an octagon, a rounded rectangle, etc. A pixel driving circuit (described below) for driving the second light-emitting device 42 is also provided in the second display area AA2, and the anode connecting portion 422 is electrically connected to the pixel driving circuit of the second light-emitting device 42.

[0117] For example, refer to Figure 7 , the second repeating unit P2 may include a plurality of sub-pixels arranged in 4 rows and 4 columns. In the first row, sub-pixel 21 and sub-pixel 22 are arranged in the first column and the third column, respectively. In the second row, two sub-pixels 23 are arranged in the second column and the fourth column, respectively. In the third row, sub-pixel 22 and sub-pixel 21 are arranged in the first column and the third column, respectively. In the fourth row, two sub-pixels 23 are arranged in the second column and the fourth column, respectively.

[0118] It should be noted that Figure 7 The arrangement of sub-pixels shown in the figure is only an exemplary arrangement of some embodiments of the present disclosure, and is not a limitation to the embodiments of the present disclosure. In other embodiments, the sub-pixels may be arranged in other ways.

[0119] For example, in some embodiments of the present disclosure, refer to Figure 7 , the area of ​​the orthographic projection of the anode main body 421 of a sub-pixel 21 on the substrate 1 is smaller than the area of ​​the orthographic projection of the anode main body 421 of a sub-pixel 22 on the substrate 1, and the area of ​​the orthographic projection of the anode main body 421 of a sub-pixel 23 on the substrate 1 is smaller than the area of ​​the orthographic projection of the anode main body 421 of a sub-pixel 21 on the substrate 1. That is, the actual light-emitting area of ​​a green sub-pixel is the smallest, the actual light-emitting area of ​​a blue sub-pixel is the largest, and the actual light-emitting area of ​​a red sub-pixel is between the green sub-pixel and the blue sub-pixel.

[0120] Combined with reference Fig. 6A , Figures 7 to 14B , the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (ie, OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0121] The display substrate may further include a plurality of signal lines, for example, the plurality of signal lines include: a scanning signal line 61 for transmitting a scanning signal Sn, a reset signal line 62 for transmitting a reset control signal RESET (for example, the reset control signal RESET may be a scanning signal of a previous row), a light control line 63 for transmitting a light control signal En, a data signal line 64 for transmitting a data signal Dm, a driving voltage line 65 for transmitting a driving voltage VDD, an initialization voltage line 66 for transmitting an initialization voltage Vint, and a power line 67 for transmitting a VSS voltage.

[0122] The storage capacitor Cst may include two capacitor plates Cst1 and Cst2. In this article, the capacitor plate Cst1 may be referred to as one end, the first end or the first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 may be referred to as the other end, the second end or the second storage capacitor electrode of the storage capacitor Cst.

[0123] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be arranged along the Figure 8 The active layer may have a curved or bent shape and may include a first active layer 20a corresponding to the first transistor T1, a second active layer 20b corresponding to the second transistor T2, a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7.

[0124] The active layer may include, for example, polysilicon, and, for example, includes a channel region, a source region, and a drain region. The channel region may not be doped or the doping type may be different from that of the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0125] The first transistor T1 includes a first active layer 20a and a first gate G1. The first active layer 20a includes a first channel region 201a, a first source region 203a, and a first drain region 205a. The gate G1 of the first transistor T1 is electrically connected to the reset signal line 62, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66. The drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3. Fig. 6A As shown, the drain D1 of the first transistor T1, one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected to the node N1. The first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset signal line 62 to transmit the initialization voltage Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, in this article, the first transistor T1 is also called a reset transistor.

[0126] The second transistor T2 includes a second active layer 20b and a second gate G2. The second active layer 20b includes a second channel region 201b, a second source region 203b, and a second drain region 205b. The gate G2 of the second transistor T2 is electrically connected to the scan signal line 61, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing the diode connection of the third transistor T3. In this article, the second transistor T2 is also referred to as a compensation transistor.

[0127] The third transistor T3 includes a third active layer 20c and a third gate G3. The third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c. The third source region 203c and the third drain region 205c extend in two opposite directions relative to the third channel region 201c. The third source region 203c of the third transistor T3 is connected to the fourth drain region 205d and the fifth drain region 205e. The third drain region 205c is connected to the second source region 203b and the sixth source region 203f. The gate G3 of the third transistor T3 is electrically connected to the node N1 through the vias VAH1 and VAH2 and the first connection portion 68. The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. Herein, the third transistor T3 is also referred to as a driving transistor.

[0128] The fourth transistor T4 includes a fourth active layer 20d and a fourth gate G4. The fourth active layer 20d includes a fourth channel region 201d, a fourth source region 203d and a fourth drain region 205d. The fourth transistor T4 is used as a switching device for selecting a light-emitting target sub-pixel. The fourth gate G4 is connected to the scan signal line 61, the fourth source region 203d is connected to the data signal line 64 through the via VAH4, and the fourth drain region 205d is connected to the first transistor T1 and the fifth transistor T5, that is, electrically connected to the node N2. The fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm to the source S3 of the third transistor T3. In this article, the fourth transistor T4 is also referred to as a switching transistor.

[0129] The fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5. The fifth active layer 20e includes a fifth channel region 201e, a fifth source region 203e and a fifth drain region 205e. The fifth source region 203e can be connected to the driving voltage line 65 through a via VAH6. The gate G5 of the fifth transistor T5 is electrically connected to the light emitting control line 63, and the source S5 of the fifth transistor T5 is electrically connected to the driving voltage line 65. The drain D5 of the fifth transistor T5 is electrically connected to the node N2. In this article, the fifth transistor T5 is also referred to as an operation control transistor.

[0130] The sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6, and the sixth active layer 20f includes a sixth channel region 201f, a sixth source region 203f and a sixth drain region 205f. The sixth drain region 205f can be connected to the anode of the OLED through a via VAH7. The gate G6 of the sixth transistor T6 is electrically connected to the light emitting control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the anode of the OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the light emitting control signal En transmitted through the light emitting control line 63 to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow into the OLED. In this article, the sixth transistor T6 is also referred to as a light emitting control transistor.

[0131] The seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7. The seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g and a seventh channel region 201g. The seventh drain region 205g is connected to the first source region 203a of the first transistor T1. The seventh drain region 205g can be electrically connected to the initialization voltage line 66 through the via VAH8, the second connection portion 69 and the via VAH5. The gate G7 of the seventh transistor T7 is electrically connected to the reset signal line 62, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66. Under the control of the seventh transistor T7, the initialization voltage Vint transmitted by the initialization voltage line 66 can be supplied to the OLED, for example, to the first electrode (e.g., anode) of the OLED to initialize the voltage on the first electrode of the OLED. In this article, the seventh transistor T7 may also be referred to as the initialization transistor T7.

[0132] One end (hereinafter referred to as a first storage capacitor electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1 , and the other end (hereinafter referred to as a second storage capacitor electrode) Cst2 is electrically connected to the driving voltage line 65 .

[0133] The anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to the power line 67 to receive the common voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.

[0134] It should be noted that in Fig. 6A In the figure, each thin film transistor T1, T2, T3, T4, T5, T6 and T7 is a p-channel field effect transistor, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 may be an n-channel field effect transistor.

[0135] In operation, in the initialization stage, a reset control signal RESET having a low level is supplied through the reset signal line 62. Subsequently, the first transistor T1 is turned on based on the low level of the reset control signal RESET, and the initialization voltage Vint from the initialization voltage line 66 is transmitted to the gate G1 of the third transistor T3 through the first transistor T1. Therefore, the third transistor T3 is initialized due to the initialization voltage Vint.

[0136] In the data programming stage, a scan signal Sn having a low level is supplied through the scan signal line 61. Subsequently, the fourth transistor T4 and the second transistor T2 are turned on based on the low level of the scan signal Sn. Therefore, the third transistor T3 is placed in a diode connection state through the turned-on second transistor T2 and is biased in a forward direction.

[0137] Subsequently, a compensation voltage Dm+Vth (for example, Vth is a negative value) obtained by subtracting the threshold voltage Vth of the third transistor T3 from the data signal Dm supplied via the data signal line 64 is applied to the gate G3 of the third transistor T3. Subsequently, the driving voltage VDD and the compensation voltage Dm+Vth are applied to both terminals of the storage capacitor Cst, so that charges corresponding to the voltage difference between the corresponding terminals are stored in the storage capacitor Cst.

[0138] In the light emitting phase, the light emitting control signal En from the light emitting control line 63 changes from a high level to a low level. Subsequently, in the light emitting phase, the fifth transistor T5 and the sixth transistor T6 are turned on based on the low level of the light emitting control signal En.

[0139] Then, a driving current is generated based on a difference between a voltage of a gate G3 of the third transistor T3 and the driving voltage VDD. A driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the sixth transistor T6.

[0140] In the light emitting stage, based on the current-voltage relationship of the third transistor T3, the gate-source voltage of the third transistor T3 is maintained at (Dm+Vth)-VDD due to the storage capacitor Cst. The driving current Id is related to (Dm-VDD) 2 Therefore, the driving current Id may not be affected by the change of the threshold voltage Vth of the third transistor T3.

[0141] Combined with reference Figures 7 to 14B , the display substrate includes a base substrate 1 and a plurality of film layers disposed on the base substrate 1. In some embodiments, the plurality of film layers include at least a semiconductor layer 20, a first conductive layer 21, a second conductive layer 22, a third conductive layer 23 and a fourth conductive layer 24. The semiconductor layer 20, the first conductive layer 21, the second conductive layer 22 and the third conductive layer 23 are sequentially disposed away from the base substrate 1. The plurality of film layers also include at least a plurality of insulating film layers, for example, the plurality of insulating film layers may include a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer IDL and a passivation layer PVX. The first gate insulating layer GI1 may be disposed between the semiconductor layer 20 and the first conductive layer 21, the second gate insulating layer GI2 may be disposed between the first conductive layer 21 and the second conductive layer 22, the interlayer insulating layer IDL may be disposed between the second conductive layer 22 and the third conductive layer 23, and the passivation layer PVX may be disposed between the third conductive layer 23 and the fourth conductive layer 24.

[0142] For example, the semiconductor layer 20 may be formed of a semiconductor material such as low temperature polysilicon, and the film thickness thereof may be in the range of 400 to 800 angstroms, for example, 500 angstroms. The first conductive layer 21 and the second conductive layer 22 may be formed of a conductive material forming a gate electrode of a thin film transistor, for example, the conductive material may be Mo, and the film thickness thereof may be in the range of 2000 to 4000 angstroms, for example, 3000 angstroms. The third conductive layer 23 and the fourth conductive layer 24 may be formed of a conductive material forming a source electrode and a drain electrode of a thin film transistor, for example, the conductive material may include Ti, Al, etc. The third conductive layer 23 may have a stacked structure formed of Ti / Al / Ti, and the film thickness thereof may be in the range of 6000 to 9000 angstroms. For example, in the case where the third conductive layer 23 or the fourth conductive layer 24 has a stacked structure formed of Ti / Al / Ti, the thickness of each layer of Ti / Al / Ti may be approximately 500 angstroms, 6000 angstroms, and 500 angstroms, respectively. For example, the first gate insulating layer GI1 and the second gate insulating layer GI2 may be formed of silicon oxide, silicon nitride or silicon oxynitride, and each layer may have a thickness of about 1000 to 2000 angstroms. For example, the interlayer insulating layer IDL and the passivation layer PVX may be formed of silicon oxide, silicon nitride or silicon oxynitride, and have a thickness of about 3000 to 6000 angstroms.

[0143] The display substrate includes a scanning signal line 61, a reset signal line 62, a light emission control line 63, and an initialization voltage line 66 arranged along a row direction X to apply a scanning signal Sn, a reset control signal RESET, a light emission control signal En, and an initialization voltage Vint to each sub-pixel. The display substrate may further include a data signal line 64 and a drive voltage line 65 crossing the scanning signal line 61, the reset signal line 62, the light emission control line 63, and the initialization voltage line 66 to apply a data signal Dm and a drive voltage VDD to each sub-pixel.

[0144] Combined with reference Fig. 9 , Fig. 12A and Fig. 12B , the scanning signal line 61, the reset signal line 62 and the light emission control line 63 are all located in the first conductive layer 21. The gates G1 to G7 of the above-mentioned transistors are also located in the first conductive layer 21. For example, the portion where the reset signal line 62 overlaps with the semiconductor layer 20 forms the gate G1 of the first transistor T1 and the gate G7 of the seventh transistor T7, respectively, the portion where the scanning signal line 61 overlaps with the semiconductor layer 20 forms the gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4, respectively, and the portion where the light emission control line 63 overlaps with the semiconductor layer 20 forms the gate G6 of the sixth transistor T6 and the gate G5 of the fifth transistor T5, respectively.

[0145] Continue to refer to Fig. 9 , the display substrate may further include a plurality of first storage capacitor electrodes Cst1. The plurality of first storage capacitor electrodes Cst1 are also located in the first conductive layer 21. The portion of the first storage capacitor electrode Cst1 overlapping the semiconductor layer 20 forms the third gate G3 of the third transistor T3. The first storage capacitor electrode Cst1 also forms one terminal of the storage capacitor Cst. That is, the first storage capacitor electrode Cst1 is used as the gate G3 of the third transistor T3 and one electrode of the storage capacitor Cst at the same time.

[0146] For example, the orthographic projection of the first storage capacitor electrode Cst1 on the substrate 1 may be substantially rectangular. Here, “substantially rectangular” may include a rectangle, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, and the like.

[0147] like Fig.10As shown, the initialization voltage line 66 is located in the second conductive layer 22. The display substrate may also include a plurality of second storage capacitor electrodes Cst2. The plurality of second storage capacitor electrodes Cst2 are also located in the second conductive layer 22. The plurality of second storage capacitor electrodes Cst2 are respectively arranged corresponding to the plurality of first storage capacitor electrodes Cst1. That is, the orthographic projections of the plurality of second storage capacitor electrodes Cst2 on the base substrate 1 overlap at least partially with the orthographic projections of the corresponding first storage capacitor electrodes Cst1 on the base substrate 1. The second storage capacitor electrode Cst2 forms another terminal of the storage capacitor Cst. That is, the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 are arranged opposite to each other, and the orthographic projections of the two on the base substrate 1 overlap at least partially with each other, and a second gate insulating layer GI2 is arranged between them. For example, the first storage capacitor electrode Cst1 can be electrically connected to the node N1 through the vias VAH1 and VAH2 and the first connecting portion 68, and the second storage capacitor electrode Cst2 can be electrically connected to the driving voltage line 65 through the via VAH9, that is, the two are connected to different voltage signals. Thus, a portion where the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 overlap each other may form the storage capacitor Cst.

[0148] Combined with reference Fig.10 , Figure 12 and Fig.14A , the second storage capacitor electrode Cst2 may include a through hole TH2 to facilitate electrical connection between the first storage capacitor electrode Cst1 located below the second storage capacitor electrode Cst2 and a component located in the third conductive layer 23. For example, a portion of the first connection portion 68 is formed in the via hole VAH1 to form a conductive plug 681. The conductive plug 681 extends through the through hole TH2 and is electrically connected to the first storage capacitor electrode Cst1. In this way, one end of the first connection portion 68 is electrically connected to one end Cst1 of the storage capacitor.

[0149] For example, the orthographic projection of the through hole TH2 on the substrate 1 may be substantially rectangular. Here, “substantially rectangular” may include a rectangle or a square, a rectangle or a square with at least one rounded corner, a rectangle or a square with at least one chamfered corner, and the like.

[0150] Reference Fig.11 The data signal line 64 and the driving voltage line 65 are located in the third conductive layer 23. In addition, the first connecting portion 68 and the second connecting portion 69 are also located in the third conductive layer 23.

[0151] Reference Fig. 12A , Fig. 12B and Fig.13 , the third connection portion 70 is located in the fourth conductive layer 24. One end of the third connection portion 70 is electrically connected to the sixth transistor T6, and the other end is electrically connected to the anode of the OLED.

[0152] Reference Fig.13 and Fig. 14B , the display substrate 100 may further include an insulating layer, such as a planarization layer PLN, disposed between the fourth conductive layer 24 and the fifth conductive layer 25. For example, the planarization layer PLN may include a single film layer or multiple film layers. In the case where the planarization layer PLN includes multiple film layers, the multiple film layers of the planarization layer PLN may be respectively represented as a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3. The via VAH10 may penetrate the planarization layer PLN. The anode 42A of the second light-emitting device 42 is located in the fifth conductive layer 25. A portion of the anode connection portion 422 is formed in the via VAH10, and the portion extends downward to be electrically connected to a portion of the third connection portion 10.

[0153] Thus, one end of the third connection portion 70 is electrically connected to the sixth transistor T6 through the via hole VAH7, and the other end of the third connection portion 70 is electrically connected to the anode connection portion 422 through the via hole VAH10. In order to meet the preset PPI requirements, the sub-pixels on the display substrate need to be arranged in a prescribed manner, so that the extension lengths of the third connection portions 70 in the sub-pixels may be equal or unequal.

[0154] For example, refer to Figure 7 , Fig. 12A and Fig. 12B ,in, Fig. 12A A plan view of a pixel driving circuit of the sub-pixel 21 or the sub-pixel 22 is shown. Fig. 12B FIG. 2 is a plan view of a pixel driving circuit of the sub-pixel 23 . In an embodiment of the present disclosure, the extension length of the third connection portion 70 in the sub-pixel 23 may be smaller than the extension length of the third connection portion 70 in the sub-pixel 21 or the sub-pixel 22 .

[0155] Figure 6B is an equivalent circuit diagram of a pixel driving circuit of a sub-pixel group located in a first display area of ​​a display substrate according to some exemplary embodiments of the present disclosure. Fig.15 is a plan view illustrating an exemplary embodiment of a sub-pixel in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure, wherein a plan view of one repeating unit in the first display area AA1 is schematically illustrated. Fig.16A is a plan view showing a semiconductor layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 16B It is shown Fig.16A A local enlarged view of the semiconductor layer at the reset transistor shown in FIG. Fig.17Ais a plan view showing a first conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 17B 2 is a plan view illustrating a combination of a semiconductor layer and a first conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig.18A is a plan view illustrating a second conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig.18B is a plan view showing a combination of a semiconductor layer, a first conductive layer, and a second conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig.19A is a plan view showing a third conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig.19B is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 20A is a plan view showing a first transparent conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 20B is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, and a first transparent conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig.21A is a plan view showing a fourth conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 20B is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, and a fourth conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig.22A is a plan view showing a second transparent conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 22B is a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, a fourth conductive layer, and a second transparent conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig.23A is a plan view showing a fifth conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 23Bis a plan view showing a combination of a semiconductor layer, a first conductive layer, a second conductive layer, a first transparent conductive layer, a fourth conductive layer, a second transparent conductive layer and a fifth conductive layer of a sub-pixel group in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig.24A FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig. 21B Schematic diagram of the cross-sectional structure taken along line DD' in FIG. Fig. 24B FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig.23A Schematic diagram of the cross-sectional structure taken along line EE' in FIG.

[0156] It should be noted that, in the following description, the difference between the structure of the sub-pixel located in the first display area AA1 and the structure of the sub-pixel located in the second display area AA2 is mainly described, and the similarities between the two can refer to the above description.

[0157] It should also be noted that, in order to make the description of this article more concise, in the following, elements with the same or similar functions and / or structures in the first display area and the second display area may be represented by the same reference numerals, for example, each transistor, storage capacitor, and signal line located in the first display area may be represented by reference numerals corresponding to each transistor, storage capacitor, and signal line located in the second display area. It should be understood that in the following description, these elements and structures are located in the first display area AA1.

[0158] Combined with reference Figure 6B , Figures 15 to 24B In the first display area AA1, the pixel driving circuit of the sub-pixels 11, 12, and 13 may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes a gate, a source, and a drain.

[0159] The multiple signal lines include: a scanning signal line 61 for transmitting a scanning signal Sn, a reset signal line 62 for transmitting a reset control signal RESET (for example, the reset control signal RESET can be a scanning signal of a previous row), a light control line 63 for transmitting a light control signal En, a data signal line 164 for transmitting a data signal Dm, a driving voltage line 165 for transmitting a driving voltage VDD, an initialization voltage line 66 for transmitting an initialization voltage Vint, and a power line 67 for transmitting a VSS voltage.

[0160] It should be understood that, similar to the above-mentioned second display area AA2, in the embodiment of the present disclosure, in the first display area AA1, the display substrate further includes a pixel defining layer located on the side of the first electrode away from the pixel driving circuit, the pixel defining layer includes a plurality of openings, each sub-pixel corresponds to at least one (e.g., one) pixel defining layer opening, and the actual light-emitting area or display area of ​​the sub-pixel is substantially equivalent to the pixel defining layer opening corresponding to the sub-pixel. In some embodiments, the area of ​​the pixel defining layer opening or the actual light-emitting area corresponding to each sub-pixel is smaller than the area of ​​the first electrode (e.g., the anode), and the projection on the base substrate completely falls within the projection of the first electrode on the base substrate.

[0161] like Fig.15 as well as Figure 23A to Figure 23B As shown, each sub-pixel located in the first display area AA1 may include a light-emitting device (such as an OLED). For the convenience of description, the light-emitting device located in the first display area AA1 is referred to as a first light-emitting device 41. For example, the first light-emitting device 41 may include a stacked anode 41A (refer to Fig. 24B ), a light-emitting material layer and a cathode. It should be noted that, for the sake of clarity, the relevant drawings use the anode of the first light-emitting device 41 to schematically illustrate the first light-emitting device 41, thereby schematically representing the sub-pixel located in the first display area AA1. For example, in the first display area AA1, the anode of the first light-emitting device 41 includes an anode body 411 and an anode connecting portion 412. The orthographic projection of the anode body 411 on the base substrate 1 may have a regular shape, such as a circle, an ellipse, a rectangle, a hexagon, an octagon, a rounded rectangle, etc. A pixel driving circuit (to be described below) for driving the first light-emitting device 41 is also provided in the first display area AA1, and the anode connecting portion 412 is electrically connected to the pixel driving circuit of the first light-emitting device 41.

[0162] Reference Fig.15 , schematically showing the pixel defining layer opening and the anode. Consistent with the anode body, the orthographic projection of the opening OPH on the substrate substrate 1 can have a regular shape, such as a circle, an ellipse, a rectangle, a hexagon, an octagon, a rounded rectangle, etc. The projection of the opening OPH on the substrate substrate 1 completely falls within the projection of the anode body 411 on the substrate substrate 1.

[0163] It should be noted that, for the sake of convenience, in the embodiments of the present disclosure, the approximate position and shape of the first electrode (eg, anode) of the sub-pixel are mainly shown to represent the distribution of each sub-pixel.

[0164] For example, in some embodiments of the present disclosure, the arrangement of sub-pixels in each repeating unit may refer to conventional pixel arrangements, such as GGRB, RGBG, RGB, etc., and the embodiments of the present disclosure are not limited to this.

[0165] Similar to the second repeating unit P2, refer to Fig.15 , the first repeating unit P1 may include a plurality of sub-pixels arranged in 4 rows and 4 columns. In the first row, sub-pixel 11 and sub-pixel 12 are arranged in the first column and the third column, respectively. In the second row, two sub-pixels 13 are arranged in the second column and the fourth column, respectively. In the third row, sub-pixel 12 and sub-pixel 11 are arranged in the first column and the third column, respectively. In the fourth row, two sub-pixels 13 are arranged in the second column and the fourth column, respectively.

[0166] It should be noted that Fig.15 The arrangement of sub-pixels shown in the figure is only an exemplary arrangement of some embodiments of the present disclosure, and is not a limitation to the embodiments of the present disclosure. In other embodiments, the sub-pixels may be arranged in other ways.

[0167] Reference Figure 6B , Figures 15 to 23B In an embodiment of the present disclosure, the display substrate may include a plurality of sub-pixel groups located in the first display area AA1, for example, one sub-pixel group may include at least two sub-pixels. For the convenience of description, two sub-pixels of the at least two sub-pixels are referred to as a first sub-pixel and a second sub-pixel, respectively. For example, the first sub-pixel may be one of the above-mentioned sub-pixels 11, 12, and 13, and the second sub-pixel may be one of the above-mentioned sub-pixels 11, 12, and 13 that is different from the first sub-pixel. For example, the first sub-pixel and the second sub-pixel may be sub-pixels of different colors.

[0168] For example, in some embodiments of the present disclosure, refer to Fig.15 , the area of ​​the orthographic projection of the anode main body 421 of a sub-pixel 11 on the substrate 1 is smaller than the area of ​​the orthographic projection of the anode main body 421 of a sub-pixel 12 on the substrate 1, and the area of ​​the orthographic projection of the anode main body 421 of a sub-pixel 13 on the substrate 1 is smaller than the area of ​​the orthographic projection of the anode main body 421 of a sub-pixel 11 on the substrate 1. That is, the actual light-emitting area of ​​a green sub-pixel is the smallest, the actual light-emitting area of ​​a blue sub-pixel is the largest, and the actual light-emitting area of ​​a red sub-pixel is between the green sub-pixel and the blue sub-pixel.

[0169] In an embodiment of the present disclosure, in a sub-pixel group, the first sub-pixel may be one of a red sub-pixel and a blue sub-pixel, and the second sub-pixel may be a green sub-pixel. Thus, hereinafter, some exemplary embodiments of the present disclosure are described by taking the first sub-pixel as sub-pixel 11 or sub-pixel 12 and the second sub-pixel as sub-pixel 13 as an example.

[0170] It should be noted that Figures 15 to 23B A plan view of a sub-pixel group located in the first display area AA1 is shown, wherein in each plan view, the upper left view is a plan view of the first sub-pixel 11 (12), and the lower right view is a plan view of the second sub-pixel 13.

[0171] Reference Figure 6B In the equivalent circuit diagram of a sub-pixel group, a first sub-pixel driving circuit and a second sub-pixel driving circuit are provided. Schematically, Figure 6B The dotted line frame on the left side shows the first sub-pixel driving circuit DR1. Figure 6B The dotted line frame on the right side of the figure shows the second sub-pixel driving circuit DR2. The first sub-pixel driving circuit DR1 is used to drive the first light emitting device 41 of the first sub-pixel 11 (12) to emit light. The second sub-pixel driving circuit DR2 is used to drive the first light emitting device 41 of the second sub-pixel 13 to emit light.

[0172] and Fig. 6A Similar to the pixel driving circuit of a sub-pixel, each of the first sub-pixel driving circuit DR1 and the second sub-pixel driving circuit DR2 may include: a plurality of thin film transistors and a storage capacitor Cst. For example, the plurality of thin film transistors may include a first transistor (also called a reset transistor) T1, a second transistor (also called a compensation transistor) T2, a third transistor (also called a driving transistor) T3, a fourth transistor (also called a switching transistor) T4, a fifth transistor (also called an operation control transistor) T5, a sixth transistor (also called a light emitting control transistor) T6, and a seventh transistor (also called an initialization transistor) T7. Each transistor includes a gate, a source, and a drain.

[0173] In the embodiments of the present disclosure, for the convenience of description, the multiple thin film transistors T1~T7 included in the first sub-pixel driving circuit DR1 are respectively referred to as the first reset transistor T1, the first compensation transistor T2, the first driving transistor T3, the first switching transistor T4, the first operation control transistor T5, the first light emission control transistor T6 and the first initialization transistor T7; the multiple thin film transistors T1~T7 included in the second sub-pixel driving circuit DR2 are respectively referred to as the second reset transistor T1', the second compensation transistor T2, the second driving transistor T3, the second switching transistor T4, the second operation control transistor T5, the second light emission control transistor T6 and the second initialization transistor T7.

[0174] In an embodiment of the present disclosure, the first reset transistor T1 of the first sub-pixel driving circuit DR1 and the second reset transistor T1 ′ of the second sub-pixel driving circuit DR2 are at least partially shared.

[0175] It should be noted that, in this article, "the first reset transistor and the second reset transistor are at least partially shared" means that there is a shared part between the first reset transistor and the second reset transistor, that is, this part serves as a part of the first reset transistor and plays a role in the first sub-pixel driving circuit; and serves as a part of the second reset transistor and plays a role in the second sub-pixel driving circuit.

[0176] For example, combined with reference Figure 6B , the first reset transistor may include a common transistor T10 and a first sub-transistor T11, and the second reset transistor includes the common transistor T10 and a second sub-transistor T12. Thus, in this exemplary embodiment, the common transistor T10 serves as both a part of the first reset transistor and a part of the second reset transistor, and plays a role in the first sub-pixel driving circuit DR1 and the second sub-pixel driving circuit DR2, respectively.

[0177] For example, continue to refer to Figure 6B , each of the common transistor T10, the first sub-transistor T11 and the second sub-transistor T12 includes a gate G1, a source S1 and a drain D1, the gate of each of the common transistor T10, the first sub-transistor T11 and the second sub-transistor T12 is connected to a reset control signal RESET, one of the source or the drain of the common transistor T10 is connected to an initialization voltage signal Vint, and the other of the source or the drain of the common transistor T10 is electrically connected to the first sub-transistor T11 and the second sub-transistor T12, respectively.

[0178] In an embodiment of the present disclosure, in the under-screen camera area, the pixel driving circuits of multiple sub-pixels can share at least a portion of the reset transistor. This is helpful in reducing the area occupied by the pixel driving circuits corresponding to some sub-pixels, thereby achieving a higher PPI in the under-screen camera area while ensuring that the transmittance of the under-screen camera area meets the requirements.

[0179] Combined with reference Figures 15 to 24B, the display substrate includes a base substrate 1 and a plurality of film layers disposed on the base substrate 1. In some embodiments, the plurality of film layers at least include a semiconductor layer 20, a first conductive layer 21, a second conductive layer 22, a third conductive layer 23, a first transparent conductive layer 26, a fourth conductive layer 24, a second transparent conductive layer 28, and a fifth conductive layer 25. The semiconductor layer 20, the first conductive layer 21, the second conductive layer 22, the third conductive layer 23, the first transparent conductive layer 26, the fourth conductive layer 24, the second transparent conductive layer 28, and the fifth conductive layer 25 are sequentially disposed away from the base substrate 1. The plurality of film layers also include at least a plurality of insulating film layers, for example, the plurality of insulating film layers may include a first gate insulating layer GI1, a second gate insulating layer GI2, an interlayer insulating layer IDL, a passivation layer PVX, and a planarization layer PLN. The first gate insulating layer GI1 may be disposed between the semiconductor layer 20 and the first conductive layer 21, the second gate insulating layer GI2 may be disposed between the first conductive layer 21 and the second conductive layer 22, the interlayer insulating layer IDL may be disposed between the second conductive layer 22 and the third conductive layer 23, and the passivation layer PVX may be disposed between the third conductive layer 23 and the first transparent conductive layer 26. For example, the planarization layer PLN may include a plurality of film layers, which are respectively referred to as the first planarization layer PLN1, the second planarization layer PLN2, and the third planarization layer PLN3 for the convenience of description. In some embodiments, the first planarization layer PLN1 may be disposed between the first transparent conductive layer 26 and the fourth conductive layer 24, the second planarization layer PLN2 may be disposed between the fourth conductive layer 24 and the second transparent conductive layer 28, and the third planarization layer PLN3 may be disposed between the second transparent conductive layer 28 and the fifth conductive layer 25.

[0180] In the first display area AA1, the pixel driving circuit of each sub-pixel includes a reset transistor T1, a compensation transistor T2, a driving transistor T3, a switch transistor T4, an operation control transistor T5, a light emission control transistor T6 and an initialization transistor T7. Fig.16A The active layer may have a curved or bent shape and may include a first active layer 20a corresponding to the reset transistor T1, a second active layer 20b corresponding to the transistor T2, a third active layer 20c corresponding to the driving transistor T3, a fourth active layer 20d corresponding to the switching transistor T4, a fifth active layer 20e corresponding to the operation control transistor T5, a sixth active layer 20f corresponding to the light emission control transistor T6, and a seventh active layer 20g corresponding to the initialization transistor T7.

[0181] Reference Fig.16AIn one sub-pixel group, the active layers 20a~20f of the first reset transistor T1, the first compensation transistor T2, the first drive transistor T3, the first switch transistor T4, the first operation control transistor T5 and the first light emission control transistor T6 of the first sub-pixel driving circuit DR1 of the first sub-pixel 11 (12) are formed as a part of a continuous extension of the semiconductor layer 20; the active layers 20b~20f of the second compensation transistor T2, the second drive transistor T3, the second switch transistor T4, the second operation control transistor T5 and the second light emission control transistor T6 of the second sub-pixel driving circuit DR2 of the second sub-pixel 13 are formed as a part of a continuous extension of the semiconductor layer 20.

[0182] It should be noted that, in this article, “continuous extension” means that there is no disconnection in the middle of the component.

[0183] In a sub-pixel group, the seventh active layer 20g of the first initialization transistor T7 of the first sub-pixel driving circuit DR1 of the first sub-pixel 11 (12) is spaced apart from other parts of the first sub-pixel driving circuit DR1 located in the semiconductor layer 20 (i.e., the active layers 20a~20f of the first reset transistor T1, the first compensation transistor T2, the first driving transistor T3, the first switching transistor T4, the first operation control transistor T5 and the first light emission control transistor T6 of the first sub-pixel driving circuit DR1); the seventh active layer 20g of the second initialization transistor T7 of the second sub-pixel driving circuit DR2 of the second sub-pixel 13 is spaced apart from other parts of the second sub-pixel driving circuit DR2 located in the semiconductor layer 20 (i.e., the active layers 20a~20f of the second reset transistor T1', the second compensation transistor T2, the second driving transistor T3, the second switching transistor T4, the second operation control transistor T5 and the second light emission control transistor T6 of the second sub-pixel driving circuit DR2).

[0184] In one subpixel group, the active layer 20a of the first reset transistor T1 of the first subpixel driving circuit DR1 of the first subpixel 11 (12) and the active layer 20a of the second reset transistor T1' of the second subpixel driving circuit DR2 of the second subpixel 13 are at least partially shared. Fig. 16B, the common transistor T10 includes a common active layer 200a, which includes a common channel portion 2010a, a common source portion 2030a, and a common drain portion 2050a. The first sub-transistor T11 includes a first sub-active layer 211a, which includes a first channel portion 2011a, a first sub-source portion 2031a, and a first sub-drain portion 2051a. The second sub-transistor T12 includes a second sub-active layer 212a, which includes a second channel portion 2012a, a second sub-source portion 2032a, and a second sub-drain portion 2052a. The common source portion 2030a and the common drain portion 2050a are respectively located on both sides of the common channel portion 2010a, the first sub-source portion 2031a and the first sub-drain portion 2051a are respectively located on both sides of the first channel portion 2011a, and the second sub-source portion 2032a and the second sub-drain portion 2052a are respectively located on both sides of the second channel portion 2012a. The common active layer 200a, the first sub-active layer 211a and the second sub-active layer 212a extend continuously. For example, one end of the common active layer 200a connects the first sub-active layer 211a and the second sub-active layer 212a.

[0185] In the embodiment of the present disclosure, the shared active layer 200a and the first sub-active layer 211a constitute the active layer 20a of the first reset transistor T1 of the first sub-pixel driving circuit DR1 of the first sub-pixel 11 (12). The shared active layer 200a and the second sub-active layer 212a constitute the active layer 20a of the second reset transistor T1' of the second sub-pixel driving circuit DR2 of the second sub-pixel 13. That is, the active layer 20a of the first reset transistor T1 and the active layer 20a of the second reset transistor T1' have at least a shared portion, namely, the shared active layer 200a.

[0186] In the embodiment of the present disclosure, the active layer 20a of the second reset transistor T1' of the second sub-pixel driving circuit DR2 is formed in the occupied area of ​​the first sub-pixel driving circuit DR1, which is beneficial to reduce the area occupied by the second sub-pixel driving circuit DR2.

[0187] Continue to refer to Fig.16AIn the first sub-pixel driving circuit DR1, the active layer 20g of the first initialization transistor T7 is spaced apart from the active layer 20a of the first reset transistor T1. The active layer 20a of the first reset transistor T1 is connected to the active layer 20b of the first compensation transistor T2, the active layer 20b of the first compensation transistor T2 is connected to the active layer 20c of the first driving transistor T3 and the active layer 20f of the first light emission control transistor T6, and the active layer 20c of the first driving transistor T3 is connected to the active layer 20d of the first switching transistor T4 and the active layer 20e of the first operation control transistor T5. That is, the common active layer 200a, the first sub-active layer 211a and the second sub-active layer 212a, the active layer 20b of the first compensation transistor T2, the active layer 20c of the first driving transistor T3, the active layer 20f of the first light emission control transistor T6, the active layer 20d of the first switching transistor T4, and the active layer 20e of the first operation control transistor T5 are continuously extended. The active layer 20g of the first initialization transistor T7 is disposed apart from these active layers.

[0188] In the second sub-pixel driving circuit DR2, the active layer 20b of the second compensation transistor T2 is connected to the active layer 20c of the second driving transistor T3 and the active layer 20f of the second light emission control transistor T6, and the active layer 20c of the second driving transistor T3 is connected to the active layer 20d of the second switching transistor T4 and the active layer 20e of the second operation control transistor T5. That is, the active layer 20b of the second compensation transistor T2, the active layer 20c of the second driving transistor T3, the active layer 20f of the second light emission control transistor T6, the active layer 20d of the second switching transistor T4 and the active layer 20e of the second operation control transistor T5 extend continuously. The active layer 20g of the second initialization transistor T7 is spaced apart from these active layers.

[0189] Combined with reference Figure 8 and Fig. 9 For a sub-pixel located in the second display area AA2, the active layer 20g of the first initialization transistor T7 extends from the active layer 20a of the first reset transistor T1 in a direction away from the scanning signal line 61 of the sub-pixel, that is, the active layer 20g of the first initialization transistor T7 is located above the right of the active layer 20a of the first reset transistor T1. Through such a setting, the active layer 20g of the first initialization transistor T7 can extend toward the active layer of the adjacent sub-pixel located above the same column, which is conducive to the active layers of the sub-pixels located in the same column to form a continuously extended structure.

[0190] Reference Fig.16A17, for the sub-pixel located in the first display area AA1, the active layer 20g of the first initialization transistor T7 extends in a direction close to the scanning signal line 61 of the sub-pixel relative to the active layer 20a of the first reset transistor T1, that is, the active layer 20g of the first initialization transistor T7 is located at the lower right of the active layer 20a of the first reset transistor T1. With such a setting, the outline of the occupied area of ​​the active layer of a sub-pixel located in the first display area AA1 is a square or approximately a square.

[0191] In this article, the expression "occupied area" refers to the maximum area covered by the orthographic projection of a pattern, layer structure, etc. on the substrate substrate. Specifically, the orthographic projection of a pattern, layer structure, etc. on the substrate substrate has two sides that are farthest apart in the first direction X and two sides that are farthest apart in the second direction Y. The extension lines of these four sides will intersect to enclose an area, which is the occupied area of ​​the pattern, layer structure, etc.

[0192] Specifically, refer to Figure 8 and Fig.16A For a sub-pixel located in the second display area AA2, the occupied area of ​​its active layer has a rectangular or substantially rectangular shape, such as Figure 8 As shown, a dotted box is used to schematically illustrate an occupied area of ​​an active layer of a sub-pixel located in the second display area AA2, and the occupied area has a dimension along the first direction X (i.e., width W2) and a dimension along the second direction Y (i.e., length L2), wherein the length L2 is greater than the width W2, or in other words, the length L2 is more than 1.2 times the width W2, that is, the occupied area has a rectangular shape.

[0193] For a sub-pixel located in the first display area AA1, the occupied area of ​​its active layer has a square or substantially square shape, such as Fig.16A As shown, a dotted box is used to schematically illustrate an occupied area of ​​an active layer of a sub-pixel located in the first display area AA1, and the occupied area has a dimension along a first direction X (i.e., width W1) and a dimension along a second direction Y (i.e., length L1), wherein the length L1 is substantially equal to the width W1.

[0194] In the embodiment of the present disclosure, the occupied area of ​​the active layer of a sub-pixel located in the first display area AA1 is smaller than the occupied area of ​​the active layer of a sub-pixel of the same color located in the second display area AA2. In this way, the occupied area of ​​the pixel driving circuit of the sub-pixel located in the first display area AA1 can be reduced, and this point will be further described in detail below.

[0195] Similarly, if Fig.17A and Fig. 17BAs shown, the scanning signal line 61, the reset signal line 62 and the light emitting control line 63 are all located in the first conductive layer 21. The gates G1 to G7 of the above transistors are also located in the first conductive layer 21. The first storage capacitor electrode Cst1 is also located in the first conductive layer 21. The first conductive layer 21 is located on the side of the semiconductor layer 20 away from the base substrate 1.

[0196] Reference Fig.17A and Fig. 17B , the first sub-pixel 11 (12) and the second sub-pixel 13 share a reset signal line 62. That is, the reset signal line 62 is only provided in the occupied area of ​​the first sub-pixel driving circuit DR1 of the first sub-pixel 11 (12), and the reset signal line 62 is not provided in the occupied area of ​​the second sub-pixel driving circuit DR2 of the second sub-pixel 13. That is, in the occupied area of ​​the first sub-pixel driving circuit DR1 of the first sub-pixel 11 (12), the scanning signal line 61, the reset signal line 62 and the light emission control line 63 are provided; in the occupied area of ​​the second sub-pixel driving circuit DR2 of the second sub-pixel 13, the scanning signal line 61 and the light emission control line 63 are provided.

[0197] Combined with reference Figure 6B and Fig. 17B In the first sub-pixel 11 (12), the portion where the scanning signal line 61 overlaps with the semiconductor layer 20 forms the gate G2 of the first compensation transistor T2 and the gate G4 of the first switch transistor T4, respectively, and the other portion where the scanning signal line 61 overlaps with the semiconductor layer 20 also forms the gate G7 of the first initialization transistor T7. That is, in the embodiment of the present disclosure, in the first display area AA1, the gates of the first initialization transistor T7, the first compensation transistor T2, and the first switch transistor T4 are all supplied with the scanning signal Sn.

[0198] As described above, under the control of the first initialization transistor T7, the initialization voltage Vint transmitted by the initialization voltage line 66 can be supplied to the OLED, for example, to the first electrode (eg, anode) of the OLED, to initialize the voltage on the first electrode of the OLED.

[0199] In the second sub-pixel 13, the portion where the scanning signal line 61 overlaps with the semiconductor layer 20 forms the gate G2 of the second compensation transistor T2 and the gate G4 of the second switch transistor T4, respectively, and the other portion where the scanning signal line 61 overlaps with the semiconductor layer 20 also forms the gate G7 of the second initialization transistor T7. That is, in the embodiment of the present disclosure, in the first display area AA1, the gates of the second initialization transistor T7, the second compensation transistor T2, and the second switch transistor T4 are all supplied with the scanning signal Sn.

[0200] Continue to refer to Fig.17AIn a sub-pixel, a reset signal line 62 includes a first portion 621, a second portion 622 and a third portion 623 located in the first display area AA1, and the orthographic projections of the first portion 621, the second portion 622 and the third portion 623 on the base substrate 1 coincide with the orthographic projections of the common channel portion 2010a, the first channel portion 2011a and the second channel portion 2012a on the base substrate 1, respectively. The gate of the common transistor T10 includes the first portion 621, the gate of the first sub-transistor T11 includes the second portion 622, and the gate of the second sub-transistor T12 includes the third portion 623.

[0201] For example, the first portion 621 of the reset signal line 62 may extend substantially along the second direction Y, and the second portion 622 and the third portion 623 of the reset signal line 62 may extend substantially along the first direction X, i.e., the first portion 621 of the reset signal line 62 is substantially perpendicular to the second portion 622 and the third portion 623 of the reset signal line 62.

[0202] In this way, the gate of each of the common transistor T10 , the first sub-transistor T11 , and the second sub-transistor T12 is connected to the reset control signal RESET.

[0203] Thus, in the embodiment of the present disclosure, the orthographic projection of each of the first reset transistor T1 (including the common transistor T10 and the first sub-transistor T11) of the first sub-pixel driving circuit DR1 and the second reset transistor T1' (including the common transistor T10 and the second sub-transistor T12) of the second sub-pixel driving circuit DR2 on the base substrate 1 falls within the orthographic projection of the occupied area of ​​the first sub-pixel driving circuit DR1 on the base substrate 1. In this way, the area of ​​the occupied area of ​​the second sub-pixel driving circuit DR2 of the second sub-pixel can be reduced.

[0204] It should be noted that, here, the orthographic projection of the first reset transistor T1 of the first sub-pixel driving circuit DR1 on the substrate 1 can be represented by the orthographic projection of the channel region of the first reset transistor T1 of the first sub-pixel driving circuit DR1 on the substrate 1; the orthographic projection of the second reset transistor T1' of the second sub-pixel driving circuit DR2 on the substrate 1 can be represented by the orthographic projection of the channel region of the second reset transistor T1' of the second sub-pixel driving circuit DR2 on the substrate 1.

[0205] like Fig.18A and Fig.18BAs shown, the initialization voltage line 66 and the second storage capacitor electrode Cst2 are located in the second conductive layer 22. The second conductive layer 22 is located on a side of the first conductive layer 21 away from the base substrate 1.

[0206] Reference Fig.18A and Fig.18B , the first sub-pixel 11 (12) and the second sub-pixel 13 share one initialization voltage line 66. That is, the initialization voltage line 66 is only provided in the occupied area of ​​the first sub-pixel driving circuit DR1 of the first sub-pixel 11 (12), and the initialization voltage line 66 is not provided in the occupied area of ​​the second sub-pixel driving circuit DR2 of the second sub-pixel 13.

[0207] Reference Fig.10 For a sub-pixel located in the second display area AA2, the second storage capacitor electrode Cst2 includes a through hole TH2, and the combination of the solid part of the second storage capacitor electrode Cst2 and the through hole TH2 is projected on the base substrate 1 in a rectangular or rounded rectangular shape.

[0208] Reference Fig.18A and Fig.18B For a sub-pixel located in the first display area AA1, the second storage capacitor electrode Cst2 has a notch NTH1 at a corner, that is, the orthographic projection of the second storage capacitor electrode Cst2 on the base substrate 1 is in an "L" shape. In other words, the orthographic projection of the combination of the solid part of the second storage capacitor electrode Cst2 and the notch NTH1 on the base substrate 1 is in the shape of a rectangle or a rounded rectangle.

[0209] The notch NTH1 exposes a portion of the first storage capacitor electrode Cst1 under the second storage capacitor electrode Cst2 so that the first storage capacitor electrode Cst1 is electrically connected to the other portion.

[0210] In the embodiment of the present disclosure, the area of ​​the orthographic projection of the second storage capacitor electrode Cst2 of a sub-pixel located in the first display area AA1 on the base substrate 1 is smaller than the area of ​​the orthographic projection of the second storage capacitor electrode Cst2 of a sub-pixel located in the second display area AA2 on the base substrate 1. On this basis, the second storage capacitor electrode Cst2 of a sub-pixel located in the first display area AA1 is designed to be "L"-shaped, and there is no need to form the through hole in the second storage capacitor electrode Cst2, which is conducive to ensuring that the overlapping area of ​​the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 of a sub-pixel located in the first display area AA1 is large, that is, ensuring that the capacitance value of the storage capacitor Cst is large.

[0211] like Fig.19A and Fig.19BAs shown, the connection parts 168, 169, 170 and 171 are located in the third conductive layer 23. The third conductive layer 23 is located on a side of the second conductive layer 22 away from the substrate 1.

[0212] A portion of the connection portion 168 is formed in the via hole VH6, and the portion extends downward to be electrically connected to the portion of the first storage capacitor electrode Cst1 exposed by the notch NTH1. Another portion of the connection portion 168 is formed in the via hole VH2, and the portion extends downward to be electrically connected to the drain electrode D2 of the first compensation transistor T2 and the drain electrode D1 of the first reset transistor T1. The connection portion 168 can electrically connect the first storage capacitor electrode Cst1, the drain electrode D2 of the first compensation transistor T2, and the drain electrode D1 of the first reset transistor T1, that is, form Figure 6B Node N1 shown in .

[0213] The connection portion 169 includes a first connection sub-portion 1691 and a second connection sub-portion 1692. The first connection sub-portion 1691 and the second connection sub-portion 1692 are connected to each other to form a continuously extending connection portion 169. A portion of the first connection sub-portion 1691 is formed in the via hole VH12, and the portion extends downward to be electrically connected to the initialization voltage line 66. Another portion of the first connection sub-portion 1691 is formed in the via hole VH124, and the portion extends downward to be electrically connected to one of the common source portion 2030a and the common drain portion 2050a of the common transistor T10. In this way, the initialization voltage line 66 is electrically connected to the source or drain of the common transistor T10, and the initialization voltage Vint transmitted by the initialization voltage line 66 can be supplied to the source or drain of the first reset transistor T1 of the first sub-pixel driving circuit DR1 and the source or drain of the second reset transistor T1' of the second sub-pixel driving circuit DR2.

[0214] Another portion of the second connection sub-portion 1692 is formed in the via hole VH4 and extends downward to be electrically connected to the drain D7 of the first initialization transistor T7. In this way, the initialization voltage Vint transmitted by the initialization voltage line 66 can be supplied to the drain D7 of the first initialization transistor T7.

[0215] A portion of the connection portion 170 is formed in the via hole VH5, and the portion extends downward to be electrically connected to the source S7 of the first initialization transistor T7. Another portion of the connection portion 170 is formed in the via hole VH10, and the portion extends downward to be electrically connected to the drain D6 of the first light emission control transistor T6. Through the connection portion 170, the source S7 of the first initialization transistor T7 and the drain D6 of the first light emission control transistor T6 can be electrically connected, that is, forming Figure 6B The N4 node shown in .

[0216] A portion of the connection portion 171 is formed in the via hole VH7, and the portion extends downward to be electrically connected to the second storage capacitor electrode Cst2. Another portion of the connection portion 171 is formed in the via hole VH9, and the portion extends downward to be electrically connected to the source electrode S5 of the first operation control transistor T5. Through the connection portion 171, the second storage capacitor electrode Cst2 can be electrically connected to the source electrode S5 of the first operation control transistor T5.

[0217] Continue to refer to Fig.19A and Fig.19B In the region where the second sub-pixel 13 is located, the connecting portion 168 ′, the connecting portion 170 ′ and the connecting portion 171 ′ are located in the third conductive layer 23 .

[0218] A portion of the connection portion 168' is formed in the via hole VH6', and the portion extends downward to be electrically connected to the portion of the first storage capacitor electrode Cst1 exposed by the notch NTH1. Another portion of the connection portion 168' is formed in the via hole VH2', and the portion extends downward to be electrically connected to the drain electrode D2 of the second compensation transistor T2. Through the connection portion 168', the first storage capacitor electrode Cst1 and the drain electrode D2 of the second compensation transistor T2 can be electrically connected.

[0219] A portion of the connection portion 170' is formed in the via hole VH5', and the portion extends downward to be electrically connected to the source S7 of the second initialization transistor T7. Another portion of the connection portion 170' is formed in the via hole VH10', and the portion extends downward to be electrically connected to the drain D6 of the second light emission control transistor T6. Through the connection portion 170', the source S7 of the second initialization transistor T7 and the drain D6 of the second light emission control transistor T6 can be electrically connected.

[0220] A portion of the connection portion 171' is formed in the via hole VH7', and the portion extends downward to be electrically connected to the second storage capacitor electrode Cst2. Another portion of the connection portion 171' is formed in the via hole VH9', and the portion extends downward to be electrically connected to the source electrode S5 of the second operation control transistor T5. Through the connection portion 171', the second storage capacitor electrode Cst2 can be electrically connected to the source electrode S5 of the second operation control transistor T5.

[0221] Combined with reference Fig. 20A and Fig. 20B In the first display area AA1, a first transparent conductive layer 26 is disposed. For example, the first transparent conductive layer 26 may be made of a transparent conductive material such as indium tin oxide (ie, ITO).

[0222] In the first display area AA1, the data signal line 164 and the driving voltage line 165 are located in the first transparent conductive layer 26. That is, the data signal line 164 and the driving voltage line 165 are made of a transparent conductive material such as indium tin oxide (ie, ITO).

[0223] The display substrate may further include a plurality of transparent conductive connection parts in the first transparent conductive layer 26. For example, the plurality of transparent conductive connection parts may include a first transparent conductive connection part 161, a second transparent conductive connection part 162, a third transparent conductive connection part 163, and a fourth transparent conductive connection part 166. That is, these transparent conductive connection parts are all made of a transparent conductive material such as indium tin oxide (i.e., ITO).

[0224] The display substrate may further include a plurality of conductive leads in the first transparent conductive layer 26. For example, the plurality of conductive leads may include a third conductive lead 263 and a fourth conductive lead 266. That is, these conductive leads are all made of a transparent conductive material such as indium tin oxide (ie, ITO).

[0225] It should be noted that, in this article, the component used to electrically connect the elements in the pixel driving circuit of multiple sub-pixels in a sub-pixel group is called a conductive connection part, and the component used to electrically connect the elements in the pixel driving circuit of multiple sub-pixels respectively located in different sub-pixel groups (for example, adjacent sub-pixel groups) is called a conductive lead. Such expression is only for the purpose of convenience of description, and is not intended to specifically limit these components to be different. For example, some features of these components may be the same, for example, at least some of these components may be located in the same conductive layer, for example, all located in the first transparent conductive layer 26, or, at least some of these components may be composed of the same conductive material, for example, all composed of transparent conductive materials such as indium tin oxide (i.e., ITO).

[0226] For example, the data line 164 may extend substantially continuously along the second direction Y. A portion of the data signal line 164 is formed in the via hole VH3 and extends downward to be electrically connected to the source S4 of the first switch transistor T4 , thereby supplying the data signal Dm transmitted by the data signal line 164 to the first switch transistor T4 .

[0227] The driving voltage line 165 is disconnected at the pixel driving circuit of the sub-pixel in the first display area AA1 and is divided into two parts. For the convenience of description, the two parts are respectively represented as a first driving voltage sub-line 1651 and a second driving voltage sub-line 1652.

[0228] For example, the positive projection of the first driving voltage sub-line 1651 on the substrate substrate 1 intersects with the positive projection of the initialization voltage line 66 on the substrate substrate 1, and the positive projection of the first driving voltage sub-line 1651 on the substrate substrate 1 at least partially overlaps with the positive projection of the reset signal line 62 on the substrate substrate 1.

[0229] For another example, the positive projection of the second driving voltage sub-line 1652 on the substrate substrate 1 intersects with the positive projection of the light emitting control line 63 on the substrate substrate 1, and the positive projection of the second driving voltage sub-line 1652 on the substrate substrate 1 at least partially overlaps with the positive projection of the second storage capacitor electrode Cst2 on the substrate substrate 1. A portion of the second driving voltage sub-line 1652 is formed in the via hole VH20, and the portion extends downward to be electrically connected to a portion of the connecting portion 171, thereby being electrically connected to the second storage capacitor electrode Cst2. In this way, the electrical connection between the driving voltage line, the second storage capacitor electrode Cst2 and the source S5 of the first operation control transistor T5 can be achieved.

[0230] The first driving voltage sub-line 1651 and the second driving voltage sub-line 1652 are spaced apart from each other by a certain distance in the second direction Y. For example, the orthographic projection of one end of the first driving voltage sub-line 1651 close to the second driving voltage sub-line 1652 on the substrate substrate 1 partially overlaps with the orthographic projection of the reset signal line 62 on the substrate substrate 1, and the orthographic projection of one end of the second driving voltage sub-line 1652 close to the first driving voltage sub-line 1651 on the substrate substrate 1 partially overlaps with the orthographic projection of the part of the second storage capacitor electrode Cst2 close to the light emitting control line 63 on the substrate substrate 1. The spaced apart first driving voltage sub-line 1651 and second driving voltage sub-line 1652 are electrically connected together through the connecting portion, which will be described in detail below.

[0231] In an embodiment of the present disclosure, a first transparent conductive connection portion 161 is provided between the first sub-pixel and the second sub-pixel for electrically connecting the second reset transistor T1' (including the common transistor T10 and the second sub-transistor T12) located in the occupied area of ​​the first sub-pixel to the second sub-pixel driving circuit DR2.

[0232] Reference Fig. 20A and Fig. 20B, one end of the first transparent conductive connection portion 161 is electrically connected to one of the second sub-source portion 2032a and the second sub-drain portion 2052a through the via hole VH21, and the other end of the first transparent conductive connection portion 161 is electrically connected to the gate of the second driving transistor T3 of the second sub-pixel driving circuit DR2 through the via hole VH22. In this way, the second reset transistor T1' (including the common transistor T10 and the second sub-transistor T12) located in the occupied area of ​​the first sub-pixel can be electrically connected to the second sub-pixel driving circuit DR2.

[0233] For example, the orthographic projection of the first transparent conductive connection portion 161 on the base substrate 1 partially overlaps with the orthographic projection of the active layer 20g of the first initialization transistor T7 on the base substrate 1, and the orthographic projection of the first transparent conductive connection portion 161 on the base substrate 1 partially overlaps with the orthographic projection of the active layer 20g of the second initialization transistor T7 on the base substrate 1.

[0234] For example, the first transparent conductive connection portion 161 at least includes a first portion 1611, a second portion 1612, and a third portion 1613. The second portion 1612 is located between the first portion 1611 and the third portion 1613, connecting the first portion 1611 and the third portion 1613. That is, the first transparent conductive connection portion 161 is a continuously extending connection portion. The third portion 1613 of the first transparent conductive connection portion extends along the first direction X, the second portion 1612 of the first transparent conductive connection portion extends along the second direction Y, and the first portion 1611 of the first transparent conductive connection portion extends along an inclined direction that is inclined relative to both the first direction X and the second direction Y.

[0235] The orthographic projection of the first portion 1611 of the first transparent conductive connection portion on the substrate 1 partially overlaps with the orthographic projection of the active layer 20g of the first initialization transistor T7 on the substrate 1. The orthographic projection of the third portion 1613 of the first transparent conductive connection portion on the substrate 1 partially overlaps with the orthographic projection of the active layer 20g of the second initialization transistor T7 on the substrate 1. The second portion 1612 of the first transparent conductive connection portion is located in the light-transmitting region between the first sub-pixel and the second sub-pixel. For example, a portion of the first portion 1611 of the first transparent conductive connection portion and a portion of the third portion 1613 of the first transparent conductive connection portion are also located in the light-transmitting region between the first sub-pixel and the second sub-pixel.

[0236] In an embodiment of the present disclosure, a second transparent conductive connection portion 162 is provided between the first sub-pixel and the second sub-pixel for electrically connecting the reset signal line 66 located in the occupied area of ​​the first sub-pixel to the second sub-pixel driving circuit DR2, thereby connecting the reset signal RESET to the second sub-pixel driving circuit DR2.

[0237] In some exemplary embodiments of the present disclosure, the resistance of the first transparent conductive connection portion 161 may be reduced. For example, the line width of the first transparent conductive connection portion 161 may be increased, for example, the line width of the first transparent conductive connection portion 161 may be greater than the line width of each of the conductive connection portions 162, 163, and 166. For example, the extension length of the first transparent conductive connection portion 161 may be shortened. For example, the first transparent conductive connection portion may be formed by connecting conductive portions in two conductive layers in parallel, for example, the first portion of the first transparent conductive connection portion may be located in the first transparent conductive layer, the second portion may be located in the third conductive layer, the fourth conductive layer, or the second transparent conductive layer, and the first portion and the second portion are connected in parallel to form the first transparent conductive connection portion.

[0238] In some exemplary embodiments of the present disclosure, among the transparent conductive connection parts 161, 162, 163 and 166, the first transparent conductive connection part 161 may be arranged at the side of the most edge. That is, the arrangement order of the transparent conductive connection parts 161, 162, 163 and 166 is not limited to Figure 20A to Figure 20B For example, the first transparent conductive connection part 161 can be arranged on a side of the second conductive connection part 162 away from the third conductive connection part 163. In this way, the influence of other electronic components or electrical environment on the first transparent conductive connection part 161 can be minimized, so that the stability of the reset signal transmitted by the first transparent conductive connection part 161 can be ensured.

[0239] In some exemplary embodiments of the present disclosure, in combination with reference Figure 6C and Fig. 20B By adjusting the resistance of the path where the reset signal is transmitted to the gates of the driving transistors T3 of the two sub-pixels, the resistance of the reset signal transmission path can be made substantially consistent, or in other words, the resistance of the reset signal transmission path of different sub-pixels can be made adjustable. For example, Figure 6C The resistors R1 and R3 in the figure schematically represent the resistance on the path of the reset signal being transmitted to the gate of the driving transistor T3 of the first sub-pixel, and the resistors R2 and R4 schematically represent the resistance on the path of the reset signal being transmitted to the gate of the driving transistor T3 of the second sub-pixel.

[0240] For example, as described above, the line width of the first transparent conductive connection portion 161 can be increased, the extension length of the first transparent conductive connection portion 161 can be shortened, or conductive portions located in two conductive layers (such as the first transparent conductive layer and the second transparent conductive layer) can be connected in parallel to form the first transparent conductive connection portion to adjust the resistance on the path where the reset signal is transmitted to the gate of the driving transistor T3 of the second sub-pixel, so that the resistance on the path where the reset signal is transmitted to the gate of the driving transistor T3 of the two sub-pixels is basically consistent.

[0241] Continue to refer to Figure 6C and Fig. 20B , the coupling capacitor acting on the node N1 can be adjusted to adjust the potential at the node N1 of different sub-pixels, so that the potential at the node N1 of different sub-pixels remains stable, that is, basically consistent. For example, Figure 6C Cst1 -ref1 in the figure schematically shows the coupling capacitance acting on the node N1 of the first sub-pixel driving circuit DR1 , and Cst1 -ref2 schematically shows the coupling capacitance acting on the node N1 of the second sub-pixel driving circuit DR2 .

[0242] For example, the first transparent conductive connection portion 161 (i.e., the wire for transmitting the reset signal to the gate of the driving transistor of the second sub-pixel driving circuit) can be moved to the vicinity of the driving voltage line (e.g., the first driving voltage sub-line 1651), that is, the positions of the transparent conductive connection portions 161, 162, and 163 can be exchanged; or, the first transparent conductive connection portion 161 can overlap with the film layer having the VDD potential; or, a portion of the initialization signal line 66 is extended downward so that it overlaps with the first transparent conductive connection portion 161. That is, in some exemplary embodiments, the first transparent conductive connection portion 161 can be arranged to overlap with the conductive portion or film layer having a constant potential to form a coupling capacitor acting on the node N1. For another example, the overlapping areas in the two sub-pixels (e.g., the first sub-pixel and the second sub-pixel) sharing the reset transistor can be made different, so as to realize the differentiated design of different sub-pixels, so as to adjust the electrical environment of the conductive parts at each location of the node N1. In this way, the potential at the node N1 in the pixel driving circuit of different sub-pixels can be kept consistent, which is conducive to improving the uniformity of the display substrate.

[0243] It should be noted that although the resistors R1 to R4 and the coupling capacitors Cst1-ref1 and Cst1-ref2 are simultaneously arranged at Figure 6CHowever, the embodiments of the present disclosure are not limited thereto. For example, in some embodiments, only the resistors R1 to R4 may be set to adjust the resistance on the path of the reset signal transmitted to the gate of the driving transistor T3 of the two sub-pixels. In some embodiments, only the coupling capacitor acting on the node N1 may be set to adjust the potential at the node N1 of different sub-pixels.

[0244] Reference Fig. 20A and Fig. 20B , one end of the second transparent conductive connection portion 162 is electrically connected to the connection portion 169 through the via hole VH23, and the other end of the second transparent conductive connection portion 162 is electrically connected to one end of the active layer 20g of the second initialization transistor T7 of the second sub-pixel driving circuit DR2 through the via hole VH24. For example, the orthographic projection of the via hole VH23 on the base substrate 1 at least partially overlaps with the orthographic projection of the via hole VH4 on the base substrate 1. That is, one end of the second transparent conductive connection portion 162 is electrically connected to one end of the connection portion 169 through the via hole VH23 ( Fig. 20B The other end of the second transparent conductive connection portion 162 is electrically connected to the seventh source region 203g or the seventh drain region 205g of the second initialization transistor T7 through the via hole VH24. In this way, the reset signal RESET transmitted by the reset signal line 66 can be supplied to the source or drain of the second initialization transistor T7 of the second sub-pixel driving circuit DR2.

[0245] For example, the second transparent conductive connection portion 162 at least includes a first portion 1621, a second portion 1622, and a third portion 1623, wherein the second portion 1622 is located between the first portion 1621 and the third portion 1623. The first portion 1621 of the second transparent conductive connection portion extends along a first direction X, the third portion 1623 of the second transparent conductive connection portion extends along a second direction Y, and the second portion 1622 of the second transparent conductive connection portion extends along an inclined direction that is inclined relative to both the first direction X and the second direction Y.

[0246] The second transparent conductive connection portion 162 may be located in the light-transmitting region between the first sub-pixel and the second sub-pixel. For example, the first portion 1621, the second portion 1622 and the third portion 1623 of the second transparent conductive connection portion 162 are all located in the light-transmitting region between the first sub-pixel and the second sub-pixel.

[0247] like Fig.21A and Fig. 21B As shown, the connection portion 172 and the conductive connection portion 173 are located in the fourth conductive layer 24 .

[0248] A portion of the connection portion 172 is formed in the via hole VH1, and the portion extends downward to be electrically connected to the first drive voltage sub-line 1651. Another portion of the connection portion 172 is formed in the via hole VH7", and the portion extends downward to be electrically connected to the second drive voltage sub-line 1652. That is, through the connection portion 172, the first drive voltage sub-line 1651 and the second drive voltage sub-line 1652 can be electrically connected, so that the drive voltage lines of each sub-pixel located in the same column can be connected, so as to supply the drive voltage signal VDD to each sub-pixel.

[0249] In some embodiments of the present disclosure, the first driving voltage sub-line 1651 and the second driving voltage sub-line 1652 may be connected at the pixel driving circuit, so that the connecting portion 172 may not be required.

[0250] In some embodiments of the present disclosure, the first driving voltage sub-line 1651 and the second driving voltage sub-line 1652 can be disconnected at the pixel driving circuit, and a connecting portion 172 can be provided. In this way, the connecting portion 172 is connected in parallel with a portion of the driving voltage line 165, which is beneficial to reducing the resistance on the driving voltage line 165.

[0251] A portion of the conductive connection portion 173 is formed in the via hole VH10 ′, and the via hole VH10 ′ exposes a portion of the connection portion 170 , so that the conductive connection portion 173 can be electrically connected to the connection portion 170 .

[0252] like Fig.22A and Fig. 22B As shown, in the first display area AA1, a second transparent conductive layer 28 is provided, for example, the second transparent conductive layer 28 can be made of a transparent conductive material such as indium tin oxide (i.e., ITO). The second transparent conductive layer 28 is located on the side of the fourth conductive layer 24 away from the base substrate 1. The display substrate also includes a first conductive lead 181 and a second conductive lead 182 provided on the base substrate 1. The first conductive lead 181 and the second conductive lead 182 can be located in the second transparent conductive layer 28. That is, the first conductive lead 181 and the second conductive lead 182 are made of a transparent conductive material such as indium tin oxide (i.e., ITO).

[0253] like Fig.22A and Fig. 22B As shown, except for the reset transistors T1 and T1 ′, the other transistors T2 ˜ T7 in the first sub-pixel driving circuit DR1 and the second sub-pixel driving circuit DR2 may be arranged in a mirror image.

[0254] Fig.25A and Fig.25B1 is a plan view showing an exemplary embodiment of a plurality of sub-pixel groups in a first display area AA1 of a display substrate according to some exemplary embodiments of the present disclosure. Fig. 20A , Fig. 20B , Fig.22A , Fig. 22B and Fig.25A and Fig.25B In the first display area AA1, the scanning signal line 61, the reset signal line 62, the light emitting control line 63 and the initialization voltage line 66 extending along the first direction X are electrically connected through the conductive leads or the transparent conductive connecting parts in the transparent conductive layer. In this way, in the light-transmitting area of ​​the first display area AA1, only transparent conductive leads and transparent conductive connecting parts are arranged, and no conductive leads made of opaque materials such as metal are arranged. In this way, the light transmittance of the first display area AA1 can be ensured to be relatively high.

[0255] For example, within a sub-pixel group, the first scanning signal line 61 of the first sub-pixel 11 (12) and the second scanning signal line 61 of the second sub-pixel 13 are electrically connected through a third transparent conductive connection part 163, and the first light-emitting control line 63 of the first sub-pixel 11 (12) and the second light-emitting control line 63 of the second sub-pixel 13 are electrically connected through a fourth transparent conductive connection part 166.

[0256] For example, third conductive leads 263 are respectively provided on both sides of a sub-pixel group to electrically connect the scan signal lines 61 of each sub-pixel group in the same row. A portion of the third conductive lead 263 located on the left side is formed in the via hole VH15, and the portion extends downward to be electrically connected to one end of the first scan signal line 61. A portion of the third conductive lead 263 located on the right side is formed in the via hole VH15, and the portion extends downward to be electrically connected to one end of the second scan signal line 61. With the third transparent conductive connection portion 163 and the third conductive lead 263, the scan signal lines 61 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the scan signal Sn.

[0257] On both sides of a sub-pixel group, fourth conductive leads 266 are respectively provided to electrically connect the light emitting control lines 63 of each sub-pixel group in the same row. A portion of the fourth conductive lead 266 located on the left side is formed in the via hole VH17, and the portion extends downward to be electrically connected to one end of the first light emitting control line 63. A portion of the fourth conductive lead 266 located on the right side is formed in the via hole VH17, and the portion extends downward to be electrically connected to one end of the second light emitting control line 63. With the help of the fourth transparent conductive connection portion 166 and the fourth conductive lead 266, the light emitting control lines 63 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the light emitting control signal Em.

[0258] First conductive leads 181 are respectively provided on both sides of the reset signal line 62 of a sub-pixel group. A portion of one first conductive lead 181 is formed in the via hole VH13, and the portion extends downward to be electrically connected to one end of the reset signal line 62. A portion of another first conductive lead 181 is formed in the via hole VH14, and the portion extends downward to be electrically connected to the other end of the reset signal line 62. With the help of the first conductive leads 181, the reset signal lines 62 of the sub-pixel groups in the same row can be electrically connected to facilitate the supply of the reset signal Reset.

[0259] On both sides of the initialization voltage line 66 of a sub-pixel group, second conductive leads 182 are respectively provided. A portion of one second conductive lead 182 is formed in the via hole VH11, and the portion extends downward to be electrically connected to one end of the initialization voltage line 66. A portion of another second conductive lead 182 is formed in the via hole VH12, and the portion extends downward to be electrically connected to the other end of the initialization voltage line 66. With the help of the second conductive leads 182, the initialization voltage lines 66 of the sub-pixel groups in the same row can be electrically connected to facilitate the supply of the light-emitting initialization voltage signal Vinit.

[0260] In other words, combined with reference Fig.25A and Fig.25B , the plurality of sub-pixel groups at least include a first sub-pixel group SP1 and a second sub-pixel group SP2 that are located in the same row and are adjacent. One end of a first conductive lead 181 is electrically connected to the reset signal line 62 in the first sub-pixel group SP1 through a via hole VH13, and the other end of the first conductive lead 181 is electrically connected to the reset signal line 62 in the second sub-pixel group SP1 through a via hole VH14. One end of a second conductive lead 182 is electrically connected to the initialization voltage line 66 in the first sub-pixel group SP1 through a via hole VH11, and the other end of the second conductive lead 182 is electrically connected to the initialization voltage line 66 in the second sub-pixel group SP2 through a via hole VH12.

[0261] In an embodiment of the present disclosure, the orthographic projection of at least one of the first conductive lead 181 and the second conductive lead 182 on the substrate 1 intersects with the orthographic projection of at least one of the data line 164 and the driving voltage line 165 (the first driving voltage sub-line 1651 and / or the second driving voltage sub-line 1652) on the substrate 1.

[0262] like Fig.23A and Fig. 23B As shown, the first electrode (eg, anode) of the first light emitting device 41 may be located in the fifth conductive layer 25. As described above, the anode of the first light emitting device 41 includes an anode body 411 and an anode connection portion 412.

[0263] In the first sub-pixel 11 (12), a portion of the anode connection portion 412 may be formed in the via hole VH10", and the via hole VH10" exposes a portion of the conductive connection portion 173, so that the anode connection portion 412 may be electrically connected to the conductive connection portion 173, and then connected to the connection portion 170. That is, through the conductive connection portion 173 and the connection portion 170, the anode of the first light-emitting device 41 of the first sub-pixel, the source S7 of the first initialization transistor T7, and the drain D6 of the first light-emitting control transistor T6 may be electrically connected, that is, Figure 6B The N4 node shown in .

[0264] In the second sub-pixel 13, a portion of the anode connection portion 412 may be formed in the via hole VH10", and the via hole VH10" exposes a portion of the conductive connection portion 173, so that the anode connection portion 412 may be electrically connected to the conductive connection portion 173, and then connected to the connection portion 170. That is, through the conductive connection portion 173 and the connection portion 170, the anode of the first light-emitting device 41 of the second sub-pixel, the source S7 of the second initialization transistor T7, and the drain D6 of the second light-emitting control transistor T6 may be electrically connected, that is, forming Figure 6B The N4 node shown in .

[0265] Combined with reference Figure 4 , Fig.23A and Fig. 23B as well as Fig.25A and Fig.25B , in the first display area AA1, the pixel driving circuits of sub-pixels 11, 12, and 13 can be basically reduced to the size of the first light-emitting device 41, and placed under the light-emitting device 41. In this way, in the first display area AA1 (i.e., the camera area under the screen), the pixel driving circuit of each sub-pixel can be built into the corresponding sub-pixel, and there is no need to place it externally in the spacing area SR, which can avoid the various problems caused by the external placement of the above-mentioned pixel driving circuit. Moreover, in the embodiments of the present disclosure, the pixel driving circuit of each sub-pixel is built into the corresponding sub-pixel and hidden under the light-emitting device of the corresponding sub-pixel, which can ensure that the transmittance of the first display area is relatively large, that is, it is conducive to achieving high transmittance of the first display area. It can be combined with reference Figure 4 In the first display area AA1, there is a light-transmitting area TRA between each adjacent sub-pixel. Since the pixel driving circuit of each sub-pixel can be basically reduced to the size of the first light-emitting device 41 and placed under the light-emitting device 41, it is beneficial to achieve a larger area of ​​the light-transmitting area TRA, thereby ensuring a higher light transmittance of the first display area. Moreover, in the light-transmitting area TRA, only transparent conductive leads are provided, and no opaque leads exist, thereby further ensuring a higher light transmittance of the first display area.

[0266] Reference Figure 7 and Fig.13 In the second display area AA2, the area occupied by the pixel driving circuit of each sub-pixel 21, 22, and 23 is larger. For example, the area occupied by the pixel driving circuit of sub-pixel 23 (i.e., the green sub-pixel) is larger than the area occupied by the pixel driving circuit of sub-pixel 13 (i.e., the green sub-pixel).

[0267] In this article, the occupied area of ​​the pixel driving circuit of each sub-pixel 21, 22, 23 in the second display area AA2 can be represented by the following area: Fig. 12A and Fig. 12B For the pixel driving circuits of each sub-pixel 21, 22, and 23, in the first direction X, the data signal line 64 and the sixth active layer 20f of the first light-emitting control transistor T6 are respectively located at the leftmost and rightmost sides, that is, the distance between the two in the first direction X is the largest; in the second direction Y, the initialization voltage line 66 and the light-emitting control line 63 are respectively located at the uppermost and lowermost sides, that is, the distance between the two in the second direction Y is the largest. Thus, in the orthographic projection of the pixel driving circuit of a sub-pixel on the substrate, the data signal line 64 has a first side away from the sixth active layer 20f of the first light emitting control transistor T6, the sixth active layer 20f of the first light emitting control transistor T6 has a second side away from the data signal line 64, the initialization voltage line 66 has a third side away from the light emitting control line 63, and the light emitting control line 63 has a fourth side away from the initialization voltage line 66, wherein the first side and the second side extend along the second direction Y, and the third side and the fourth side extend along the first direction X, and the extension lines of the four sides will intersect to enclose and form an area, which is the occupied area of ​​the pixel driving circuit of a sub-pixel located in the second display area AA2, as shown in FIG. Fig. 12A The area AR22 surrounded by the dotted line box is shown in FIG.

[0268] In this article, the occupied area of ​​the pixel driving circuit of each sub-pixel 11, 12, 13 in the first display area AA1 can be represented by the following area: Fig.23A and Fig. 23B For the first sub-pixel 11 (12), vias VH11, VH12, VH13, VH14, VH15, VH16, VH17, VH18 and VH23 are respectively located at the outermost side of the pixel driving circuit, and vias VH9 and VH10" are located at the outermost side of the pixel driving circuit. The centers of every two adjacent vias among the 11 vias are connected in sequence to enclose a region, such as Fig. 23BThe area AR1 surrounded by the dotted box shown in FIG. 1 may be an occupied area of ​​a first sub-pixel driving circuit of a first sub-pixel located in the first display area AA1. For the second sub-pixel 13, vias VH24, VH16', VH18', VH9, VH10", VH17, VH15 and VH3 are respectively located at the outermost side of the pixel driving circuit, and the centers of every two adjacent vias of the eight vias are connected in sequence to form an area, such as Fig. 23B The area AR2 surrounded by the dotted line frame shown in FIG. 1 may be an occupied area of ​​a second sub-pixel driving circuit of a second sub-pixel located in the first display area AA1 .

[0269] In this document, unless otherwise specified, the occupied area of ​​the light-emitting device of the sub-pixel in the second display area AA2 can be represented by the coverage area of ​​the orthographic projection of the anode of the light-emitting device on the substrate. Similarly, the occupied area of ​​the light-emitting device of the sub-pixel in the first display area AA1 can be represented by the coverage area of ​​the orthographic projection of the anode of the light-emitting device on the substrate.

[0270] In the embodiment of the present disclosure, the PPI in the first display area AA1 is substantially equal to the PPI in the second display area. That is, within the same area, the number of the first repeating units P1 arranged in the first display area AA1 is substantially equal to the number of the second repeating units P2 arranged in the second display area AA2, or the number of the sub-pixels arranged in the first display area AA1 is substantially equal to the number of the sub-pixels of the same color arranged in the second display area AA2. In this way, both the first display area and the second display area have a higher PPI, can achieve a higher display quality, and have better display uniformity.

[0271] Herein, unless otherwise specified, the expressions “substantially equal”, “substantially equal to”, etc. may mean that the ratio of the two values ​​being compared is approximately equal to 1. For example, the ratio of the two values ​​being compared may be in the range of 0.8 to 1.2.

[0272] In some embodiments, the area occupied by the light-emitting device of each sub-pixel in the first display area AA1 is substantially equal to the area occupied by the light-emitting device of the sub-pixel of the same color in the second display area AA2. For example, the area of ​​the positive projection of the anode of the first light-emitting device 41 of the sub-pixel 11 on the substrate substrate 1 is substantially equal to the area of ​​the positive projection of the anode of the second light-emitting device 42 of the sub-pixel 21 on the substrate substrate 1; the area of ​​the positive projection of the anode of the first light-emitting device 41 of the sub-pixel 12 on the substrate substrate 1 is substantially equal to the area of ​​the positive projection of the anode of the second light-emitting device 42 of the sub-pixel 22 on the substrate substrate 1; the area of ​​the positive projection of the anode of the first light-emitting device 41 of the sub-pixel 13 on the substrate substrate 1 is substantially equal to the area of ​​the positive projection of the anode of the second light-emitting device 42 of the sub-pixel 23 on the substrate substrate 1. Through such a setting, it is conducive to achieving that the PPI in the first display area AA1 is substantially equal to the PPI in the second display area. In addition, the display uniformity between the first display area and the second display area can be better, and the life uniformity of the light-emitting material between the first display area and the second display area is also better.

[0273] It should be noted that the embodiments of the present disclosure are not limited to the above-mentioned embodiments. In other embodiments, the area occupied by the light-emitting devices of each sub-pixel in the first display area AA1 may not be equal to the area occupied by the light-emitting devices of the sub-pixels of the same color in the second display area AA2, as long as the PPI in the first display area AA1 is basically equal to the PPI in the second display area.

[0274] In the embodiment of the present disclosure, the area occupied by the pixel driving circuit of each sub-pixel 11, 12, 13 in the first display area AA1 is reduced, which is conducive to hiding the pixel driving circuit of each sub-pixel under the light-emitting device of the corresponding sub-pixel.

[0275] As mentioned above, refer to Fig. 17B For a first sub-pixel located in the first display area AA1, the active layer 20g of the first initialization transistor T7 extends in a direction close to the scanning signal line 61 of the sub-pixel relative to the active layer 20a of the first reset transistor T1, that is, the active layer 20g of the first initialization transistor T7 is located at the lower right of the active layer 20a of the first reset transistor T1. With such a setting, the outline of the occupied area of ​​the active layer of a first sub-pixel located in the first display area AA1 is a square or approximately a square. Fig.23A and Fig. 23B The positive projection of the anode body of the first sub-pixel 11 (12) and the first light-emitting device 41 on the substrate is a circle. This arrangement is conducive to achieving that the anode of each sub-pixel covers the pixel driving circuit of the sub-pixel.

[0276] Reference Fig. 23B The orthographic projection of the anode of the first light-emitting device 41 of the first sub-pixel 11 (12) on the substrate substrate 1 at least partially overlaps with the orthographic projection of the occupied area AR1 of the pixel driving circuit of the first sub-pixel 11 (12) on the substrate substrate 1. For example, the orthographic projection of the anode of the first light-emitting device 41 of the first sub-pixel 11 (12) on the substrate substrate 1 basically completely covers the orthographic projection of the occupied area AR1 of the pixel driving circuit of the first sub-pixel 11 (12) on the substrate substrate 1.

[0277] Herein, unless otherwise specifically stated, the expression "substantially completely covers" means covering more than 90% of the entire area of ​​a certain orthographic projection.

[0278] Reference Fig. 23B The orthographic projection of the anode of the first light-emitting device 41 of the second sub-pixel 13 on the substrate substrate 1 at least partially overlaps with the orthographic projection of the occupied area AR2 of the pixel driving circuit of the second sub-pixel 13 on the substrate substrate 1. For example, the orthographic projection of the anode of the first light-emitting device 41 of the second sub-pixel 13 on the substrate substrate 1 basically completely covers the orthographic projection of the occupied area AR2 of the pixel driving circuit of the second sub-pixel 13 on the substrate substrate 1.

[0279] In the embodiments of the present disclosure, the area of ​​the orthographic projection of the anode of the first light-emitting device 41 of sub-pixel 13 on the substrate substrate 1 is smaller than the area of ​​the orthographic projection of the anode of the first light-emitting device 41 of sub-pixel 11 on the substrate substrate 1, and the area of ​​the orthographic projection of the anode of the first light-emitting device 41 of sub-pixel 11 on the substrate substrate 1 is smaller than the area of ​​the orthographic projection of the anode of the first light-emitting device 41 of sub-pixel 12 on the substrate substrate 1.

[0280] In the embodiment of the present disclosure, the reset transistor in the pixel driving circuit of the second sub-pixel 13 is set to be at least partially shared with the reset transistor in the pixel driving circuit of the first sub-pixel 11 (12), which can reduce the number of transistors that need to be set in the occupied area AR2 of the pixel driving circuit of the second sub-pixel 13, thereby reducing the area of ​​the occupied area AR2 of the pixel driving circuit of the second sub-pixel 13. In this way, although the area of ​​the anode of the first light-emitting device 41 of the second sub-pixel 13 is small, it can still be ensured that the anode of the first light-emitting device 41 of the second sub-pixel 13 can basically cover the pixel driving circuit of the second sub-pixel 13, that is, the pixel driving circuit of the second sub-pixel 13 is hidden under the anode of its light-emitting device.

[0281] For example, in the first display area AA1, the positive projection of the anode of the first light-emitting device 41 of each sub-pixel on the base substrate 1 at least covers the positive projection of the storage capacitor Cst (including the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2) of the pixel driving circuit of the sub-pixel and multiple transistors on the base substrate 1.

[0282] Herein, unless otherwise specifically stated, the expression “an orthographic projection of a transistor on a substrate” includes a combination of an orthographic projection of an active layer, a gate, a source, and a drain of the transistor on the substrate.

[0283] For example, refer to Fig. 23B The positive projection of the anode of the first light-emitting device 41 of the second sub-pixel 13 on the substrate 1 covers the positive projection of the second compensation transistor T2, the second driving transistor T3, the second switching transistor T4, the second operation control transistor T5, the second light-emitting control transistor T6, the second initialization transistor T7 and the storage capacitor Cst of the pixel driving circuit of the second sub-pixel 13 on the substrate 1.

[0284] For example, refer to Fig. 23B , the positive projection of the anode of the first light-emitting device 41 of the first sub-pixel 11 (12) on the substrate substrate 1 covers the positive projection of the first reset transistor T1, the first compensation transistor T2, the first driving transistor T3, the first switch transistor T4, the first operation control transistor T5, the first light-emitting control transistor T6, the first initialization transistor T7 and the storage capacitor Cst of the pixel driving circuit of the first sub-pixel 11 (12) on the substrate substrate 1. In addition, the positive projection of the anode of the first light-emitting device 41 of the first sub-pixel 11 (12) on the substrate substrate 1 also covers the positive projection of the second reset transistor T1' of the pixel driving circuit of the second sub-pixel 13 on the substrate substrate 1.

[0285] In an embodiment of the present disclosure, through such a setting method, the pixel driving circuit of each sub-pixel can be set below the light-emitting device (such as the anode), so that the pixel driving circuit will not occupy the light-transmitting area between the sub-pixels, which is beneficial for the first display area to have a high transmittance. At the same time, a high PPI can be achieved in the first display area, which is conducive to achieving high display quality in the under-screen camera area.

[0286] Fig.26A , Fig.26B and Fig.26C They are shown respectively Fig.15 A plan view of a combination of a blocking layer, a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first transparent conductive layer, a fourth conductive layer, a second transparent conductive layer and a fifth conductive layer of an exemplary embodiment of three sub-pixels included in one repeating unit. Fig. 27FIG. 2 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Fig.26A Schematic diagram of the cross-sectional structure taken along line FF'.

[0287] Reference FIG. 26A to FIG. 27 In an embodiment of the present disclosure, the display substrate may further include a shielding layer LS. The shielding layer LS may be disposed between the base substrate 1 and the semiconductor layer 20 to protect the semiconductor layer 20 to prevent the active layer of each transistor of the pixel driving circuit of each sub-pixel from being affected by external light.

[0288] For example, the shielding layer LS may be made of a light-proof metal material. The shielding layer LS may also include a semiconductor film layer such as amorphous silicon, polycrystalline silicon, etc.

[0289] The orthographic projection of the shielding layer LS of each sub-pixel on the base substrate 1 can cover the orthographic projection of the occupied area AR1 or AR2 of the pixel driving circuit of the sub-pixel on the base substrate 1. With such a setting, the pixel driving circuit of each sub-pixel can be prevented from being affected by external light.

[0290] For example, the shielding layer LS may be connected to a fixed voltage to prevent it from being in a suspended state (ie, floating).

[0291] In some embodiments, the shielding layer LS may be in a planar or grid shape. The orthographic projection of the shielding layer LS on the base substrate 1 may at least partially overlap with the orthographic projection of the structure or part in the first transparent conductive layer and / or the second transparent conductive layer on the base substrate 1 .

[0292] Return to reference Figure 4 The first light emitting device 41 may include an anode, a light emitting material layer and a cathode which are stacked. The display substrate may include a sixth conductive layer, and the cathode CAT is located in the sixth conductive layer.

[0293] In some embodiments, in the first display area AA1, the sixth conductive layer may be patterned. That is, the sixth conductive layer may include a plurality of cathodes CAT and a plurality of cathode openings 271. The cathode openings 271 may be located between adjacent cathodes CAT.

[0294] For example, in the first display area AA1, the positive projection of the cathode CAT of the first light emitting device 41 of each sub-pixel on the base substrate 1 may cover the positive projection of the anode of the first light emitting device 41 of the sub-pixel on the base substrate 1. The positive projection of each cathode opening 271 on the base substrate 1 may overlap with the positive projection of the light-transmitting area TRA between each sub-pixel on the base substrate 1. With such a setting, it is possible to ensure that the light transmittance of the light-transmitting area in the first display area AA1 is high.

[0295] At least some embodiments of the present disclosure also provide a display panel, wherein the display panel includes the display substrate as described above. For example, the display panel may be an OLED display panel.

[0296] Reference Figure 1 At least some embodiments of the present disclosure further provide a display device. The display device may include the display substrate described above.

[0297] The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0298] It should be understood that the display panel and the display device according to the embodiments of the present disclosure have all the characteristics and advantages of the above-mentioned display substrate. For details, please refer to the above description, which will not be repeated here.

[0299] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will appreciate that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, comprising a first display area and a second display area, wherein the light transmittance of the first display area is greater than the light transmittance of the second display area, wherein: The display substrate comprises: substrate substrate; a plurality of sub-pixels disposed on the base substrate and located in the first display area, the sub-pixels comprising a first pixel driving circuit and a first light-emitting device, the first pixel driving circuit being electrically connected to the first light-emitting device for driving the first light-emitting device to emit light; and A plurality of sub-pixels are disposed on the base substrate and located in the second display area, wherein the sub-pixels located in the second display area include a second pixel driving circuit and a second light-emitting device, wherein the second pixel driving circuit is electrically connected to the second light-emitting device and is used to drive the second light-emitting device to emit light, Wherein, the plurality of sub-pixels located in the first display area include a plurality of sub-pixel groups, each sub-pixel group includes a first sub-pixel and a second sub-pixel, the first pixel driving circuit includes a first sub-pixel driving circuit and a second sub-pixel driving circuit, the first sub-pixel driving circuit is used to drive a first light-emitting device of the first sub-pixel to emit light, and the second sub-pixel driving circuit is used to drive a first light-emitting device of the second sub-pixel to emit light, the first sub-pixel driving circuit includes at least a first reset transistor, the second sub-pixel driving circuit includes at least a second reset transistor, the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit are at least partially shared; the first reset transistor includes a common transistor and a first sub-transistor, and the second reset transistor includes the common transistor and a second sub-transistor; The display substrate further comprises a semiconductor layer disposed on the base substrate and a first conductive layer located on a side of the semiconductor layer away from the base substrate, the display substrate further comprises a reset signal line disposed on the base substrate, the reset signal line is used to transmit a reset control signal, and the reset signal line is located in the first conductive layer; and The reset signal line includes a first portion, a second portion and a third portion located in the first display area, the semiconductor layer includes a common channel portion, a first channel portion and a second channel portion located in the first display area, the orthographic projections of the first portion, the second portion and the third portion on the substrate respectively coincide with the orthographic projections of the common channel portion, the first channel portion and the second channel portion on the substrate, the gate of the common transistor includes the first portion, the gate of the first sub-transistor includes the second portion, and the gate of the second sub-transistor includes the third portion.

2. The display substrate according to claim 1, characterized in that: The orthographic projection of each of the first reset transistor of the first sub-pixel driving circuit and the second reset transistor of the second sub-pixel driving circuit on the substrate falls within the orthographic projection of the occupied area of ​​the first sub-pixel driving circuit on the substrate.

3. The display substrate according to claim 1 or 2, characterized in that: Each of the common transistor, the first sub-transistor and the second sub-transistor includes a gate, a source and a drain. The gate of each of the common transistor, the first sub-transistor and the second sub-transistor is connected to a reset control signal, one of the source or the drain of the common transistor is connected to an initialization voltage signal, and the other of the source or the drain of the common transistor is electrically connected to the first sub-transistor and the second sub-transistor respectively.

4. The display substrate according to claim 1, characterized in that: The common transistor includes a common source portion and a common drain portion located in the semiconductor layer, the first sub-transistor includes a first sub-source portion and a first sub-drain portion located in the semiconductor layer, and the second sub-transistor includes a second sub-source portion and a second sub-drain portion located in the semiconductor layer; as well as The common source portion and the common drain portion are respectively located on both sides of the common channel portion, the first sub-source portion and the first sub-drain portion are respectively located on both sides of the first channel portion, and the second sub-source portion and the second sub-drain portion are respectively located on both sides of the second channel portion.

5. The display substrate according to claim 4, characterized in that: The display substrate further comprises an initialization voltage line disposed on the base substrate and a first connection portion disposed on the base substrate; One of the common source portion and the common drain portion is electrically connected to the initialization voltage line through a first via hole, and the other of the common source portion and the common drain portion is continuously extended with one of the first sub-source portion and the first sub-drain portion; as well as The other of the first sub-source portion and the first sub-drain portion is electrically connected to one end of the first connection portion through a second via hole.

6. The display substrate according to claim 5, characterized in that: The first sub-pixel driving circuit further includes a first driving transistor, the first driving transistor includes a gate, and the other end of the first connecting portion is electrically connected to the gate of the first driving transistor through a third via hole.

7. The display substrate according to claim 5 or 6, characterized in that: The display substrate further comprises a first transparent conductive connection portion disposed on the base substrate; the other of the common source portion and the common drain portion also extends continuously with one of the second sub-source portion and the second sub-drain portion; as well as The other of the second sub-source portion and the second sub-drain portion is electrically connected to one end of the first transparent conductive connection portion through a third via hole.

8. The display substrate according to claim 7, characterized in that: The second sub-pixel driving circuit further includes a second driving transistor, the second driving transistor includes a gate, and the other end of the first transparent conductive connection portion is electrically connected to the gate of the second driving transistor through a fourth via hole.

9. The display substrate according to claim 7, characterized in that: The initialization voltage line is located in the second conductive layer, the first connection portion is located in the third conductive layer, the second conductive layer is located on a side of the first conductive layer away from the base substrate, and the third conductive layer is located on a side of the second conductive layer away from the base substrate.

10. The display substrate according to claim 9, characterized in that: The first transparent conductive connection portion is located in a first transparent conductive layer, and the first transparent conductive layer is located on a side of the third conductive layer away from the base substrate.

11. The display substrate according to claim 10, characterized in that: The first sub-pixel driving circuit further includes a first initialization transistor, the first initialization transistor including an active layer located in the semiconductor layer; The second sub-pixel driving circuit further includes a second initialization transistor, the second initialization transistor including an active layer located in the semiconductor layer; as well as The orthographic projection of the first transparent conductive connection portion on the base substrate partially overlaps with the orthographic projection of the active layer of the first initialization transistor on the base substrate, and the orthographic projection of the first transparent conductive connection portion on the base substrate partially overlaps with the orthographic projection of the active layer of the second initialization transistor on the base substrate.

12. The display substrate according to claim 11, characterized in that: The display substrate further comprises a first scanning signal line and a second scanning signal line disposed on the base substrate, the first scanning signal line being used to supply a scanning signal to the first sub-pixel driving circuit, and the second scanning signal line being used to supply a scanning signal to the second sub-pixel driving circuit; as well as The orthographic projection of the first scanning signal line on the base substrate partially overlaps with the orthographic projection of the active layer of the first initialization transistor on the base substrate, and the orthographic projection of the second scanning signal line on the base substrate partially overlaps with the orthographic projection of the active layer of the second initialization transistor on the base substrate.

13. The display substrate according to claim 11, characterized in that: The first transparent conductive connection portion includes at least a first part, a second part and a third part, the third part of the first transparent conductive connection portion extends along a first direction, the second part of the first transparent conductive connection portion extends along a second direction, and the first part of the first transparent conductive connection portion extends along an inclined direction that is inclined relative to both the first direction and the second direction.

14. The display substrate according to claim 13, characterized in that: The orthographic projection of the first portion of the first transparent conductive connection portion on the base substrate partially overlaps with the orthographic projection of the active layer of the first initialization transistor on the base substrate; and / or, The orthographic projection of the third portion of the first transparent conductive connection portion on the base substrate partially overlaps with the orthographic projection of the active layer of the second initialization transistor on the base substrate; and / or, The second portion of the first transparent conductive connection portion is located in the light-transmitting area between the first sub-pixel and the second sub-pixel.

15. The display substrate according to claim 11, characterized in that: The active layer of the first initialization transistor is spaced apart from other parts of the first sub-pixel driving circuit located in the semiconductor layer; and / or, The active layer of the second initialization transistor is spaced apart from other parts of the second sub-pixel driving circuit located in the semiconductor layer.

16. The display substrate according to claim 11, characterized in that: The display substrate also includes a second connection portion disposed on the base substrate, a first end of the second connection portion being electrically connected to the initialization voltage line through a fifth via hole, and a second end of the second connection portion being electrically connected to a first end of the active layer of the first initialization transistor through a sixth via hole.

17. The display substrate according to claim 16, characterized in that: The display substrate also includes a second transparent conductive connection portion arranged on the base substrate, the first end of the second transparent conductive connection portion is electrically connected to the second end of the second connection portion through a seventh via hole, and the second end of the second transparent conductive connection portion is electrically connected to the first end of the active layer of the second initialization transistor through an eighth via hole.

18. The display substrate according to claim 17, characterized in that: The second connecting portion is located in the third conductive layer; and / or the second transparent conductive connecting portion is located in the first transparent conductive layer.

19. The display substrate according to claim 12, characterized in that: The display substrate also includes a third transparent conductive connection portion arranged on the base substrate, one end of the third transparent conductive connection portion is electrically connected to the first scanning signal line through a ninth via hole, and the other end of the third transparent conductive connection portion is electrically connected to the second scanning signal line through a tenth via hole.

20. The display substrate according to claim 19, characterized in that: The display substrate further includes a first light emitting control line and a second light emitting control line disposed on the base substrate, the first light emitting control line being used to supply a light emitting control signal to the first sub-pixel driving circuit, and the second light emitting control line being used to supply a light emitting control signal to the second sub-pixel driving circuit; and The display substrate also includes a fourth transparent conductive connection portion arranged on the base substrate, one end of the fourth transparent conductive connection portion is electrically connected to the first light-emitting control line through an eleventh via hole, and the other end of the fourth transparent conductive connection portion is electrically connected to the second light-emitting control line through a twelfth via hole.

21. The display substrate according to claim 5, characterized in that: In at least one sub-pixel group, the first sub-pixel and the second sub-pixel share the reset signal line and the initialization voltage line.

22. The display substrate according to claim 20, characterized in that: The plurality of sub-pixel groups at least include a first sub-pixel group and a second sub-pixel group located in the same row and adjacent to each other; and The display substrate also includes a first conductive lead arranged on the base substrate, one end of the first conductive lead is electrically connected to the reset signal line in the first sub-pixel group through a thirteenth via hole, and the other end of the first conductive lead is electrically connected to the reset signal line in the second sub-pixel group through a fourteenth via hole.

23. The display substrate according to claim 22, characterized in that: The display substrate also includes a second conductive lead arranged on the base substrate, one end of the second conductive lead is electrically connected to the initialization voltage line in the first sub-pixel group through a fifteenth via hole, and the other end of the second conductive lead is electrically connected to the initialization voltage line in the second sub-pixel group through a sixteenth via hole.

24. The display substrate according to claim 23, characterized in that: The third transparent conductive connection portion and / or the fourth transparent conductive connection portion are located in the first transparent conductive layer; and, The first conductive lead and / or the second conductive lead are located in the second transparent conductive layer, Wherein, the second transparent conductive layer is located on a side of the first transparent conductive layer away from the base substrate; The display substrate further includes: a data signal line for transmitting a data signal; and a driving voltage line for transmitting a driving voltage; and The data signal line and the driving voltage line are both located in the first transparent conductive layer.

25. The display substrate according to claim 24, wherein: The driving voltage line is disconnected at the first sub-pixel driving circuit and the second sub-pixel driving circuit, so that the driving voltage line includes a first driving voltage sub-line and a second driving voltage sub-line, and the first driving voltage sub-line and the second driving voltage sub-line are spaced apart in an extending direction of the driving voltage line; The display substrate further includes a third connection portion, one end of the third connection portion is electrically connected to the first driving voltage sub-line through a seventeenth via hole, and the other end of the third connection portion is electrically connected to the second driving voltage sub-line through an eighteenth via hole; The display substrate comprises a fourth conductive layer disposed on the base substrate, wherein the fourth conductive layer is located between the first transparent conductive layer and the second transparent conductive layer; and The third connection portion is located in the fourth conductive layer.

26. The display substrate according to claim 1 or 2, characterized in that: The first light emitting device at least comprises a first electrode and a light emitting material layer, wherein the light emitting material layer is arranged on a side of the first electrode away from the base substrate; The area of ​​the orthographic projection of the first electrode of the first sub-pixel on the base substrate is larger than the area of ​​the orthographic projection of the first electrode of the second sub-pixel on the base substrate; as well as The orthographic projection of the first electrode of the first sub-pixel on the base substrate covers the orthographic projection of the occupied area of ​​the first sub-pixel driving circuit on the base substrate; And / or, the orthographic projection of the first electrode of the second sub-pixel on the base substrate covers the orthographic projection of the occupied area of ​​the second sub-pixel driving circuit on the base substrate.

27. A display panel comprising the display substrate according to any one of claims 1-26.

28. A display device comprising the display substrate according to any one of claims 1 to 26 or the display panel according to claim 27.

29. The display device according to claim 28, wherein: The display device further includes at least one image sensor; and The orthographic projection of the at least one image sensor on the base substrate falls within the orthographic projection of the first display area on the base substrate.

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