Control of a resonant converter using a switching path during power-up

Abstract

Control of a resonant power converter using switching paths during power up is described herein. During power up, a first switching path sinks current from a resonant capacitor, while a second switching path sources current to a high-side capacitor. In this manner, the high-side capacitor can be predictably charged to a sufficient bootstrap voltage for steady state operation. Additionally, a third switching path can control current to a low-side capacitor.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 62 / 948,444, filed December 16, 2019, which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates generally to power converters, and more particularly to powering on a resonant converter. BACKGROUND

[0004] Electronic devices use electrical power to operate. Switched mode power converters are commonly used to power many electronic devices today due to their high efficiency, small size, and low weight. Conventional wall outlets provide high voltage alternating current (ac) power. In a switched power converter, the high voltage ac input is converted by an energy transfer element to provide a well-regulated direct current (dc) output. Switched mode power converter controllers typically provide output regulation by sensing one or more inputs representative of one or more output quantities and controlling the output in a closed loop. In operation, switches are utilized to provide the desired output by varying the duty cycle (typically the ratio of the on time of the switch to the total switching period), varying the switching frequency, or varying the number of pulses per unit time of the switches in the switched mode power converter.

[0005] One type of switched mode power converter is a resonant converter, which includes a resonant circuit (e.g., an inductor and a capacitor) as part of the power stage. The resonant circuit can advantageously improve power conversion efficiency by availing zero current and / or zero voltage switching.

[0006] One subset of resonant converters, the series inductor-inductor-capacitor (LLC) converter, uses a resonant circuit with two inductors and a capacitor connected in series to form an LLC resonant circuit. Typically, the power stage of the LLC converter is controlled such that the power stage switches are subjected to zero voltage switching. SUMMARY

[0007] The present application provides a scheme to control a resonant converter using a switching path during power up.

[0008] In a first aspect, the present application provides a half-bridge circuit electrically coupled to a resonant network, the resonant network comprising a resonant capacitor, the half-bridge circuit comprising: a high-side device driven by a high-side driver; a low-side device driven by a low-side driver, the low-side device electrically coupled to the high-side device; a first switch path electrically coupled to the low-side device and providing a current flow path in parallel with the low-side device; a high-side bootstrap capacitor coupled to cyclically provide power to the high-side driver and form a capacitive voltage divider with the resonant capacitor; and a second switch path configured to provide a high-side charging current to the high-side bootstrap capacitor, wherein during a power-up state, the first switch path is configured to: require a shunt current greater than the high-side charging current, wherein the shunt current is required while the low-side device is driven on and the first switch path is coupled to divert the shunt current away from the resonant network to reduce a resonant capacitor voltage.

[0009] In a second aspect, the present application provides a method of operating a resonant converter during a power-up state, the resonant converter comprising a resonant capacitor, the method comprising: providing a high-side charging current to a high-side bootstrap capacitor while a low-side device is driven on; requiring a shunt current greater than the high-side charging current while the high-side charging current is provided to the high-side bootstrap capacitor while the low-side device is driven on; and diverting the shunt current away from a resonant network to reduce a resonant capacitor voltage. BRIEF DESCRIPTION OF DRAWINGS

[0010] Non-limiting and non-exhaustive embodiments for resonant converter control using switch paths during power-up are described with reference to the following drawings, wherein like reference numerals are used to refer to like elements throughout.

[0011] Figure 1A A simplified schematic of an LLC converter is illustrated according to an embodiment.

[0012] Figure 1B A simplified schematic of an LLC converter is illustrated according to another embodiment.

[0013] Figure 2A is a schematic of a half-bridge circuit including a switch path according to a first embodiment.

[0014] Figure 2B is a schematic of a half-bridge circuit including a switch path according to a second embodiment.

[0015] Figure 2C is a schematic diagram of a half-bridge circuit including a switching path according to a third embodiment.

[0016] Figure 2D is a schematic diagram of a half-bridge circuit including a switching path according to a fourth embodiment.

[0017] Figure 3A A control circuit according to an embodiment is illustrated.

[0018] Figure 3B A control circuit according to an embodiment is illustrated.

[0019] Figure 3C A control circuit according to an embodiment is illustrated.

[0020] Figure 3D A control circuit according to an embodiment is illustrated.

[0021] Figure 4 A schematic diagram of a half-bridge circuit according to an embodiment is illustrated.

[0022] Figure 5 A waveform according to an embodiment is illustrated.

[0023] Figure 6A A conceptual block diagram for operating a resonant converter during a power-up state according to an embodiment is illustrated.

[0024] Figure 6B A conceptual block diagram for operating a resonant converter during a power-up state according to an embodiment of Figure 6A is illustrated.

[0025] In all of the several views of the drawings, corresponding reference characters indicate corresponding parts throughout the several views. Skilled artisans will appreciate that the elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements to help improve the understanding of various embodiments of the present application. Also, common but well-understood elements that are useful in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present application. DETAILED DESCRIPTION

[0026] In the following description, numerous specific details are set forth to provide a thorough understanding of the use of a switching path for control of a power converter during power-up. However, it will be apparent to one skilled in the art that the present teachings can be practiced without the specific details. In other instances, well-known materials, components, and / or methods have not been described in detail in order to avoid obscuring aspects of the present disclosure.

[0027] References throughout this specification to "one embodiment", "an embodiment", "one example" or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the teachings. The appearances of the phrase "in one embodiment" or "in an embodiment" or "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable

[0028] In the context of the present application, when a transistor is in an "off state" or "off", the transistor blocks current and / or does not substantially conduct current. In contrast, when a transistor is in an "on state" or "on", the transistor is capable of significantly conducting current. For example, in one embodiment, a high voltage transistor comprises an N-channel field effect transistor (FET); the N-channel field effect transistor (FET) can be a metal oxide semiconductor field effect transistor (MOSFET), where high voltage is supported between a first terminal, i.e., drain, and a second terminal, i.e., source. In another embodiment, the field effect transistor (FET) can be a junction field effect transistor (JFET), i.e., a depletion mode device, whereby transport is primarily by majority carriers.

[0029] In some embodiments, an integrated controller circuit can be used to drive the power switch when regulating the energy provided to a load. In addition, for the purposes of the present disclosure, "ground" or "ground potential" refers to a reference voltage or potential relative to which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured.

[0030] As described above, one type of switched mode power converter is a resonant converter that uses a resonant circuit, also referred to as a resonant network or "tank" circuit, having an inductance and a capacitance as part of the power conversion process. Compared to non-resonant switched mode power converters, resonant converters can have some advantages such as soft switching (e.g., zero voltage switching), generally higher efficiency, lower losses when operating at higher frequencies, and lower harmonic content in the switching waveform. These, in turn, can reduce packaging and component costs by allowing the use of smaller magnetic elements and smaller electromagnetic interference (EMI) filters.

[0031] Resonant converters generally include a half-bridge circuit. The half-bridge circuit can include a low-side device driven by a low-side driver and a high-side device driven by a high-side driver. In a steady state switching condition (i.e., in a steady state condition), the high-side driver can use a high-side capacitor, commonly referred to as a bootstrap capacitor, to cyclically provide power to the high-side driver. In addition, the low-side driver can use a low-side capacitor, referred to as a hold-up capacitor, to maintain power to the low-side driver.

[0032] As can be appreciated by one of ordinary skill in the art, bootstrap circuitry can be needed to benefit the bootstrap voltage of the bootstrap capacitor. For example, power (i.e., charge) can be provided to the high-side driver and its bootstrap capacitor by using a switching bootstrap method. In steady state (i.e., during a steady state operating condition), the switching bootstrap method can cyclically provide energy to the bootstrap capacitor according to a steady state switching cycle. When the low-side device is on, charge can be replenished from a power source referenced to ground via a bootstrap device (e.g., a bootstrap diode and / or FET).

[0033] The capacitance of the high-side capacitor and the capacitance of the low-side capacitor can be selected to ensure sufficient power during steady state switching and during light load conditions. For example, the capacitance can be selected to be greater than a minimum hold-up capacitance (e.g., one hundred nano farads) to maintain sufficient voltage and to provide sufficient power to the high-side driver and / or the low-side driver.

[0034] The resonant converter can also include a resonant network (i.e., resonant circuit). For example, the resonant converter can use a resonant network that includes two inductors and one resonant capacitor to form an LLC (inductor-inductor-capacitor) resonant converter. In addition, the inductance and the capacitance of the resonant network can be designed for a desired operating point, gain, and performance specifications. Thus, the capacitance of the resonant capacitor can be constrained by design.

[0035] Transitioning from power-up success to steady state can also depend on the ratio of the capacitance of the resonant capacitor to the capacitance of the high-side capacitor. For example, during power-up, the high-side capacitor and the resonant capacitor can be electrically coupled in a circuit path; and, by virtue of the capacitance divider formed by the high-side capacitor and the resonant capacitor, the high-side voltage (i.e., bootstrap voltage) on the high-side capacitor can be limited. Conventionally, the solution to ensure sufficient bootstrap voltage is to limit the capacitance of the high-side capacitor relative to the capacitance of the resonant capacitor.

[0036] Unfortunately, limiting the capacitance of the high-side capacitor can be undesirable. Accordingly, there is a need for a half-bridge circuit that can successfully power-up to steady state independent of the capacitance of the resonant capacitor. Further, there is a need for a half-bridge circuit that can successfully power-up to steady state independent of the ratio of the capacitance of the resonant capacitor to the capacitance of the high-side capacitor.

[0037] Further, as modern switching converters and modern LLC converters seek to operate at higher switching frequencies, there is a need for improved and enhanced power-up and power-up sequencing. For example, during power-up, there can be unbalanced, unknown conditions (e.g., internal initial conditions and / or external initial conditions) that can cause destructive overstress, destructive inrush current, and / or slow response time in reaching steady state zero voltage switching. Unfortunately, the goal of operating at higher frequencies can result in unbalanced initial conditions. Accordingly, there is also a need for a half-bridge circuit that can successfully power-up to steady state without electrical overstress to components.

[0038] Described herein is control of a resonant power converter using switching paths during power-up. During power-up, a first switching path sinks current from a resonant capacitor, while a second switching path sources current to a high-side capacitor. In this manner, the high-side capacitor can be predictably charged to sufficient bootstrap voltage to support steady state operation. Further, a third switching path can control current to a low-side capacitor.

[0039] According to the teachings herein, the switching paths can advantageously enhance the ability of an LLC converter to achieve steady state and fast zero voltage switching by reducing the transient time required to reach steady state. Further, using switching paths can benefit a controllable and repeatable power-up method to advantageously reduce stress (i.e., overcurrent and / or overvoltage stress) on the high-side driver and the low-side driver.

[0040] Figure 1A A schematic diagram of an LLC converter 100 is illustrated in accordance with an embodiment. The LLC converter 100 includes a half-bridge circuit 102, a resonant network 104, a secondary network 106, and a controller 108. A direct current (dc) input voltage V INA source of input power can be applied at the primary input of the LLC converter 100. In steady state, the controller 108 can control the LLC converter 100 to convert the input power to a dc output power delivered to the load 109. For ease of presentation, the schematic of the LLC converter 100 has been simplified to provide a less obstructed view of the switching paths 121-123.

[0041] As illustrated, the half-bridge circuit 102 includes a first switching path 121, a second switching path 122, and a third switching path 123. The first switching path 121 receives a control signal V C1 . The second switching path 122 receives a control signal V C2 ; and the third switching path 123 receives a control signal V C3 . As described herein, the switching paths 121-123 can be controlled by their respective control signals V C1 -V C3 to ensure a transition from a power-up (i.e., from a power-up state) to a steady state.

[0042] In steady state (i.e., during a steady state switching condition), the LLC converter 100 can regulate a dc output power delivered to the load 109. This dc output power can be delivered to the load 109 at a regulated output voltage V O with respect to the secondary ground RTN. Further, during steady state, the controller 108 can provide a primary drive signal S DRV to the half-bridge circuit 102. Further, the primary drive signal S DRV may be provided in response to a secondary signal S SEC and / or a resonant network signal S RES to regulate the dc output power delivered to the load 109.

[0043] As illustrated, the half-bridge circuit 102 includes a high-side capacitor C BHS and a low-side capacitor C BLS ; and the resonant network 104 includes a leakage inductor L LK , a magnetizing inductor L M , and a resonant capacitor C RES . Also as illustrated, the high-side capacitor C BHS , the low-side capacitor C BLS , and the resonant capacitor C RES may operate at voltages V CHS , V CLS , and V CRES , respectively. The high-side capacitor C BHS may also be referred to as a bootstrap capacitor C BHS; and voltage V CHS . Similarly, low-side capacitor C CHS . Similarly, low-side capacitor C BLS may also be referred to as a low-side hold-up capacitor C BLS ; and voltage V CLS may be referred to as a low-side hold-up voltage V CLS .

[0044] As can be appreciated by one of ordinary skill in the art, the resonant tank frequency can be determined, at least in part, by the capacitance of resonant capacitor C RES and the inductance of magnetizing inductor L M and / or leakage inductor L LK . In steady state, current I X may be provided to the resonant network 104 as an alternating current having a frequency comparable to the resonant tank frequency; and voltage V CRES may vary in proportion to current I X .

[0045] Also as illustrated, the half-bridge circuit 102 includes a high-side driver 132 and a low-side driver 133. The high-side driver 132 is electrically coupled to a first terminal of high-side capacitor C BHS at a high-side node NHS, and also coupled to a second terminal of high-side capacitor C BHS at a half-bridge switch node NSW. When sufficient voltage V CHS (e.g., 10 volts) is available from high-side capacitor C BHS , the high-side driver 132 can provide a gate signal GH. The low-side driver 133 is electrically coupled to a first terminal of low-side capacitor C BLS at a low-side node NLS, and also coupled to a second terminal of low-side capacitor C BLS at ground GND. When sufficient voltage V CLS (e.g., 10 volts) is available from low-side capacitor C BLS , the low-side driver 133 can provide a gate signal GL.

[0046] During power-up (i.e., in a power-up state), voltages V CHS and V CLS may have transient values (i.e., transient voltage levels), whereby the high-side driver 132 and / or the low-side driver 133 do not have sufficient power (i.e., voltage and / or energy) to provide adequate gate signals GH, GL. In accordance with the teachings herein, the first switch path 121 can shunt (i.e., sink) current I1 from resonant capacitor C RES , while the second switch path 122 provides (i.e., sources) current I2 to high-side capacitor C BHS .CHS For example, the first switch path 121 can divert the current II to boost (i.e., increase) the current I CHS In this manner, the aforementioned capacitance divider formed by the resonant capacitor C BHS and the high-side capacitor C RES can be substantially eliminated during power-up. Thus, during power-up, the high-side capacitor C BHS can advantageously be charged (i.e., increased) to a voltage V CHS (i.e., bootstrap voltage V CHS ) sufficient to power the high-side driver 132.

[0047] Further, the third switch path 123 can provide (i.e., supply) the current I BLS to the low-side capacitor C CLS such that the low-side hold voltage V CLS reaches a steady state value in a controlled manner.

[0048] Alternatively, and additionally, the third switch path 123 can provide the current I CLS to the low-side capacitor C BLS as a function of the low-side hold voltage V CLS . As discussed below with respect to Figure 5 , the third switch path 123 can limit and / or control the current I3 to follow the function of the low-side hold voltage V CLS . Controlling the current I3 as a function of the hold voltage V CLS can advantageously reduce thermal stress and / or thermal failure due to faults (e.g., short circuit faults).

[0049] As mentioned above, the schematic of the LLC converter 100 is a non-limiting embodiment simplified to provide an unobstructed view of the switch paths 121-123. For example, the controller 108 has been simplified to show only three signals, namely the primary drive signal S DRV , the secondary signal S SEC , and the resonant network signal S RES . As can be appreciated by one of ordinary skill in the art, the half-bridge circuit 102 can be used in other converter architectures, including inductor-capacitor-capacitor (LCC) resonant converters and / or various non-resonant converters. As can be appreciated by one of ordinary skill in the art, the controller 108 can exert control with more or less than three signals; and other configurations are possible.

[0050] For example, Figure 1BA simplified schematic of an LLC converter 150 is illustrated in accordance with another embodiment. The LLC converter 150 is similar to the LLC converter 100, except that the half-bridge circuit 102 is replaced with a full-bridge circuit 103. The full-bridge circuit 103 includes half-bridge circuits 102a-102b. The half-bridge circuits 102a-102b can be similar to the half-bridge circuit 102 and can each include a switching path (e.g., switching paths 121-123).

[0051] As can be appreciated by one of ordinary skill in the art, the LLC converter 150 is connected in a full-bridge configuration, whereby the resonant network 104 is electrically coupled between the half-bridge circuits 102a-102b. As illustrated, in the full-bridge configuration, a current Ix is provided from the half-bridge circuit 102a to the resonant network 104; and the current Ix is provided from the resonant network 104 to the half-bridge circuit 102b.

[0052] Figure 2A is a schematic of a half-bridge circuit 102 including switching paths 121a-123a in accordance with a first embodiment. In addition, the half-bridge circuit 102 includes a high-side capacitor C BHS , a high-side driver 132, a high-side device 206, a low-side capacitor C BLS , a low-side driver 133, and a low-side device 208. The high-side device 206 and the low-side device 208 can operate as switches; and as illustrated, the high-side device 206 and the low-side device 208 can be implemented with N-channel field effect transistors (FETs). Thus, the high-side (HS) device 206 can also be referred to as a high-side FET 206, and the low-side (LS) device 208 can also be referred to as a low-side FET 208.

[0053] The high-side driver 132 receives power (i.e., energy) from the high-side capacitor C BHS , and can provide a gate signal GH (i.e., a gate voltage GH) to a gate of the high-side FET 206. In addition, the low-side driver 133 receives power (i.e., energy) from the low-side capacitor C BLS , and can provide a gate signal GL (i.e., a gate voltage GL) to a gate of the low-side FET 208. As described above, the gate signals GL, GH can be voltages. Thus, the gate signal GH can also be referred to as a gate voltage GH, and the gate signal GL can also be referred to as a gate voltage GL.

[0054] A resonant network 204 is also illustrated that is electrically coupled to the half-bridge circuit 102. The resonant network 204 includes a resonant capacitor C RES and a lumped impedance 205. In accordance with an embodiment, the resonant capacitor C RESThe capacitance of the resonant capacitor C RES may represent the total capacitance of the resonant tank (e.g., resonant network 204), which can include parasitic capacitance and / or external capacitance. Further, the resonant capacitor C BHS forms a capacitance voltage divider; as discussed above, the capacitance voltage divider can reduce the available bootstrap voltage V CHS . In accordance with the teachings herein, during power-up, the switch path 121a-122a can be used to allow the high-side capacitor C BHS to reach a sufficient (i.e., large enough) bootstrap voltage V CHS to power the high-side driver 132.

[0055] Further, during power-up, the third switch path 123a can be used to control the current I BLS to the low-side capacitor C CLS ; and, although the teachings are discussed with respect to the half-bridge circuit 102 driving the resonant network 204, other networks and configurations are possible. For example, the resonant network 204 can represent any network that receives power (e.g., current Ix) from the half-bridge circuit 102 and has an impedance similar to that of a series capacitance element of the resonant capacitor C RES .

[0056] The high-side driver 132 receives power (i.e., energy) from the high-side capacitor C BHS and can provide a gate signal GH (i.e., gate voltage GH) to the gate of the high-side FET 206. Further, the low-side driver 133 receives power (i.e., energy) from the low-side capacitor C BLS and can provide a gate signal GL (i.e., gate voltage GL) to the gate of the low-side FET 208. As described above, the gate signals GL, GH can be voltages. Thus, the gate signal GH can also be referred to as the gate voltage GH, and the gate signal GL can also be referred to as the gate voltage GL.

[0057] The high-side FET 206 and the low-side FET 208 are electrically connected as a half-bridge to provide a half-bridge voltage V X from the half-bridge switch node NSW. As illustrated, the source of the high-side FET 206 and the drain of the low-side FET 208 are electrically connected together at the half-bridge switch node NSW.

[0058] In steady state, the half-bridge voltage V X may be provided in the form of a switched waveform (e.g., a square wave switched waveform). The steady state switched waveform can transition between a maximum voltage provided by the source of the high-side FET 206 and a minimum voltage provided by the drain of the low-side FET 208.

[0059] As illustrated, the half-bridge circuit 102 is electrically coupled to the resonant network 204 by way of the drain of the low-side FET 208 and the source of the high-side FET 206. The dc input voltage V IN is provided to the drain of the high-side FET 206, and the source of the low-side FET 208 is electrically coupled to ground GND. During steady state, the high-side FET 206 and the low-side FET 208 are switched to function as a half-bridge. Thus, for at least a portion of one steady state switching cycle, the high-side FET 206 can be turned on at the same time the low-side FET 206 is turned off; alternatively, the low-side FET 206 can be turned off at the same time the high-side FET 208 is turned on. Thus, when the high-side FET 206 receives a sufficient gate voltage GH (i.e., a sufficient gate-to-source voltage), the maximum voltage provided by the high-side FET 206 can be substantially equal to the input voltage V IN ; and when the low-side FET 208 receives a sufficient gate voltage GL (i.e., a sufficient gate-to-source voltage), the minimum voltage provided by the low-side FET 208 can be substantially equal to ground GND.

[0060] During power-up and prior to reaching steady state, the low-side capacitor C BLS and the high-side capacitor C BHS may not have sufficient charge (i.e., energy). Thus, the low-side driver 133 can not receive sufficient power (i.e., sufficient hold-up voltage V CLS ) from the low-side capacitor C BLS to provide a sufficient gate voltage GL; and the high-side driver 132 can not receive sufficient power (i.e., sufficient bootstrap voltage V CHS ) from the high-side capacitor C BHS to provide a sufficient gate voltage GH. In accordance with the teachings herein, the switching paths 121a-123a can be controlled to predictably charge the low-side capacitor C BLS and the high-side capacitor C BHS during power-up (i.e., during a power-up state).

[0061] The switching paths 121a-123a include a first switching path 121a, a second switching path 122a, and a third switching path 123a. The first switching path 121a includes a diode Dl, an N-channel junction field effect transistor (JFET) Ql, and a switch SWl electrically coupled in series. Similarly, the second switching path 122a includes a diode D2, an N-channel junction field effect transistor (JFET) Q2, and a switch SW2 electrically coupled in series; and the third switching path 123a includes a diode D3, an N-channel junction field effect transistor (JFET) Q3, and a switch SW3 electrically coupled in series. In some embodiments, the diode D3 can be optionally excluded from the third switching path 123a.

[0062] As can be appreciated by those of ordinary skill in the art, JFETs Q1-Q3 can be implemented as integrated and / or discrete JFETs Q1-Q3. In other embodiments, JFETs Q1-Q3 can be implemented with tap elements as disclosed by U.S. Patent No. 6,865,093 B2 to Donald R. Disney. In this regard, switch paths 121a-123a can also be referred to as tap paths 121a-123a; and currents II-13 can also be referred to as tap currents II-13.

[0063] First switch path 121a can be configured to block and conduct current II in response to control signal V C1 For example, switch SW1 can be opened and closed by control signal V C1 thereby conducting current II when closed and blocking current II when open. First switch path 121a can also block and conduct current by virtue of diode Dl. As illustrated, diode Dl can block current II in a reverse bias condition and conduct current II in a forward bias condition. In this way, current II can flow when diode Dl is forward biased and can be blocked when diode Dl is reverse biased. In one embodiment, diode Dl can advantageously block reverse substrate current.

[0064] Similarly, second switch path 122a can be configured to block and conduct current I2 in response to control signal V C2 ; and third switch path 123a can be configured to block and conduct current I3 in response to control signal V C3 For example, switch SW2 can conduct current I2 when closed and block current I2 when open in response to control signal V C2 ; and switch SW3 can conduct current I3 when closed and block current I3 when open in response to control signal V C3 ; and switch SW3 can conduct current I3 when closed and block current I3 when open in response to control signal V C3 Furthermore, diode D2 can block current I2 in a reverse bias condition and conduct current I2 in a forward bias condition; and in one embodiment, diode D2 can advantageously block reverse substrate current. Diode D3 can block current I3 in a reverse bias condition and conduct current I3 in a forward bias condition. As described above, diode D3 can optionally be excluded from third switch path 123a. For example, in some embodiments, current I3 can be a dc current to ground, thereby eliminating the need for diode D3.

[0065] Furthermore, the first switch path 121a can be configured to limit the current II. For example, the JFET Ql can limit a maximum value of the current II by virtue of its operating point (e.g., gate-to-source voltage and drain-to-source voltage). As illustrated, the gate of the JFET Ql can be electrically coupled to ground GND (i.e., biased to a ground potential). According to semiconductor device physics, when the operating point (e.g., drain-to-source voltage and gate-to-source voltage) causes the JFET Ql to enter saturation (i.e., enter its current saturation region), the JFET Ql can limit the current II to have a substantially constant value.

[0066] Similarly, the second switch path 122a can be configured to limit the current I2. For example, the JFET Q2 can limit a maximum value of the current I2 by virtue of its operating point. As illustrated, the gate of the JFET Q2 can be biased at the half-bridge potential V X According to semiconductor device physics, when the operating point (e.g., drain-to-source voltage and gate-to-source voltage) causes the JFET Q2 to enter its current saturation region, the JFET Q2 can limit the current I2 to have a substantially constant value.

[0067] Furthermore, the third switch path 123a can be configured to limit the current I3. For example, the JFET Q3 can limit a maximum value of the current I3 by virtue of its operating point. As illustrated, the gate of the JFET Q3 can be electrically coupled to ground GND (i.e., biased to a ground potential). According to semiconductor device physics, when the operating point (e.g., drain-to-source voltage and gate-to-source voltage) causes the JFET Q3 to enter its current saturation region, the JFET Q3 can limit the current I3 to have a substantially constant value.

[0068] Furthermore, the third switch path 123a can be configured to limit the current I3 according to the low-side hold voltage V CLS For example, as discussed below with respect to Figure 5 the current I3 can be controlled to be a step and / or a step function of the low-side hold voltage V CLS In this way, the current I CLS that varies proportionally with the current I3 is also limited according to the low-side hold voltage V CLS .

[0069] As discussed above, during power-up, prior to steady state, the low-side capacitor C BLS may not initially be charged to a sufficient low-side hold voltage V CLS ; and the high-side capacitor C BHS (i.e., the bootstrap capacitor C BHS ) can not receive a sufficient bootstrap voltage V CHS. Further, low-side driver 133 can not receive sufficient power (i.e., hold voltage V CLS ), high-side driver 132 can not receive sufficient power (i.e., bootstrap voltage V CHS ); thus, high-side FET 206 and low-side FET 208 can not receive sufficient gate voltages GL, GH to be turned on and off during power-up.

[0070] As illustrated, first switch path 121a can be electrically coupled to the drain of low-side FET 208 to provide a parallel (i.e., shunt) circuit path to ground GND. During power-up (i.e., power-up state), control signal V C1 may be applied to first switch path 121a to sink (i.e., shunt) current II and allow half-bridge voltage V X to be pulled low. For example, when control signal V C1 causes switch SW1 to close (i.e., turn on), half-bridge voltage V X may be pulled low to a voltage determined at least in part by the operating conditions of diode D1 and JFET Q1.

[0071] Second switch path 122a can be electrically coupled between the drain of high-side FET 206 and high-side capacitor C BHS . During power-up, control signal V C2 may be applied to second switch path 122a to provide (i.e., source) current I2 to high-side capacitor C BHS . For example, when control signal V C2 causes switch SW2 to close (i.e., turn on), current I BHS may be provided to high-side capacitor C CHS . According to basic circuit theory, current I CHS may be a component of current I2 sourced by second switch path 122a.

[0072] Control signal V C1 may be provided concurrently with control signal V C2 such that first switch path 121a sinks current II (i.e., requires current II); while second switch path 122a sources current I2 (i.e., utilizes current I2). The amount of current I BHS available to charge high-side capacitor C CHS may depend at least in part on the operating conditions of diode D2 and JFET Q2. For example, according to semiconductor device physics, the amount of current I2 utilized by second switch path 122a can depend at least in part on the saturation current of JFET Q2.

[0073] Furthermore, the operating conditions of the first switching path 121a and the second switching path 122a can be adjusted so that capacitor C RES No interference with the high-side capacitor C BHS The charging process. For example, JFET Q1 and JFET Q2 can be designed to operate with characteristic curves such that the first switching path 121a requires more current I1 than the second switching path 122a can supply. In these conditions, the first circuit path 121a can pull down the half-bridge voltage V. X This, in turn, can reduce (i.e., transfer away) the amount of material used in the resonant capacitor C. RES The current Ix. In this way, the resonant capacitor C RES The current is shunted by the first switching path 121a, causing the resonant capacitor voltage V to... CRES It is significantly reduced. Therefore, the current I CHS The high-side capacitor C can be BHS Charge to a sufficient bootstrap voltage V CHS And no resonant capacitor C was provided. RES Significant charging. As discussed in this article, a control signal V can be provided. C1 and V C2 To make the bootstrap voltage V CHS Adjust and / or limit to the maximum value (e.g., 12 volts).

[0074] Furthermore, the third switching path 123a can be electrically coupled to the drain of the high-side FET 206 and the low-side capacitor C. BLS Between. During power-on, the control signal V C3 It can be applied to the third switching path 123a to supply power to the low-side capacitor C. BLS Provide (i.e., supply) current I3. According to basic circuit theory, current I CLS It can be a component of the current I3 supplied by the third switch path 123a.

[0075] Control signal V can be provided C3 This allows the third switching path 123a to supply and limit the current I3, thereby protecting the low-side capacitor C. BLS Provided to the low-side capacitor C BLS Current I CLS The current can be limited, at least in part, by the operating conditions of diode D3 and JFET Q3. For example, the amount of current can be limited by the operating conditions of JFET Q3 (e.g., its characteristic curve). As discussed herein, a control signal V can be provided. C3 To maintain the low-side voltage V CLS Adjust and / or limit to the maximum value (e.g., 12 volts).

[0076] Furthermore, as described herein, the current I3may be a function of the low-side hold voltage V CLS . As discussed below with respect to Figure 5 , the current I3may be controlled and thus the current I CLS may be controlled in accordance with the hold voltage V CLS . In this way, components of the third switch path 123a (e.g., JFET Q3) can be protected from shorting and / or thermal stress of the hold voltage V CLS .

[0077] Figure 2B is a schematic diagram of a half-bridge circuit 102 including switch paths 121b-123b in accordance with a second embodiment. Figure 2B The half-bridge circuit 102 of Figure 2A is similar to the half-bridge circuit of , except that the switch paths 121a-123a are replaced by switch paths 121b-123b. The switch paths 121b-123b include a first switch path 121b, a second switch path 122b, and a third switch path 123b.

[0078] Similar to the switch paths 121a-123a, the switch paths 121b-123b can be used during power-up. Like the switch paths 121a-122a, the switch paths 121b-122b can be configured to ensure that the high-side capacitor C BHS is charged to a sufficient bootstrap voltage V CHS by the current I CHS ; and like the third switch path 123a, the third switch path 123b can be configured to limit the current I CLS and prevent inrush to the low-side hold capacitor C BLS .

[0079] In contrast to the switch paths 121a-123a, the switch paths 121b-123b include N-channel field effect transistors (NFETs) M1-M3 instead of JFETs Q1-Q3 and switches SW1-SW3. As illustrated, the first switch path 121b includes a diode D1 electrically coupled in series with the NFET M1; a cathode of the diode D1 can be electrically coupled to a drain of the NFET M1. The second switch path 122b includes a diode D2 electrically coupled in series with the NFET M2; a cathode of the diode D2 can be electrically coupled to a drain of the NFET M2. The third switch path 123b includes a diode D3 electrically coupled in series with the NFET M3; a cathode of the diode D3 can be electrically coupled to a drain of the NFET M3.

[0080] By way of the control signals V C1 -V C3The switch paths 121b-123b can provide similar electrical functionality as the switch paths 121a-123a.

[0081] With respect to the switch paths 121a-123a, control signals V C1 -V C3 may be provided to their respective switches SW1-SW3 to control the switches SW1-SW3 to individually operate in either an on state or an off state. As discussed above, in the switch paths 121a-123a, the currents II-III can be adjusted (i.e., limited) by virtue of the operating conditions of the JFETs Q1-Q3; as discussed above, the currents II-III can be limited according to the saturation characteristics of the JFETs Q1-Q3 and the device operating points (e.g., the applied gate-to-source voltage and / or the applied drain-to-source voltage).

[0082] With respect to the switch paths 121b-123b, control signals V C1 -V C3 may be provided to (i.e., can drive) the gates of the NFETs M1-M3. In this manner, the behavior of the currents II-III in the switch paths 121b-123b can be similar to the behavior of the currents II-III in the switch paths 121a-123a.

[0083] For example, a control signal V C1 may be provided to the gate of the NFET M1 to turn off the NFET M1 by forcing the gate-to-source voltage of the NFET M1 to be less than the threshold voltage; alternatively, and additionally, a control signal V C1 may be provided to the gate of the NFET M1 to force the NFET M1 to operate in its saturation region as a function of the amplitude of the control signal V C1 . In this manner, the electrical behavior of the first switch path 121b can be adjusted to have similar electrical behavior (i.e., similar needs for current II) as the first switch path 121a. Similarly, a control signal V C2 may be provided to the gate of the NFET M2 such that the second switch path 122b is adjusted to have similar electrical behavior (i.e., similar supply of current I2) as the second switch path 122a; and a control signal V C3 may be provided to the gate of the NFET M3 such that the third switch path 123b is adjusted to have similar electrical behavior (i.e., similar supply of current I3) as the third switch path 123a.

[0084] Figure 2C is a schematic diagram of a half-bridge circuit 102 including switch paths 121c-123c according to a third implementation. Figure 2C The half-bridge circuit 102 of Figure 2Bhalf-bridge circuit 102 of FIG. 1, except that the switch paths 121b-123b are replaced by switch paths 121c-123c. The switch paths 121c-123c include a first switch path 121c, a second switch path 122c, and a third switch path 123c.

[0085] Similar to the switch paths 121a-123a and the switch paths 121b-123b, the switch paths 121c-123c can be used during power-up. Like the switch paths 121a-122a and the switch paths 121b-122b, the switch paths 121c-122c can be configured to ensure that the high-side capacitor C BHS by the current I CHS to the sufficient bootstrap voltage V CHS ; and like the third switch path 123a and the third switch path 123b, the third switch path 123c can be configured to limit the current I CLS to the low-side hold capacitor C BLS rush-in.

[0086] In contrast to the switch paths 121b-123b, the switch paths 121c-123c further include resistors R1-R3. As illustrated, the first switch path 121c includes a diode D1 electrically coupled in series with the NFET M1 and with the resistor R1. The second switch path 122c includes a diode D2 electrically coupled in series with the NFET M2 and with the resistor R2; and the third switch path 123c includes a diode D3 electrically coupled in series with the NFET M3 and with the resistor R3.

[0087] The resistors R1-R3 can advantageously provide additional freedom levels and / or degrees of freedom for current limiting in the switch paths 121c-123c. Moreover, using the resistors R1-R3 to limit the currents I1-I3 accordingly can mitigate variability in process and / or operating conditions. For example, in some embodiments, there can be large variations (e.g., process variations) in the saturation characteristics of NFETs (e.g., the NFET M1, the NFET M2, and / or the NFET M3), while there can be small variations in the resistances (e.g., sheet resistances) of resistors (e.g., the resistor R1, the resistor R2, and / or the resistor R3).

[0088] Figure 2D is a schematic diagram of a half-bridge circuit 102 including switch paths 121d-123d according to a third embodiment. Figure 2D the half-bridge circuit 102 of FIG. 1, except that the switch paths 121b-123b are replaced by switch paths 121c-123c. The switch paths 121c-123c include a first switch path 121c, a second switch path 122c, and a third switch path 123c. Figure 2AA half-bridge circuit similar to that of FIG. 1A, except that the switch paths 121a-123a are replaced by switch paths 121d-123d. The switch paths 121d-123d include a first switch path 121d, a second switch path 122d, and a third switch path 123d.

[0089] Similar to the switch paths 121a-123a, the switch paths 121b-123b, and the switch paths 121c-123c, the switch paths 121d-123d can be used during power-up. The switch paths 121d-122d can be similarly configured to ensure that the high-side capacitor C BHS by the current I CHS to a sufficient bootstrap voltage V CHS ; and the third switch path 123d can be configured to control the current I CLS .

[0090] In contrast to the switch paths 121a-122a, the switch paths 121d-122d further include resistors R11-R12. As illustrated, the first switch path 121d includes a diode D1 electrically coupled in series with the JFET Q1, with the switch SW1, and with the resistor R11; and the second switch path 122d includes a diode D2 electrically coupled in series with the JFET Q2, with the switch SW2, and with the resistor R12. The resistance of the resistor R11 and the resistance of the resistor R12 can be selected to ensure that the first switch path 121d requires more current I1 than can be provided by the second switch path 122d. For example, in one implementation, the resistance of the resistor R12 can be greater than the resistance of the resistor R11.

[0091] In contrast to the third switch path 123a, the third switch path 123d includes a current selection element 222. As illustrated, the first switch path 123d includes a diode D3 electrically coupled in series with the JFET Q3, with the switch SW3, and with the control selection element 222; further, the current selection element 222 can receive a control signal V C3 In addition to controlling the switch SW3 to conduct or block the current I3, the control signal V C3 may also vary the amount (e.g., amplitude) of the current I3. For example, in one application, the current selection element 222 can be a voltage-controlled current source that limits the current I3 in proportion to the control signal V C3 . Alternatively, and additionally, the current selection element 222 can include a voltage-controlled resistance that limits the current I3 in accordance with the control signal V C3 . Further, the current selection element 222 can include a switched resistor network with discrete resistance values in accordance with the control signal V C3 .

[0092] Figure 3AA control circuit 301 according to one embodiment is illustrated. As illustrated, the control circuit 301 includes a comparator 305. The comparator 305 can be referenced to ground GND and can receive a low-side holding voltage V at its inverting input. CLS And it receives the peak VLP (e.g., the reference voltage VLP) at its non-inverting input.

[0093] As illustrated, control circuit 301 can be based on low-side holding voltage V CLS The control signal V is provided by comparing it with the peak value VLP. C3 (That is, the output of comparator 305). For example, when the low-side holding voltage V... CLS When the peak value VLP is less than the peak value, the control circuit 301 can apply a control signal V. C3 The switch SW3 is turned on and / or the gate of NFET M3 is driven high. Alternatively, the low-side holding voltage V is maintained high. CLS When the peak value VLP is greater than the peak value, the control circuit 301 can apply a control signal V. C3 Turn off switch SW3 and / or drive the gate of NFET M3 low.

[0094] In this way, the control signal V C3 The low-side holding voltage V can be adjusted. CLS In one implementation, the low-side holding voltage V CLS The voltage can be adjusted to between 10 volts and 20 volts; and as those skilled in the art will understand, other configurations are possible. For example, the low-side holding voltage V can instead be... CLS The scaled value is compared with the peak VLP.

[0095] Figure 3B A control circuit 302 according to one embodiment is illustrated. As illustrated, the control circuit 302 includes a comparator 306. The comparator 306 can reference the half-bridge voltage V. X Instead of referencing ground (GND), comparator 306 can receive a bootstrap voltage V at its inverting input. CHS And it receives the peak VHP at its non-inverting input.

[0096] As illustrated, the control circuit 302 can be based on the bootstrap voltage V. CHS The control signal V is provided by comparing it with the peak value VHP. C2 (That is, the output of comparator 306). For example, when the bootstrap voltage V CHS When the value is less than the peak value VHP, the control circuit 302 can apply a control signal V. C2 The switch SW2 is high when it is turned on and / or the gate of NFET M2 is driven. Alternatively, the bootstrap voltage V is high when the switch SW2 is turned on.CHS When the value is greater than the peak value VHP, the control circuit 302 can apply a control signal V. C2 Turn off switch SW2 and / or drive the gate of NFET M2 low.

[0097] In this way, the control signal V C2 The bootstrap voltage V can be adjusted. CHS In one implementation, the bootstrap voltage V CHS The voltage can be adjusted to between 10 volts and 20 volts; and as those skilled in the art will understand, other configurations are possible. For example, the bootstrap voltage V can instead be... CHS The scaled value is compared with the peak VHP.

[0098] Figure 3C An example of a control circuit 303 according to one embodiment is illustrated. As illustrated, the control circuit 303 may be a digital signal processor (DSP) control circuit 303 that provides control signals V based on system variables and / or state variables. C1 For example, control signal V C1 The gate of the NFET M3 can be driven high based on the operating state of the half-bridge circuit 102 (e.g., voltage and / or current).

[0099] As presented in the description above, control circuits 301-303 are non-limiting embodiments shown for illustrative purposes. Other configurations are possible, as will be understood by those skilled in the art. For example, as discussed below with respect to control circuit 311, one or more of control circuits 301-303 can provide a control signal V based on temperature (e.g., junction temperature). C1 -V C3 In addition, a control signal V can be provided. C1 -V C3 One or more of them provide variable amplitude.

[0100] Figure 3D An example is illustrated according to another embodiment for providing control signal V. C3 The control circuit 311 includes an over-temperature circuit 321, a comparator 322, a comparator 323, an inverter 324, an AND gate 325, an analog multiplexer 326, and an analog multiplexer 327.

[0101] The over-temperature circuit 321 can provide a logic signal OT (e.g., a logic voltage OT) based on temperature (e.g., device junction temperature). For example, when the temperature exceeds a threshold temperature (e.g., 85 degrees Celsius), the logic signal OT can transition to a logic high value. As will be understood by those skilled in the art, there are many ways to implement the over-temperature circuit 321 for determining when the temperature exceeds the threshold temperature.

[0102] As illustrated, comparator 322 can be referenced to ground GND and can receive a low-side holding voltage V at its non-inverting input. CLS And it receives the threshold VLY at its inverting input. As illustrated, comparator 322 can respond to the low-side holding voltage V CLS And provide logic signal O1. As configured, when the low-side holding voltage V CLS When the threshold VLY is exceeded, the logic signal O1 can transition to high (i.e., from logic low to logic high).

[0103] Comparator 323 can be referenced to ground (GND) and can receive a low-side holding voltage V at its inverting input. CLS It also receives the peak value VLP at its non-inverting input. Comparator 322 can also respond to the low-side holding voltage V. CLS And provide logic signal O2. As configured, when the low-side holding voltage V CLS When the peak value VLP is exceeded, the logic signal O2 can transition to low (i.e., from logic high to logic low).

[0104] As illustrated, inverter 324 inverts the logic signal OT to provide the logic signal OTB (i.e., the logical NOT of the logic signal OT). Furthermore, AND gate 325 performs a logical AND operation between the logic signal OTB and the logic signal O1 to provide the logic signal Y1.

[0105] Analog multiplexer 326 receives logic signal Y1 at its control input CNT and analog signals VA and VB at its low select input S0 and high select input S1, respectively. As will be understood by those skilled in the art, analog multiplexer 326 can function as an analog switch to provide analog signal V in response to logic signal Y1. OM As illustrated, when logic signal Y1 is low (i.e., logic low), analog multiplexer 326 can convert analog signal V... OM Switching to an equal (i.e., substantially equal) analog signal VA. Conversely, when logic signal Y1 is high (i.e., logic high), analog multiplexer 326 can switch analog signal V... OM Switch to an equal (i.e., substantially equal) analog signal VB.

[0106] The analog multiplexer 327 receives the logic signal O2 at its control input CNT. In addition, the analog multiplexer 327 receives ground GND and the analog signal V OM at its low select input SO and high select input SI, respectively. As can be appreciated by one of ordinary skill in the art, the analog multiplexer 327 can function as an analog switch to provide the control signal V C3 in response to the logic signal O2. As illustrated, when the logic signal O2 is high, the analog multiplexer 327 can switch (i.e., can provide) the control signal V C3 to be equal (i.e., substantially equal) to ground GND (i.e., a logic low). Conversely, when the logic signal O2 is low (i.e., a logic low), the analog multiplexer 327 can switch the control signal V C3 to be equal (i.e., substantially equal) to the analog signal V OM .

[0107] With reference to the switch path 123d, the control circuit 311 can provide the control signal V C3 to benefit voltage regulation and current limiting. For example, by virtue of the comparator 323 and the analog multiplexer 327, when the low-side hold voltage V CLS exceeds the peak value VLP, the logic signal O2 can switch the control signal V C3 to ground (i.e., low). In addition, by virtue of the analog multiplexers 326-327, when the low-side hold voltage V CLS is less than the peak value VLP, the logic signal O2 can switch the control signal V C3 to the equal analog signal V OM .

[0108] With further reference to the switch path 123d, the control circuit 311 can benefit current limiting in accordance with temperature. In addition, the current I3 can be limited to a relatively low initial value (e.g., two milliamps) until the low-side hold voltage V CLS reaches a threshold value VLY (e.g., seven volts). In one embodiment, reaching the threshold value VLY can indicate a safe operating condition of no fault (e.g., short circuit fault). After exceeding the threshold value, the current I3 is further increased to a larger value (e.g., ten milliamps) to benefit increased current to the low-side driver 133 and the low-side capacitor C BLS .

[0109] According to embodiments of the teachings herein, the switch paths (i.e., switch paths 121-123, switch paths 121a-123a, switch paths 121b-123b, switch paths 121c-123c, and / or switch paths 121d-123d) can be active during power-up (i.e., power-up state); and after reaching steady state (i.e., steady state switch condition), the switch paths (e.g., switch paths 121-123) can be open. For example, after reaching steady state, the control circuits 301-303 can be configured to disable (i.e., open) the switch paths (i.e., switch paths 121-123, switch paths 121a-123a, switch paths 121b-123b, switch paths 121c-123c, and / or switch paths 121d-123d). Thus, in steady state, the control signals V C1 -V C3 to turn off the switches SW1-SW3 and / or to drive the gates of the NFETs M1-M3 low. In steady state, the high-side FET 206 and the low-side FET 208 can switch according to a steady state switching frequency; and a conventional circuit can be implemented (i.e., realized) for recycling the bootstrap voltage V CHS and / or for providing the low-side hold voltage V CLS .

[0110] For example, Figure 4 A schematic diagram of a half-bridge circuit 402 is illustrated according to another embodiment. The half-bridge circuit 402 is similar to the half-bridge circuit 102, except that it includes a bootstrap diode DB. An anode of the bootstrap diode DB is electrically coupled to the low-side node NLS; and a cathode of the bootstrap diode DB is electrically coupled to the high-side node NHS. As discussed above, during the steady state switch condition (i.e., during steady state), the switch paths 121-122 can be open. Further, in steady state, the bootstrap diode DB can recycle the bootstrap voltage V X according to a switching waveform (e.g., square wave) of the half-bridge voltage V CHS at the half-bridge switching node NSW.

[0111] The schematic diagram of the half-bridge circuit 402 also illustrates the resonant network 104 and an auxiliary supply 404. The auxiliary supply 404 includes a rectifying diode DA, an auxiliary winding 410, a decoupling capacitor C10, and a decoupling resistor R12. The auxiliary winding 410 is electrically connected between the ground GND and an anode of the rectifying diode DA. A first terminal of the decoupling capacitor C10 is electrically connected to a cathode of the rectifying diode DA; and a second terminal of the decoupling capacitor C10 is electrically connected to the ground GND. The decoupling resistor R12 is connected between the cathode of the rectifying diode DA and the low-side node NLS to provide the low-side hold voltage V CLS .

[0112] As discussed above, during steady-state switching conditions (i.e., during steady-state conditions), switching path 123 can be an open circuit. Furthermore, in steady state, auxiliary supply device 404 can hold capacitor C on the low side. BLS Provide low-side holding voltage V CLS (That is, DC rectified voltage V) CLS ).

[0113] Figure 5 Waveforms 501-509 according to one embodiment are illustrated. (Reference) Figure 4 Waveform 501 can correspond to the half-bridge voltage V. X Waveform 502 can correspond to the bootstrap voltage V. CHS Waveforms 503 and 504 correspond to currents I1 and I2, respectively. Waveforms 505 and 506 correspond to control signal V, respectively. C1 and control signal V C2 Waveform 507 can correspond to the low-side holding voltage V. CLS Waveform 508 can correspond to current I3; waveform 509 can correspond to control signal V. C3 .

[0114] Waveforms 501-509 are presented as a function of time. As illustrated, power is applied at time t0; and the half-bridge circuit 402, resonant network 104, and auxiliary power supply device 404 can operate in an instantaneous state (i.e., in the powered-on state) between times t0 and tss. After time tss, the half-bridge circuit 402, resonant network 104, and auxiliary power supply device 404 can transition to a steady state (i.e., operate in steady state).

[0115] Furthermore, and in accordance with the teachings of this document, waveforms 505 and 506 can respectively exemplify providing control signals V to switch paths 121 and 122. C1 and V C2 Methods and / or sequences. For example, control circuit 303 may be based at least in part on, but not limited to, the low-side holding voltage V. CLS The value and / or bootstrap voltage V CHS The value of the state provides the control signal V. C1 Control signal V C2 This can be provided by control circuit 302; and as discussed above with respect to Figure 3, it can be relative to (i.e., reference) the half-bridge voltage V. X Provide control signal V C2 .

[0116] Between time t0 and time t1, there may be a second switching path 122 and a high-side capacitor C. BHSof the resonant network 104. As illustrated by the waveform 506, between the time to and the time tl, the control signal V C2 may ramp up (i.e., increase) to a value V2M (e.g., five volts) relative to the half-bridge voltage V X . In response, the second switch path 122 can conduct the current I2 by way of a switch (e.g., switch SW2) and / or a NFET (e.g., NFET M2). For example, as illustrated by the waveform 504, between the time to and the time tl, the current I2 increases to a value I2M (e.g., two milliamps).

[0117] Furthermore, as illustrated by the waveform 505, a low control signal V C1 (e.g., ground and / or zero volts) can be applied by the control circuit 303. Accordingly, the first switch path 121 can block the current II by way of the switch SW1 and / or the NFET Ml; and as illustrated by the waveform 503, the current II remains low (i.e., substantially equal to zero). Because the first switch path 121 blocks the current II, the current I2 can be provided to the resonant network 104 and can contribute to the current I X .

[0118] Accordingly, between the time to and the time tl, the half-bridge voltage V X may increase by way of a capacitive divider formed by the high-side capacitor C BHS and the resonant capacitor C RES ; accordingly, the waveform 501 (i.e., the half-bridge voltage V X ) can increase toward a value VXY. Meanwhile, the bootstrap voltage V CHS may also increase by way of a capacitive divider of the high-side capacitor C BHS and the resonant capacitor C RES ; and as illustrated by the waveform 502, the bootstrap voltage V CHS may approach a value VHY (e.g., seven volts).

[0119] Furthermore, as illustrated by the waveform 504, as the half-bridge voltage V X approaches the value VXY, the current I2 can decay according to any impedance presented by the circuit path including the second switch path 122, the high-side capacitor C BHS , and the resonant network 104.

[0120] The value VXY can be determined, at least in part, by the input voltage V IN and the bootstrap voltage V CHS . For example, according to circuit theory, the value VXY can be substantially equal to the value of the input voltage VIN minus the bootstrap voltage V CHSand subtract any bootstrap voltage across the second switching path 122. As discussed above, the value VHY (e.g., seven volts) can be too low for steady state operation; and in accordance with the teachings herein, the switching paths 121 and 122 can be used to increase the bootstrap voltage V CHS .

[0121] As illustrated by the waveforms 501-506, between the time tl and the time t2, the low control signal V C1 may continue to be applied; and the high control signal V C2 may continue to be applied (i.e., to the value V2M). Thus, the bootstrap voltage V CHS may continue to be limited to the value VHY while the half-bridge voltage V X maintains the value VXY. Further, the current I2may continue to decay towards zero (i.e., zero milliamps) while the current II remains at zero (i.e., zero milliamps).

[0122] In accordance with the teachings herein, at the time t2, the high control signal V C1 may be applied such that the first switching path 121 requires more current II than can be provided by the second switching path 122. For example, at the time t2, the control circuit 303 can apply the control signal V CHS to the value VI M (e.g., five volts) based on a status condition including, but not limited to, the value (e.g., the value VHY) of the bootstrap voltage V X and / or the value (e.g., the value VXY) of the half-bridge voltage V C1 . Thus, as illustrated by the waveform 501, at the time t2, the first switching path 121 can pull the half-bridge voltage V X to a low voltage (e.g., zero volts).

[0123] As illustrated by the waveforms 505 and 506, between the time t2 and the time t3, the control signal V C1 may be applied to the value VI M; and the control signal V C2 may be applied to the value V2M. In accordance with the teachings herein, the first switching path 121 can be configured to require (i.e., sink) more current II than can be supplied (i.e., sourced) by the second switching path 122.

[0124] As illustrated by the waveform 502, the bootstrap voltage V CHS may increase to a peak value VHP (e.g., twelve volts) at the time t3. In response, the low control voltage V C2 may be applied by the control circuit 302 (i.e., the waveform 506). From the time t3 to the time t6, the high control signal V C1 is applied; and the first switching path 121 and the second switching path 122 can sink the bootstrap voltage VCHS maintained (i.e., regulated) to the peak VHP. For example, as exemplified by waveforms 502-506, from time t3 to time t6, the bootstrap voltage V CHS may be limited to the peak VHP in response to the control circuit 302 changing state at times t4 and t5.

[0125] At time t6, the control circuit 303 can apply a low control signal V C1 to the third switch path 123 based on the state condition. For example, in response to the bootstrap voltage V CHS and / or the low-side hold voltage V CLS having reached a sufficient voltage level, the low control signal V C1 may be applied at time t6. Further, after reaching steady state, the control circuit 303 can continue to apply the low control signal V C1 in accordance with the teachings herein.

[0126] At time t7, the low-side driver 133 and the high-side driver 132 can have sufficient voltage for providing (i.e., driving) the gate signals GL and GH. Thus, at time t7, the half-bridge voltage V X (i.e., waveform 501) begins to switch to a higher value VXM. It can be appreciated that, in steady state, the value VXM can depend at least in part on the steady state value of the low-side hold voltage V CLS . Further, the value VXM can be greater than the value VXY. For example, the value VXY can be seventy-five percent of the value VXM.

[0127] Waveform 509 can also exemplify a method and / or sequence of providing a control signal V C3 to the third switch path 123 (e.g., third switch path 123d) in accordance with the teachings herein. The control signal V C3 may be provided by the control circuit 301 and / or the control circuit 311; further, the third switch path 123 (e.g., switch path 123d) can be configured to provide a current I3 in accordance with the low-side hold voltage V CLS (i.e., waveform 507). As discussed above, providing the current I3 in accordance with the hold voltage V CLS and thus the current I CLS may advantageously provide short-circuit protection and / or thermal overload protection to components of the third switch path 123.

[0128] Between times t0 and tll, the control signal V C3 (i.e., waveform 509) increases to a value V3Y (e.g., two volts); and the low-side hold voltage V CLS (i.e., waveform 507) increases to a threshold VLY (e.g., seven volts). Between times tll and t12, the control signal V C3The low-side hold voltage V CLS can transition to a value V3M (e.g., five volts) in response to reaching the threshold VLY. Further, between time t11 and time t12, the low-side hold voltage V CLS can increase from the threshold VLY (e.g., seven volts) to the peak VLP (e.g., twelve volts).

[0129] According to the teachings herein, the switch path 123 can be configured to block the current I3 (i.e., open circuit) in response to the low-side hold voltage V CLS providing the current I3 (i.e., waveform 508). For example, between time to and time t11, when the hold voltage V CLS is less than the threshold VLY, the current I3 can be limited to a value I3Y (e.g., two milliamps). For times greater than time t11, when the hold voltage V CLS is greater than the threshold VLY and less than the peak VLP, the current I3 can be limited to a value I3M (e.g., ten milliamps). Thus, the current I3 follows a step function of the voltage V CLS .

[0130] At time t12, in response to the hold voltage V CLS reaching its peak VLP, the control circuit 301 and / or the control circuit 311 can apply the low control signal V C3 . From time t12 to time tss, the third switch path 123 can maintain (i.e., regulate) the low-side hold voltage V CLS to the peak VLP. For example, as exemplified by waveforms 507-509, from time t12 to time tss, in response to the comparator 303 changing state at time t12-t16, the low-side hold voltage V CLS can be limited to the peak VLP.

[0131] After time tss, the half-bridge voltage V X continues to switch in steady state; and according to the teachings herein, the switch paths 121-123 can be configured to block the currents I1-I3 (i.e., open circuit). In steady state, the auxiliary supply 404 can provide the low-side hold voltage V CLS ; and according to the switching cycle of the waveform 501, the bootstrap diode DB can recover the bootstrap voltage V CHS .

[0132] For example, as exemplified by waveform 507, at time tss, the auxiliary supply 404 can provide the low-side hold voltage V CLS to reach a steady state value VLM (e.g., eighteen volts). Because the steady state value VLM is greater than the peak VLP (i.e., the value limited by the control circuit 301 and / or the control circuit 311), the low control signal V C3 is applied (i.e., waveform 509).

[0133] Similarly, bootstrap diode DB can recycle bootstrap voltage V CHS (i.e., waveform 502) to reach a steady state value VHM(e.g., relative to half-bridge voltage V X of eighteen volts). Because steady state value VHMis greater than peak value VHP(i.e., the value limited by control circuit 302), low control signal V C2 (i.e., waveform 506) is also applied.

[0134] Although Figure 5 waveforms 501-509 are shown in accordance with an embodiment of a half-bridge circuit (e.g., half-bridge circuit 402), other configurations and waveforms are possible. For example, in another embodiment, second switch path 122 can also be configured to provide current I2in accordance with bootstrap voltage V BHS In this way, similar to third switch path 123, second switch path 122 can also benefit thermal overload protection of its components (e.g., JFET Q2).

[0135] Figure 6A Conceptual block diagram 600 illustrates operating a resonant converter (e.g., LLC converter 100) during a power-up state in accordance with an embodiment. Conceptual block diagram 600 includes element 602 and element 604. Element 602 includes the concept of providing a high-side charging current (i.e., current I2and / or current I CHS and element 604 includes the concept of diverting a shunt current (i.e., current II). As described herein, during power-up, a first switch path (e.g., any of first switch paths 121, 121a-c) can be configured to require (i.e., absorb) current II. Meanwhile, a second switch path (e.g., any of second switch paths 122, 122a-c) can be configured to supply (i.e., source) current I2. In accordance with the teachings herein, when the requirement for current IIexceeds the supply of current I2, then current I CHS may be sufficient to charge bootstrap capacitor C BHS with sufficient bootstrap voltage V CHS for high-side driver 132.

[0136] Figure 6B Conceptual block diagram 610 illustrates operating a resonant converter (e.g., LLC converter 100) during a power-up state in accordance with an embodiment of Figure 6A Conceptual block diagram 610 includes element 612 and element 614.

[0137] Element 612 can correspond to the additional result of conceptual block diagram 600: namely, resonant capacitor voltage (i.e., voltage V CRES). Element 612 can also relate to the condition of conceptual block diagram 600: that is, the need for current II exceeds the supply of current I2. According to the teachings herein, when the need for current II exceeds the supply of current I2, the resonant capacitor voltage V CRES may be reduced such that the resonant capacitor C RES does not interfere with the charging of the bootstrap capacitor C BHS .

[0138] Element 614 can also correspond to an additional result of conceptual block diagram 600: that is, the bootstrap voltage V CHS may be increased. According to the teachings herein, when the need for current II exceeds the supply of current I2, the current I CHS may sufficiently charge the bootstrap capacitor C BHS to supply (that is, increase) an adequate bootstrap voltage V CHS for the high-side driver 132.

[0139] Although conceptual block diagram 600 has been described with respect to a resonant converter (that is, LLC converter 100), other switching converters are possible. For example, as described above, the elements of conceptual block diagram 600 and conceptual block diagram 610 can be applied to other switching converters in which the half-bridge circuit 102 is electrically coupled to a network having a capacitive element, such as the capacitive elements of resonant network 204. The teachings herein can also be applied, for example, to an LCC converter.

[0140] The above description of illustrated embodiments of the disclosure, including what is described in the abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific implementations and embodiments are described herein for illustrative purposes, various equivalent modifications are possible of the systems, apparatuses, and / or methods as described, without departing from the more broad spirit and scope of the disclosure. Indeed, it will be apparent to one of ordinary skill in the art, viewing the above teachings, that further modifications that will come to mind and / or are desired to adapt the general principles of the disclosure to a particular implementation or embodiment. Accordingly, it is intended that the scope of the disclosure be governed solely by the appended claims, and not by the detailed description, which serves only to explain the preferred embodiments.

[0141] While the application is defined in the claims, it is understood that the application can alternatively be defined according to the following embodiments.

[0142] Example 1: A half-bridge circuit (e.g., half-bridge circuit 102) electrically coupled to a resonant network, the half-bridge circuit comprising: a high-side device, a low-side device, and a first switching path. The low-side device is electrically coupled to the high-side device. The first switching path is electrically coupled to the low-side device. For example, the first switching path can be electrically coupled to a drain of the low-side device. During a power-up state (i.e., power-up), the first switching path is configured to divert a shoot-through current (e.g., current II) from the resonant network.

[0143] Example 2: The half-bridge circuit of example 1, wherein the first switching path comprises a field-effect transistor (e.g., JFET Ql and / or NFET Ml).

[0144] Example 3: The half-bridge circuit of example 2, wherein the field-effect transistor is a junction field-effect transistor (e.g., JFET Ql).

[0145] Example 4: The half-bridge circuit of any one of the preceding examples, wherein the first switching path comprises a diode (e.g., diode Dl).

[0146] Example 5: The half-bridge circuit of any one of the preceding examples, wherein the first switching path comprises a switch (e.g., switch SWl).

[0147] Example 6: The half-bridge circuit of any one of the preceding examples, wherein during the power-up state, the first switching path is configured to divert the shoot-through current to reduce a resonant capacitor voltage (e.g., voltage V CRES ).

[0148] Example 7: The half-bridge circuit of any one of the preceding examples, wherein during a steady state, the first switching path is configured to be open.

[0149] Example 8: The half-bridge circuit of any one of the preceding examples, further comprising: a high-side capacitor (i.e., bootstrap capacitor C BHS ) and a second switching path. The second switching path is configured to provide a high-side charging current (e.g., current II CHS ) to the high-side capacitor.

[0150] Example 9: The half-bridge circuit of any one of the preceding examples, wherein the high-side capacitor is configured to provide a high-side voltage (e.g., bootstrap voltage V CHS ), and wherein the first switching path is configured to divert the shoot-through current to increase the high-side voltage.

[0151] Embodiment 10: The half-bridge circuit according to any of the preceding embodiments, wherein the second switch path is configured to provide the high-side charge current from the high-side voltage.

[0152] Embodiment 11: The half-bridge circuit according to any of the preceding embodiments, wherein the second switch path comprises a field effect transistor (e.g., JFET Q2 and / or NFET M2).

[0153] Embodiment 12: The half-bridge circuit according to any of the preceding embodiments, wherein the field effect transistor is a junction field effect transistor (e.g., JFET Q2).

[0154] Embodiment 13: The half-bridge circuit according to any of the preceding embodiments, wherein the second switch path comprises a diode (e.g., diode D2).

[0155] Embodiment 14: The half-bridge circuit according to any of the preceding embodiments, wherein the second switch path comprises a switch (e.g., switch SW2).

[0156] Embodiment 15: The half-bridge circuit according to any of the preceding embodiments, wherein during the power-up state, the second switch path is configured to regulate the high-side voltage.

[0157] Embodiment 16: The half-bridge circuit according to any of the preceding embodiments, wherein during steady state, the second switch path is configured to be open.

[0158] Embodiment 17: The half-bridge circuit according to any of the preceding embodiments, further comprising a low-side hold capacitor (i.e., low-side capacitor C BLS ) and a third switch path. The third switch path is configured to provide a low-side charge current (i.e., current I CLS ) to the low-side hold capacitor.

[0159] Embodiment 18: The half-bridge circuit according to any of the preceding embodiments, wherein the low-side hold capacitor is configured to provide a low-side hold voltage (i.e., voltage V CLS ).

[0160] Embodiment 19: The half-bridge circuit according to any of the preceding embodiments, wherein the third switch path is configured to provide the low-side charge current from the low-side hold voltage.

[0161] Embodiment 20: The half-bridge circuit according to any of the preceding embodiments, wherein during the power-up state, the third switch path is configured to regulate the low-side hold voltage.

[0162] Embodiment 21 : The half-bridge circuit according to any of the preceding embodiments, wherein the third switch path comprises a field effect transistor.

[0163] Embodiment 22: The half-bridge circuit according to embodiment 19, wherein the field effect transistor is a junction field effect transistor (e.g., JFET Q3).

[0164] Embodiment 23: The half-bridge circuit according to any of the preceding embodiments, wherein the third switch path comprises a diode (e.g., diode D3).

[0165] Embodiment 24: The half-bridge circuit according to any of the preceding embodiments, wherein the third switch path comprises a switch (e.g., switch SW3).

[0166] Embodiment 25: The half-bridge circuit according to any of the preceding embodiments, wherein during steady state, the third switch path is configured to be open.

[0167] Embodiment 26: A method of operating a resonant converter during a power-up state, comprising: providing a high-side charging current to a high-side capacitor; and diverting a shunt current (e.g., current II) from a resonant network.

[0168] Embodiment 27: The method according to any of the preceding embodiments, wherein diverting the shunt current from the resonant network comprises: reducing a resonant capacitor voltage.

[0169] Embodiment 28: The method according to any of the preceding embodiments, further comprising: increasing a high-side voltage of the high-side capacitor (i.e., element 614).

[0170] Embodiment 29: The method according to any of the preceding embodiments, wherein providing the high-side charging current to the high-side capacitor comprises: regulating a high-side voltage.

[0171] Embodiment 30: The method according to any of the preceding embodiments, wherein the high-side voltage is twelve volts.

[0172] Embodiment 31 : The method according to any of the preceding embodiments, further comprising: providing a low-side charging current to a low-side hold-up capacitor.

Claims

1. A half-bridge circuit, the half-bridge circuit being electrically coupled to a resonant network, the resonant network including a resonant capacitor, the half-bridge circuit comprising: High-side device driven by high-side driver (132); A low-side device driven by a low-side driver (133), the low-side device being electrically coupled to the high-side device; A first switching path, which is electrically coupled to the low-side device and provides a current flow path in parallel with the low-side device; A high-side bootstrap capacitor is coupled to cyclically supply power to the high-side driver and form a capacitive voltage divider with the resonant capacitor; as well as A second switching path is configured to provide a high-side charging current to the high-side bootstrap capacitor. During the power-on state, the first switching path is configured to require a shunt current greater than the high-side charging current, wherein the shunt current is required simultaneously with providing the high-side charging current to the high-side bootstrap capacitor when the low-side device is driven to conduct, and the first switching path is coupled to divert the shunt current away from the resonant network to reduce the resonant capacitor voltage.

2. The half-bridge circuit according to claim 1, wherein the first switching path comprises a field-effect transistor.

3. The half-bridge circuit according to claim 2, wherein the field-effect transistor is a junction field-effect transistor.

4. The half-bridge circuit of claim 1, wherein the first switching path includes a diode coupled to block current flowing through the first switching path under reverse bias.

5. The half-bridge circuit according to claim 1, wherein the first switching path includes a switch.

6. The half-bridge circuit of claim 1, wherein the first switching path is configured to be open during steady state.

7. The half-bridge circuit of claim 1, wherein the high-side bootstrap capacitor is configured to provide a high-side voltage; and wherein the first switching path is configured to divert the shunt current to increase the high-side voltage.

8. The half-bridge circuit of claim 7, wherein the second switching path is configured to provide the high-side charging current based on the high-side voltage.

9. The half-bridge circuit of claim 7, wherein the second switching path comprises a field-effect transistor.

10. The half-bridge circuit according to claim 9, wherein the field-effect transistor is a junction field-effect transistor.

11. The half-bridge circuit of claim 7, wherein the second switching path includes a diode coupled to block current flowing through the second switching path under reverse bias.

12. The half-bridge circuit of claim 7, wherein the second switching path comprises a switch.

13. The half-bridge circuit of claim 7, wherein during the power-on state, the second switching path is configured to regulate the high-side voltage.

14. The half-bridge circuit of claim 7, wherein the second switching path is configured to be open during steady state.

15. The half-bridge circuit according to claim 1, further comprising: Low-side holding capacitor; as well as A third switching path is configured to provide a low-side charging current to the low-side holding capacitor.

16. The half-bridge circuit of claim 15, wherein the low-side holding capacitor is configured to provide a low-side holding voltage.

17. The half-bridge circuit of claim 16, wherein the third switching path is configured to provide the low-side charging current based on the low-side holding voltage.

18. The half-bridge circuit of claim 16, wherein during the power-on state, the third switching path is configured to regulate the low-side holding voltage.

19. The half-bridge circuit of claim 15, wherein the third switching path comprises a field-effect transistor.

20. The half-bridge circuit of claim 19, wherein the field-effect transistor is a junction field-effect transistor.

21. The half-bridge circuit of claim 15, wherein the third switching path includes a diode coupled to block current flowing through the third switching path under reverse bias.

22. The half-bridge circuit of claim 15, wherein the third switching path includes a switch.

23. The half-bridge circuit of claim 15, wherein the third switching path is configured to be open during steady state.

24. A method of operating a resonant converter during a powered-on state, the resonant converter including a resonant capacitor, the method comprising: High-side charging current is supplied to the high-side bootstrap capacitor, while the low-side devices are driven to conduct. When the low-side device is driven to be turned on, it provides the high-side charging current to the high-side bootstrap capacitor, while requiring a shunt current greater than the high-side charging current. as well as The shunt current is diverted from the resonant network to reduce the voltage of the resonant capacitor.

25. The method of claim 24, further comprising: Increase the high-side voltage of the high-side bootstrap capacitor.

26. The method of claim 24, wherein providing the high-side charging current to the high-side bootstrap capacitor comprises: Adjust the high-side voltage.

27. The method of claim 26, wherein the high-side voltage is twelve volts.

28. The method of claim 24, further comprising: Provide low-side charging current to the low-side holding capacitor.

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