Network on chip (noc) with flexible data width

Abstract

The techniques described herein can relate to providing a programmable interconnection network (e.g., a programmable network-on-chip (NOC)). A method can include determining a transmission parameter, combining one or more lanes of the interconnection network based at least in part on the transmission parameter, and power gating any unused lanes after the combining.

Description

Background Technology

[0001] This disclosure generally relates to network-on-chip (NOC) circuitry for integrated circuit devices, and more particularly to network-on-chip (NOC) capable of flexibly supporting different data widths.

[0002] This section is intended to introduce the reader to various aspects of the field in relation to the various aspects of this disclosure, which are described below and / or claimed. It is believed that this discussion will help provide the reader with background information to facilitate a better understanding of the various aspects of this disclosure. Therefore, it should be understood that these statements are to be read in this context and not as an admission of prior art.

[0003] Advances in microelectronics have enabled ever-increasing transistor density in various integrated circuit devices. Indeed, some advanced integrated circuits (such as field-programmable gate arrays (FPGAs) or other programmable logic devices) can include a large number of transistors, enabling an increasingly wide variety of programmable circuit designs that can implement a large number of different functions. In some programmable logic devices, data can be packetized and routed to or from these different functions using data transmission protocols via a fixed interconnect network circuit called a network on chip (NOC). However, because the circuit design of the programmable logic device may not be known in advance, the NOC can be designed based on the possible use cases of the future circuit design. Therefore, for example, if the NOC does not have sufficient bandwidth for certain broadband protocols, it may not be able to accommodate those protocols. Similarly, when the circuit design uses a protocol with a bandwidth less than that of the NOC, the NOC may be underutilized. This underutilization can lead to inefficiencies in FPGA designs and result in higher power consumption. Attached Figure Description

[0004] The advantages of this disclosure will become apparent when reading the following detailed description and when referring to the accompanying drawings, in which:

[0005] Figure 1 This is a block diagram of a computing system, according to an embodiment, that can be used to program an integrated circuit system having a programmable interconnect network;

[0006] Figure 2 According to the embodiments Figure 1 A block diagram of an integrated circuit;

[0007] Figure 3 It is programmed by a computing system according to the embodiment. Figure 1 A block diagram of an integrated circuit system;

[0008] Figure 4 This is according to an embodiment, such as that used in a field-programmable gate array (FPGA). Figure 3 A block diagram illustrating examples of programmable logic architectures and programmable interconnect networks;

[0009] Figure 5A According to the embodiments Figure 3 A block diagram of a generalized example of a programmable interconnect network;

[0010] Figure 5B According to the embodiment, data packets are acquired in the first instance and used to transmit data packets through logically bonded data channels. Figure 5A A block diagram of a programmable interconnect network;

[0011] Figure 5C According to the embodiment, data packets are acquired at a second time and used to transmit data packets through logically combined data channels. Figure 5A A block diagram of a programmable interconnect network;

[0012] Figure 6 According to the embodiments and Figure 5A A block diagram of a bridge associated with a programmable interconnect network;

[0013] Figure 7 According to the embodiments Figure 3 A schematic representation of an example programmable interconnect network;

[0014] Figure 8 According to the embodiments Figure 3 Another example is a schematic representation of a programmable interconnect network;

[0015] Figure 9A According to the embodiments Figure 8 A schematic representation of a sample configuration of a programmable interconnect network;

[0016] Figure 9B According to the embodiments Figure 8 A schematic representation of a sample configuration of a programmable interconnect network;

[0017] Figure 10 According to the embodiments Figure 8 A schematic representation of a sample configuration of a programmable interconnect network;

[0018] Figure 11 According to the embodiments Figure 8 A schematic representation of a sample configuration of a programmable interconnect network; and

[0019] Figure 12 It is used to determine according to the embodiments. Figure 8 A method for configuring a programmable interconnect network. Detailed Implementation

[0020] One or more specific embodiments of this disclosure will now be described. While aiming to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be understood that, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as complying with system-related and business-related constraints, which may vary from implementation to implementation. Moreover, it should be understood that such development efforts can be complex and time-consuming, but will still be routine tasks of design, fabrication, and manufacturing for those skilled in the art who benefit from this disclosure. The techniques proposed and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that do indeed improve the art and are therefore not abstract, intangible, or purely theoretical.

[0021] When describing elements of various embodiments of this disclosure, the articles “a (a, an)” and “described” are intended to mean the presence of one or more of the stated elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that additional elements may exist in addition to the listed elements. Furthermore, it should be understood that references to “an embodiment” or “an embodiment” in this disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the stated features. Additionally, the phrase “A based on B” is intended to mean that A is at least partially based on B. Moreover, unless explicitly stated otherwise, the term “or” is intended to be inclusive (e.g., logical OR) rather than exclusive (e.g., logical XOR). In other words, the phrase “A or B” is intended to mean A, B, or both A and B.

[0022] Programmable logic devices, such as Field-Programmable Gate Arrays (FPGAs), are advanced integrated circuits (they have proven their value for processing operations), and consequently, many new use cases for programmable logic devices have been developed and emerged. Data can be routed to or from different areas of a programmable logic device using fixed interconnect network circuitry called a network on-chip (NOC). However, programmable logic devices, as well as other integrated circuits, may not fully utilize fixed interconnect networks.

[0023] Programmable interconnect networks with flexible data paths (e.g., network-on-a-chip (NOC)) can support a wide range of possible bandwidths, resulting in more efficient utilization and scalability, and allowing integrated circuit manufacturers to meet Quality of Service (QoS) metrics and / or design parameters (e.g., where customers can specify desired bandwidth or transmission characteristics). For example, if an interconnect uses a fixed data path width of 64 bytes (64B) and transmits a payload with a width of 16 bytes (16B) using that fixed data path width, the interconnect is considered underutilized, and power and / or resources may be wasted. In contrast, a programmable interconnect network with programmable data path widths can be programmed to allocate higher or lower data path widths for integrated circuit-based applications.

[0024] A programmable interconnect network may include one or more data paths (the type of data transmitted based on the data path is also referred to as a data channel and / or address channel), and data may be transmitted between one or more circuit elements of an integrated circuit via the data paths. For example, one or more data paths may transmit data between one or more application functional units programmed into a programmable logic architecture. Application functional units may encapsulate transactions into data packets (e.g., command packets), and may use a bridge circuit system and the transport layer of the programmable interconnect network to send the data packets to additional application functional units or other components. In this way, the bridge circuit system may be located within or on the boundary between the application functional unit that generates the data and the programmable interconnect network. Note that in circuits such as application-specific integrated circuits (ASICs) or other programmable circuits besides programmable logic devices, the application functional unit may be a circuit system that generates data to be transmitted to other circuit systems via the programmable interconnect network.

[0025] Routers in a programmable interconnect network can be logically combined based on transmission parameters (e.g., based on an expected transmission pattern) associated with data to be transmitted between application functional units. This logical combination can be accomplished during configuration of the programmable interconnect network based on the transmission parameters. Individual routers can be programmed during configuration time to have a master or slave configuration. The routers then work together (e.g., a master router with one or more slave routers) to transmit received data packets following a lockstep transmission format. Transmission parameters may include, for example, transmission direction, power and / or delay considerations, transmission bandwidth associated with the data to be transmitted, and / or prioritization indications describing which corresponding transmission parameter should be prioritized, or the like. Transmission parameters can be derived by software during the circuit design process, or can be included as indications in a document, or incorporated as part of a circuit design to be optimized, placed, and / or routed. In this way, transmission parameters can be at least partially based on transmission direction indications, destination application functional unit indications, destination location indications, power considerations, delay considerations, and / or prioritization indications, or the like.

[0026] Routers and associated data paths are logically combined, at least in part, based on transmission parameters that define the transmission characteristics of data to be transferred between routers (e.g., from one application functional unit to another). Thus, more data channels can be combined to transmit data with relatively large bandwidth, while fewer data paths can be combined to transmit data with smaller bandwidth. These implementations described herein can be implemented in programmable logic devices (e.g., FPGAs), application-specific integrated circuits (ASICs), or any other suitable device (e.g., a suitable processor that executes instructions to implement the programmable interconnect network implementation of this disclosure).

[0027] Considering the foregoing, Figure 1 The diagram illustrates a block diagram of a system 10 that can be used to program integrated circuit 12. Integrated circuit 12 may be reconfigurable (e.g., an FPGA) or may be an application-specific integrated circuit (ASIC). A user may use design software 14 (such as a version of Intel® Quartus) to implement the circuit design to be programmed onto integrated circuit 12.

[0028] Design software 14 may be executed by one or more processors 16 of computing system 18. Computing system 18 may include any suitable device capable of executing design software 14, such as a desktop computer, laptop computer, mobile electronic device, server, or the like. Computing system 18 may access, configure, and / or communicate with integrated circuit 12. The processors 16 may include multiple microprocessors, one or more other integrated circuits (e.g., ASICs, FPGAs, reduced instruction set processors, and the like), or some combination of these devices.

[0029] One or more memory devices 20 may store design software 14. Additionally, the memory devices 20 may store information related to integrated circuit 12, such as control software, configuration software, lookup tables, configuration data, etc. In some embodiments, the processors 16 and / or the memory devices 20 may be external to the computing system 18. The memory devices 20 may include tangible, non-transitory machine-readable media, such as volatile memory (e.g., random access memory (RAM)) and / or non-volatile memory (e.g., read-only memory (ROM)). The memory devices 20 may store a variety of information that can be used for various purposes. For example, the memory devices 20 may store machine-readable and / or processor-executable instructions (e.g., firmware or software) that are executed by the processors 16, such as instructions for determining the speed of integrated circuit 12 or regions of integrated circuit 12, determining the criticality of paths to designs programmed in integrated circuit 12 or regions of integrated circuit 12, programming designs in integrated circuit 12 or regions of integrated circuit 12, and such instructions. One or more memory devices 20 may include one or more storage devices (e.g., non-volatile storage devices), which may include read-only memory (ROM), flash memory, hard drives, or any other suitable optical, magnetic, or solid-state storage media, or any combination thereof.

[0030] Design software 14 can use compiler 22 to generate low-level circuit design programs 24 (bitstreams), sometimes referred to as program object files, which program integrated circuit 12. That is, compiler 22 can provide integrated circuit 12 with machine-readable instructions representing the circuit design. For example, integrated circuit 12 can receive one or more programs 24 as bitstreams describing the hardware implementation that should be stored in integrated circuit 12. Program 24 (bitstreams) can be programmed into integrated circuit 12 as program configuration 26.

[0031] The controller can receive program 24 (bit stream) and operate according to program 24 (bit stream) to configure integrated circuit 12. For example, as Figure 2 As depicted, integrated circuit 12 may be an FPGA that can be reconfigured according to program 24 (bit stream) to perform a wide range of tasks and / or functions.

[0032] Figure 2 yes Figure 1 The diagram illustrates an integrated circuit 12 and includes a programmable interconnect network 28 (e.g., a network on-chip (NOC)) and a programmable logic architecture 30 that is programmable (and reprogrammable) based on program 24 (bitstream). The programmable logic architecture 30 may include multiple programmable logic elements having operations defined by a configuration memory (e.g., configuration random access memory (CRAM)). Programmable logic elements may include lookup tables, registers, multiplexers, routing wires, etc. Designers can program the programmable logic architecture 30 to perform a variety of desired functions. The programmable interconnect network 28 and the programmable logic architecture 30 may be programmed at similar or simultaneous times. Parts or regions of the programmable logic architecture 30 may be programmed to perform copies of the same function and / or different functions. Sometimes, the programmable logic architecture 30 is programmed to interact with other circuit systems via interconnect boundary circuit systems 31 and interconnect blocks 32. Other circuitry may include any combination of the following: memory, transceiver, ASIC, and / or any suitable circuitry other than programmable logic architecture 30 that can be used to perform processing or functional operations associated with integrated circuit 12. Programmable interconnect network 28 can be used to facilitate memory transactions between multiple sectors, between multiple dies, and / or between integrated circuit 12 and external systems. Programmable interconnect network 28 can be further used to decrypt configuration program (bitstream) 24 (e.g., configuration data), to locally order reads and writes for on-memory error detection and correction, and / or to order test control signals to implement various test modes.

[0033] As described above, the programmable logic architecture 30 can have two independently programmable parts: part 33A and part 33B. Part 33A can perform processing operations separately from part 33B. The processing operations of part 33A can be unique and therefore different from the processing operations of part 33B. In some cases, parts 33A can transfer data between each other to complete the processing operations. For example, part 33A can identify faces in an image, and part 33B can perform processing on images other than faces. In this way, it may be desirable to transfer data from part 33A to part 33B to complete the processing operations.

[0034] Two methods may exist for performing this operation. A first technique may be used to send data from part 33A to part 33B via data path 34 of programmable interconnect network 28. A second technique may be used to send data from part 33A to part 33B via data path 35 of programmable logic configuration 30. Using data path 35 may be a slower and less efficient method of transferring data from part 33A to part 33B. Furthermore, data path 35 may use valuable programmable logic configuration 30 in the path, making it a more costly option than data path 34 of programmable interconnect network 28. Part 33A may transfer data to data path 34 via interconnect boundary circuit system 31. As will be appreciated, interconnect boundary circuit system 31 may include various circuits for facilitating the grouping and / or transfer of data between parts 33. For example, interconnect boundary circuit system 31 may be coupled to application function units of integrated circuit 12, and bridge circuit systems may be used to transfer data between part 33 and programmable interconnect network 28.

[0035] like Figure 3 As shown, integrated circuit 12 can operate within data processing system 36 to assist in processing dataset 38. Data processing system 36 can represent, for example, a computing device in a data center that can process network traffic, image data, video data, financial data, or any other suitable form of data. In some examples, machine learning or neural network algorithms can be used to process dataset 38, employing the programmable interconnect network 28 of this disclosure to transfer and pass data within integrated circuit 12 and / or data processing system 36 from a first location to a second location. Processor complex 40 can execute instructions (e.g., software or firmware) stored in memory 42 to receive and route dataset 38, and to control integrated circuit 12. For example, processor complex 40 can run software to analyze and process network traffic, image data, video data, financial data, or any other suitable form of data, thereby offloading operations best suited for processing on integrated circuit 12 to integrated circuit 12. The memory 42 may store one or more programs 24 (bit streams) that can be used to program the programmable logic configuration 30 of the integrated circuit 12 (e.g., when the integrated circuit 12 is a programmable logic device (PLD), such as an FPGA).

[0036] Figure 4This is a block diagram depicting a programmable interconnect network 28, one or more routers 62, one or more physical paths 64 (e.g., data channels), and interconnect boundary circuit systems 31, each of which includes one or more application function units (AFUs) 65 and bridges 70. The example depicted illustrates a programmable interconnect network 28 as used in a programmable logic device. Each of the AFUs 65 represents a programmable function of the programmable logic device and is therefore configured by loading one or more programs 24 (bit streams) into CRAM associated with logic blocks of the programmable logic architecture 30. Thus, the AFUs 65 can generate and / or receive any suitable packetized data from external circuit systems or from other AFUs 65 via the programmable interconnect network 28. In some embodiments, the programmable interconnect network 28 is deployed around the perimeter of the programmable logic architecture 30 of the integrated circuit 12. When the programmable interconnect network 28 is not integrated into the programmable logic architecture 30, the integrated circuit 12 may include circuitry for transferring packetized data from a first portion of the programmable logic architecture 30 to a second portion of the programmable logic via physical paths 64. Integrated circuit 12 may include bridge 70, which performs the function of transferring data from programmable logic architecture 30 to programmable interconnect network 28.

[0037] To facilitate data transmission between AFUs 65, one or more routers 62 can transmit data between corresponding routers 62. For example, to transmit data from bridge 70A to bridge 70D, router 62A can transmit the data to router 62B, and router 62B can then transmit the data to router 62C. Data transmission via other routers 62 can follow paths including routers 62C, 62D, 62E, 62F, and 62G.

[0038] In some embodiments, the example interconnect network may have a hardened transmission path that provides a set bandwidth. When the corresponding FPGA is programmed to have and use the interconnect network, the FPGA can use data with a bandwidth smaller than the set bandwidth. When this data is transmitted through the interconnect network, the interconnect network is considered underutilized or over-provided (e.g., as an example of over-providence) because the bandwidth of the programmable interconnect network 28 is greater than the actual bandwidth required for successful transmission. This over-providence of bandwidth in the programmable interconnect network 28 may result in less efficient data transmission, at least in terms of power consumption and utilization, because more physical paths are powered than the hardened transmission path is sufficient for transmission.

[0039] To correct this, the programmable interconnect network 28 can be programmed to have application-dependent bandwidth when configuring the programmable logic architecture 30. In this way, the router 62 can be configured to logically combine a subset of physical paths 64 to form a larger path. Thus, a larger bandwidth path can be formed from physical paths 64, each with a smaller bandwidth. The combination of physical paths 64 can be based on specific data of a specific design loaded onto the integrated circuit 12 (e.g., stored in configuration memory such as CRAM). For example, when configuring (e.g., programming) the programmable logic architecture 30 (e.g., during device configuration), it can be determined (e.g., by compiler 22 or computing system 18) that the appropriate bandwidth for the programmable interconnect network is 16 bytes for one path and 32 bytes for another. Therefore, in response to this determination, the programmable interconnect network 28 can be programmed to have 16 bytes of bandwidth for one physical path and 32 bytes of bandwidth for another, rather than the entire programmable interconnect network 28 being programmed to have 32 bytes of bandwidth.

[0040] Although Figure 4 Specific use cases for the programmable interconnect network 28 are described, but Figure 5A This is a block diagram of a generalized example of a programmable interconnect network 28. Therefore, the depicted programmable interconnect network 28 can be used in a variety of embodiments. As described above, each of the routers 62 is interconnected with each other and connected to the bridge 70 to form the programmable interconnect network 28. Each router can be individually configurable to provide logical combinations. For example, during the configuration of integrated circuit 12, each router can be programmed as a master router or a slave router based on the number and pattern of logical combinations to be made by physical paths 64.

[0041] During operation and after configuration, one or more of the AFUs 65 can transmit data to the programmable interconnect network 28 via a bridge 70 coupled to the transmitting AFU 65. The bridge 70 is operable to transmit a data clock input (e.g., based on a clock signal defining the transmission time) from data packets to the programmable interconnect network 28. Upon receiving packetized data, each router 62 analyzes the data, looks up an identifier associated with the data in a lookup table, and transmits the data to another router 62 or the coupled bridge 70 circuitry based on the result of the lookup table query.

[0042] In some cases, bridge 70 will transmit one or more data packets to external circuitry via interconnect block 32. For this purpose, bridge 70 transmits data to interconnect block 32. Interconnect block 32 may include circuitry for transmitting packetized data between integrated circuit 12 and external circuitry. Interconnect block 32 may assign identifiers to data packets to be decoded by router 62 at a future time during a lookup operation.

[0043] The depicted example of programmable interconnect network 28 is a generalized example of programmable interconnect network 28. In this way, the depicted programmable interconnect network 28 can be applied to a variety of network topologies. For example, programmable interconnect network 28 can be applied to mesh topologies, cube topologies, hypercube topologies, balanced and / or unbalanced tree topologies, ring topologies, split topologies, etc.

[0044] To explain in detail the operation of the programmable interconnect network 28, Figure 5B The transmission operation is performed immediately. Figure 5A A block diagram of an example programmable interconnect network 28, while Figure 5C The transmission operation is performed at the second time. Figure 5A A block diagram of an example programmable interconnect network 28. For clarity of detail, Figure 5B and Figure 5C Together Figure 5A They will be explained together in this article.

[0045] Figure 5A , Figure 5B and Figure 5C Together, they described the lockstep transmission operation. Figure 5A In this process, data packet 71 is received at interconnect block 32 and divided into smaller data packets 71A and 71B for transmission over programmable interconnect network 28. The division of data packet 71 can be based on the number of logically combined physical paths 64 of programmable interconnect network 28. Data packets 71A and 71B are transmitted to programmable interconnect network 28 via bridge 70.

[0046] Data packets 71A and 71B are transmitted from bridge 70 to target AFU 65 via router 62 using lockstep transmission. Lockstep transmission is a transmission scheme in which latency is compensated for by means of the inherent delay introduced by the arrangement of the physical path 64. For example, data packet 71A is transmitted via a combination of routers 62, the combination of which is equal to the number of routers 62 associated with the transmission of data packet 71B at the end of the transmission. Therefore, the same amount of clock delay is added to the transmission of data packet 71A before it reaches the router 62 coupled to the destination bridge 70.

[0047] With this in mind, Figure 6 This is a block diagram of bridges 70 coupled to each other via a programmable interconnect network 28 (e.g., NOC interconnect). It should be understood that additional components may be coupled between bridges 70 and programmable interconnect network 28. It should also be understood that while a particular interconnect topology is discussed herein, many other topologies can also benefit from the disclosed techniques.

[0048] Before the data packet is successfully transmitted from the first location to the second location, the data packet to be transmitted may be processed by one or more of the bridge 70 and / or other processing circuitry. For example, the destination decoder may communicate with the router 62 via an identifier to convey where the data packet will be transmitted. The router 62 may use the identifier to determine the destination address when referring to a lookup table, wherein the destination address at least partially indicates the transmission direction associated with the data packet (e.g., storage location, the slave router to which the data packet will be transmitted, or any suitable transmission direction information). In this way, the router 62 may include configurable components, such as, but not limited to, configuration memory (e.g., CRAM), and at least memory storing the lookup table.

[0049] After determining the target destination (e.g., router 62 or bridge 70), bridge 70 can transmit data packets for transmission and routing to different bridges 70. For example, data packets from bridge 70A are transmitted to bridge 70B via programmable interconnect network 28. As described above, this transmission is facilitated by transmitting data packets via router 62 through physical path 64.

[0050] The physical path 64 of the programmable interconnect network 28 may include a data channel 72 and an address channel 74. The bridge 70 may transmit the payload of data packets, the payload being at least separate from the address corresponding to the payload and stored within the data packet. The bridge 70 may transmit addresses (e.g., synthesized and decipherable by the router 62) via the address channel 74 and transmit the payload via the data channel 72.

[0051] Sometimes data transmission occurs between bridges 70. One method for coupling multiple physical paths 64 together includes using multiple point-to-point interconnects, such that each bridge 70 is coupled to every other bridge 70, as... Figure 7 As shown in the image. Figure 7 This is a schematic representation 84 of the illustrated example interconnect network 87. It should be understood that the interconnects and data paths have been simplified for ease of discussion, but any suitable components may be included together with the bridge 70 or between programmable interconnect networks 87.

[0052] In the depicted example, each of the bridges 70 can communicate with and / or facilitate data packet transmission between each other. For example, bridge 70A can communicate with bridge 70B and / or bridges 70E, 70F, 70G. Bridges 70 can communicate (e.g., transmit data packets) via point-to-point hardwired data paths 88 (e.g., channels, physical paths). In this way, some data paths remain unused for each transaction. For example, if bridge 70A wants to transmit a data packet to bridge 70B, bridge 70A transmits the payload via hardwired data path 86, which includes the aforementioned data channel 72 and address channel 74. Therefore, by using this example interconnect network 87, losses and inefficiencies may be introduced into the integrated circuit, in addition to using a relatively large number of interconnects and physical routes.

[0053] In contrast to Internet 87, Figure 8 An example of a programmable interconnect network 28 is depicted in the figure. Figure 8 This is a schematic representation of an example programmable interconnect network 28. It should be understood that the interconnects and data paths have been simplified for ease of discussion, but any suitable components for facilitating the routing and transmission of data packets, such as router 62, decoder, or any other suitable circuitry and / or processing functionality, may be included in conjunction with bridge 70 or between components of programmable interconnect network 28. Programmable interconnect network 28 may include one or more data channels 72 (e.g., 72A, 72B, 72C, 72D) and one or more address channels 74 (e.g., 74A, 74B). Each of the data channels 72 may be combined (e.g., logically combined) in any suitable subgroup combination. For example, data channel 72A and data channel 72B may be logically combined.

[0054] To emphasize the benefits associated with the combination technology, consider how a single data channel 72 can have a specific bandwidth. For example, data channel 72A could have a bandwidth of 16 bytes (16B). It should be noted that any data path in the data path (e.g., data channel 72 and / or address channel 74) can have any suitable size. When two data channels are combined, the total bandwidth can be additive. For example, if data channel 72A is combined with data channel 72B, the total bandwidth could be 32 bytes (32B). Similarly, if all four data channels 72 are combined, the total bandwidth could be 64 bytes (64B). Therefore, corresponding data channels 72 can be selectively combined with each other to transmit data packets of different bandwidths. In this way, data channels 72 sufficient for data transmission are enabled and used in data transmission.

[0055] Similarly, address channels 74 can each have a specific bandwidth, such as 8 bytes (8B). Address channels 74 can also be selectively powered when the programmable logic architecture 30 is programmed. When the compiler 22 or computing system 18 determines which channels 72, 74 are combined and which channels 72, 74 remain unused, the unused channels 72, 74 can be power-gated (e.g., the power supplied to channels 72, 74 is reduced) or their power can be removed (e.g., disconnected from the power supply of integrated circuit 12). For example, if data channel 72A was to be combined with data channel 72B, and data channels 72C and 72D remain unused, data channel 72D can be power-gated (e.g., reduced, or reduced to zero in the event of power removal). By power-gating or removing the power supplied to the unused channels among channels 72, 74, the power consumed by the programmable interconnect network 28 can be reduced, and therefore the power consumed by integrated circuit 12 is also reduced. Therefore, the benefits of using the techniques described herein include not only improved utilization of the programmable interconnect network 28, but also reduced power consumption by the programmable interconnect network 28.

[0056] Combining can be permitted using any suitable logical (e.g., logic-based) combination technique. For example, one or more corresponding data channels 72 can be combined using a master-slave technique or any suitable technique or combination thereof. The master-slave technique uses a lockstep operation to logically combine the corresponding data channels 72. The lockstep operation allows logically combined data channels 72 to transmit portions of the same data packets in parallel with each other but offset in position (as referenced above). Figure 5A , Figure 5B and Figure 5C (As described). The master-slave technique can generate a predictable output using one or more well-defined states (e.g., associated with a state machine) in response to a specific input to a particular data channel 72. More specifically, one or more routers 62 associated with the combined data channel 72 can operate in a lockstep manner, such that one or more routers 62 can output (e.g., respond) the same output as the same input. When data channels are logically combined, the same specific input to one or more logically combined routers 62 can generate the same predictable output, such that each combined data channel acts in a lockstep manner to complete (e.g., execute) a transmission. In this way, the master router 62 can receive input, generate output, and instruct one or more slave routers 62 to output the same output (e.g., where the data channel 72 receiving the instruction is a slave data channel 72) but offset in position to allow lockstep operation over time. Thus, the master router 62 and the slave router 62 transmit equivalently, thereby enabling logical combination to occur.

[0057] Considering the above, Figure 9A This is a schematic representation of a sample configuration of the programmable interconnect network 28. Figure 9B It is a diagram. Figure 9A A schematic representation of an embodiment of the sample configuration. Note that in Figure 9A or Figure 9B The sample configuration depicted can be a valid configuration that will be applied to the programmable interconnect network 28 when the programmable logic architecture 30 is configured to meet the transmission parameters of the transactions to be executed. For ease of comparison, it is described below together. Figure 9A and Figure 9B .

[0058] In this use case example, a first transaction of size 32 bytes will be sent from bridge 70B to bridge 70A, and a second transaction of size 32 bytes will be sent mutually exclusively from bridge 70C to bridge 70D. Bandwidth utilization is prioritized in both transactions, but power consumption is still taken into consideration. The compiler 22 and / or computing system 18 can determine these transmission parameters during design analysis for the configuration of the programmable logic architecture 30.

[0059] Figure 9A A first solution option is described, in which a first logical channel (e.g., a total of 32 bytes) is provided by combining data channel 72A with data channel 72B. Compiler 22 and / or computing system 18 can determine whether to power-gated or de-energize the remaining data channels (i.e., data channels 72C and 72D). Address channel 74A can be used to transmit addresses associated with transactions, and address channel 74B can be power-gated or, in some cases, de-energized. Transactions between bridges 70C and 70D can use the same combination of data channels 72A and 72B and the same address channel 74A (e.g., as shown in the image). Figure 9A (As depicted in the document). Alternatively, transactions between bridge 70C and bridge 70D can use different combined data channels.

[0060] Figure 9B A second solution option is depicted, in which a first logical channel (e.g., 32 bytes) is provided by combining data channel 72A with data channel 72B, and a second logical channel (e.g., 32 bytes) is provided by combining data channel 72C with data channel 72D. Since the separate data channels 72 are combined into separate subgroups, both address channels 74 will be used during transmission, therefore neither address channels 74A nor address channel 74B can be power-gated. Note that in this example, none of the depicted data channels 72 are power-gated or de-energized, because each data channel is used.

[0061] To illustrate another use case example, Figure 10This is a schematic representation of a sample configuration of the programmable interconnect network 28. In this use case example, a first transaction of size 32 bytes will be sent from bridge 70B to bridge 70C, a second transaction of size 16 bytes will be sent from bridge 70A to bridge 70C, and a third transaction of size 16 bytes will be sent from bridge 70E to bridge 70F. In the first transaction, bandwidth utilization and latency concerns are prioritized, while in the second and third transactions, latency concerns take precedence over bandwidth utilization. The compiler 22 and / or computing system 18 can determine these transmission parameters when analyzing the data packets to be transmitted.

[0062] The described solution includes a 32-byte logical channel and a 16-byte logical channel for three transactions. The first transaction uses the 32-byte logical channel provided by combining data channel 72A with data channel 72B. The first transaction uses address channel 74A. The second and third transactions share data channel 72C. Because two transactions (e.g., the second and third transactions) can occur without interrupting any transaction paths, the same address channel 74B and the same data channel 72C can be used. Data channel 72D can be unused and therefore can be power-gated or, in some cases, powered down.

[0063] To explain another use case example, Figure 11 This is a schematic representation of another sample configuration of the programmable interconnect network 28. In this use case example, a transaction of size 64 bytes will be sent from bridge 70B to bridge 70C, bridge 70A, and bridge 70D. For this transfer, bandwidth utilization is prioritized. Compiler 22 and / or computing system 18 can determine these transmission parameters when analyzing the data packets to be transmitted.

[0064] The depicted solution includes a 64-byte logical channel for transactions. Transactions utilize this 64-byte logical channel, provided by combining data channel 72A with data channels 72B, 72C, and 72D. The transaction is depicted as using address channel 74A. Address channel 74B may be unused and therefore can be power-gated or, in some cases, powered down. Note that in this example, none of the depicted data channels 72 are power-gated or powered down, as each data channel is in use.

[0065] To help explain the process of configuring the programmable interconnect network 28, as described above... Figure 12This is a method 90 for determining the configuration of a programmable interconnect network 28. Typically, method 90 includes: determining transmission parameters (block 92), incorporating the programmable interconnect network 28 at least in part based on the transmission parameters (block 94), and power gating any unused channels (block 96). In some embodiments, method 90 may be implemented at least in part by executing instructions stored in a tangible, non-transitory, computer-readable medium (such as memory 42) using a processing circuitry system (such as compiler 22 and / or computing system 18).

[0066] Therefore, in some embodiments, compiler 22 and / or computing system 18 may determine transmission parameters associated with the current configuration to be processed and loaded into integrated circuit 12 associated with programmable interconnect network 28 (e.g., programmable logic architecture 30) (block 92). As defined above, transmission parameters include any settings or configuration options considered when determining how to route data packets through programmable interconnect network 28 and to which bridges 70 to route the data packets. In this way, transmission parameters include transmission direction, indication of destination bridge 70 or destination location, power and / or latency considerations, transmission bandwidth associated with the data to be transmitted, or the like. In some embodiments, transmission parameters also include prioritization indications that indicate which of the transmission parameters is preferred (e.g., enforced priority) when the configuration of programmable interconnect network 28 is finally determined. Transmission parameters may be determined by one or more of the bridges 70 or any other suitable processing circuitry associated with integrated circuit 12.

[0067] After the transfer parameters are determined, compiler 22 and / or computing system 18 can combine programmable interconnect network 28 (box 94) at least in part based on the transfer parameters. Programmable interconnect network 28 is a dynamically configurable interconnect network that is selectively combined and used on a per-use basis (e.g., per-device configuration basis). In this way, programmable interconnect network 28 can be adapted to accommodate changes in transfer parameters for different device configurations. In response to a reconfiguration of programmable logic architecture 30 or a partial reconfiguration of programmable logic architecture 30, or in response to any suitable change in integrated circuit 12, the transfer parameters can be redefined and used to recombine programmable interconnect network 28. In specific use cases of FPGAs or programmable logic devices, partial reconfiguration of programmable logic architecture 30 can occur when a portion of programmable logic architecture 30 is updated with a configuration file to perform modified functionality. Therefore, the transfer parameters associated with that portion of programmable logic architecture 30 can also change with partial reconfiguration. Thus, the changed transfer parameters can be used to reprogram programmable interconnect network 28.

[0068] For example, combination based on transmission parameters may include analyzing the data bandwidth of one or more potential transactions and determining which data channels 72 are available for combination or assignment to additively create data bandwidth corresponding to the transaction with the highest bandwidth usage. Note that combination includes deciding not to combine or to self-combine, resulting in the combination of 1 data channel (e.g., refer to...). Figure 10 Data channel 72C is an example of a self-associative data channel 72. Furthermore, the associativity can be changed based on the priority of each transmission parameter. For example, with... Figure 10 The programmable interconnect network 28 depicted is used as an example. In this example, the first transaction prioritizes bandwidth, while the second and third transactions have placed lower priority on bandwidth. The combination decision is affected by this, and thus the first transaction is assigned data channels 72A, 72B and address channel 74A, while the second and third transactions have been assigned to the shared data channel 72C.

[0069] Continuing with method 90, once specific channels 72, 74 are combined based on transmission parameters, compiler 22 and / or computing system 18 can configure integrated circuit 12 to perform power gating on any unused channels 72, 74 (block 96). Power gating can occur simultaneously with the completion of a transaction (e.g., with the transmission of data via programmable interconnect network 28) (or can begin simultaneously). It should be noted that power gating refers to reducing the power supplied to any of the unused channels 72, 74. Power can be gated to zero, at which point unused channels 72, 74 can be considered de-energized. Compiler 22 and / or computing system 18 can program integrated circuit 12 to cause power gating or de-energization to occur, such as by operating the circuitry (e.g., switching the circuitry) to induce power adjustment via the activation of one or more control signals. One or more control signals can be initiated in a manner similar to the start time of data transmission associated with the completion of a transaction request. Because unused channels 72 and 74 can be power-gated or de-energized, utilization and power consumption can be based on the actual use of the programmable interconnect network 28 rather than on the overall size of the programmable interconnect network 28 (e.g., because more channels may consume more power when no channels are being power-gated).

[0070] By using the techniques and examples described above, a programmable interconnect network with dynamic configurability can be provided. The programmable interconnect network allows for dedicated configurations and / or use case-specific programming. Other benefits include power savings in FPGA and / or integrated circuit systems through power gating or power-down of unused channels, and improved footprint, as dynamically programmable interconnect networks can reside in a smaller footprint compared to other programmable interconnect networks using multiple point-to-point channels (e.g., as shown in the image). Figure 7(As depicted in the document). Furthermore, the techniques described herein allow for tailored and programmable interconnect network configurations on a per-use basis, based on transmission parameters that define the bandwidth and / or latency of a transaction.

[0071] This application provides the following technical solution:

[0072] Technical Solution 1. An integrated circuit, comprising:

[0073] The first part of the circuit system of the integrated circuit;

[0074] The second part of the circuit system of the integrated circuit; and

[0075] A programmable network-on-a-chip (CN-on-chip) includes a plurality of data channels, wherein the CN-on-a-chip is configured to combine subsets of the plurality of data channels to generate a combined data channel, the combined data channel having a bandwidth that varies at least in part based on the size of the subset of the plurality of data channels combined, and wherein the CN-on-a-chip is configured to transfer data from a first portion of a circuit system to a second portion of a circuit system via the combined data channel.

[0076] Technical Solution 2. The integrated circuit as described in Technical Solution 1, wherein the programmable on-chip network includes one or more routers associated with the combined data channel, wherein the one or more routers are configured to transmit data in a lockstep manner.

[0077] Technical Solution 3. The integrated circuit as described in Technical Solution 1, wherein the bandwidth of the combined data channels is logically combined at least in part based on the following operation: additively generating a bandwidth greater than that of any corresponding data channel associated with the combined data channels.

[0078] Technical Solution 4. The integrated circuit as described in Technical Solution 1, wherein the plurality of data channels includes unused data channels, wherein when transmitting data packets, the combined data channels exclude the unused data channels.

[0079] Technical Solution 5. The integrated circuit as described in Technical Solution 1, wherein the plurality of data channels includes unused data channels configured to be power-gated when transmitting data packets by the plurality of data channels.

[0080] Technical Solution 6. The integrated circuit as described in Technical Solution 1, comprising a bridge configured to couple between the first portion of the circuit system and the network on the programmable chip, wherein the bridge is configured to:

[0081] Receive data packets from the first part of the circuit system; and

[0082] The data packets are transmitted to the second part of the circuit system via the plurality of data channels.

[0083] Technical Solution 7. The integrated circuit of Technical Solution 1, wherein the programmable on-chip network includes a first router and a second router associated with the combined data channel, wherein the first router is configured to operate as a master router, and wherein the second router is configured to operate as a slave router of the first router.

[0084] Technical Solution 8. The integrated circuit of Technical Solution 1, wherein a first combined data channel is configured to transmit data packets in response to a first expected data transmission mode, and wherein a second combined data channel is configured to transmit the data packets in response to a second expected data transmission mode, the second expected data transmission mode being different from the first expected data transmission mode.

[0085] Technical Solution 9. An apparatus comprising:

[0086] Programmable logic architecture, including a first part of the circuit system and a second part of the circuit system; and

[0087] A programmable network-on-a-chip (CN-on-chip) configured to be coupled to a programmable logic architecture, wherein the CN-on-a-chip includes a plurality of data channels, wherein the CN-on-a-chip is configured to have variable transmission characteristics based on the number of data channels in a subset of the plurality of data channels combined together, and wherein the CN-on-a-chip is configured to transfer data from a first portion of a circuit system to a second portion of a circuit system at least in part based on the variable transmission characteristics.

[0088] Technical Solution 10. The apparatus of Technical Solution 9, wherein the variable transmission characteristic specifies a minimum bandwidth of the data channel, the minimum bandwidth being used to allow the data to be transmitted via the programmable on-chip network.

[0089] Technical Solution 11. The apparatus as described in Technical Solution 9, wherein the variable transmission characteristics include a Quality of Service (QoS) metric.

[0090] Technical Solution 12. The apparatus as described in Technical Solution 9, wherein the variable transmission characteristic includes transmission bandwidth.

[0091] Technical Solution 13. The apparatus of Technical Solution 9, wherein the variable transmission characteristic includes reducing the power supplied to the additional subset of the plurality of data channels based on the fact that an additional subset of the plurality of data channels is unused.

[0092] Technical Solution 14. The apparatus of Technical Solution 9, wherein the bandwidth of a corresponding data channel among the plurality of data channels is less than the bandwidth of the combined data channel.

[0093] Technical Solution 15. The apparatus of Technical Solution 9, wherein the programmable on-chip network includes an additional channel that is not powered at least in part based on the variable transmission characteristics.

[0094] Technical Solution 16. The apparatus of Technical Solution 15, wherein the additional channel includes an address channel configured to transmit address data associated with the data passed from the first portion of the circuit system to the second portion of the circuit system.

[0095] Technical Solution 17. A method comprising:

[0096] The determination of combining two or more data channels to form or generate combined data channels is based at least in part on transmission parameters, wherein the two or more data channels are configured to couple a first portion of the circuitry of the programmable logic device to a second portion of the circuitry of the programmable logic device; and

[0097] The programmable logic device is programmed to configure a programmable on-chip network, wherein the programmable on-chip network is configured to generate the combined data channel.

[0098] Technical Solution 18. The method of Technical Solution 17, wherein the combined data channel excludes at least one data channel of the on-chip network, and wherein programming the programmable logic device includes initiating power gating of the at least one data channel excluded from the combined data channel.

[0099] Technical Solution 19. The method of Technical Solution 17, wherein the transmission parameters include transmission direction, destination circuit system, destination location, power considerations, delay considerations, transmission bandwidth, priority indication, or any combination thereof.

[0100] Technical Solution 20. The method of Technical Solution 19, comprising: prioritizing the implementation of additional transmission parameters including the transmission parameters when determining whether to combine two or more data channels based at least in part on an indication of a corresponding priority associated with each of the transmission parameters.

[0101] While the embodiments set forth in this disclosure may allow for various modifications and alternatives, specific embodiments have been shown by way of example in the accompanying drawings and have been described in detail herein. However, it should be understood that this disclosure is not intended to limit it to the specific forms disclosed. This disclosure is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure as defined by the following appended claims.

[0102] Referring to the technology proposed and claimed herein and applying it to practical material objects and specific examples, which undeniably improve the technical field, and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements specified as "a component for [performing] [the function]..." or "a step for [performing] [the function]...", it is intended that such elements be interpreted under the applicable regulations. However, for any claim containing elements specified in any other way, it is intended that such elements not be interpreted under the applicable regulations.

Claims

1. An integrated circuit, comprising: First programmable logic circuit; Second programmable logic circuit; as well as A chip-on-a-chip network (NoC) between the first programmable logic circuit and the second programmable logic circuit, wherein the NoC has a configurable data width, and wherein the NoC includes: Multiple data paths sharing the configurable data width; and A plurality of packet switches interconnected with each other via corresponding paths in the plurality of data paths, wherein the first packet switch among the plurality of packet switches is: Receive a first packet from the first programmable logic circuit, wherein the first packet includes a destination identifier; Perform a first lookup operation in the table based on the destination identifier; and Based at least in part on the result of the first lookup operation, the first packet is transmitted to a second packet switch among the plurality of packet switches using one of the data paths among the plurality of data paths.

2. The integrated circuit of claim 1, wherein the route for transmitting the first packet via the NoC is programmable.

3. The integrated circuit of claim 1, comprising an on-chip network NoC access bridge between the NoC and the first programmable logic circuit.

4. The integrated circuit of claim 3, wherein the NoC access bridge transmits the partitioned data associated with the first packet to the NoC.

5. The integrated circuit of claim 3, wherein the NoC access bridge controls access based on Quality of Service (QoS) settings.

6. The integrated circuit of claim 1, wherein the configurable data width of the NoC is configurable to one of a plurality of data widths.

7. The integrated circuit of claim 6, wherein the plurality of data widths includes a first data width and a second data width, and wherein the plurality of data paths collectively have: At the first moment, the first data width between the first programmable logic circuit and the second programmable logic circuit; and At the second time, the second data width based on parameters between the first programmable logic circuit and the second programmable logic circuit.

8. The integrated circuit of claim 1, comprising an exit bridge that receives the first packet from the NoC at the exit.

9. The integrated circuit of claim 1, wherein the NoC is configurable to transfer the first packet to a memory outside the programmable logic region.

10. The integrated circuit of claim 1, wherein the first lookup operation identifies the output from the first packet switch, the first packet switch determining where the first packet was sent.

11. The integrated circuit of claim 1, wherein the NoC is configurable to implement the parameter-based configurable data width.

12. An integrated circuit, comprising: First programmable logic circuit; Second programmable logic circuit; A network-on-a-chip (NOC) access bridge receives a first packet from the first programmable logic circuit. The first group includes a destination identifier; On-chip network NoC exit bridge; as well as A network-on-a-chip (NoC) is provided, which is coupled to the first programmable logic circuit via a NoC access bridge and to the second programmable logic circuit via a NoC output bridge. The NoC can be configured to transmit data based on a data width among multiple data widths, wherein the data width among the multiple data widths is parameter-based. The NoC is programmable to transmit the data via any of a plurality of routes, and the NoC includes: Multiple data paths that share the data width of the plurality of data widths; and A plurality of packet switches interconnected with each other via corresponding paths in the plurality of data paths, wherein the first packet switch among the plurality of packet switches is: Receive the first packet from the first programmable logic circuit; Perform a first lookup operation in the table based on the destination identifier; and Based at least in part on the result of the first lookup operation, the first packet is transmitted to a second packet switch among the plurality of packet switches using one of the data paths among the plurality of data paths.

13. The integrated circuit of claim 12, wherein the NoC access bridge transmits the partitioned data associated with the first packet to the NoC.

14. The integrated circuit of claim 13, wherein the NoC access bridge controls the entry of the segmented data based on QoS settings.

15. The integrated circuit of claim 12, wherein the NoC is configurable to transfer the first packet to a memory outside the programmable logic region.

16. An integrated circuit system, comprising: A programmable logic device, the programmable logic device comprising: First programmable logic circuit; The second programmable logic circuit; and A chip-on-a-chip network (NoC) between the first programmable logic circuit and the second programmable logic circuit, wherein the NoC has a configurable data width, and wherein the NoC includes: Multiple data paths associated with the configurable data width; and A plurality of packet switches interconnected with each other via corresponding paths in the plurality of data paths, wherein the first packet switch among the plurality of packet switches is: Receive a first packet, wherein the first packet includes a destination identifier associated with the first programmable logic circuit; Perform a first lookup operation in the table based on the destination identifier; and Based at least in part on the result of the first lookup operation, the first packet is transmitted to a second packet switch among the plurality of packet switches using one of the plurality of data paths; and A memory storing the first packet, wherein the memory is configurable to send the first packet as a transaction from the memory to the first programmable logic circuit; and The interconnect block that couples the programmable logic device to the memory.

17. The integrated circuit system of claim 16, comprising: A computer-readable medium storing instructions that, when executed by a processor, cause a computing system to: generate a configuration for programming the NoC to transfer the first packet from the memory to the first programmable logic circuit; as well as The configuration used for programming the NoC is stored.

18. The integrated circuit system of claim 16, wherein the routing for transmitting data via the NoC is programmable.

19. The integrated circuit system of claim 16, comprising an on-chip network NoC access bridge between the NoC and the first programmable logic circuit.

20. The integrated circuit system of claim 19, wherein the NoC access bridge transmits the partitioned data associated with the first packet to the NoC.

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