A data transmission system, method and device

Abstract

A data transmission system, method and device for flexibly implementing service data transmission. The system includes: at least one source switching network interface circuit, at least one switching device, and multiple destination switching network interface circuits. Among them, the first source switching network interface circuit maps the first service data stream to multiple first data frames, and the destination address field of each first data frame includes a load balancing domain; according to the balancing sequence, multiple first data frames are sent to the first switching device, and one element in the balancing sequence is inserted into the load balancing domain corresponding to each first data frame. The number of elements in the balancing sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit; the first switching device sends multiple first data frames to the first destination switching network interface circuit; the first destination switching network interface circuit sorts and decapsulates the multiple first data frames to obtain the first service data stream.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a data transmission system, method, and device. Background Art

[0002] Currently, most of the switching networks of time-division multiplexing (TDM) communication devices, such as synchronous digital hierarchy (SDH) devices or optical transport network (OTN) devices, etc., use dedicated switching chips. For example, application-specific integrated circuit (ASIC) chips, etc. The above TDM communication devices implement TDM service switching through proprietary switching chips. The proprietary switching chips need to be specially customized, and the investment cost is relatively high. Moreover, the internal protocol of the switching chips is privatized, and each manufacturer cannot interchange them, resulting in limited device applications and thus unable to flexibly implement service data transmission. Summary of the Invention

[0003] This application provides a data transmission method and device to flexibly implement service data transmission.

[0004] In a first aspect, the present application provides a data transmission system. The system may include: at least one source switching network interface circuit, at least one switching device, and multiple destination switching network interface circuits. Among them, the first source switching network interface circuit maps the first service data stream to multiple first data frames, and the destination address field of each of the multiple first data frames includes a load balancing domain, and the load balancing domain is used to implement load balancing of the first switching device. The first source switching network interface circuit sends the multiple first data frames to the first switching device according to an equalization sequence. Among them, one element of the equalization sequence is inserted into the load balancing domain corresponding to each of the multiple first data frames. The number of elements in the equalization sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit. The first switching device sends the multiple first data frames to the first destination switching network interface circuit; the first destination switching network interface circuit sorts the multiple first data frames and decapsulates the sorted multiple first data frames to obtain the first service data stream. Among them, the first source switching network interface circuit is any one of the at least one source switching network interface circuit, the first switching device is one or more of the at least one switching device, and the first destination switching network interface circuit is any one of the multiple destination switching network interface circuits.

[0005] It should be understood that the first source switching network interface circuit sending the multiple first data frames to the first switching device according to the equalization sequence means that when the first source switching network interface circuit sends a data frame, it needs to determine the destination switching device to be sent according to an element of the equalization sequence carried by the load balancing domain included in the data frame. That is to say, the first source switching network interface circuit sends the first data frame according to the elements of the equalization sequence.

[0006] In the above data transmission system, when the source switching network interface circuit sends a data frame, an element of an equalization sequence can be inserted into the load balancing domain of the data frame to achieve load balancing of the switching device. In this way, it is not necessary to change the processing flow of the switching device. Therefore, a general switching device can be used to achieve balanced distribution of service data, which can avoid the dependence of the data transmission system on dedicated chips, the data transmission is relatively flexible, and the interchangeability of each manufacturer can be achieved, and it has a wide range of applications.

[0007] In a possible design, when the first switching device is a single-stage switching device, the number of elements in the balancing sequence is related to the number of first connection channels. Specifically, it can be: the number of elements in the balancing sequence is equal to the number of first connection channels. In this way, the switching device can accurately achieve balanced transmission of multiple first data frames through the balancing sequence. In another possible design, when the first switching device is an N-stage switching device, the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit. Specifically, it can be: the number of first connection channels is the number of connection channels between the Nth-stage switching device in the first switching device and the first destination switching network interface circuit. Further, the number of elements in the balancing sequence is related to the number of first connection channels. Specifically, it can be: the number of elements in the balancing sequence is equal to a first value, and the first value is the least common multiple of the number of connection channels between every two stages of switching devices in the N-stage switching device and the number of first connection channels. Wherein, N is an integer greater than or equal to 2. In this way, the switching device can accurately achieve balanced transmission of multiple first data frames through the balancing sequence. In a possible design, the least common multiple can be the least common multiple. In this way, the implementation is relatively simple and the complexity is reduced.

[0008] In a possible design, the elements inserted into the load balancing domain corresponding to each first data frame among the multiple first data frames are related to the receiving ports of the first destination switching network interface circuit. After one element is inserted into a first data frame, the value of the destination address field of this first data frame corresponds to the receiving port of the first destination switching network interface circuit. In this way, the load balancing of the first switching device can be accurately achieved.

[0009] In a possible design, one element in the balancing sequence is inserted into the load balancing domain corresponding to each first data frame among the multiple first data frames. Specifically, it can be: among the first P groups of first data frames, H first data frames in each group of first data frames are respectively inserted with elements in the balancing sequence in turn; Q first data frames in the (P + 1)th group of first data frames are respectively inserted with the first Q elements in the balancing sequence in turn. Wherein, H is equal to the number of elements in the balancing sequence, P is the integer quotient obtained by dividing T by H, Q is the remainder obtained by dividing T by H, and T is the number of the multiple first data frames. H is an integer greater than or equal to 1, P is an integer greater than or equal to 1, Q is a positive integer, and Q is less than H. In this way, one element in the balancing sequence can be successfully inserted into the load balancing domain corresponding to each first data frame, and the implementation method is simple.

[0010] In a possible design, the source address field of each of the multiple first data frames includes a first domain, and the first domain is used to indicate the sorting of each of the multiple first data frames. Before the first source switching network interface circuit sends the multiple first data frames to the first switching device according to the equalization sequence, the first source switching network interface circuit inserts a timestamp or a sequence number into the first domain corresponding to each of the multiple first data frames in a set order. This can achieve the preservation of the order of service data frames, so as to accurately restore the service data stream subsequently. Exemplarily, the set order may be an increasing order or the like.

[0011] In a possible design, the first destination switching network interface circuit sorts the multiple first data frames. Specifically, the first destination switching network interface circuit sorts the multiple first data frames according to the timestamp or the sequence number in the first domain corresponding to each first data frame. This can enable the first destination switching network interface circuit to accurately restore the service data stream. Exemplarily, the first destination switching network interface circuit may sort the multiple first data frames in an increasing order according to the timestamp or the sequence number in the first domain corresponding to each first data frame.

[0012] In a possible design, at least one of the switching devices is a local area network (LAN) switch (LSW) switching chip. This can use a general Ethernet switching chip to implement service data transmission, with simple implementation and flexible data transmission.

[0013] In a second aspect, the present application provides a data transmission method. The method may include: mapping a first service data stream to multiple first data frames, where the destination address field of each of the multiple first data frames includes a load balancing domain, and the load balancing domain is used to achieve load balancing of the first switching device. Sending the multiple first data frames to the first switching device according to the equalization sequence. Wherein, an element of the equalization sequence is inserted into the load balancing domain corresponding to each of the multiple first data frames. The number of elements in the equalization sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit. It can achieve the balanced distribution of service data of the first switching device, with flexible data transmission, and can achieve the interchange between different manufacturers, and has a wide range of applications.

[0014] In a possible design, when the first switching device is a single-stage switching device, the specific description of the relationship between the number of elements in the equalization sequence and the number of first connection channels can refer to the description in the possible design of the first aspect above, and will not be repeated here.

[0015] In a possible design, when the first switching device is an N-level switching device, the specific solution description can refer to the description in the possible design of the first aspect above, and will not be repeated here.

[0016] In a possible design, for the relevant description of the elements where the load balancing domain corresponding to each of the multiple first data frames is inserted downward, reference can be made to the relevant description in the possible design of the first aspect above, and will not be repeated here.

[0017] In a possible design, for the relevant description of the source address field of each of the first data frames, reference can be made to the relevant description in the possible design of the first aspect above, and will not be repeated here.

[0018] In a third aspect, the present application further provides a data transmission device. The data transmission device has the function of implementing the method in the second aspect or each possible design example of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions.

[0019] In a possible design, the structure of the data transmission device includes a transceiver unit and a processing unit. These units can execute the corresponding functions in the second aspect or each possible design example of the second aspect. For specific reference, see the detailed description in the method example, and will not be elaborated here.

[0020] In a possible design, the structure of the data transmission device includes a communication interface and a processor. Optionally, the data transmission device further includes a memory. The communication interface is used for receiving and transmitting data and for communicating with other devices in the data transmission system. The processor is configured to support the data transmission device to execute the corresponding functions in the second aspect or each possible design example of the second aspect. The memory is coupled to the processor and stores the necessary program instructions and data of the data transmission device.

[0021] In a fourth aspect, an embodiment of the present application provides a data transmission system. The data transmission system may include at least one source switching network interface circuit (such as the first source switching network interface circuit), at least one switching device (such as the first switching device), and multiple destination switching network interface circuits (such as the first destination switching network interface circuit, etc.) mentioned above.

[0022] Fifth aspect, a computer-readable storage medium provided by an embodiment of the present application. The computer-readable storage medium stores program instructions, which when run on a computer, cause the computer to execute the method described in the second aspect and any possible design thereof in the embodiments of the present application. Exemplarily, the computer-readable storage medium may be any available medium that can be accessed by a computer. Taking this as an example but not limited to: the computer-readable medium may include a non-transitory computer-readable medium, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer.

[0023] Sixth aspect, a computer program product provided by an embodiment of the present application includes computer program code or instructions. When it runs on a computer, it causes the computer to implement the method described in the above second aspect or any possible design of the second aspect.

[0024] For the various aspects from the third aspect to the sixth aspect above and the possible technical effects that each aspect may achieve, please refer to the technical effects that can be achieved by the various possible solutions in the first aspect or the second aspect above, and will not be repeated here. Description of the Drawings

[0025] Figure 1 It is a schematic structural diagram of an OTN device provided by the present application;

[0026] Figure 2 It is a schematic architecture diagram of a data transmission system provided by the present application;

[0027] Figure 3 It is a schematic architecture diagram of another data transmission system provided by the present application;

[0028] Figure 4 It is a schematic architecture diagram of yet another data transmission system provided by the present application;

[0029] Figure 5 It is a schematic structural diagram of a first data frame provided by the present application;

[0030] Figure 6 It is a schematic diagram of mapping a first service data stream to multiple first data frames provided by the present application;

[0031] Figure 7Schematic diagram of the completion location of service encapsulation / de-encapsulation in the data transmission system provided by this application;

[0032] Figure 8 Schematic diagram of a location that requires equalization processing provided by this application;

[0033] Figure 9 Schematic diagram of the equalization processing of unicast service provided by this application;

[0034] Figure 10 Schematic diagram of the equalization location in a multi-level multi-plane switching system provided by this application;

[0035] Figure 11 Schematic diagram of the equalization processing of a multi-level switching device provided by this application;

[0036] Figure 12 Schematic diagram of the sequence preservation of a service provided by this application;

[0037] Figure 13 Flowchart of a data transmission method provided by this application;

[0038] Figure 14 Schematic diagram of the structure of a data transmission device provided by this application;

[0039] Figure 15 Schematic diagram of the structure of another data transmission device provided by this application. Detailed implementation manners

[0040] The following will further describe this application in detail with reference to the accompanying drawings.

[0041] The embodiments of this application provide a data transmission method and device to flexibly implement service data transmission. Among them, the method and device of this application are based on the same technical concept. Since the principles of the method and device for solving problems are similar, the implementation of the device and the method can be referred to each other, and the repeated parts will not be elaborated.

[0042] In the description of this application, terms such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0043] In the description of this application, "at least one (kind)" means one (kind) or more than one (kind), and more than one (kind) means two (kinds) or more than two (kinds).

[0044] The data transmission method provided by the embodiments of the present application can be applied to a communication system composed of data exchange devices and the like. Among them, the communication system can be, but is not limited to, a data transmission system, a data exchange system (network), an optical transmission network, a time division multiplexing system, etc. For example, in an optical transmission network, the data exchange device can be an optical transport network (OTN) device. Figure 1 It is a schematic structural diagram of a possible OTN device. Exemplarily, an OTN device may include tributary boards, line boards, cross-connect boards, and system control and communication type single boards, and may also include power supplies, fans, auxiliary single boards, and optical layer processing single boards ( Figure 1 not shown in the figure). It should be noted that according to specific needs, the specific types and quantities of single boards included in each OTN device may be different. For example: The OTN device as a core node may not have tributary boards. The OTN device as an edge node may have multiple tributary boards. Among them, the power supply is used to supply power to the OTN device and may include main and standby power supplies. The fan is used to dissipate heat from the device. The auxiliary single board is used to provide auxiliary functions such as external alarms or access to external clocks. The tributary boards, cross-connect boards, and line boards are mainly used to process the electrical layer signals of the OTN. Among them, the tributary board is used to implement the reception and transmission of various client services, such as synchronous digital hierarchy (SDH) services, packet services, Ethernet services, and fronthaul services, etc. Further, the tributary board can be divided into a client-side optical module and a signal processor. Among them, the client-side optical module can be an optical transceiver for receiving and / or sending service data. The signal processor is used to implement the mapping and demapping processing of service data to data frames. The cross-connect board is used to implement the exchange of data frames and complete the exchange of one or more types of data frames. The line board mainly implements the processing of line-side data frames. Specifically, the line board can be divided into a line-side optical module and a signal processor. Among them, the line-side optical module can be a line-side optical transceiver for receiving and / or sending data frames. The signal processor is used to implement the multiplexing and demultiplexing, or mapping and demapping processing of the line-side data frames. The system control and communication type single board is used to implement system control and communication. Specifically, information can be collected from different single boards through the backplane, or control instructions can be sent to the corresponding single boards. It should be noted that unless otherwise specified, a specific component (such as: the signal processor) can be one or more, and the present application does not make any restrictions. It should also be noted that the embodiments of the present application do not make any restrictions on the types of single boards included in the device, as well as the specific functional design and quantity of the single boards.

[0045] Since most of the switching networks of current OTN devices and the like use dedicated switching chips. For example, ASIC chips and the like, that is, OTN devices and the like implement service switching through proprietary switching chips. However, since proprietary switching chips need to be specially customized, the investment cost is relatively high, and the internal protocol of the switching chips is privatized, and each manufacturer cannot interchange, resulting in limited application of the devices, and thus the service data transmission cannot be flexibly realized. Based on this, the embodiments of the present application provide a data transmission system, method and device. To achieve the universality of devices of each manufacturer and flexibly realize service data transmission.

[0046] Figure 2 FIG. shows a data transmission system provided by an embodiment of the present application. The data transmission system may include at least one source switching network interface circuit, at least one switching device, and multiple destination switching network interface circuits. Exemplarily, in Figure 2 FIG., at least one source switching network interface circuit is shown as source switching network interface circuit 1 and source switching network interface circuit 2. At least one switching device is shown as switching device 1 and switching device 2. Multiple destination switching network interface circuits are shown as destination switching network interface circuit 1, destination switching network interface circuit 2, and destination switching network interface circuit 3. It should be noted that Figure 2 the numbers of the source switching network interface circuit, the switching device, and the destination switching network interface circuit shown in FIG. are only examples and do not limit the data transmission system of the present application.

[0047] Among them, the source switching network interface circuit may be referred to as an upstream switching network interface circuit. For example, the upstream switching network interface circuit may be an upstream switching network interface circuit (fabric interface circuit, FIC), etc. The destination switching network interface circuit may be referred to as a downstream switching network interface circuit. For example, a downstream FIC, etc. The switching device may be a chip. For example, it may be a general-purpose Ethernet switching chip, such as a local area network (LAN) switch (LSW) switching chip, etc. The switching device may also be an independent device, and the present application does not limit this.

[0048] In one embodiment, the switching device in the data transmission system may be a single-stage switching device. For example Figure 3 the shown data transmission system takes multiple single-stage LSW switching chips as the switching device, the upstream FIC as the source switching network interface circuit, and the downstream FIC as the destination switching network interface circuit as an example. Figure 3 The shown data transmission system may also be referred to as a single-stage multi-plane switching system, which uses a general-purpose Ethernet switching chip to expand multiple planes to build a large-capacity switching system.

[0049] In another embodiment, the switching device in the data transmission system may be a multi-stage switching device. For exampleFigure 4 The data transmission system shown takes the switching device as a multi - level LSW switching chip, the source switching network interface circuit as the upstream FIC, and the destination switching network interface circuit as the downstream FIC as an example. Figure 4 The data transmission system shown can also be called a multi - level multi - plane switching system. By cascading multi - level switching chips, Figure 3 on the basis of the single - level multi - plane switching system shown, the system capacity is further expanded.

[0050] It should be noted that Figure 3 and Figure 4 the numbers of the upstream FIC, LSW switching chip, and downstream FIC in

[0051] are merely examples and do not limit this application. Figures 2 - 4 Through the data transmission system shown above, service distribution, switching, and balancing can be achieved. Specifically, for any source switching network interface circuit (illustrated by the first source switching network interface circuit), through one or more switching devices (illustrated by the first switching device), the process of sending service data (illustrated by the first service data stream) to any destination switching network interface circuit (illustrated by the first destination switching network interface circuit) can be as follows:

[0052] The first source switching network interface circuit maps the first service data stream to multiple first data frames. The destination address field of each of the multiple first data frames includes a load - balancing domain. The load - balancing domain is used to achieve load balancing of the first switching device. The first source switching network interface circuit can send multiple first data frames to the first switching device according to an equalization sequence. Among them, an element in the equalization sequence is inserted into the load - balancing domain corresponding to each of the multiple first data frames. The number of elements in the equalization sequence is related to the first connection channel number, and the first connection channel number is the number of connection channels between the first switching device and the first destination switching network interface circuit. The first switching device sends the multiple first data frames to the first destination switching network interface circuit. The first destination switching network interface circuit sorts the multiple first data frames and de - encapsulates the sorted multiple first data frames to obtain the first service data stream.

[0053] Exemplarily, the data structure of the service data stream mapping in the embodiments of this application can be a general Ethernet frame structure. That is, the structure of each of the multiple first data frames can be a general Ethernet frame structure. For example, the structure of the first data frame can be as Figure 5As shown. In this application, the meanings of the destination address (DA) field and the source address (SA) field in the Ethernet frame are redefined. Among them, the source switching network interface circuit and the destination switching network interface circuit process data according to the meanings of the redefined DA field and SA field. The switching device processes data according to the current meanings of the DA field and SA field in the Ethernet frame. That is to say, for the switching device, the meanings of the DA field and SA field are not redefined, and the switching device can adopt the existing processing flow to process data. This can avoid changing the current processing flow of the switching device.

[0054] Specifically, as Figure 5 shown, for unicast services, the redefined DA field may include a multicast (MC) field, a reserve (RES) field, a destination FIC identity (DFIC_ID) field, and a load balance (LB) field. For example, for unicast services, the specific meaning of the redefined DA field can be shown in Table 1. For multicast services, the redefined DA field may include an MC field, a RES field, a multicast identity (MID) field, and an LB field. For example, for multicast services, the specific meaning of the redefined DA field can be shown in Table 2. The redefined SA field may include a RES field, a source FIC identity (SFIC_ID) field, a flow identity (FLOW_ID) field, and a timestamp_serial number (TS_SN) field. For example, the specific meaning of the redefined SA field can be shown in Table 3.

[0055] Table 1 Specific meaning of the redefined DA field for unicast services

[0056] Domain Name Ethernet DA Bit Field Meaning Explanation MC DA

[47] Unicast / Multicast Indicator, 0 indicates unicast service, 1 indicates multicast service RES DA[46:16] Reserved Field DFIC_ID DA[15:6] Destination FIC, destination FIC for unicast service exchange LB DA[5:0] Load Balancing Field, used to achieve load balancing for switching devices

[0057] Among them, it can be seen from Table 1 that for unicast services, the 48 bits occupied by the DA field (i.e., DA[47:0]) are allocated as follows: the LB field occupies the first 6 bits of the DA field, i.e., bits 0 - 5. The DFIC_ID field occupies the 7th bit to the 16th bit of the DA field, i.e., bits 6 - 15. The RES field occupies the 17th bit to the 47th bit of the DA field, i.e., bits 16 - 46. The MC field occupies the last bit (the 48th bit) of the DA field, i.e., bit 47.

[0058] Table 2 Specific meanings of the redefined DA field for multicast services

[0059] Domain Name Bit Field Meaning Explanation MC DA

[47] Unicast / Multicast Indicator, 0 indicates unicast service, 1 indicates multicast service RES DA[46:23] Reserved Field MID DA[22:6] Multicast ID, multicast service group number, used to distinguish different multicast groups LB DA[5:0] Load Balancing Field, used to achieve load balancing for switching devices

[0060] Among them, as can be seen from Table 2, for the multicast service, the allocation of the 48 bits occupied by the DA field (i.e., DA[47:0]) is as follows: The LB field occupies the first 6 bits of the DA field, i.e., bits 0 - 5. The MID field occupies the 7th bit to the 23rd bit of the DA field, i.e., bits 6 - 22. The RES field occupies the 24th bit to the 47th bit of the DA field, i.e., bits 23 - 46. The MC field occupies the last bit (the 48th bit) of the DA field, i.e., bit 47.

[0061] Table 3 Specific meanings of the redefined SA field

[0062]

[0063] Among them, as can be seen from Table 3, the allocation of the 48 bits occupied by the SA field (i.e., SA[47:0]) is as follows: The TS_SN field occupies the first 20 bits of the SA field, i.e., bits 0 - 19. The FLOW_ID field occupies the 21st bit to the 36th bit of the SA field, i.e., bits 20 - 35. The SFIC_ID field occupies the 37th bit to the 46th bit of the SA field, i.e., bits 36 - 45. The RES field occupies the last two bits (the 47th and 48th bits) of the SA field, i.e., bits 46 - 47.

[0064] Among them, the load balancing domain included in the destination address field of each of the multiple first data frames is the LB field included in the DA field in Table 1 or Table 2 above. The first domain included in the source address field of each of the multiple first data frames is the TS_SN field included in the SA field in Table 2 above.

[0065] The process in which the first source switching network interface circuit maps the first service data stream to multiple first data frames is the process in which the first source switching network interface circuit completes the encapsulation of the service into the first data frames involved above. That is, service encapsulation is performed. Among them, the payload field in each of the multiple first data frames carries part of the service data. Exemplarily, a schematic diagram of mapping the first service data stream to multiple first data frames can be as Figure 6 shown. In this application, the service encapsulation based on the first data frame is performed in the source switching network interface circuit (such as the upstream FIC), and the corresponding service decapsulation is performed in the destination switching network interface circuit (such as the downstream FIC). For example, Figure 7 shows the completion location of service encapsulation / decapsulation in the data transmission system.

[0066] After the service encapsulation is completed, the balanced distribution of services needs to be carried out. To avoid uneven workloads between multiple switching devices and different input / output (IO) ports of the same switching device, which may lead to buffer overflow or increased transmission delay jitter in the switching device. The first source switching network interface circuit (such as the uplink FIC) can perform balanced distribution of service data. For example, Figure 8 The positions (1) and (2) shown in are the positions where balanced processing needs to be carried out. At (1), the uplink FIC can achieve balance by sending data frames in a round-robin (RR) manner to different switching devices. In the current embodiment, the balanced processing at (2) is implemented in a dedicated switching chip. In this application, since the switching device uses a general device or chip, in order to avoid changing the current hardware processing flow, it can be indirectly implemented through the first source switching network interface circuit (such as the uplink FIC). That is, the balanced distribution of the service data stream by the switching device can be indirectly achieved through the first source switching network interface circuit to achieve load balance.

[0067] Specifically, since the redefined DA field in this application has added a load balancing field, the switching device can use the value corresponding to the DA field to find the characteristics of the port, and allocate H DAs to the same destination switching network interface circuit. H is related to the number of connection channels (such as media access control (MAC) channels) between the switching device and the destination switching network interface circuit. When the source switching network interface circuit distributes, each of the multiple first data frames inserts an element of the equalization sequence independently in the load balancing domain. For example, when H = 4, the equalization sequence can be {0, 1, 2, 3}, and when H = 3, the load balancing domain can be {0, 1, 2}. By evenly inserting the elements of the equalization sequence, the switching device can be controlled to evenly distribute to different outgoing IOs. The value of the load balancing domain in the first data frame, that is, the element inserted in the equalization sequence, is related to the receiving port of the first destination switching network interface circuit to which it needs to be sent. After the element of the equalization sequence is inserted into the load balancing domain in the first data frame, the value of the DA field corresponding to the first data frame corresponds to the receiving port of the first destination switching network interface circuit.

[0068] Among them, the first source switching network interface circuit can insert the elements in the equalization sequence into the load balancing fields of multiple first data frames according to a preset rule. In an alternative embodiment, one element in the equalization sequence is inserted into the load balancing field corresponding to each of the multiple first data frames. Specifically, it can be: among the first P groups of first data frames, H first data frames in each group of the first data frames are sequentially inserted with the elements in the equalization sequence. The Q first data frames in the (P + 1)-th group of first data frames are sequentially inserted with the first Q elements in the equalization sequence. Wherein, H is equal to the number of elements in the equalization sequence, P is the integer quotient obtained by dividing T by H, Q is the remainder obtained by dividing T by H, and T is the number of the multiple first data frames. H is an integer greater than or equal to 1, P is an integer greater than or equal to 1, Q is a positive integer, and Q is less than H. For example, if there are 10 first data frames (i.e., T is 10) and the equalization sequence is {0, 1, 2, 3} (i.e., H is 4), then P is 2 and Q is 2 at this time. That is to say, the 10 first data frames can be divided into 2 + 1 groups, and there are two first data frames in the third group. When the first source switching network interface circuit inserts one element in the equalization sequence into each of the 10 first data frames, it can cyclically insert the elements in the order of 0, 1, 2, 3 into the load balancing fields of the 10 first data frames in sequence. That is, in the first data frames in the first 2 groups of the 10 first data frames, 0, 1, 2, 3 are sequentially inserted, and in the first data frames in the third group, the first 2 elements in the equalization sequence are inserted, that is, 0 and 1 are inserted. That is, the elements inserted into the load balancing fields of the 10 first data frames are: 0, 1, 2, 3, 0, 1, 2, 3, 0, 1.

[0069] It should be noted that the method of inserting elements into the load balancing field of the above first data frame is only an example. The first source switching network interface circuit can also insert the elements in the equalization into the load balancing field of each first data frame by other methods, which will not be listed one by one here in this application.

[0070] In a specific embodiment, when the first switching device is a single-stage switching device, that is, when the data transmission system is a system as shown in Figure 3 the figure. The number of elements in the equalization sequence is related to the number of first connection channels. Specifically, the number of elements in the equalization sequence is equal to the number of first connection channels.

[0071] For example, when the first switching device is a single-stage switching device, Figure 9The figure shows a schematic diagram of the equalization process for unicast services. Assume that the identifier of the first destination switching network interface circuit is 5, that is, DFIC_ID = 5. The number of connection channels from the first switching device to the first destination switching network interface circuit is 4, for example, the number of IO links is 4. The equalization sequence is {0, 1, 2, 3}. At this time, the configured MAC address forwarding table of the first switching device can allocate 4 MAC addresses [{0, 0, 5, 0}, {0, 0, 5, 1}, {0, 0, 5, 2}, {0, 0, 5, 3}] for the FIC with DFIC_ID = 5. The corresponding egress IO of the first switching device is {IO_0, IO_1, IO_2, IO_3}. In each first data frame mapped by the first service data stream sent to the first destination switching network interface circuit with DFIC_ID = 5, except that the DFIC_ID field is fixed to 5, the load balancing field can sequentially repeat an element in the sequence {0, 1, 2, 3}. From Figure 9 As can be seen from this, through the above method, the MAC addresses corresponding to the first data frames sent by the first switching device from the IO_0, IO_1, IO_2, and IO_3 ports to the first destination switching device are sequentially {0, 0, 5, 0}, {0, 0, 5, 1}, {0, 0, 5, 2}, {0, 0, 5, 3} in a cyclic repetition. That is, the MAC addresses corresponding to the first data frames sent out from IO_0 of the first device are all {0, 0, 5, 0}, and the element 0 is inserted into the load balancing field. The MAC addresses corresponding to the first data frames sent out from IO_1 are all {0, 0, 5, 1}, and the element 1 is inserted into the load balancing field. The MAC addresses corresponding to the first data frames sent out from IO_2 are all {0, 0, 5, 2}, and the element 2 is inserted into the load balancing field. The MAC addresses corresponding to the first data frames sent out from IO_3 are all {0, 0, 5, 3}, and the element 3 is inserted into the load balancing field. In this way, the first switching device can forward the first data frame according to the MAC address forwarding table in the current forwarding mode, realizing switching and load balancing.

[0072] In another specific embodiment, when the first switching device is an N-level switching device, that is, when the data transmission system is Figure 4 the system shown. The first number of connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit. Specifically, it can be: the first number of connection channels is the number of connection channels between the Nth-level switching device in the first switching device and the first destination switching network interface circuit. Further, the number of elements in the equalization sequence is related to the first number of connection channels. Specifically, it can be: the number of elements in the equalization sequence is equal to the first value, and the first value is the least common multiple of the number of connection channels between every two levels of switching devices in the N-level switching device and the first number of connection channels. Where N is an integer greater than or equal to 2.

[0073] Optionally, the first value can be the least common multiple of the number of connection channels between every two levels of switching devices in the N-level switching device and the first connection channel number. For example, taking the first switching device as a three-level switching device as an example, as follows Figure 10 As shown. The number of connection channels between every two levels of the first, second, and third-level switching devices are K, L, and M respectively. That is, the number of IOs output by each level of switching device and connected to the downstream switching device are K, L, and M respectively. Among them, M is the above-mentioned first connection channel number. At this time, the number of elements in the equalization sequence can be the least common multiple W = LCM(K, L, M) of K, L, and M. Then the value range of the load balancing domain in the first data frame can be LB = {0, 1, 2,..., W - 1}. That is, the equalization sequence can be {0, 1, 2,..., W - 1}.

[0074] In the case of the above three-level switching device, in addition to implementing load balancing of the first-level switching device through the first source switching network interface circuit, the output of the three-level switching device still needs to perform three equalizations, as Figure 10 shown in the positions of the second equalization, third equalization, and fourth equalization. For example, after determining the number of elements in the equalization sequence through the least common multiple determined above, the first source switching network interface circuit can independently insert an element in the equalization sequence into the load balancing domain of each first data frame. The three-level switching device forwards the first data frame corresponding to the specified DA to the specified port through static configuration of the MAC address forwarding table to implement switching and load balancing processing.

[0075] As Figure 11As shown in the figure, assume that the number of IOs of the first, second, and third-level switching devices connected to the downstream devices are {K, L, M} = {5, 5, 4} respectively. Then the number of equalization sequences can be LCM(K, L, M) = LCM(5, 5, 5) = 20. The equalization sequences that the first source switching network interface circuit is inserted into the load balancing domain of multiple first data frames can be LB = {0, 1, 2, 3, …, 17, 18, 19}. The first source switching network circuit sequentially repeats inserting one element from LB = {0, 1, 2, 3, …, 17, 18, 19} into multiple first data frames of the first service data stream. When the first-level switching device outputs: The first data frames with LB = {0, 5, 10, 15} inserted into the load balancing domain are output from IO_0 of the first switching device. The first data frames with LB = {1, 6, 11, 16} inserted into the load balancing domain are output from IO_1 of the first switching device. The first data frames with LB = {2, 7, 12, 17} inserted into the load balancing domain are output from IO_2 of the first switching device. The first data frames with LB = {3, 8, 13, 18} inserted into the load balancing domain are output from IO_3 of the first switching device. The first data frames with LB = {4, 9, 14, 19} inserted into the load balancing domain are output from IO_4 of the first switching device. When the second-level switching device outputs: The messages with LB = {0, 5, 10, 15} inserted into the load balancing domain are output from IO_0. The first data frames with LB = {1, 6, 11, 16} inserted into the load balancing domain are output from IO_1 of the first switching device. The first data frames with LB = {2, 7, 12, 17} inserted into the load balancing domain are output from IO_2 of the first switching device. The first data frames with LB = {3, 8, 13, 18} inserted into the load balancing domain are output from IO_3 of the first switching device. The first data frames with LB = {4, 9, 14, 19} inserted into the load balancing domain are output from IO_4 of the first switching device. When the third-level switching device outputs: The first data frames with LB = {0, 4, 8, 12, 16} inserted into the load balancing domain are output from IO_0. The first data frames with LB = {1, 5, 9, 13, 17} inserted into the load balancing domain are output from IO_1 of the first switching device. The first data frames with LB = {2, 6, 10, 14, 18} inserted into the load balancing domain are output from IO_2 of the first switching device. The first data frames with LB = {3, 7, 11, 15, 19} inserted into the load balancing domain are output from IO_3 of the first switching device. Through the above method, the load balancing of the switching device is achieved.

[0076] In the examples of the elements of the above-mentioned balanced sequence, they are all sequential sequences starting from element 0. It should be understood that the balanced sequence can also have other possible composition methods. For example, when the number of elements in the balanced sequence is 4, in addition to the above-listed balanced sequence {0, 1, 2, 3}, the balanced sequence can also be {1, 2, 3, 4}, or it can also be {2, 4, 6, 8}. Of course, it can also be other compositions, which will not be listed one by one here.

[0077] In order to achieve lossless switching of services, after the data frames are aggregated to the destination source switching network interface circuit, an in-sequence recovery process needs to be performed. That is, after multiple first data frames are aggregated to the first destination source switching network interface circuit, the first destination source switching network interface circuit needs to perform an in-sequence recovery process. For example, the in-sequence function of the service needs to be implemented in the uplink FIC and the downlink FIC respectively. As Figure 12 shown, the uplink FIC is implemented in the TS_SN, and the downlink FIC implements sorting and recombination.

[0078] In an alternative embodiment, before the first source switching network interface circuit sends multiple first data frames to the first switching device according to the balanced sequence, the first source switching network interface circuit inserts a timestamp or a sequence number into the first domain corresponding to each of the multiple first data frames in a set order. Exemplarily, the set order can be an increasing order or other orders, which are not limited in this application. Among them, the sequence number can be an increasing sequence number. When inserting a timestamp, it is required that the clocks of all source switching network interface circuits and destination switching network interface circuits in the data transmission system be synchronized.

[0079] Furthermore, the first destination switching network interface circuit sorts the multiple first data frames. Specifically, it can be: the first destination switching network interface circuit sorts the multiple first data frames according to the timestamp or sequence number in the first domain corresponding to each first data frame (for example, in increasing order). In this way, the in-sequence recovery of the service can be completed.

[0080] Exemplarily, when a timestamp is inserted into the first domain in the data frame, when the first destination switching network interface circuit receives data frames from multiple services, the first destination switching network interface circuit does not distinguish between services and performs a global unified timestamp sorting. The data frames of all services are sorted in chronological order to complete the in-sequence recovery of the service.

[0081] By using the data transmission system provided in the embodiments of the present application, the balanced distribution of service data can be achieved by using a general switching device, which can avoid the dependence of the data transmission system on a dedicated chip, the data transmission is relatively flexible, and the interchange of each manufacturer can be realized, and it has a wide application.

[0082] Based on the above embodiments, the embodiments of the present application also provide a data transmission method. As Figure 13As shown, the specific process of this method may include:

[0083] Step 1301: The first source switching network interface circuit maps the first service data stream to multiple first data frames. The destination address field of each of the multiple first data frames includes a load balancing domain. The load balancing domain is used to implement load balancing of the first switching device.

[0084] Specifically, for the implementation process of how the first source switching network interface circuit maps the first service data stream to multiple first data frames, reference can be made to the relevant descriptions involved in the above data transmission system, which will not be repeated here.

[0085] Step 1302: The first source switching network interface circuit sends multiple first data frames to the first switching device according to the balancing sequence. Among them, one element of the balancing sequence is inserted into the load balancing domain corresponding to each of the multiple first data frames. The number of elements in the balancing sequence is related to the number of first connection channels. The number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit.

[0086] In an optional implementation manner, when the first switching device is a single-stage switching device, the number of elements in the balancing sequence is related to the number of first connection channels, specifically: the number of elements in the balancing sequence is equal to the number of first connection channels. In another optional implementation manner, when the first switching device is an N-stage switching device, the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit, specifically: the number of first connection channels is the number of connection channels between the Nth-stage switching device in the first switching device and the first destination switching network interface circuit. The number of elements in the balancing sequence is related to the number of first connection channels, specifically: the number of elements in the balancing sequence is equal to a first value, and the first value is the least common multiple of the number of connection channels between every two-stage switching devices in the N-stage switching device and the number of first connection channels. Wherein, N is an integer greater than or equal to 2. Optionally, the least common multiple can be the least common multiple.

[0087] Specifically, for the specific introduction of inserting one element of the balancing sequence into each of the multiple first data frames, reference can be made to the relevant descriptions involved in the introduction of the above transmission system, which will not be repeated here.

[0088] Step 1303: The first switching device sends multiple first data frames to the first destination switching network interface circuit.

[0089] Specifically, for the implementation process of the first switching device sending multiple first data frames to the first destination switching network interface circuit, reference can be made to the relevant descriptions and examples in the introduction of the above data transmission system, which will not be repeated here.

[0090] Step 1304: The first destination switching network interface circuit sorts multiple first data frames and decapsulates the sorted multiple first data frames to obtain a first service data stream.

[0091] Exemplarily, the source address field of each of the multiple first data frames includes a first domain, and the first domain is used to indicate the sorting of each of the multiple first data frames. Before sending the multiple first data frames to the first switching device according to the equalization sequence, the first source switching network interface circuit inserts a timestamp or a sequence number into the first domain corresponding to each of the multiple first data frames in a set order (such as an increasing order, etc.). Further, the first destination switching network interface circuit sorts the multiple first data frames. Specifically, the first destination switching network interface circuit sorts the multiple first data frames according to the timestamp or the sequence number in the first domain corresponding to each of the multiple first data frames (such as an increasing sort). Specifically, the above process can refer to the relevant descriptions involved in the introduction of the above data transmission system, and will not be repeated here.

[0092] By using the data transmission method provided in the embodiments of the present application, data can be flexibly transmitted, and data can be evenly distributed without relying on dedicated devices during data transmission.

[0093] Based on the above embodiments, the embodiments of the present application further provide a data transmission device. As Figure 14 shown, the data transmission device 1400 includes a transceiver unit 1401 and a processing unit 1402. Among them, the transceiver unit 1401 is used for the data transmission device 1400 to receive data and / or send data, and the processing unit 1402 is used to control and manage the operations performed by the data transmission device 1400. The processing unit 1402 can also control the data receiving / sending steps performed by the transceiver unit 1401.

[0094] Exemplarily, the data transmission device 1400 is specifically the source switching network interface circuit in the above embodiments, or a processor, a chip, a chip system, or a functional module in the source switching network interface circuit, etc.

[0095] For example, when the data transmission device is used to implement the function of the first source switching network interface circuit in the above Figure 13 embodiment, the processing unit 1402 is used to execute the above step 1301. The transceiver unit 1401 is used to execute the above step 1302. Repetitive parts will not be repeated here.

[0096] It should be noted that the division of units in the embodiments of this application is illustrative, merely a logical function division, and there may be other division methods in actual implementation. In the embodiments of this application, each functional unit may be integrated into a processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0097] If the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, may be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0098] Based on the above embodiments, the embodiments of this application also provide another data transmission device. As Figure 15 shown, the data transmission device 1500 includes a communication interface 1501 and a processor 1502. Optionally, the data transmission device 1500 further includes a memory 1503. The memory 1503 may be provided inside the data transmission device 1500 or outside the data transmission device 1500. The processor 1502 controls the communication interface 1501 to receive and send data, etc.

[0099] Specifically, the processor 1502 can be a central processing unit (CPU), a network processor (NP), or a combination of a CPU and an NP. The processor 1502 can further include a hardware chip. The above-mentioned hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The above-mentioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0100] Among them, the communication interface 1501, the processor 1502, and the memory 1503 are interconnected with each other. Optionally, the communication interface 1501, the processor 1502, and the memory 1503 can be interconnected through a bus 1504. The bus 1504 can be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The bus can be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 15 only a thick line is used to represent it in the figure, but it does not mean that there is only one bus or one type of bus.

[0101] In an alternative embodiment, the memory 1503 is used to store programs and the like. Specifically, the program can include program code, and the program code includes computer operation instructions. The memory 1503 may include a RAM, and may also include a non-volatile memory, such as one or more disk memories. The processor 1502 executes the application program stored in the memory 1503 to implement the above functions, thereby implementing the functions of the data transmission device 1500.

[0102] Exemplarily, the data transmission device 1500 can specifically be the source switching network interface circuit in the above embodiment. For example, when the data transmission device is used to implement the Figure 13 functions of the first source switching network interface circuit in the above embodiment, the communication interface 1501 can implement Figure 13The transceiver operations performed by the first source switching network interface circuit in the illustrated embodiment. The processor 1502 may implement Figure 13 Other operations performed by the first source switching network interface circuit in the illustrated embodiment other than the transceiver operations. For the relevant specific descriptions, reference may be made to Figure 13 The relevant descriptions in the illustrated embodiment, which will not be elaborated here.

[0103] Based on the above embodiments, an embodiment of the present application provides a data transmission system. The data transmission system includes at least one source switching network interface circuit (such as the first source switching network interface circuit), at least one switching device (such as the first switching device), and multiple destination switching network interface circuits (such as the first destination switching network interface circuit) involved in the above embodiments, etc.

[0104] An embodiment of the present application also provides a computer-readable storage medium. The computer-readable storage medium is used to store a computer program, and when the computer program is executed by a computer, the computer can implement the data transmission method provided in the above method embodiment.

[0105] An embodiment of the present application also provides a computer program product. The computer program product is used to store a computer program, and when the computer program is executed by a computer, the computer can implement the data transmission method provided in the above method embodiment.

[0106] An embodiment of the present application also provides a chip, including a processor and a communication interface. The communication interface is used to receive and / or send data; the processor is used to enable the chip to implement the data transmission method provided in the above method embodiment.

[0107] Those skilled in the art should understand that the embodiments of the present application may be provided as a method, a system, or a computer program product. Therefore, the present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0108] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate for implementation in the processFigure 1 means for the functions specified in one or more processes and / or boxes Figure 1 or boxes.

[0109] These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means that implement the functions specified in one Figure 1 or more processes and / or boxes Figure 1 or boxes.

[0110] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable apparatus provide steps for implementing the functions specified in one Figure 1 or more processes and / or boxes Figure 1 or boxes.

[0111] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A data transmission system, characterized in that, it includes: at least one source switching network interface circuit, at least one switching device, and multiple destination switching network interface circuits, where: The first source switching network interface circuit maps the first service data stream to multiple first data frames, and the destination address field of each of the multiple first data frames includes a load balancing domain, and the load balancing domain is used to implement load balancing of the first switching device; The first source switching network interface circuit sends the multiple first data frames to the first switching device according to an equalization sequence, where an element in the equalization sequence is inserted into the load balancing domain corresponding to each of the multiple first data frames, and the number of elements in the equalization sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit; The first switching device sends the multiple first data frames to the first destination switching network interface circuit; The first destination switching network interface circuit sorts the multiple first data frames and decapsulates the sorted multiple first data frames to obtain the first service data stream; wherein, the first source switching network interface circuit is any one of the at least one source switching network interface circuit, the first switching device is one or more of the at least one switching device, and the first destination switching network interface circuit is any one of the multiple destination switching network interface circuits.

2. The system according to claim 1, characterized in that, when the first switching device is a single-stage switching device, the number of elements in the equalization sequence is related to the number of first connection channels, including: The number of elements in the equalization sequence is equal to the number of first connection channels.

3. The system according to claim 1, characterized in that, when the first switching device is an N-stage switching device, the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit, including: The number of first connection channels is the number of connection channels between the Nth-stage switching device in the first switching device and the first destination switching network interface circuit; The number of elements in the equalization sequence is related to the number of first connection channels, including: The number of elements in the equalization sequence is equal to a first value, and the first value is the least common multiple of the number of connection channels between every two-stage switching devices in the N-stage switching device and the number of first connection channels; wherein, N is an integer greater than or equal to 2.

4. The system according to claim 3, characterized in that, The least common multiple is the least common multiple.

5. The system according to any one of claims 1-4, characterized in that, The element inserted into the load balancing domain corresponding to each of the multiple first data frames is related to the receiving port of the first destination switching network interface circuit.

6. The system according to any one of claims 1-4, characterized in that, An element in the equalization sequence is inserted into the load balancing domain corresponding to each of the multiple first data frames, including: In the first data frames of each group in the first P groups of first data frames, H first data frames in each group of first data frames are respectively and sequentially down-sampled by elements in the equalization sequence; Q first data frames in the (P + 1)-th group of first data frames are respectively and sequentially down-sampled by the first Q elements in the equalization sequence; Wherein, H is equal to the number of elements in the equalization sequence, P is the integer quotient obtained by dividing T by H, Q is the remainder obtained by dividing T by H, and T is the number of the multiple first data frames; H is an integer greater than or equal to 1, P is an integer greater than or equal to 1, Q is a positive integer, and Q is less than H.

7. The system according to any one of claims 1-4, Characterized in that, The source address field of each first data frame of the multiple first data frames includes a first domain, and the first domain is used to indicate the sorting of each first data frame of the multiple first data frames; Before the first source switching network interface circuit sends the multiple first data frames to the first switching device according to the equalization sequence, it further includes: The first source switching network interface circuit inserts a timestamp or a serial number into the first domain corresponding to each first data frame of the multiple first data frames in a set order.

8. The system according to claim 7, Characterized in that, The first destination switching network interface circuit sorts the multiple first data frames, including: The first destination switching network interface circuit sorts the multiple first data frames according to the timestamp or the serial number in the first domain corresponding to each first data frame of the multiple first data frames.

9. The system according to any one of claims 1-4, Characterized in that, At least one of the switching devices is a local area network switching LSW switching chip.

10. A data transmission method, Characterized in that, Including: Mapping a first service data stream to multiple first data frames, and the destination address field of each first data frame of the multiple first data frames includes a load balancing domain, and the load balancing domain is used to implement load balancing of the first switching device; Sending the multiple first data frames to the first switching device according to the equalization sequence, wherein, one element in the equalization sequence is inserted into the load balancing domain corresponding to each first data frame of the multiple first data frames, and the number of elements in the equalization sequence is related to the number of first connection channels, and the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit.

11. The method according to claim 10, Characterized in that, When the first switching device is a single-stage switching device, the number of elements in the equalization sequence is related to the number of first connection channels, including: The number of elements in the equalization sequence is equal to the number of first connection channels.

12. The method according to claim 10, Characterized in that, When the first switching device is an N-stage switching device, the number of first connection channels is the number of connection channels between the first switching device and the first destination switching network interface circuit, including: The number of the first connection channels is the number of connection channels between the Nth-level switching device in the first switching device and the first destination switching network interface circuit; The number of elements in the equalization sequence is related to the number of the first connection channels, including: The number of elements in the equalization sequence is equal to a first value, and the first value is the least common multiple of the number of connection channels between every two levels of switching devices in the Nth-level switching device and the number of the first connection channels; wherein, N is an integer greater than or equal to 2.

13. The method according to claim 12, characterized in that the least common multiple is the least common multiple.

14. The method according to any one of claims 10-13, characterized in that the elements inserted into the load balancing domain corresponding to each first data frame among the multiple first data frames are related to the receiving ports of the first destination switching network interface circuit.

15. The method according to any one of claims 10-13, characterized in that one element in the equalization sequence is inserted into the load balancing domain corresponding to each first data frame among the multiple first data frames, including: H first data frames in each group of the first P groups of first data frames are respectively inserted with the elements in the equalization sequence in turn; Q first data frames in the (P + 1)th group of first data frames are respectively inserted with the first Q elements in the equalization sequence in turn; wherein, H is equal to the number of elements in the equalization sequence, P is the integer quotient obtained by dividing T by H, Q is the remainder obtained by dividing T by H, and T is the number of the multiple first data frames; H is an integer greater than or equal to 1, P is an integer greater than or equal to 1, Q is a positive integer, and Q is less than H.

16. The method according to any one of claims 10-13, characterized in that the source address field of each first data frame among the multiple first data frames includes a first domain, and the first domain is used to indicate the sorting of each first data frame among the multiple first data frames; Before sending the multiple first data frames to the first switching device according to the equalization sequence, the method further includes: inserting a timestamp or a serial number into the first domain corresponding to each first data frame among the multiple first data frames in a set order.

17. A data transmission device, characterized in that it includes a memory, a processor and a communication interface, wherein: the memory is used for storing computer instructions; the communication interface is used for receiving and sending data; the processor is coupled with the memory and is used for calling the computer instructions in the memory to enable the data transmission device to execute the method according to any one of claims 10-16.

18. A data transmission device, characterized in that it includes a processor and a communication interface, wherein: the communication interface is used for receiving and sending data; the processor is used for enabling the data transmission device to execute the method according to any one of claims 10-16.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions that, when called by the computer, are used to cause the computer to execute the method described in any one of claims 10-16 above.

20. A computer program product comprising instructions, wherein, when the computer program product runs on a computer, it causes the computer to execute the method described in any one of claims 10-16.

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