Synchronization method for high-frequency and low-frequency clocks

Abstract

The present invention discloses a synchronization method between high-frequency and low-frequency clocks, which includes: when a sleep enable signal is received, recording the current time of the low-frequency clock as the first low-frequency clock time T0, and triggering a sleep signal by the low-frequency clock; when a sleep signal is received, recording the current time of the high-frequency clock as the first high-frequency clock time t0, and the high-frequency clock stops timing and enters sleep; when a wake-up enable signal is received, recording the current time of the low-frequency clock as the second low-frequency clock time T1, and triggering a wake-up signal by the low-frequency clock; and when a wake-up signal is received, waking up the high-frequency clock, calculating the sleep time T1 - T0 and determining the delay time t_delay, so as to update the current time of the high-frequency clock with the sleep time T1 - T0 and the delay time t_delay. The present invention uses the signal generated at the moment when the count of the low-frequency clock counter changes to control the switch of the high-frequency clock module, achieving the purpose of accurate synchronization between the high-frequency and low-frequency clock domains.

Description

Technical Field

[0001] The present invention relates to the technical field of clock synchronization, and particularly to a synchronization method for high-frequency and low-frequency clocks. Background Art

[0002] Low-power systems, such as low-power MCUs, can save power by going into sleep mode. For example, in applications with low-power Bluetooth (BLE) connections, the connection event interval can be as short as 7.5 ms and as long as 4 s. It takes about 300 μs for software and hardware to process one connection event. Therefore, during a large part of the time between the current connection and the next connection event, software and hardware intervention is not required. At this time, the MCU can be set to the sleep state to save power. When the next connection time arrives, the MCU is woken up by a time interrupt and enters the normal working state.

[0003] Low-power MCUs generally have a CPU, RAM, FLASH, data bus, high-frequency clock module (i.e., high-frequency clock, generally driven by an external crystal oscillator, with common main frequencies of 32 M and 40 M and a working current of 80 μA to 150 μA), low-frequency clock module (i.e., low-frequency clock, generally driven by an external crystal oscillator, with a common main frequency of 32.768 kHz and a working current of about 0.2 μA), and various peripheral modules (such as GPIO, UART, I2C, SPI, etc.). Before the low-power MCU enters the sleep mode, many internal modules including the high-frequency clock need to be turned off, and the low-frequency clock is used for timing and wake-up operations to achieve the purpose of saving power.

[0004] After the MCU is woken up, some modules such as the LC module of BLE, the system OS module, and some modules with real-time requirements need to compensate the sleep time into the internal clock of the module. The currently common clock compensation method is as follows:

[0005] 1. Before the MCU goes to sleep, the software records the time T0 of the low-frequency clock at the time of sleep (with an error of 0 to 1 clock cycle (tick)), stops the internal (high-frequency) clock of the module, and records the current time t0 of the module;

[0006] 2. After the MCU is woken up, the software reads the current time T1 of the low-frequency clock again (with an error of 0 to 1 tick);

[0007] 3. The software calculates the sleep time = T1 - T0, converts this time, and compensates it into the internal clock of the module, enables the internal clock of the module, and the module starts timing independently.

[0008] The process of the software putting the internal modules (i.e., subroutines) of the MCU into sleep and waking them up can be seen in Figure 1 , and this software is usually the code running in the CPU.

[0009] However, in the process of compensating the time of the low-frequency clock to the time of the high-frequency clock, there are problems such as inability to achieve precise synchronization, complex software operations, large and uncertain delays, specifically including:

[0010] 1. Large time error. For example, the maximum error in steps 1 and 2 of the above method is 2 ticks of the low-frequency clock (calculated with an external crystal oscillator of 32.768 kHz, approximately 2×30.5 μs, i.e., 61 μs);

[0011] 2. Complex software operations. The time difference introduced by software operations is difficult to quantify, and the delay for each operation is uncertain;

[0012] 3. The entire time synchronization process consumes a long time;

[0013] 4. In the actual design process of hardware and software, it is necessary to sacrifice performance and power consumption to eliminate the impact of time error.

[0014] In response to these above problems, there are currently some improved technical solutions. For example, in the "Method and Device for Clock Technology Synchronization" with Chinese Patent Application No. 202110585580.5, it is proposed to perform synchronization based on the principle of the least common multiple between the period of the low-frequency clock (32 kHz) and the period of the high-frequency clock (24 MHz), so as to simplify software operations. However, the time synchronization process consumes a long time and cannot effectively solve the problem of time error.

[0015] In addition, in the "Method and Device for Starting a High-Frequency Clock after a Sleep Mode in a Mobile Station Operating in a Time-Slot Paging Mode" with Chinese Patent Application No. 00818116.0, it is proposed to use a transition mode clock preferably with the same frequency as the active mode high-frequency clock to partially compensate for frequency drift and timing deviation. This transition mode clock is used at the beginning and end of each sleep cycle, and can accurately record the number of active mode high-frequency clock cycles to be compensated within one low-frequency sleep clock cycle at the beginning and end of each sleep cycle. However, additionally using the transition mode clock still requires sacrificing performance and power consumption, and the operations of its software / hardware are relatively complex. Specifically, in this method and device, the sleep time needs to be predicted in advance, and then a wake-up time of a high-frequency clock is calculated based on the sleep time, and the high-frequency clock needs to run in advance for a period of time before the actual end of the sleep. Therefore, if the system wakes up in advance (woken up by an external GPIO interrupt) using this method, clock synchronization cannot be performed, and since the high-frequency clock needs to be turned on a long time in advance, the power consumption is still large. In addition, this method and device include multiple module designs, and the implementation is relatively complex, and it is difficult to be actually applied to a low-power MCU.

[0016] Therefore, it is necessary to design a synchronization method for high- and low-frequency clocks to solve the above-mentioned technical problems. Summary of the Invention

[0017] To achieve the above object, the present invention provides a synchronization method for high- and low-frequency clocks, which includes:

[0018] Step 100, when a sleep enable signal is received, record the current time of the low-frequency clock as the first low-frequency clock time T0, and trigger a sleep signal by the low-frequency clock;

[0019] Step 200, when a sleep signal is received, record the current time of the high-frequency clock as the first high-frequency clock time t0, and the high-frequency clock stops timing and enters sleep;

[0020] Step 300, when a wake-up enable signal is received, record the current time of the low-frequency clock as the second low-frequency clock time T1, and trigger a wake-up signal by the low-frequency clock; and

[0021] Step 400, when a wake-up signal is received, wake up the high-frequency clock, calculate the sleep time T1 - T0, and determine the delay time t_delay, so as to update the current time of the high-frequency clock with the sleep time T1 - T0 and the delay time t_delay.

[0022] Among them, step 400 may include: first wake up the high-frequency clock to start timing from the first high-frequency clock time t0, and after calculating the sleep time T1 - T0 and determining the delay time t_delay, send a time update signal to the high-frequency clock, instructing the high-frequency clock to add (T1 - T0) + t_delay to its current time to update its current time; where the delay time t_delay is the time for signal transmission, which is a fixed value and can be determined in advance;

[0023] Step 400 may also include: first calculate the sleep time T1 - T0 and determine the delay time t_delay, and after completion, wake up the high-frequency clock and send a time update signal to it, instructing the high-frequency clock to update its current time to t0 + (T1 - T0) + t_delay and start timing from the updated time; where the delay time t_delay is the time for calculation and signal transmission, which is a fixed value and can be determined in advance.

[0024] It can be seen that, compared with directly putting the high-frequency clock into sleep and waking it up in the prior art, in the present invention, the low-frequency clock is used to trigger the sleep and wake-up signals, so that the high-frequency clock enters the sleep state and is woken up, and the sleep time can be accurately calculated, and the time of the high-frequency clock can be accurately updated based on this (excluding the above-mentioned delay time t_delay, at least it can be accurate to 2 ticks of the high-frequency clock), thereby realizing the precise synchronization between the high-frequency and low-frequency clocks. This method has a short synchronization time, does not require introducing an additional clock, and has simple operation and low power consumption.

[0025] In a preferred embodiment, the MCU has a high-frequency clock module, a low-frequency clock module, and a signal conversion module. The high-frequency clock module includes a high-frequency clock, a high-frequency clock counter for counting the clock cycles of the high-frequency clock, and one or more high-frequency clock registers for storing the count in the high-frequency clock counter; the low-frequency clock module includes a low-frequency clock, a low-frequency clock counter for counting the clock cycles of the low-frequency clock, and two or more low-frequency clock registers for storing the count in the low-frequency clock counter;

[0026] The time of the high-frequency and low-frequency clocks is determined by the number of their clock cycles. For example, the rising edge (or falling edge) of the high-frequency and low-frequency clock cycles can be used to trigger the high-frequency and low-frequency clock counters to increment by 1 to count the number of high-frequency and low-frequency clock cycles; in this embodiment, the rising edge of the high-frequency and low-frequency clock cycles is used to trigger the high-frequency and low-frequency clock counters to determine the time of the high-frequency and low-frequency clocks;

[0027] The low-frequency clock processes the received signal (such as a sleep / wake-up enable signal) at the falling edge of its clock cycle and issues a signal generation event state (such as a sleep / wake-up signal) at the rising edge of its clock cycle. The high-frequency clock receives and processes the received signal generation event state (such as a sleep / wake-up signal, a time update signal) at the rising edge of its clock cycle.

[0028] In this embodiment, in the synchronization method between the high-frequency and low-frequency clocks, the low-frequency clock is always in the normal working state, and the low-frequency clock counter is always normally counting, and the rising edge of the low-frequency clock cycle sequentially triggers the low-frequency clock counter to increment by 1.

[0029] Step 100 includes: at the first falling edge after the low-frequency clock receives the sleep enable signal, the low-frequency clock processes the sleep enable signal, and at the subsequent first rising edge, issues a sleep signal to the signal conversion module, and stores the count in the low-frequency clock counter triggered by this rising edge into the first low-frequency clock register; thus, the value R0 in the first low-frequency clock register corresponds to the first low-frequency clock time T0.

[0030] Before receiving the sleep signal, the high-frequency clock is in a normal operating state, and the high-frequency clock counter counts normally, where the rising edge of each high-frequency clock cycle triggers the high-frequency clock counter to increment by 1 in sequence.

[0031] Step 200 includes: The high-frequency clock receives and processes the sleep signal at the first rising edge after the sleep signal arrives from the signal conversion module. After triggering the high-frequency clock counter to increment by 1 at this rising edge, the high-frequency clock enters the sleep state, and the high-frequency clock counter stops counting accordingly; thus, the count N in the high-frequency clock corresponds to the first high-frequency clock time t0.

[0032] Step 300 includes: The low-frequency clock processes the wake-up enable signal at the first falling edge after receiving the wake-up enable signal, and issues a wake-up signal to the signal conversion module at the subsequent first rising edge, storing the count of the low-frequency clock counter triggered by this rising edge into the second low-frequency clock register; thus, the value R1 in the second low-frequency clock register corresponds to the second low-frequency clock time T1.

[0033] Step 400 includes: After receiving the wake-up signal from the signal conversion module, the high-frequency clock is awakened and continues its clock cycle from the rising edge when it enters the sleep state, and the rising edge of its clock cycle continues to trigger the high-frequency clock counter to increment by 1 in sequence, and the high-frequency clock counter starts counting from N;

[0034] The signal conversion module calculates the number of high-frequency clock sleep time periods (R1 - R0) × f_hfc / f_lfc corresponding to the sleep time T1 - T0, and determines the delay time t_delay expressed as the number of high-frequency clock cycle counts. After completion, it sends a time update signal to the high-frequency clock. The high-frequency clock processes the time update signal at the rising edge of receiving the time update signal, and stores the number of high-frequency clock sleep time periods r0 = (R1 - R0) × f_hfc / f_lfc + t_delay into the high-frequency clock register. After triggering the high-frequency clock counter to increment by 1 at the subsequent rising edge, the value r0 in the high-frequency clock register is added to the current count N' of the high-frequency clock counter, and the high-frequency clock timer continues to count from the value N' + r0. Wherein, f_hfc is the clock frequency of the high-frequency clock, and f_lfc is the clock frequency of the low-frequency clock.

[0035] Preferably, the sleep enable signal is issued by the Bluetooth controller module of the MCU, and the wake-up enable signal is issued by the sleep management module of the MCU.

[0036] In other embodiments, the sleep enable signal and / or the wake-up enable signal are issued by software.

[0037] In other embodiments, the sleep signal, the wake-up signal, and / or the time update signal are issued by software.

[0038] In other embodiments, only one signal can be used for the low-frequency clock module. Before entering the sleep mode, this signal is triggered to generate an event. At the moment when the low-frequency clock counter changes, its current count value (i.e., the changed count value) is latched into a low-frequency clock register, and an event is generated. After the software waits for this event, this value is read out. After exiting the sleep mode, this signal is triggered again. At the moment when the low-frequency clock counter changes, its current count value is latched into a low-frequency clock register, and the same event is generated. The software reads out this count value. Additionally, the latched value can also be the count value before the low-frequency clock counter changes.

[0039] That is, some functions of the signal conversion module adopted in this application can be implemented by software. Additionally, for example, before entering the sleep mode, the software can use the event generated by the low-frequency clock module to trigger the sleep signal of the high-frequency clock module through certain means. After waking up, the software can use the time generated by the low-frequency clock module to trigger the wake-up signal of the high-frequency clock module through certain means. The calculation of the sleep time can also be completed by the software.

[0040] It can be seen that the present invention controls the low-frequency clock by outputting a control signal to the low-frequency clock module, and controls the low-frequency clock to latch the count value into the low-frequency clock register at the moment of the most recent change of the low-frequency clock timer. A signal is generated at the moment when the count of the low-frequency clock counter changes to control the on / off of the high-frequency clock module, achieving the purpose of precise synchronization between the high-frequency and low-frequency clock domains. Moreover, the present invention can achieve the jump of the count value of the high-frequency clock counter during operation (which cannot be achieved by the existing software-based clock compensation method) by outputting a time update signal to the high-frequency clock module and through the high-frequency clock register, thereby achieving the purpose of time synchronization. The present invention mainly uses a hardware circuit to synchronize the clock. Therefore, the relevant operation delays, such as the delays caused by signal conversion, counter value conversion, etc., can be quantitatively compensated. And the present invention can achieve hardware automatic synchronization, basically without the intervention of software, without occupying CPU resources for a long time, and realizes fast and efficient synchronization.

[0041] The following will further illustrate the concept, specific structure and technical effects of the present invention with reference to the accompanying drawings to fully understand the purpose, features and effects of the present invention. Description of the Drawings

[0042] Figure 1 is a flowchart of the prior art software sleep and wake-up subroutines.

[0043] Figure 2 is a system for implementing the synchronization method between high-frequency and low-frequency clocks of the present invention in a preferred embodiment.

[0044] Figure 3In a preferred embodiment, during the process of implementing the method for synchronizing high and low frequency clocks according to the present invention, Figure 2 The module timing diagram in the system shown.

[0045] Figure 4 Depicts Figure 2 An example of signal processing and event generation of the low frequency clock module in the system shown.

[0046] Figure 5 Is for sending Figure 2 An example of the control structure for sending control signals to the low frequency clock module in the system shown.

[0047] Figure 6 Depicts Figure 2 An example of signal processing and event generation of the high frequency clock module in the system shown.

[0048] Figure 7 Is for sending Figure 2 An example of the control structure for sending control signals to the high frequency clock module in the system shown. Detailed implementation

[0049] In a preferred embodiment of the present invention, there is provided a method for synchronizing high and low frequency clocks according to the present invention, where the low power MCU has a high frequency clock module, a low frequency clock module, and a signal conversion module, and implements the method for synchronizing high and low frequency clocks according to the present invention, as Figure 2 Shown. The present invention is also applicable to other systems with a sleep function for synchronizing high and low frequency clocks therein.

[0050] In this embodiment, the high frequency clock module of the low power MCU includes a high frequency clock, a high frequency clock counter counter for counting the clock cycles of the high frequency clock, and one or more high frequency clock registers r0, r1,..., rn for storing the count in the high frequency clock counter. The clock frequency of the high frequency clock is 40 MHz, and it receives control signals from the signal conversion module, such as a sleep signal timer_stop, a time update signal timer_update, and a wake-up signal timer_start.

[0051] The low-frequency clock module of the low-power MCU includes a low-frequency clock, a low-frequency clock counter COUNTER that counts the clock cycles of the low-frequency clock, and two or more low-frequency clock registers R0, R1, …, Rn for storing the count in the high-frequency clock counter. The clock frequency of the low-frequency clock is 32.768 kHz. It receives control signals from outside, such as a sleep enable signal sleep_en and a wake-up enable signal wakeup_en, and sends control signals to the signal conversion module, such as a sleep signal sleep_done and a wake-up signal wakeup_done.

[0052] The signal conversion module of the low-power MCU is used to relay control signals, such as a sleep signal and a wake-up signal, between the high-frequency clock module and the low-frequency clock module. That is, after receiving the sleep signal sleep_done from the low-frequency clock module, it sends a sleep signal timer_stop to the high-frequency clock module, and after receiving the wake-up signal wakeup_done from the low-frequency clock module, it sends a wake-up signal timer_start to the high-frequency clock module. The signal conversion module is also used to perform calculations on the sleep time, determine the delay time, and send a time update signal timer_update to the high-frequency clock after completing the calculations and determinations.

[0053] It should be noted that these modules described here do not have to be physically independent hardware. They can include software to implement some of their functions, and they do not have to be physically clearly separable in the MCU. For example, the high- and low-frequency clock registers can be registers in the MCU, and the signal conversion module can include software for triggering the sleep / wake-up of the high-frequency clock module, etc.

[0054] The time of the high- and low-frequency clocks is determined by the number of their clock cycles. For example, the high- and low-frequency clock counters can be incremented by 1 by triggering on the rising or falling edge of the high- and low-frequency clock cycles to count the number of high- and low-frequency clock cycles. The low-frequency clock can process the received control signals at the falling or rising edge of its clock cycle and generate an event state of the control signal at the rising or falling edge of its clock cycle. The high-frequency clock can receive and process the received control signals to generate an event state at the rising or falling edge of its clock cycle.

[0055] In this embodiment, the rising edge of the high- and low-frequency clock cycles is used to trigger the high- and low-frequency clock counters to determine the high- and low-frequency clock time. The low-frequency clock processes the received signals at the falling edge of its clock cycle and sends the sleep / wake-up signals at the rising edge of its clock cycle. The high-frequency clock receives and processes the received signals at the rising edge of its clock cycle.

[0056] Figure 3The module timing diagram during the process of synchronizing between high-frequency and low-frequency clocks is shown. The following will describe the method for synchronizing between high-frequency and low-frequency clocks according to the present invention in combination with Figure 3 as follows. As Figure 3 shown, the synchronization method mainly includes four steps, namely:

[0057] Step 100, when receiving the sleep enable signal, latch the current count R0 of the low-frequency clock counter COUNTER as the current time T0 of the low-frequency clock, and trigger the sleep signal by the low-frequency clock;

[0058] Step 200, when receiving the sleep signal, record the current count N of the high-frequency clock counter counter as the current time t0 of the high-frequency clock, and the high-frequency clock enters the sleep state, and the high-frequency clock counter stops counting;

[0059] Step 300, when receiving the wake-up enable signal, latch the current count R1 of the low-frequency clock counter COUNTER as the current time T1 of the low-frequency clock, and trigger the wake-up signal by the low-frequency clock; and

[0060] Step 400, when receiving the wake-up signal, first wake up the high-frequency clock to start timing from the time t0 before sleep. Correspondingly, the high-frequency clock counter counter starts counting from the count N before sleep to N'. During this period, the signal conversion module calculates the sleep time LFC_T representing the number of clock cycles of the low-frequency clock as T1 - T0. The signal conversion module converts the sleep time LFC_T representing the number of clock cycles of the low-frequency clock into the sleep time HFC_T representing the number of clock cycles of the high-frequency clock as HFC_T = LFC_T * f_hfc / f_lfc. The signal conversion module determines the delay time t_delay representing the number of clock cycles of the high-frequency clock, and stores the number of clock cycles HFC_T + t_delay to be compensated to the high-frequency clock into the high-frequency clock register r0, that is, r0 = HFC_T + t_delay. Then, a time update signal is sent to the high-frequency clock, making the high-frequency clock counter start counting from N' + r0, thereby updating the current time of the high-frequency clock. The delay time t_delay is the time for signal transmission, which is a fixed value and can be determined in advance, for example, by hardware simulation or by theoretical analysis.

[0061] In other embodiments, step 400 may also be that when a wake-up signal is received, first calculate the sleep time T1 - T0 and determine the delay time t_delay, and after completion, wake up the high-frequency clock and send a time update signal to it, instructing the high-frequency clock to update its current time to t0+(T1 - T0)+t_delay and start timing from the updated time; where the delay time t_delay is the time for calculation and signal transmission, which is a fixed value and can be determined in advance through hardware simulation. The execution of step 400 in other embodiments is similar to the process described above regarding Figure 3 and thus it can be determined similarly that in this embodiment, the high-frequency clock counter starts counting from N + r0 = N + HFC_T + t_delay = N + LFC_T * f_hfc / f_lfc + t_delay. The following will mainly describe the operations in this embodiment regarding Figure 3 and those skilled in the art can understand the operations of step 400 in other embodiments from this.

[0062] Specifically, the low-frequency clock is always in a normal working state, and the low-frequency clock counter always counts normally, where the rising edge of the low-frequency clock period triggers the low-frequency clock counter to increment by 1 in sequence.

[0063] In step 100, the sleep enable signal sleep_en from outside the low-frequency clock module arrives at the low-frequency clock module. At the first falling edge in the low-frequency clock period after receiving the sleep enable signal sleep_en, process the sleep enable signal sleep_en, and at the subsequent first rising edge, send the sleep signal sleep_done to the high-frequency clock module via the signal conversion module, and store the count of the low-frequency clock counter COUNTER triggered by this rising edge into the first low-frequency clock register R0; thus the value in the first low-frequency clock register R0 (herein referring to the value by the register number, so this value is also denoted as R0) corresponds to the first low-frequency clock time T0.

[0064] For example, referring to the example in Figure 4 , the external sleep enable signal sleep_en arrives at the low-frequency clock in the first half of the first period shown in the figure. The low-frequency clock then processes the sleep enable signal sleep_en at the falling edge within this first period and sends the sleep signal sleep_done at the subsequent rising edge (i.e., the end of this first period).

[0065] As described above, the low-frequency clock counter COUNTER has been working. However, for the sake of easy understanding, it is assumed here that the count of the low-frequency clock counter COUNTER was 0 before, so that it is triggered by the rising edge at the end of the first cycle, and the count is incremented by 1, that is, the count therein is 1. The count 1 of the low-frequency clock counter COUNTER triggered by this rising edge is stored in the first low-frequency clock register R0, so R0 = 1.

[0066] In this embodiment, the sleep enable signal sleep_en is issued by the Bluetooth controller module of the MCU. However, in other embodiments, it can also be issued by software, as in the prior art software-based clock compensation method. A control structure as shown in Figure 5 can be used to handle the above two cases, that is, whether the sleep enable signal sleep_en is issued by a hardware module such as the Bluetooth controller module (i.e., the hardware sleep signal in the figure) or by software (i.e., software sleep), the sleep enable signal sleep_en can be sent to the low-frequency clock module through the control structure shown in Figure 5 .

[0067] In step 200, the signal conversion module relays the sleep signal from the low-frequency clock module to the high-frequency clock module, that is, after receiving the sleep signal sleep_en from the low-frequency clock module, it issues a sleep signal timer_stop to the high-frequency clock module to stop the high-frequency clock from timing.

[0068] The time required for the signal conversion module to relay this sleep signal is very short and fixed, generally several clock cycles of the driving clock (such as 40 MHz) of the digital module that constructs the signal conversion module.

[0069] Before receiving the sleep signal timer_stop, the high-frequency clock is in a normal working state, and the high-frequency clock counter counts normally, where the rising edge of the high-frequency clock cycle sequentially triggers the high-frequency clock counter to increment by 1.

[0070] At the first rising edge of the high-frequency clock cycle after the sleep signal timer_stop arrives at the high-frequency clock module, the sleep signal timer_stop is received and processed, and the count N of the high-frequency clock counter counter triggered by this rising edge is retained in the counter, corresponding to the first high-frequency clock time t1; at the same time, the high-frequency clock completes the current clock cycle and stops, and the high-frequency clock counter counter stops accordingly.

[0071] For example, see Figure 6In the example in [description], the sleep signal timer_stop from the signal conversion module reaches the high-frequency clock at the falling edge in the second cycle shown in the figure. The high-frequency clock then processes the sleep signal timer_stop at the subsequent rising edge (i.e., at the end of the second cycle), and the rising edge triggers the high-frequency clock counter counter, and the count of the high-frequency clock counter counter is incremented by 1 and becomes 2. At the same time, the high-frequency clock completes the current clock cycle (i.e., the second clock cycle in the figure) and stops, and the high-frequency clock counter stops accordingly and holds its count of 2.

[0072] In this embodiment, the sleep signal timer_stop is issued by the signal conversion module, but in other embodiments, it can also be issued by software, as in the prior art software-based clock compensation method. A control structure as shown in Figure 7 can be used to handle the above two cases, that is, whether the sleep signal timer_stop is issued via the signal conversion module (i.e., the hardware stop clock signal in the figure) or by software (i.e., software stop clock), the sleep signal timer_stop can be sent to the high-frequency clock module through the control structure shown in Figure 7 .

[0073] In step 300, the wake-up enable signal wakeup_en from outside the low-frequency clock reaches the low-frequency clock module. At the first falling edge in the low-frequency clock cycle after receiving the wake-up enable signal wakeup_en, the wake-up enable signal wakeup_en is processed, and a wake-up signal wakeup_done is issued at the subsequent first rising edge via the signal conversion module to the high-frequency clock module, and the count of the low-frequency clock counter COUNTER triggered by the rising edge is stored in the second low-frequency clock register R1; thus the value in the second low-frequency clock register R1 (herein the value is denoted by the register number, so this value is also denoted as R1) corresponds to the second low-frequency clock time T1.

[0074] For example, see the example in Figure 4 . The external sleep enable signal wakeup_en reaches the low-frequency clock at the falling edge in the fourth cycle shown in the figure. The low-frequency clock then has to process the wake-up enable signal wakeup_en at the next falling edge, i.e., the falling edge within the fifth cycle, and issue a wake-up signal wakeup_done at the subsequent rising edge (i.e., at the end of the fifth cycle).

[0075] As described above, the low-frequency clock counter COUNTER has been working, so it is triggered by the rising edge at the end of the fifth cycle, and the count after incrementing the count by 1 is 5. The count 5 of the low-frequency clock counter COUNTER triggered by this rising edge is stored in the second low-frequency clock register R1, so R1 = 5.

[0076] Similarly, a control structure as shown in Figure 5 can be used to handle the above two cases, that is, regardless of whether the wake-up enable signal wakeup_en is sent by a hardware module such as a Bluetooth controller module (i.e., the hardware wake-up signal in the figure) or sent by software (i.e., software wake-up), the wake-up enable signal wakeup_en can be sent to the low-frequency clock module through the Figure 5 control structure shown.

[0077] In step 400, after receiving the wake-up signal wakeup_done from the low-frequency clock module, the signal conversion module needs to send a wake-up signal timer_start to the high-frequency clock module, and also needs to calculate the sleep time based on the count of the low-frequency clock counter, thereby calculating the clock cycles that need to compensate for the high-frequency clock during sleep, and sending a time update signal timer_update to the high-frequency clock module to update the timing (i.e., counting) of the compensated high-frequency clock.

[0078] As described above, the order of the wake-up signal timer_start and the time update signal timer_update sent by the signal conversion module to the high-frequency clock module can be adjusted, that is, the wake-up signal timer_start can be sent first to make the high-frequency clock start timing from the clock time before sleep, and then the high-frequency clock time can be updated with the calculation result, or the time update signal timer_update can be sent first to update the high-frequency clock time with the calculation result, and then the high-frequency clock can be awakened to start timing from the updated clock time.

[0079] In this embodiment, the signal conversion module first sends the wake-up signal timer_start, and then performs calculations and sends the time update signal timer_update, which is specifically described as follows.

[0080] The signal conversion module sends the wake-up signal timer_start to the high-frequency clock module immediately after receiving the wake-up signal wakeup_done from the low-frequency clock module. In Figure 6In the example shown, the high-frequency clock enters the sleep state after the second clock cycle (the corresponding clock cycles are shown as dashed lines), and the high-frequency clock counter "counter" stops counting and maintains its count at 2, which is the count at the time of sleep. When the wake-up signal "timer_start" arrives at the high-frequency clock, the high-frequency clock is awakened and continues its clock cycle from the rising edge at which it entered the sleep state (i.e., the rising edge at the end of the second clock cycle, which is also the rising edge at the end of the sixth clock cycle after accounting for the four clock cycles during the sleep period). Thus, the subsequent rising edge (i.e., the rising edge at the end of the seventh clock cycle in the figure, where the four clock cycles during the sleep period are accounted for) triggers the high-frequency clock counter "counter" to increment its count by 1, becoming 3; the high-frequency clock continues to count normally, and the rising edge of its clock cycle sequentially triggers the high-frequency clock counter to increment by 1.

[0081] During this period, the signal conversion module calculates the number of clock cycles that need to compensate for the high-frequency clock during the sleep period, and after the calculation is completed, sends a time update signal "timer_update" to the high-frequency clock module.

[0082] The number of clock cycles that need to compensate for the high-frequency clock during the sleep period includes two parts: The first part is the number of high-frequency clock sleep time cycles corresponding to the sleep time T1 - T0, which is (R1 - R0) × f_hfc / f_lfc, where f_hfc is the clock frequency of the high-frequency clock and f_lfc is the clock frequency of the low-frequency clock. The second part is the delay time t_delay, which is expressed as the number of high-frequency clock sleep time cycles. It should be noted that in this embodiment, since the signal conversion module first sends the wake-up signal "timer_start", and then performs the calculation and sends the time update signal "timer_update", the time used by the signal conversion module for calculation has been counted by the awakened high-frequency clock. At this time, the delay time t_delay that needs to be considered is mainly the time for signal transmission. The time for signal transmission of the signal conversion module as a hardware module is a fixed value, which is expressed as the number of clock cycles of the high-frequency clock and is usually 3 high-frequency clock cycles. However, in other embodiments, if the signal conversion module first performs the calculation and sends the time update signal "timer_update", and then sends the wake-up signal "timer_start", then the delay time t_delay that needs to be considered also includes the time for calculation. The time for calculation of the signal conversion module as a hardware module is also a fixed value, which is expressed as the number of clock cycles of the high-frequency clock and is usually 83 high-frequency clock cycles.

[0083] As mentioned above, in this embodiment, the clock frequency of the high-frequency clock adopted is 40 MHz, and the clock frequency of the low-frequency clock is 32.768 kHz. Therefore, the actual calculated f_hfc / f_lfc is quite large (greater than 1000), which is not convenient for illustration. In order to be able toFigure 6 The process of compensating the clock cycles of the high-frequency clock is clearly shown above. Here, it is assumed that f_hfc / f_lfc = 1 (that is, the actual clock frequencies of the high and low-frequency clocks in this embodiment are ignored). Then, substituting R1 = 5 and R0 = 1 obtained from the previous example into the formula (R1 - R0)×f_hfc / f_lfc, the number of high-frequency clock sleep time periods HFC_T corresponding to the sleep time LFC_T = R1 - R0 can be obtained as 4. Additionally, for convenience, the delay time is not considered here, that is, the delay time t_delay = 0 is taken, so as to determine that the number of high-frequency clock cycles r0 to be compensated is r0 = HFC_T + t_delay = 4.

[0084] The signal conversion module then stores the number of high-frequency clock cycles r0 to be compensated determined by the signal conversion module into the high-frequency clock register r0, that is, r0 = 4 (here, the value is represented by the register number, so this value is also denoted as r0), and immediately sends a time update signal timer_update to the high-frequency clock. In this example, as Figure 6 shown, the high-frequency clock receives and processes this time update signal timer_update at the next rising edge (that is, the rising edge at the end of the tenth clock cycle). This rising edge triggers the count of the high-frequency clock counter to increment by 1, changing from 5 to 6, that is, the current count N' = 6. At the same time, the value r0 in the high-frequency clock register is added to the current count N' of the high-frequency clock counter, and this value N' + r0 = 6 + 4 = 10. The high-frequency clock timer continues to count starting from 10. It can be seen that the high-frequency clock has been successfully compensated for the clock cycles during its sleep period, and the synchronization between the high and low-frequency clocks is completed.

[0085] The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations based on the concept of the present invention without creative efforts. Therefore, all technical solutions that can be obtained by those skilled in the art of this technology based on the concept of the present invention through logical analysis, reasoning, or limited experiments on the basis of the prior art should be within the protection scope determined by the claims.

Claims

1. A synchronization method between high-frequency and low-frequency clocks, comprising: Step 100, when receiving a sleep enable signal, record the current time of the low-frequency clock as the first low-frequency clock time T0, and trigger a sleep signal by the low-frequency clock; Step 200, when receiving the sleep signal, record the current time of the high-frequency clock as the first high-frequency clock time t0, and the high-frequency clock stops timing and enters sleep; Step 300, when receiving a wake-up enable signal, record the current time of the low-frequency clock as the second low-frequency clock time T1, and trigger a wake-up signal by the low-frequency clock; And Step 400, when receiving the wake-up signal, wake up the high-frequency clock, calculate the sleep time T1 - T0, and determine the delay time t_delay, so as to update the current time of the high-frequency clock with the sleep time T1 - T0 and the delay time t_delay.

2. The method according to claim 1, characterized in that The step 400 includes: First, wake up the high-frequency clock to start timing from the first high-frequency clock time t0, and after calculating the sleep time T1 - T0 and determining the delay time t_delay, send a time update signal to the high-frequency clock, instructing the high-frequency clock to add (T1 - T0) + t_delay to its current time; Wherein the delay time t_delay is the time for signal transmission, which is a fixed value and can be determined in advance.

3. The method according to claim 1, characterized in that, The step 400 includes: First, calculate the sleep time T1 - T0 and determine the delay time t_delay, and after completion, wake up the high-frequency clock and send a time update signal to it, instructing the high-frequency clock to update its current time to t0 + (T1 - T0) + t_delay and start timing from the updated time; Wherein the delay time t_delay is the time for calculation and signal transmission, which is a fixed value and can be determined in advance.

4. The method according to claim 2, wherein The MCU has a high-frequency clock module, a low-frequency clock module, and a signal conversion module, Wherein the high-frequency clock module includes the high-frequency clock, a high-frequency clock counter for counting the clock cycles of the high-frequency clock, and one or more high-frequency clock registers for storing the count in the high-frequency clock counter; the low-frequency clock module includes the low-frequency clock, a low-frequency clock counter for counting the clock cycles of the low-frequency clock, and two or more low-frequency clock registers for storing the count in the low-frequency clock counter; Wherein the low-frequency clock processes the received signal at the falling edge of its clock cycle, the low-frequency clock emits a signal at the rising edge of its clock cycle, and the high-frequency clock receives and processes the received signal at the rising edge of its clock cycle.

5. The method according to claim 4, wherein The step 100 includes: At the first falling edge of the low-frequency clock after receiving the sleep enable signal, process the sleep enable signal, and at the subsequent first rising edge, send a sleep signal to the signal conversion module, and store the count in the low-frequency clock counter triggered by the rising edge into the first low-frequency clock register; thus, the value R0 in the first low-frequency clock register corresponds to the first low-frequency clock time T0.

6. The method according to claim 5, wherein The step 200 includes: At the first rising edge after the sleep signal arrives from the signal conversion module, the high-frequency clock receives and processes the sleep signal. After triggering the high-frequency clock counter to increment by 1 at this rising edge, the high-frequency clock enters the sleep state and the high-frequency clock counter stops counting accordingly. Thus, the count N in the high-frequency clock corresponds to the first high-frequency clock time t0.

7. The method according to claim 6, wherein Step 300 includes: At the first falling edge after the low-frequency clock receives the wake-up enable signal, it processes the wake-up enable signal and sends a wake-up signal to the signal conversion module at the subsequent first rising edge, storing the count of the low-frequency clock counter triggered by this rising edge into the second low-frequency clock register. Thus, the value R1 in the second low-frequency clock register corresponds to the second low-frequency clock time T1.

8. The method according to claim 7, wherein Step 400 includes: After receiving the wake-up signal from the signal conversion module, the high-frequency clock is awakened and continues its clock cycle starting from the rising edge when it entered the sleep state. The subsequent rising edges continue to trigger the high-frequency clock counter to increment by 1 in sequence, and the high-frequency clock counter starts counting from N. The signal conversion module calculates the number of high-frequency clock sleep time periods corresponding to the sleep time T1 - T0, which is (R1 - R0) × f_hfc / f_lfc, and determines the delay time t_delay expressed as the number of high-frequency clock cycle counts. After completion, it sends a time update signal to the high-frequency clock. The high-frequency clock processes the time update signal at the rising edge when it receives the time update signal, storing the number of high-frequency clock sleep time periods r0 = (R1 - R0) × f_hfc / f_lfc + t_delay into the high-frequency clock register. To add the value r0 in the high-frequency clock register to the current count N' of the high-frequency clock counter after triggering the high-frequency clock counter to increment by 1 at the subsequent rising edge, the high-frequency clock counter continues counting from the value N' + r0. Where f_hfc is the clock frequency of the high-frequency clock and f_lfc is the clock frequency of the low-frequency clock.

9. The method according to claim 8, wherein f_hfc is 40 MHz and f_lfc is 32.768 kHz.

10. The method according to any one of claims 4-9, characterized in that, The sleep enable signal is sent by the Bluetooth controller module of the MCU, and the wake-up enable signal is sent by the sleep management module of the MCU.

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