Pixel circuit, display panel, display device and driving method

Abstract

The present invention discloses a pixel circuit, a display panel, a display device and a driving method, wherein the pixel circuit includes: an input unit, a compensation unit, a light-emitting driving unit and a light-emitting unit, wherein the compensation unit is configured to perform driving compensation in response to the control of a second control terminal, and includes: a first transistor, a second transistor and a first storage capacitor, the first electrode of the first transistor is electrically connected to the reference voltage terminal, the second electrode is electrically connected to the first node, the control electrode is electrically connected to the second control terminal, the first electrode of the second transistor is electrically connected to the second node, the second electrode is electrically connected to the third node, the control electrode is electrically connected to the second control terminal, the first terminal of the first storage capacitor is electrically connected to the first node, and the second terminal is electrically connected to the third node. The pixel circuit provided by the embodiment of the present invention can programmably set the compensation timing with a simplified gate line by setting the compensation unit.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit, a display panel, a display device and a driving method. Background Art

[0002] The more mature technologies in the display field are LCD display and active matrix OLED display. In the whole display system, the general technology of OLED products is to stimulate various wavelengths of spectrum through the direct recombination of electrons and holes to form graphics. The display device formed by OLED technology has a fast response speed and can maximize the contrast, so OLED display devices are expected to become the next generation of mainstream display products.

[0003] Generally, due to the limitation of process, all pixel circuits of OLED display are designed with NMOS (or PMOS). However, OLED products themselves need light-emitting devices to emit light, and the required light-emitting current needs to be provided by the driving transistor in the pixel circuit. Therefore, in order to make the product light uniform, the consistency of device characteristics must be increased, which requires compensation for the driving transistor. Since the internal compensation method is adaptive and the external driving IC is simple, small size has been widely used.

[0004] However, currently, the circuit architecture of the internal compensation circuit of the pixel circuit with programmable timing has the problem of complex structure and multiple driving circuits, or the problem of using a large number of control signal gate lines which is not conducive to a narrow frame. Summary of the invention

[0005] In order to solve at least one of the above problems, a first aspect of the present invention provides a pixel circuit, comprising: an input unit, a compensation unit, a light-emitting driving unit and a light-emitting unit, wherein:

[0006] An input unit, electrically connected to the data signal terminal, the first control terminal and the first node, and configured to access a data signal input from the data signal terminal in response to control of the first control terminal;

[0007] a compensation unit, electrically connected to the second control terminal, the reference voltage terminal, the first node, the second node and the third node, and configured to perform driving compensation in response to control of the second control terminal;

[0008] The light-emitting driving unit is electrically connected to the first power signal terminal, the light-emitting control terminal, the third node, and the fourth node, and is configured to generate a driving current for driving the light-emitting unit to emit light in response to the control of the light-emitting control terminal.

[0009] The compensation unit includes: a first transistor, a second transistor and a first storage capacitor.

[0010] The first transistor has a first electrode electrically connected to the reference voltage terminal, a second electrode electrically connected to the first node, and a control electrode electrically connected to the second control terminal.

[0011] The first electrode of the second transistor is electrically connected to the second node, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second control terminal.

[0012] The first storage capacitor has a first terminal electrically connected to the first node, and a second terminal electrically connected to the third node.

[0013] In some optional embodiments, the pixel circuit further includes a storage unit, the storage unit includes a second storage capacitor,

[0014] The first terminal of the second storage capacitor is electrically connected to the first node, and the second terminal of the second storage capacitor is electrically connected to the fourth node.

[0015] In some optional embodiments, the pixel circuit further includes a storage unit, the storage unit includes a second storage capacitor, and a ratio of a capacitance value of the first storage capacitor to a capacitance value of the second storage capacitor is greater than 1.

[0016] The first terminal of the second storage capacitor is electrically connected to the third node, and the second terminal of the second storage capacitor is electrically connected to the fourth node.

[0017] In some optional embodiments, the compensation unit further includes: a third transistor,

[0018] The first electrode of the third transistor is connected to the second reference voltage terminal, the second electrode is electrically connected to the first electrode of the second transistor, and the control terminal is electrically connected to the third control terminal.

[0019] In some optional embodiments, the light-emitting driving unit includes a fourth transistor and a fifth transistor, wherein a first electrode of the fourth transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the light-emitting control terminal; a first electrode of the fifth transistor is electrically connected to the second node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the third node.

[0020] The pixel circuit also includes a potential holding unit, which includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the reference voltage terminal, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the set control terminal.

[0021] In some optional embodiments,

[0022] The signal connected to the set control terminal is the same as the signal connected to the second control terminal, or

[0023] The signal connected to the set signal terminal is connected to a high level signal when the second control terminal and the data signal terminal are connected to a high level signal.

[0024] In some optional embodiments, the light-emitting driving unit includes a fourth transistor and a fifth transistor, wherein a first electrode of the fourth transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the light-emitting control terminal; a first electrode of the fifth transistor is electrically connected to the second node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the third node.

[0025] The pixel circuit further includes a potential holding unit, which includes a seventh transistor and an eighth transistor, wherein a first electrode of the seventh transistor is electrically connected to a reference voltage terminal, a second electrode is electrically connected to a fourth node, and a control electrode is electrically connected to a first setting control terminal, and a first electrode of the eighth transistor is electrically connected to a reference voltage terminal, a second electrode is electrically connected to a fourth node, and a control electrode is electrically connected to a second setting control terminal.

[0026] The signal connected to the first setting control terminal is the same as the signal connected to the second control terminal, and the signal connected to the second setting control terminal is the same as the signal connected to the data signal terminal.

[0027] In some optional embodiments, the data signal terminal is connected to the output signal of the gate shift register of the current frame image, and the signal connected to the second control signal terminal is the signal of the gate shift register of the previous frame image; or

[0028] The data signal terminal is connected to the gate line signal which is independent from each other, and the second control signal terminal is connected to the gate line signal which is independent from each other.

[0029] In some optional embodiments, the input unit includes a ninth transistor, a first electrode of the ninth transistor is electrically connected to the data signal terminal, a second electrode is electrically connected to the first node, a control electrode is electrically connected to the first control terminal, and / or

[0030] The light-emitting unit includes a light-emitting device and an intrinsic capacitor, wherein the anode of the light-emitting device is electrically connected to the fourth node, the cathode is electrically connected to the second power signal terminal, the first terminal of the intrinsic capacitor is electrically connected to the fourth node, and the second terminal is electrically connected to the second power signal terminal.

[0031] A second aspect of the present application provides a display panel, comprising the pixel circuit described above.

[0032] A third aspect of the present application provides a display device, comprising the display panel described above.

[0033] A fourth aspect of the present application provides a driving method applied to the pixel circuit described above, comprising:

[0034] Setting stage: the compensation unit sets the first node and the third node according to the second control signal input from the second control terminal;

[0035] Compensation stage: the compensation unit pulls down the potential of the third node according to the input second control signal, and the first node maintains the potential set in the setting stage under the action of the first storage capacitor;

[0036] Data writing stage: the input unit writes the data signal according to the control input from the first control terminal;

[0037] Light-emitting stage: the light-emitting driving unit forms a driving current according to the light-emitting control signal input from the light-emitting control terminal, the first power signal from the first power signal terminal and the voltage of the third node and drives the light-emitting unit to emit light.

[0038] The beneficial effects of the present invention are as follows:

[0039] In view of the existing problems, the present invention develops a pixel circuit, a display panel, a display device and a driving method, and provides a compensation unit and sets the compensation unit, wherein the compensation unit includes a first transistor, a second transistor and a first storage capacitor, wherein the first storage capacitor is set between a first node and a third node, and the third node is the gate of the driving transistor, and the gate threshold voltage of the driving transistor is compensated by the cooperation of the first transistor and the second transistor with the first storage capacitor, thereby ensuring the consistency of the transistors in the pixel circuit and improving the driving capability of the driving transistor; in addition, the compensation unit makes the circuit structure simple, and can realize programmable compensation timing while simplifying the number of gate lines, which is beneficial to the design of medium and large-sized narrow borders and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1a and 1b It is a schematic diagram of the internal compensation architecture circuit of a pixel circuit in the prior art;

[0042] Figure 2 is a schematic block diagram of a pixel circuit according to an embodiment of the present application;

[0043] Figure 3 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application;

[0044] Figure 4 for Figure 3 A circuit timing diagram of a key signal terminal of the pixel circuit shown;

[0045] Figure 5is a schematic circuit diagram of a pixel circuit according to another embodiment of the present application;

[0046] Figure 6 for Figure 5 A circuit timing diagram of a key signal terminal of the pixel circuit shown;

[0047] Figure 7 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present application;

[0048] Figure 8 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present application;

[0049] Fig. 9 for Figure 8 A circuit timing diagram of a key signal terminal of the pixel circuit shown;

[0050] Fig.10 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present application;

[0051] Fig.11 for Fig.10 A circuit timing diagram of a key signal terminal of the pixel circuit shown;

[0052] Fig.12 is a schematic circuit diagram of a pixel circuit according to another embodiment of the present application; and

[0053] Fig.13 1 is a comparison diagram of driving compensation simulation between a pixel circuit according to an embodiment of the present application and a pixel circuit in related art. DETAILED DESCRIPTION

[0054] In order to more clearly illustrate the present invention, the present invention is further described below in conjunction with preferred embodiments and accompanying drawings. Similar components in the accompanying drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present invention.

[0055] It should be noted that the ordinal numbers such as "first", "second", "third", etc. in this document are not intended to limit the order of the various units, nodes, elements or components, but are only intended to distinguish the various units, nodes, elements or components. The meanings of "including", "comprising", and "having" in this document are open-ended. For example, when describing including units, nodes, elements or components, in addition to these included units, nodes, elements or components, other units, nodes, elements or components may also be included.

[0056] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, their source and drain are interchangeable. In the embodiment of the present invention, the gate of the transistor is called the control electrode, one of the source and the drain is called the first electrode, and the other is called the second electrode. In the embodiment of the present invention, the first electrode of the transistor is called the source electrode, and the second electrode is called the drain electrode. In addition, the pixel circuit of the embodiment of the present invention adopts an N-type transistor and is improved for the driving compensation architecture based on the NMOS transistor. Therefore, the conduction condition of the transistor is that the control electrode is connected to a high-level signal, which will not be repeated below.

[0057] It should also be noted that, because the pixel circuit represents a circuit that drives a pixel point in the display panel, a pixel circuit corresponds to a specific light-emitting device, and the control signal of the gate outputs the control signal row by row under the control of the signal of the gate line. Therefore, the following block diagram or circuit schematic diagram of the pixel circuit represents a pixel circuit in the nth row of pixels, and the n in the control signal represents the signal at the current moment, n-1 represents the signal at the previous moment, and n+1 represents the signal at the next moment, which will not be repeated below.

[0058] In the related art, refer to Figure 1a As shown in the figure, a programmable sequential circuit architecture with a compensation structure of a pixel circuit composed of NMOS is shown in the figure, which is a 5T1C structure, in which 4 groups of gate lines Em(n), G1(n), G2(n) and G3(n) are required to provide gate drive signals, in which each group of gate lines will correspond to a set of gate shift registers or a drive circuit group to drive different rows of pixels, so multiple groups of drive circuits will be required, which is not conducive to high PPI and narrow borders. In the related art, there is another architecture to reduce the number of gate lines, refer to Figure 1b As shown, although this structure reduces the number of gate lines, the G point compensation time is consistent with the data writing time. The compensation time is related to the display frame rate and resolution. The compensation time is not programmable and requires two different EM timings, which is still not conducive to the compensation requirements of medium and large sizes.

[0059] In order to solve one of the above problems, an embodiment of the present invention provides a pixel circuit, referring to Figure 2 As shown, it includes: an input unit 101, a compensation unit 102, a light-emitting driving unit 103 and a light-emitting unit 104, wherein:

[0060] The input unit 101 is electrically connected to the data signal terminal DL, the first control terminal G1(n) and the first node N1, and is configured to receive the data signal input from the data signal terminal DL in response to the control of the first control terminal G1(n);

[0061] The compensation unit 102 is electrically connected to the second control terminal G1(n-1), the reference voltage terminal Ref, the first node N1, the second node N2 and the third node N3, and is configured to perform driving compensation in response to the control of the second control terminal G1(n);

[0062] The light-emitting driving unit 103 is electrically connected to the first power signal terminal VDD, the light-emitting control terminal EM(n), the second node N2, the third node N3, and the fourth node N4, and is configured to generate a driving current for driving the light-emitting unit to emit light in response to the control of the light-emitting control terminal EM(n).

[0063] The compensation unit 102 includes: a first transistor T1, a second transistor T2 and a first storage capacitor Cst1.

[0064] The first transistor T1 has a first electrode electrically connected to the reference voltage terminal Ref, a second electrode electrically connected to the first node N1, and a control electrode electrically connected to the second control terminal G1(n-1).

[0065] The first electrode of the second transistor T2 is electrically connected to the second node N2, the second electrode is electrically connected to the third node N3, and the control electrode is electrically connected to the second control terminal G1(n-1).

[0066] The first storage capacitor Cst1 has a first terminal electrically connected to the first node N1 , and a second terminal electrically connected to the third node N3 .

[0067] In this embodiment, a compensation unit is provided and set, the compensation unit includes a first transistor, a second transistor and a first storage capacitor, wherein the first storage capacitor is set between the first node and the third node, the third node is the gate of the driving transistor, and the gate threshold voltage of the driving transistor is compensated by the cooperation of the first transistor and the second transistor with the first storage capacitor to ensure the consistency of the transistors in the pixel circuit and improve the driving capability of the driving transistor; in addition, the compensation unit makes the circuit structure simple, and can realize programmable compensation timing while simplifying the number of gate lines, which is beneficial to the design of medium and large-sized narrow frames.

[0068] In a specific embodiment, Figure 3 As shown, Figure 3The circuit schematic diagram of this specific embodiment is shown. As can be seen from the figure, the compensation unit 102 includes: the compensation unit 102 includes: a first transistor T1, a second transistor T2 and a first storage capacitor Cst1, the first electrode of the first transistor T1 is electrically connected to the reference voltage terminal Ref, the second electrode is electrically connected to the first node N1, the control electrode is electrically connected to the second control terminal G1 (n-1), the first electrode of the second transistor T2 is electrically connected to the second node N2, the second electrode is electrically connected to the third node N3, the control electrode is electrically connected to the second control terminal G1 (n-1), the first end of the first storage capacitor Cst1 is electrically connected to the first node N1, and the second end is electrically connected to the third node N3.

[0069] The light-emitting driving unit 103 includes a fourth transistor T4 and a fifth transistor T5. The first electrode of the fourth transistor T4 is electrically connected to the first power signal terminal VDD, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the light-emitting control terminal Em(n). The first electrode of the fifth transistor is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the third node N3. It can be seen that the fifth transistor T5 is a driving transistor in this embodiment, the potential of the third node N3 is the gate potential of the fifth transistor T5 as a driving transistor, and the potential of the fourth node N4 is the source potential of the fifth transistor T5.

[0070] The input unit 101 includes a ninth transistor T9 , a first electrode of the ninth transistor T9 is electrically connected to the data signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the first control terminal.

[0071] The light-emitting unit 104 includes a light-emitting device D, which may be a light-emitting diode (OLED). The light-emitting unit 104 also includes an intrinsic capacitor Coled, which is connected in parallel between the anode and the cathode of the light-emitting device D. Specifically, the anode of the light-emitting device D is electrically connected to the fourth node N4, the cathode is electrically connected to the second power signal terminal VSS, the first end of the intrinsic capacitor Coled is electrically connected to the fourth node N4, and the second end is electrically connected to the second power signal terminal VSS. The light-emitting device D is not limited to OLED, and may also be one of MiniLED and MicroLED, which is not specifically limited in the present invention. The intrinsic capacitor Coled is used to store charge to assist in stabilizing the potential of the fourth node N4.

[0072] In addition, continue to refer to Figure 3 As shown, the pixel circuit also includes a storage unit, which includes a second storage capacitor Cst2. In this example, the first end of the second storage capacitor Cst2 is electrically connected to the first node N1, and the second end is electrically connected to the fourth node N4. The second storage capacitor Cst2 is configured to store a data signal after data input.

[0073] In addition, the pixel circuit further includes a potential holding unit, which includes a sixth transistor T6, a first electrode of the sixth transistor T6 being electrically connected to the reference voltage terminal Ref, a second electrode being electrically connected to the fourth node N4, and a control electrode being electrically connected to the set control terminal, and configured to maintain the fourth node N4, i.e., the source potential of the fifth transistor T5 as a driving transistor, through a reference signal connected to the reference voltage terminal Ref under the control of a signal at the set control terminal. In this example, the signal connected to the set control terminal is the same as the signal connected to the second control terminal. Those skilled in the art should understand that in order to facilitate the representation of the similarities and differences of the signals of the ports in the circuit schematic diagram, they are usually represented by the same symbols, i.e., in this example, the set control terminal and the second control terminal are both represented by G1(n-1), and the ports will also be represented in the same manner in the following circuit schematic diagrams, which will not be repeated here.

[0074] In order to further understand the working principle of the above compensation unit 102 in the pixel circuit, as well as the specific functions of other specific units, such as the potential holding unit, the following is a description of the working principle of the compensation unit 102 in the pixel circuit. Figure 3 Based on the foundation Figure 4 The timing diagram is explained in detail.

[0075] The working principle of the pixel circuit is divided into four stages: setting stage, compensation stage, data writing stage and light emission stage.

[0076] Specifically, stage ① is the setting stage, at this time, the second control terminal and the setting control terminal are both represented by G1(n-1), and the two are connected to the same signal, that is, the signals of the second control terminal and the setting control terminal are both high level. Under the control of the signal of the second control terminal, the first transistor T1 and the second transistor T2 are turned on, and the reference voltage terminal Ref connected to the first electrode of the first transistor T1 sets the first node N1 to the reference voltage Vref. Under the control of the setting control terminal, the sixth transistor T6 is turned on, and the fourth node N4, that is, the source of the fifth transistor T5 is set to the high level Vref; at this time, because the signal connected to the light-emitting control terminal EM(n) is also high level, the fourth transistor T4 is turned on, and the high level signal connected to the first power signal terminal is written into the third node N3 through the turned-on fourth transistor T4 and the second transistor T2, that is, the drain D and the gate G of the fifth transistor T5 are set to the high level V through the signal of the first power signal terminal VDD. DD .

[0077] Phase ② is the compensation phase. The signal connected to the light emitting control terminal EM(n) becomes low level, the fourth transistor T4 is turned off, the second control terminal and the set control terminal G1(n-1) are connected to the same signal and are still high level, the second transistor T2, the third transistor T3 and the sixth transistor T6 remain on. Since the fourth transistor T4 is turned off, the potential of the gate G of the fifth transistor T5 is pulled down. Due to the energy storage effect of the first storage capacitor Cst1, the potential of the gate G of the fifth transistor T5 is pulled down from the high level V DD It drops to Vref+Vth, where Vth represents the threshold voltage of the fifth transistor T5. Here, the fifth transistor T5 is still in the off state. The first node N1 maintains the reference voltage Vref under the action of the first transistor T1, and the source S of the fifth transistor T5 remains unchanged under the action of the potential holding unit. In the stage, the gate G is compensated for the signal by the storage function of the first storage capacitor Cst1 through the conduction of the first transistor T1 and the second transistor T2, and its ultimate effect will be reflected in the subsequent light-emitting process.

[0078] Phase ③ is the data writing phase, in which the signal connected to the first control terminal G1(n) becomes high level, the ninth transistor T9 in the input unit 101 is turned on, and the signal level Vdata connected to the data signal terminal DL connected to the first electrode is written into the first node N1. At this time, the signal connected to the second control terminal and the set control terminal G1(n-1) is low level, the first transistor T1 and the second transistor T2 are turned off, the voltage change of the first terminal of the first storage capacitor Cst1 is ΔV=Vdata-Vref, and the voltage change of the second terminal of the first storage capacitor Cst1 should be the same as the change of the first terminal, which is also ΔV=Vdata-Vref. Therefore, the potential of the gate G of the fifth transistor T5 changes from Vref+Vth to Vref+Vth-ΔV=Vref+Vth-Vref+Vdata=Vdata+Vth. At this time, due to the existence of the intrinsic capacitor Coled, the potential of the source S of the fifth transistor T5 can be basically kept unchanged, that is, Vref is basically kept unchanged. Therefore, the gate-source voltage Vgs of the fifth transistor T5 is Vdata+Vth-Vref.

[0079] Phase ④ is the light-emitting phase, the light-emitting control signal connected to the light-emitting control terminal EM(n) becomes high level, the first control terminal G1(n), the second control terminal and the set control terminal G1(n-1) are all low level, the fourth transistor T4 and the fifth transistor T5 are turned on, the light-emitting driving unit 103 forms a driving current and drives the light-emitting device D in the light-emitting unit 104 to emit light. According to the transistor conduction current formula, Id=k*(Vgs-Vth) 2 =k*(Vdata-Vref) 2It can be seen that the potential Vref+Vth is written into the gate G of the fifth transistor T5 serving as the driving transistor during the compensation stage through the first transistor T1, the second transistor T3 and the first storage capacitor Cst1 in the compensation unit 101, and the storage function of the first storage capacitor Cst1 makes the final driving current no longer affected by the threshold voltage of the fifth transistor T5, thereby completing the compensation function.

[0080] The compensation structure set above can complete the compensation of the driving transistor with a simple architecture by introducing only one set of gate lines G1. The simple structure is conducive to narrow frame design and high PPI design. In addition, the architecture can realize programmable compensation timing by adding only one gate line (see below for details), which has broad application prospects. Figure 5 The examples are explained in detail.

[0081] In a specific example, refer to Figure 5 As shown, this example is similar to Figure 3 The example shown has exactly the same circuit structure. That is, in the pixel circuit, the compensation unit includes a first transistor T1, a second transistor T2 and a first storage capacitor Cst1; the light-emitting driving unit 103 includes a fourth transistor T4 and a fifth transistor T5, and the specific connection method of the fourth transistor T4 and the fifth transistor T5 is the same as Figure 3 The input unit 101 includes a ninth transistor T9; the light-emitting unit 104 may include a light-emitting device D and an intrinsic capacitor Coled; the potential holding unit includes a sixth transistor, and the connection relationship between the various components in the above units is the same as the above Figure 3 The circuit structure in the example shown is the same, and the pixel circuit also includes a second storage capacitor Cst2, which is also connected to Figure 3 The connection relationship in is the same.

[0082] In particular, in this example, Figure 3 In the embodiment, the first control terminal and the second control terminal are respectively connected to the gate control signal of two adjacent moments in the same gate drive circuit, and the second control terminal and the first control terminal are connected to the signal provided by different groups of gate lines, that is to say, in this example, the first control terminal of input unit 101 and the second control terminal of compensation unit 102 are connected to the gate line signal that is independent of each other. In this article, being independent of each other means that the signal that the two control terminals are connected is not associated in the generation structure, and can be controlled independently completely between the timing. For the convenience of embodying this relationship, in this example, the first control terminal is expressed as the first control terminal G1(n), and the second control terminal is expressed as G2(n).

[0083] In addition, in this example, when the signal connected to the second control terminal changes, the set control terminal of the sixth transistor T9 in the potential holding unit is also represented as G2(2), that is, the signal connected to the set control terminal is the same as the signal connected to the second control terminal.

[0084] Timing diagram Figure 6 As shown, the working principle of the pixel circuit is still divided into four stages: the setting stage, the compensation stage, the data writing stage and the light emitting stage.

[0085] Reference Figure 6 It can be seen that the length of the setting phase ① and the compensation phase ② when the first transistor T1 and the second transistor T2 are turned on is no longer related to the gate line G1(n) at the moment, that is, it is no longer limited to the gate line G1(n-1) with the same high level interval as G1(n). In other words, the phase ② that determines the compensation time of the compensation unit 102 is no longer limited to the high level length of the gate line G1, but is independently controlled by an independent gate line G2. Those skilled in the art can introduce a group of gate lines G2 to arbitrarily control the compensation time as needed.

[0086] by Figure 6 For example, in the previous example, the high level time interval of the second control terminal G2(n) starts from the high level start time of the gate line G1 (i.e., G1(n-1)) much earlier than the previous moment until the first control terminal G1(n) becomes high level, and the time length of the compensation stage ② is also greater than the time length of G1(n-1) being high level. Therefore, for the driving transistor that needs a longer time to complete the gate writing Vref+Vth, there is sufficient time to complete the compensation.

[0087] Therefore, in this example, only a group of independent gate lines G2 need to be added to make the compensation stage independent of the data writing stage, thereby realizing a compensation design with programmable compensation time through a simple compensation unit circuit structure composed of two existing transistors and a storage capacitor. By designing and adjusting the compensation time as needed, the driving transistor can be fully charged and compensated when designing a high PPI of a medium or large-sized display panel, thereby ensuring the brightness uniformity of the pixels in the display panel. In addition, while achieving display uniformity, the circuit architecture is simple, which is conducive to the design requirements of medium and large-sized narrow bezels, and has broad application prospects.

[0088] It should be noted that, although the specific processes of stages ①, ②, ③ and ④ are not described in detail, those skilled in the art should understand that the conduction principle of each transistor and the control process of the circuit are similar to Figure 3 However, those skilled in the art should also understand that the specific waveform of the light-emitting control terminal EM should be adjusted according to the second control terminal, so as to realize the light-emitting control after adjusting the signal waveform of the second control terminal, which is not repeated here.

[0089] In some other optional embodiments, it is considered to further significantly expand the data range through the structure of the pixel circuit without changing the existing compensation architecture.

[0090] In a specific embodiment, refer to Figure 7 As shown, the pixel circuit includes an input unit 101 , a compensation unit 102 , a light-emitting driving unit 103 and a light-emitting unit 104 .

[0091] The input unit 101 includes a ninth transistor T9 , a first electrode of the ninth transistor T9 is electrically connected to the data signal terminal, a second electrode is electrically connected to the first node, and a control electrode is electrically connected to the first control terminal.

[0092] The compensation unit 102 includes: the compensation unit 102 includes: a first transistor T1, a second transistor T2 and a first storage capacitor Cst1, the first electrode of the first transistor T1 is electrically connected to the reference voltage terminal Ref, the second electrode is electrically connected to the first node N1, and the control electrode is electrically connected to the second control terminal G1(n-1), the first electrode of the second transistor T2 is electrically connected to the second node N2, the second electrode is electrically connected to the third node N3, the control electrode is electrically connected to the second control terminal G1(n-1), the first end of the first storage capacitor Cst1 is electrically connected to the first node N1, and the second end is electrically connected to the third node N3.

[0093] The light-emitting driving unit 103 includes a fourth transistor T4 and a fifth transistor T5. The first electrode of the fourth transistor T4 is electrically connected to the first power signal terminal VDD, the second electrode is electrically connected to the second node N2, and the control electrode is electrically connected to the light-emitting control terminal Em(n). The first electrode of the fifth transistor is electrically connected to the second node N2, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the third node N3. It can be seen that the fifth transistor T5 is a driving transistor in this embodiment, the potential of the third node N3 is the gate potential of the fifth transistor T5 as a driving transistor, and the potential of the fourth node N4 is the source potential of the fifth transistor T5.

[0094] The light-emitting unit 104 includes a light-emitting device D, which may be a light-emitting diode (OLED). The light-emitting unit 104 also includes an intrinsic capacitor Coled, which is connected in parallel between the anode and the cathode of the light-emitting device D. Specifically, the anode of the light-emitting device D is electrically connected to the fourth node N4, the cathode is electrically connected to the second power signal terminal VSS, the first end of the intrinsic capacitor Coled is electrically connected to the fourth node N4, and the second end is electrically connected to the second power signal terminal VSS. The light-emitting device D is not limited to OLED, and may also be one of MiniLED and MicroLED, which is not specifically limited in the present invention. The intrinsic capacitor Coled is used to store charge to assist in stabilizing the potential of the fourth node N4.

[0095] In addition, the potential holding unit includes a sixth transistor T6, a first electrode of the sixth transistor T6 is electrically connected to the reference voltage terminal Ref, a second electrode is electrically connected to the fourth node N4, and a control electrode is electrically connected to the set control terminal. Because the set control terminal is connected to the same signal as the second control terminal, the set control terminal and the second control terminal are both represented by G1(n-1).

[0096] In particular, continue to refer to Figure 7 As shown, in this example, the second storage capacitor Cst2 for storing the data signal is no longer connected between the first node N1 and the fourth node N4, but is connected between the third node N3 and the fourth node N4.

[0097] Specifically, the first end of the second storage capacitor Cst2 is electrically connected to the third node N3, and the second end is electrically connected to the fourth node N4. Through this setting, in the data writing stage, while storing the data signal, the second storage capacitor Cst2 and the first storage capacitor Cst1 will change from a series connection to a parallel connection to form a voltage division for the gate G of the fifth transistor T5 as a driving transistor, and the purpose of expanding the data range is achieved through this setting.

[0098] In order to facilitate understanding of the specific implementation function, the specific process is described in detail below in conjunction with the circuit timing diagram. Figure 4 The timing is the same, so the combination Figure 4 right Figure 7 Description of working principle.

[0099] Reference Figure 4 As shown, the working principle of the pixel circuit is divided into four stages: setting stage, compensation stage, data writing stage and light emitting stage.

[0100] Specifically, in the setting stage ①, at this time, the signals of the second control terminal and the setting control terminal G1(n-1) are both high level. Under the control of the signal of the second control terminal, the first transistor T1 and the second transistor T2 are turned on, and the reference voltage terminal Ref connected to the first electrode of the first transistor T1 sets the first node N1 to the reference voltage Vref. Under the control of the setting control terminal, the sixth transistor T6 is turned on, and the fourth node N4, that is, the source of the fifth transistor T5 is set to the high level Vref; at this time, the signal connected to the light-emitting control terminal EM(n) is also high level, the fourth transistor T4 is turned on, and the high level signal connected to the first power signal terminal is written into the third node N3 through the turned-on fourth transistor T4 and the second transistor T2, that is, the drain D and the gate G of the fifth transistor T5 are set to the high level V through the signal of the first power signal terminal VDD. DD .

[0101] In the compensation stage ②, the signal connected to the light emitting control terminal EM(n) becomes low level, the fourth transistor T4 is turned off, the signals connected to the second control terminal and the set control terminal G1(n-1) are still high level, the second transistor T2, the third transistor T3 and the sixth transistor T6 remain on, and since the fourth transistor T4 is turned off, the potential of the gate G of the fifth transistor T5 is pulled down, and due to the energy storage effect of the first storage capacitor Cst1, the potential of the gate G of the fifth transistor T5 is pulled down from the high level V DD It drops to Vref+Vth, where Vth represents the threshold voltage of the fifth transistor T5. Here, the fifth transistor T5 is still in the off state, the first node N1 maintains the reference voltage Vref under the action of the first transistor T1, and the source S of the fifth transistor T5 remains unchanged under the action of the potential holding unit.

[0102] In particular, in stage ③ which is the data writing stage, the signal connected to the first control terminal G1(n) becomes a high level, the ninth transistor T9 in the input unit 101 is turned on, and the signal level connected to the data signal terminal DL connected to the first electrode is written into the first node N1. In order to reflect the relationship between the input data at this time and the input data at this time when the Cst2 range is not changed, Vdata in the formula is expressed as Vdata2.

[0103] At this time, the signals connected to the second control terminal and the set control terminal G1(n-1) are at a low level, and the first transistor T1 and the second transistor T2 are turned off. However, at this time, because the second storage capacitor Cst2 is connected in parallel with the first storage capacitor Cst1 at the gate D of the fifth transistor T5, a series voltage division is formed, and the voltage written into the gate G of the fifth transistor T5 changes from Vref+Vth-(Vref-Vdata) to Vref+Vth-Cst1*(Vref-Vdata2) / Cst2.

[0104] This expression can be converted to: Vref(Cst2-Cst1) / Cst2+Vdata2*Cst1 / Cst2+Vth. Because the source S of the fifth transistor basically keeps Vref unchanged, at this time, Vgs of the fifth transistor T5 = Vref(Cst2-Cst1) / Cst2+Vdata2*Cst1 / Cst2+Vth-Vref; and if the position of Cst2 is not changed, Vgs should originally be Vdata+Vth-Vref (such as Figure 3 (Analysis of stage ③ in the circuit), the effect after Vdata2 input should achieve the same compensation effect as before the change, so Vgs = Vref (Cst2-Cst1) / Cst2+Vdata2*Cst1 / Cst2+Vth-Vref = Vdata+Vth-Vref.

[0105] Assume Cst1 / Cst2 = a, then after simplification we get:

[0106] Vref(1-a)+Vdata2*a=Vdata, then, Vdata2=Vdata / a+Vref*(a-1) / a.

[0107] According to this expression, as long as a is greater than 1, that is, the capacitance value of Cst1 is greater than the capacitance value of Cst2, for example, a = 2, set Vdata = 1V, then Vdata2 = 1 / 2 + Vref / 2, therefore, as long as Vref is set greater than Vdata, the data range can be increased, for example, if it is much greater than Vdata, Vdata2 can be significantly greater than Vdata, for example, Vref can be set to 7V, then Vdata2 = 4V. It can be seen that the data signal written into the input unit at this time is equivalent to the circuit structure ( Figure 3 In this case, when adjusting the grayscale, the adjustment range of the data written by the input unit is no longer 0V to 1V, but 0V to 4V, thus greatly expanding the adjustment range of the data signal, which is greatly beneficial to grayscale development and extremely low grayscale display.

[0108] Stage ④ is the light-emitting stage, and the light-emitting process is similar to the above process and will not be repeated.

[0109] Through the above settings, one end of the second storage capacitor Cst2 and one end of the first storage capacitor Cst1 are both connected to the gate of the fifth transistor serving as the driving transistor, and the ratio of the capacitance values ​​of the first storage capacitor Cst1 and the second storage capacitor Cst2 is set to be greater than 1, so that the voltage-dividing relationship between the first storage capacitor and the second storage capacitor can be utilized to increase the input range of the data signal under the same driving transistor gate voltage and driving current effects, thereby expanding the grayscale adjustment range.

[0110] In some other optional embodiments, it is desired to reduce the reset current of Vref in stage ① and stage ② as much as possible.

[0111] In a specific embodiment, referring to Figure 8 As shown, the example is in Figure 3 A third transistor T3 is added on the basis of the illustrated example.

[0112] Specifically, the compensation unit also includes: a third transistor T3, the first electrode of the third transistor T3 is connected to the second reference voltage terminal Ref2, the second electrode is electrically connected to the first electrode of the second transistor T2, and the control terminal is electrically connected to the third control terminal G2(n), and the third control terminal can be connected to another group of gate lines G2.

[0113] Reference Fig. 9As shown, by introducing an additional third transistor T3, in stage ①, in the area where the third control terminal G2(n) overlaps with the second control terminal G1(n-1), the gate G of the fifth transistor is set to a second reference voltage Vref2 that is lower than the level of the first power signal terminal VDD, thereby reducing the reset current of stages ① and ②.

[0114] It is necessary to further explain that although other circuit structures are used in this example Figure 3 The same circuit diagram is used as an example, but it is not limited to this. In practical applications, the compensation unit structure in this example can also be applied to Figure 5 and Figure 7 In the basic architecture in, it is possible to further reduce the reset current while making the compensation time programmable or the input data range expandable, which will not be described in detail here.

[0115] In another optional embodiment, in order to obtain a more accurate gate voltage compensation effect of the driving transistor, it is desired to apply the driving compensation under the condition of strictly fixing the source voltage.

[0116] In a specific embodiment, referring to Fig.10 and Fig.11 As shown, in the input unit, the compensation unit, the light-emitting driving unit, the storage unit and the light-emitting unit Figure 5 While maintaining consistency with the illustrated embodiment, in particular, the potential holding unit in the pixel circuit includes: a sixth transistor T6, a first electrode of the sixth transistor T6 is electrically connected to the reference voltage terminal Ref, a second electrode is electrically connected to the fourth node N4, and a control electrode is electrically connected to the set control terminal G3(n).

[0117] Specifically, the signal connected to the set signal terminal G3 (n) is connected to a high level signal when the second control terminal and the data signal terminal are connected to a high level signal.

[0118] Combination Fig.11 As shown in the timing diagram, the set signal terminal G3(n) introduces an additional signal through an additional set of gate lines. The signal is high level during the period when the second control terminal G2(n) is high level and during the period when the first control terminal G1(n) is high level. Therefore, the reference voltage Vref drop of the reference voltage terminal Ref can be used as the source of the transistor T5 of the driving transistor to be set and maintained at Vref in the set stage ①, the compensation stage ② and the data writing stage ③. Therefore, the compensation unit uses the storage function of the first storage capacitor Cst1 to store charges and compensate the gate G. The data is accurate, thereby ensuring the uniformity of the compensation effect of the driving transistors of all pixel circuits in the display panel, improving the charging uniformity, and improving the display effect.

[0119] It should be noted that although the circuit structures of the other units except the potential holding unit shown in the example are the same as those of the Figure 5 The embodiments shown are the same, but are not intended to be limiting. Those skilled in the art should understand that this example is intended to illustrate the function of the improved potential holding unit, and the structure of the potential holding unit can also be referred to in Figure 3 and Figure 7 In the architecture shown, as long as the signal connected to the set signal terminal G3(n) is connected to a high-level signal when the second control terminal and the data signal terminal are connected to a high-level signal, it can be ensured that the source of the driving transistor maintains the same potential in stages ①, ② and ③, which will not be repeated here.

[0120] However, compared to adding a group of gate lines G3, in some application scenarios, it is more advantageous to ensure a narrow frame design while improving the compensation effect. Therefore, in some optional embodiments, referring to Fig.12 As shown, the potential holding unit is further improved to include: a seventh transistor T7 and an eighth transistor T8.

[0121] Specifically, refer to Fig.12 As shown, the first electrode of the seventh transistor T7 is electrically connected to the reference voltage terminal Ref, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the first set control terminal G2(n); the first electrode of the eighth transistor T8 is electrically connected to the reference voltage terminal Ref, the second electrode is electrically connected to the fourth node N4, and the control electrode is electrically connected to the second set control terminal G1(n).

[0122] Further integration Figure 6 As shown in the timing diagram, the signal connected to the first set control terminal G2(n) is the same as the signal connected to the second control terminal, and the signal connected to the second set control terminal G1(n) is the same as the signal connected to the data signal terminal. It can be obviously seen from the timing diagram that this setting can also ensure that the source of the fifth transistor T5 accurately maintains the same potential in the set stage ①, the compensation stage ②, and the data writing stage ③, so that the compensation unit uses the storage function of the first storage capacitor Cst1 to store charges and compensate the gate G. The data is accurate, thereby ensuring the uniformity of the compensation effect of the driving transistors of all pixel circuits in the display panel, improving the charging uniformity, and improving the display effect.

[0123] Through the above settings, a transistor can be added to the pixel circuit instead of adding a set of gate lines in the display panel. The transistor occupies a very small space and is located in the display area. It will not occupy the border area or affect the wiring of the border area. This can improve the compensation effect while being more conducive to medium and large-sized narrow border designs.

[0124] It should be noted that although the circuit structures of the other units except the potential holding unit shown in the example are the same as those of the Figure 5 The embodiments shown are the same, but are not intended to be limiting. Those skilled in the art should understand that this example is intended to illustrate the function of the improved potential holding unit, and the structure of the potential holding unit can also be referred to in Figure 3 and Figure 7 In the architecture shown, no further details are given here.

[0125] Based on the compensation architecture in the pixel circuit provided in the above embodiments, Fig.13 As shown, the inventor provides a simulation diagram of the uncompensated circuit in the prior art and the compensation effect based on the above architecture (excluding Figure 7 As can be seen from the simulation diagram, the horizontal axis represents the numerical range coordinate of the written data, the vertical axis represents the output drive current value corresponding to the written data, the black solid line in the diagram represents the uncompensated circuit simulation input-output curve when the driving transistor threshold voltage is 2V, the gray-black solid line represents the ideal input-output curve when the driving transistor threshold voltage is 0V, and the gray-black dotted line represents the input-output curve when the driving transistor threshold voltage is 2V. As can be seen from the figure, the figure shows that in the extreme case of uncompensated situation, if Vgs is offset, no drive current will be generated; and after applying the compensation architecture of the present application, within the most commonly used data input range of 4V to 6V, the compensation structure of the present application can have a good fitting effect with the simulation results under the most ideal state, achieving an excellent compensation effect.

[0126] In addition, for Figure 7 Although the circuit architecture for expanding the input data range has not been specifically simulated, those skilled in the art will understand that its effect will be similar to that of Fig.13 The method is similar to that in , except that the input data range is larger, so I will not go into details here.

[0127] Based on the same inventive concept, an embodiment of the present application further provides a driving method applied to the pixel circuit described above, comprising:

[0128] Setting stage: the compensation unit sets the first node and the third node according to the second control signal input from the second control end;

[0129] Compensation stage: the compensation unit pulls down the potential of the third node according to the input second control signal, and the first node maintains the potential set in the setting stage under the action of the first storage capacitor;

[0130] Data writing stage: the input unit writes the data signal according to the control inputted by the first control terminal;

[0131] Light-emitting stage: the light-emitting driving unit forms a driving current according to the light-emitting control signal input from the light-emitting control end, the first power signal from the first power signal end and the voltage of the third node and drives the light-emitting unit to emit light.

[0132] Those skilled in the art should understand that the specific process of the above method has been described in detail in conjunction with various timing diagrams when describing the specific circuit principle of the pixel circuit above, and will not be repeated here.

[0133] In this embodiment, by utilizing the compensation unit of the above-mentioned embodiment, the gate threshold voltage of the driving transistor is compensated by the cooperation of the first transistor, the second transistor and the first storage capacitor in the compensation stage, thereby ensuring the consistency of the transistors in the pixel circuit and improving the driving capability of the driving transistor; in addition, the compensation unit makes the circuit structure simple, and can realize programmable compensation timing while simplifying the number of gate lines, which is beneficial to the design of medium and large-sized narrow frames and has broad application prospects.

[0134] Based on the same inventive concept, an embodiment of the present application further provides a display panel, which includes the pixel circuit described in the above embodiment.

[0135] Based on the same inventive concept, an embodiment of the present application further provides a display device, comprising the display panel described in the above embodiment.

[0136] In this embodiment, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a car display, a digital photo frame or a navigator. By using a display panel with the above pixel circuit, the display uniformity can be improved during the display process of the display device, and it can be beneficial to the design requirements of medium and large-sized narrow-frame products, and has broad application prospects.

[0137] In view of the existing problems, the present invention develops a pixel circuit, a display panel, a display device and a driving method, and provides a compensation unit and sets the compensation unit, wherein the compensation unit includes a first transistor, a second transistor and a first storage capacitor, wherein the first storage capacitor is set between a first node and a third node, and the third node is the gate of the driving transistor, and the gate threshold voltage of the driving transistor is compensated by the cooperation of the first transistor and the second transistor with the first storage capacitor, thereby ensuring the consistency of the transistors in the pixel circuit and improving the driving capability of the driving transistor; in addition, the compensation unit makes the circuit structure simple, and can realize programmable compensation timing while simplifying the number of gate lines, which is beneficial to the design of medium and large-sized narrow borders and has broad application prospects.

[0138] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not limitations on the implementation methods of the present invention. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present invention are still within the protection scope of the present invention.

Claims

1. A pixel circuit, characterized in that: include: An input unit, a compensation unit, a light-emitting driving unit, a storage unit and a light-emitting unit, wherein: The input unit is electrically connected to the data signal terminal, the first control terminal and the first node, and is configured to access the data signal input by the data signal terminal in response to the control of the first control terminal; The compensation unit is electrically connected to the second control terminal, the reference voltage terminal, the first node, the second node and the third node, and is configured to perform driving compensation in response to the control of the second control terminal; The light-emitting driving unit is electrically connected to the first power signal terminal, the light-emitting control terminal, the second node, the third node, and the fourth node, and is configured to generate a driving current to drive the light-emitting unit to emit light in response to the control of the light-emitting control terminal. The compensation unit comprises: a first transistor, a second transistor and a first storage capacitor, The storage unit includes a second storage capacitor, a ratio of a capacitance value of the first storage capacitor to a capacitance value of the second storage capacitor is greater than 1, a first end of the second storage capacitor is electrically connected to the third node, and a second end of the second storage capacitor is electrically connected to the fourth node, The first electrode of the first transistor is electrically connected to the reference voltage terminal, the second electrode is electrically connected to the first node, the control electrode is electrically connected to the second control terminal, and the reference voltage terminal receives a high-level reference voltage. The first electrode of the second transistor is electrically connected to the second node, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second control terminal. The first storage capacitor has a first terminal electrically connected to the first node, and a second terminal electrically connected to the third node.

2. The pixel circuit according to claim 1, characterized in that: The compensation unit further includes: a third transistor, The first electrode of the third transistor is connected to the second reference voltage terminal, the second electrode is electrically connected to the first electrode of the second transistor, and the control terminal is electrically connected to the third control terminal.

3. The pixel circuit according to claim 1, characterized in that: The light-emitting driving unit includes a fourth transistor and a fifth transistor, wherein a first electrode of the fourth transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the light-emitting control terminal; a first electrode of the fifth transistor is electrically connected to the second node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the third node. The pixel circuit further includes a potential holding unit, which includes a sixth transistor, a first electrode of the sixth transistor being electrically connected to the reference voltage terminal, a second electrode being electrically connected to the fourth node, and a control electrode being electrically connected to the set control terminal.

4. The pixel circuit according to claim 3, characterized in that: The signal received by the setting control terminal is the same as the signal received by the second control terminal, or The signal connected to the set control terminal is connected to a high level signal when the second control terminal and the data signal terminal are connected to a high level signal.

5. The pixel circuit according to claim 1, characterized in that: The light-emitting driving unit includes a fourth transistor and a fifth transistor, wherein a first electrode of the fourth transistor is electrically connected to the first power signal terminal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the light-emitting control terminal; a first electrode of the fifth transistor is electrically connected to the second node, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the third node. The pixel circuit further includes a potential holding unit, which includes a seventh transistor and an eighth transistor, wherein a first electrode of the seventh transistor is electrically connected to the reference voltage terminal, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the first setting control terminal, and a first electrode of the eighth transistor is electrically connected to the reference voltage terminal, a second electrode is electrically connected to the fourth node, and a control electrode is electrically connected to the second setting control terminal. The signal connected to the first setting control terminal is the same as the signal connected to the second control terminal, and the signal connected to the second setting control terminal is the same as the signal connected to the data signal terminal.

6. The pixel circuit according to any one of claims 1 to 5, characterized in that: The first control terminal is connected to the output signal of the gate shift register of the current frame image, and the signal connected to the second control terminal is the signal of the gate shift register of the previous frame image; or The first control terminal is connected to a gate line signal independent of the second control terminal.

7. The pixel circuit according to claim 1, characterized in that: The input unit comprises a ninth transistor, a first electrode of the ninth transistor is electrically connected to the data signal terminal, a second electrode is electrically connected to the first node, a control electrode is electrically connected to the first control terminal, and / or The light-emitting unit includes a light-emitting device and an intrinsic capacitor, wherein the anode of the light-emitting device is electrically connected to the fourth node, the cathode is electrically connected to the second power signal terminal, the first terminal of the intrinsic capacitor is electrically connected to the fourth node, and the second terminal is electrically connected to the second power signal terminal.

8. A display panel, characterized in that: The invention comprises the pixel circuit according to any one of claims 1 to 7.

9. A display device, characterized in that: Comprising the display panel as claimed in claim 8.

10. A driving method for a pixel circuit according to any one of claims 1 to 7, characterized in that: include: Setting stage: the compensation unit sets the first node and the third node according to the second control signal input from the second control end; Compensation stage: the compensation unit pulls down the potential of the third node according to the input second control signal, and the first node maintains the potential set in the setting stage under the action of the first storage capacitor; Data writing stage: the input unit writes the data signal according to the control inputted by the first control terminal; Light-emitting stage: the light-emitting driving unit forms a driving current according to the light-emitting control signal input from the light-emitting control end, the first power signal from the first power signal end and the voltage of the third node and drives the light-emitting unit to emit light.

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