Node address allocation method and device for vehicle, vehicle device, and storage medium

Abstract

This application discloses a method, apparatus, vehicle equipment, and storage medium for allocating node addresses in a vehicle. The method includes: obtaining a node with a currently assigned address from a node set according to a first addressing mode, wherein the node set includes multiple nodes connected to a first bus of the vehicle; obtaining the address of the node based on the number of addressing instruction frames in the addressing instruction sequence, the address carried in the addressing instruction frame currently issued to the node, and the frame number of the addressing instruction frame currently issued to the node; and allocating an address to the node based on the address of the node. This method allows for precise control over node address allocation, thereby meeting preset requirements.

Description

Technical Field

[0001] This application generally relates to the field of vehicles, and specifically to a method, apparatus, vehicle equipment, and storage medium for allocating node addresses for vehicles. Background Technology

[0002] The configuration rate of in-vehicle ambient lighting in family cars is increasing, and the use of multi-color RGB ambient lighting is becoming more and more common. In order to enhance the overall atmosphere of the car, the number of ambient lights installed in the car is also gradually increasing. In order to achieve individual control of ambient lights in different parts, it is necessary to assign an address to each ambient light, so that individual control of each ambient light can be achieved based on the address of the ambient light.

[0003] In existing technologies, due to the different types of chips used in ambient lights, the address allocation methods, i.e., the addressing principles of node addressing methods, also differ. For example, the node address results obtained when using MLX 81 series chips are different from those obtained when using Indie Realplum chips, thus failing to achieve compatibility of node control schemes. Therefore, existing solutions require the development of multiple schemes to adapt to the addressing methods of different chips, making it impossible to achieve precise control of requirements. Summary of the Invention

[0004] In view of the above-mentioned defects or deficiencies in the prior art, it is desirable to provide a method, apparatus, vehicle equipment and storage medium for allocating node addresses for a vehicle.

[0005] On the one hand, this application provides a method for allocating node addresses for vehicles, including:

[0006] The node whose address is to be assigned is obtained from the node set according to the first addressing method, wherein the node set includes multiple nodes connected to the vehicle's first bus;

[0007] The address of the node is obtained based on the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the number of the address instruction frames currently issued to the node.

[0008] The node is assigned an address based on its address.

[0009] Furthermore, obtaining the node with the current address to be assigned from the node set according to the first addressing method includes:

[0010] The node search proceeds sequentially from the first node to the last node in the node set.

[0011] When the first unassigned node is found, the unassigned node is taken as the node to be assigned the current address;

[0012] or,

[0013] The node search proceeds sequentially from the tail node to the first node in the node set.

[0014] When the first unassigned node is found, it is designated as the node for the current address to be assigned.

[0015] Specifically, the first addressing mode is one of LSM addressing mode and BSM addressing mode.

[0016] In some embodiments, obtaining the address of the node based on the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the frame number of the addressing instruction frame currently issued to the node includes:

[0017] Obtain a first difference between the number of address instruction frames in the address instruction sequence and the number of address instruction frames currently issued to the node;

[0018] Obtain a second difference between the address carried in the addressing instruction frame currently issued to the node and the first difference;

[0019] The address of the node is obtained based on the second difference.

[0020] Furthermore, it also includes:

[0021] The node whose address is to be assigned is obtained from the node set according to the second addressing method;

[0022] The address of the node is obtained based on the address carried in the address instruction frame currently issued to the node in the address instruction sequence;

[0023] The node is assigned an address based on its address.

[0024] Specifically, the second addressing mode is one of LSM addressing mode and BSM addressing mode, and the second addressing mode is different from the first addressing mode.

[0025] Secondly, this application provides a node address allocation device for a vehicle, comprising:

[0026] A node determination module is used to obtain the node with the current address to be assigned from a node set according to a first addressing mode, wherein the node set includes multiple nodes connected to the vehicle's first bus;

[0027] The address determination module is used to obtain the address of the node based on the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the frame number of the address instruction frame currently issued to the node.

[0028] The allocation module is used to allocate addresses to the nodes based on their addresses.

[0029] Furthermore, the address determination module is specifically used for:

[0030] Obtain a first difference between the number of address instruction frames in the address instruction sequence and the number of address instruction frames currently issued to the node;

[0031] Obtain a second difference between the address carried in the addressing instruction frame currently issued to the node and the first difference;

[0032] The address of the node is obtained based on the second difference.

[0033] Thirdly, this application provides a vehicle that includes a vehicle node address allocation device.

[0034] Fourthly, this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the node address allocation method for a vehicle as described in any one of the embodiments of this application.

[0035] Fifthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the node address allocation method for any of the vehicle embodiments described in this application.

[0036] In summary, the vehicle node address allocation method, apparatus, vehicle equipment, and storage medium based on the present invention obtain the address of a node by acquiring the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the frame relation number of the address instruction frame currently issued to the node. This method can achieve precise control over the allocation of node addresses, thereby meeting preset requirements. Attached Figure Description

[0037] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0038] Figure 1 A flowchart illustrating a method for allocating node addresses for a vehicle, provided as an embodiment of this application;

[0039] Figure 2Internal structure diagram of the MLX81 series chip node provided for embodiments of this application;

[0040] Figure 3 A node connection diagram of the BSM addressing method provided for embodiments of this application;

[0041] Figure 4 Addressing results of the BSM addressing mode provided for embodiments of this application;

[0042] Figure 5 Internal structure diagram of an Indie Realplum chip node provided for embodiments of this application;

[0043] Figure 6 A node connection diagram for LSM addressing provided in an embodiment of this application;

[0044] Figure 7 Addressing results of the LSM addressing mode provided for embodiments of this application;

[0045] Figure 8 A structural block diagram of a vehicle node address allocation device provided for an embodiment of this application;

[0046] Figure 9 An internal structural diagram of an electronic device provided for an embodiment of this application. Detailed Implementation

[0047] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0048] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] This application generally relates to the field of vehicles, and the following embodiments of this application exemplify a method for allocating node addresses for vehicles.

[0050] See details Figure 1 This application provides a method for allocating node addresses for vehicles, including:

[0051] S101, obtain the node with the current address to be assigned from the node set according to the first addressing mode, wherein the node set includes multiple nodes connected to the first bus of the vehicle.

[0052] Specifically, the node address to be assigned is obtained from the set of all nodes, which is the set of all nodes connected to the current vehicle's bus, according to the selected addressing mode. For example, when the first bus of this vehicle connects to 3 nodes, the node address to be assigned should also be 3. The address of this node can be 0x10, 0x0F, or 0x0E. The total number of nodes can be represented by Max NAD.

[0053] In some embodiments, obtaining the node with the current address to be assigned from the node set according to the first addressing mode includes:

[0054] The node search proceeds sequentially from the first node to the last node in the node set.

[0055] When the first unassigned node is found, the unassigned node is taken as the node to be assigned the current address;

[0056] or,

[0057] The node search proceeds sequentially from the tail node to the first node in the node set.

[0058] When the first unassigned node is found, it is designated as the node for the current address to be assigned.

[0059] Specifically, the maximum NAD is sent first to allocate the largest NAD, and then allocations are made in descending order. That is, the search is performed from the first node to the last node in the set. If a node has not been assigned an address, then this node is taken as the current node to be assigned an address. Alternatively, the search is performed from the last node to the first node in the set. If a node has not been assigned an address, then this node is taken as the current node to be assigned an address.

[0060] For example, the BSM (Bus Shunt Method) addressing mode identifies the first remote LIN node by judging the difference in current value through a pull-up current source, and responds to the NAD allocation command from the nearest node to the nearest node, i.e., the node search is performed from the tail node to the head node in the set. The Indie Realplum chip uses the LSM (LIN Switch Method) addressing mode, which increases the number of online slave nodes by controlling the opening and closing of the LIN switch. Starting from the first LIN node in the nearest segment, the backend slave nodes are connected one by one from the nearest to the farthest node to respond to the NAD allocation command, i.e., the node search is performed from the head node to the tail node in the set. The addressing commands in this case are shown in Table 1.

[0061] Table 1

[0062]

[0063]

[0064] In some embodiments, the first addressing mode is one of LSM addressing mode and BSM addressing mode.

[0065] Specifically, for example, existing automatic addressing systems mostly use Melexis MLX81 series chips or IndieRealplum chips for control via LIN communication. The MLX81 series chips use the BSM (Bus Shunt Method) addressing mode, which identifies the first remote LIN node by judging the current value difference through a pull-up current source, and responds to NAD (Node address) allocation commands from the nearest to the nearest node. The IndieRealplum chips, on the other hand, use the LSM (LIN Switch Method) addressing mode, which increases the number of online slave nodes by controlling the opening and closing of the LIN switch, and connects the backend slave nodes one by one from the nearest LIN node to respond to NAD allocation commands.

[0066] The internal structure of the MLX81 series chips is as follows: Figure 2 As shown, current detection is achieved by using a closed constant current source and a pull-up current source, which enables automatic address allocation on the LIN bus BSM. The main steps are as follows:

[0067] 1. Turn off the pull-up current generator and the constant current source (Rslave);

[0068] 2. Test current value, test current offset;

[0069] 3. Pull-up current source is turned on;

[0070] 4. Test the current value at this time as a pre-selected measurement. Nodes with current values ​​less than the preset current value will proceed to the final measurement. The preset current value is 1.2mA.

[0071] 5. The constant current source is turned on;

[0072] 6. Measure the current value at this point; this is the final measured value.

[0073] 7. Turn off the pull-up current source and constant current source.

[0074] At this point, all LIN nodes are connected serially in a daisy chain configuration, as shown in the diagram. Figure 3As shown. When testing the current value, the pull-up power supply is turned on to predict the current. If the tested current value is greater than the preset current value, then this node is not the last node, and the pull-up current source needs to be turned off. When the current value is less than the preset current value, the node enters the final measurement, and then the constant current source is turned on to test the current value. It is then determined whether the current is greater than the preset current value. If the current value is less than the preset value, then it is the last node, and NAD address allocation is performed. The preset current value is 1.2mA. After addressing using BSM mode, the node address is as follows. Figure 4 As shown.

[0075] The Indie Realplum chip uses LSM addressing. The internal structure of the LIN node of this chip is as follows: Figure 5 As shown, the connection diagram of the chip's LSM addressing node is as follows: Figure 6 As shown, the next LIN node is connected via the LIN switch inside the node. Then, by checking whether the NAD is the initial value, it is determined whether an address has been allocated. Nodes without allocated NADs are identified and their new NADs are overwritten. This enables automatic address allocation on the LIN bus. The steps are as follows:

[0076] 1. All nodes disconnect the LIN switch. The first node at the near end is online. After receiving the NAD instruction, it performs a new NAD overwrite and then closes the LIN switch to connect the second node.

[0077] 2. Upon receiving the NAD allocation instruction, the first node has already stored the new NAD, the second node has the initial NAD, and the new NAD will be overwritten. This node closes the LIN switch to connect the third node.

[0078] 3. Assign NADs to all nodes. After addressing using LSM addressing, the node addresses are as follows: Figure 7 As shown.

[0079] S102, the address of the node is obtained based on the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the number of frames of the address instruction frame currently issued to the node.

[0080] Specifically, the node's address is obtained based on the number of addressing instruction frames in the current addressing sequence, the address carried by that addressing instruction, and the current number of addressing instruction frames. The number of addressing operations can be represented by Max NAD.

[0081] For example, upon receiving the first NAD allocation instruction with NAD 0xX (Max NAD), all nodes store NAD as 0xX, where X is the number of address instruction frames in the address instruction sequence, and disconnect the LIN switch; all LIN switches are disconnected, at this time only the first near-end node is online. Upon receiving the second NAD allocation instruction with NAD 0x0 (X-1), this node stores NAD as 0x01{Max NAD-(X-1)}, closes the LIN switch, and connects to the second node; the first node's LIN switch is closed, at this time the first and second near-end nodes are online, the first node's NAD is 0x01, and the second node's NAD is 0xX. Upon receiving the NAD allocation instruction with NAD 0x(X-2), the node with NAD 0xX corrects its NAD to 0x02{Max NAD-(X-2)}, and simultaneously the second node closes its LIN switch, connecting to the third node; the first and second nodes' LIN switches are closed. When the switch is closed, the three near-end nodes are online. The first node has NAD 0x01, the second node has NAD 0x02, and the third node has NAD 0xX. Upon receiving the NAD allocation instruction NAD 0x(X-3), the NAD of the node with NAD 0xX is corrected to 0x03{Max NAD-(X-3)}. At the same time, the second node closes the LIN switch. This continues until the last node is allocated. The second remote node is online. Upon receiving the NAD allocation instruction NAD 0x01, the NAD of the node with NAD 0xX is corrected to 0x(X-1). At the same time, this node closes the LIN switch. The first remote node is online, and its NAD is now stored as 0xX.

[0082] In some embodiments, obtaining the address of the node based on the number of addressing instruction frames in the addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the frame number of the addressing instruction frame currently issued to the node includes:

[0083] Obtain a first difference between the number of address instruction frames in the address instruction sequence and the number of address instruction frames currently issued to the node;

[0084] Obtain a second difference between the address carried in the addressing instruction frame currently issued to the node and the first difference;

[0085] The address of the node is obtained based on the second difference.

[0086] Specifically, for example, when the number of addressing instruction frames in the addressing instruction sequence is 5, and the number of addressing instruction frames currently issued to the node is 3, the difference is calculated to be 2, and the current difference is the first difference; based on the address 5 carried by the addressing instruction frame and the first difference 2, the difference is calculated to be 3, and the current difference is the second difference; then, based on the second difference, the address of the node is obtained as: NAD 0x03.

[0087] S103, Assign an address to the node based on the node's address.

[0088] Specifically, based on the node's address, addresses are allocated, resulting in the addresses of each node as follows: Figure 4 As shown, this enables the nodes to be the same for both LSM and BSM addressing modes, thereby achieving compatible control.

[0089] In some embodiments, the method further includes: obtaining the node with the current address to be assigned from the node set according to the second addressing method;

[0090] The address of the node is obtained based on the address carried in the address instruction frame currently issued to the node in the address instruction sequence;

[0091] The node is assigned an address based on its address.

[0092] Specifically, the node with the currently assigned address is obtained from the set of nodes using the second addressing method. The address of the node is directly based on the address carried in the addressing instruction frame currently issued to the node. For example, if the node with the currently assigned address is 3, then the address of the obtained node is 0x03.

[0093] In some embodiments, the second addressing mode is one of LSM addressing mode and BSM addressing mode, and the second addressing mode is different from the first addressing mode.

[0094] Specifically, when the first addressing mode is LSM addressing mode, the second addressing mode is BSM addressing mode; when the second addressing mode is BSM addressing mode, the first addressing mode is LSM addressing mode. By using the correspondence between the first and second addressing modes, the NAD obtained by the two addressing modes is consistent, thereby achieving compatibility control.

[0095] In summary, the vehicle node address allocation method based on the present invention obtains the address of a node by acquiring the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the relation number of the address instruction frame currently issued to the node. This method can achieve precise control over the allocation of node addresses, thereby meeting preset requirements.

[0096] Further reference Figure 8 The diagram illustrates a vehicle node address allocation device according to an embodiment of this application. The vehicle node address allocation device 200 includes: a node determination module 210, an address determination module 220, and an allocation module 230, wherein:

[0097] The node determination module 210 is used to obtain the node with the current address to be assigned from the node set according to the first addressing mode, wherein the node set includes multiple nodes connected to the first bus of the vehicle;

[0098] Address determination module 220 is used to obtain the address of the node based on the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the frame number of the address instruction frame currently issued to the node.

[0099] The allocation module 230 is used to allocate addresses to the nodes according to their addresses.

[0100] In some embodiments, the address determination module 220 is specifically used for:

[0101] Obtain a first difference between the number of address instruction frames in the address instruction sequence and the number of address instruction frames currently issued to the node;

[0102] Obtain a second difference between the address carried in the addressing instruction frame currently issued to the node and the first difference;

[0103] The address of the node is obtained based on the second difference.

[0104] In summary, the vehicle node address allocation device based on the present invention obtains the address of a node by acquiring the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the relation number of the address instruction frame currently issued to the node. This method can achieve precise control over the allocation of node addresses, thereby meeting preset requirements.

[0105] The division of modules or units mentioned in the detailed description above is not mandatory. In fact, according to the embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0106] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operational instructions of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which includes one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two connected blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified functions or operational instructions, or using a combination of dedicated hardware and computer instructions. The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-mentioned technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-mentioned technical features or their equivalent features without departing from the aforementioned disclosed concept. For example, technical solutions formed by substituting the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this application.

[0107] In one embodiment, this application provides a vehicle that employs a vehicle node address allocation device 200. The vehicle node address allocation device 200 includes: a node determination module 210, configured to obtain the node with the current address to be allocated from a node set according to a first addressing mode, wherein the node set includes multiple nodes connected to a first bus of the vehicle.

[0108] Address determination module 220 is used to obtain the address of the node based on the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the frame number of the address instruction frame currently issued to the node.

[0109] The allocation module 230 is used to allocate addresses to the nodes according to their addresses.

[0110] In some embodiments, the address determination module 220 is specifically used for:

[0111] Obtain a first difference between the number of address instruction frames in the address instruction sequence and the number of address instruction frames currently issued to the node;

[0112] Obtain a second difference between the address carried in the addressing instruction frame currently issued to the node and the first difference;

[0113] The address of the node is obtained based on the second difference.

[0114] In summary, based on the vehicle of the present invention, the address of a node is obtained by acquiring the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the relation number of the address instruction frame currently issued to the node. This method can achieve precise control over the allocation of node addresses, thereby meeting preset requirements.

[0115] In one embodiment, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the electronic device executes the computer program, it performs the following steps: obtaining a node with a currently assigned address from a set of nodes according to a first addressing mode, wherein the set of nodes includes multiple nodes connected to a first bus of a vehicle; obtaining the address of the node according to the number of addressing instruction frames in an addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the frame number of the addressing instruction frame currently issued to the node; and allocating an address to the node according to the address of the node.

[0116] In one embodiment, when the processor executes the computer program, it further performs the following steps: sequentially searching for nodes from the first node to the last node in the node set; when the first unassigned node is found, the unassigned node is used as the node to be assigned the current address; or, sequentially searching for nodes from the last node to the first node in the node set; when the first unassigned node is found, the unassigned node is used as the node to be assigned the current address.

[0117] In one embodiment, when the processor executes a computer program, it further performs the following steps: obtaining a first difference between the number of addressing instruction frames in the addressing instruction sequence and the number of addressing instruction frames currently issued to the node; obtaining a second difference between the address carried by the addressing instruction frame currently issued to the node and the first difference; and obtaining the address of the node based on the second difference.

[0118] In one embodiment, when the processor executes a computer program, it further performs the following steps: obtaining the node whose address is currently to be allocated from the node set according to the second addressing mode; obtaining the address of the node according to the address carried by the addressing instruction frame currently issued to the node in the addressing instruction sequence; and allocating an address to the node according to the address of the node.

[0119] This electronic device can be a terminal device, and its internal structure diagram can be as follows: Figure 9 As shown, the terminal device includes a processor, memory, communication interface, display screen, and input device connected via a system bus. The processor provides computing and control capabilities. The memory includes a computer-readable storage medium and internal memory. The computer-readable storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the computer-readable storage medium. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements an application opening method. The display screen can be an LCD screen or a communication e-ink display screen. The input device can be a touch layer covering the display screen, buttons, a trackball, or a touchpad mounted on the terminal device casing, or an external keyboard, touchpad, or mouse.

[0120] In summary, the electronic device based on the present invention obtains the address of a node by acquiring the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently sent to the node, and the relation number of the address instruction frame currently sent to the node. This method can achieve precise control over the allocation of node addresses, thereby meeting preset requirements.

[0121] In one embodiment, a computer-readable storage medium storing a computer program that, when executed by a processor, performs the following steps: obtaining a node with a currently unallocated address from a node set according to a first addressing mode, wherein the node set includes multiple nodes connected to a first bus of a vehicle; obtaining the address of the node based on the number of addressing instruction frames in an addressing instruction sequence, the address carried by the addressing instruction frame currently issued to the node, and the frame number of the addressing instruction frame currently issued to the node; and allocating an address to the node based on the address of the node.

[0122] In one embodiment, when the processor executes the computer program, it further performs the following steps: sequentially searching for nodes from the first node to the last node in the node set; when the first unassigned node is found, the unassigned node is used as the node to be assigned the current address; or, sequentially searching for nodes from the last node to the first node in the node set; when the first unassigned node is found, the unassigned node is used as the node to be assigned the current address.

[0123] In one embodiment, when the processor executes a computer program, it further performs the following steps: obtaining a first difference between the number of addressing instruction frames in the addressing instruction sequence and the number of addressing instruction frames currently issued to the node; obtaining a second difference between the address carried by the addressing instruction frame currently issued to the node and the first difference; and obtaining the address of the node based on the second difference.

[0124] In one embodiment, when the processor executes a computer program, it further performs the following steps: obtaining the node whose address is currently to be allocated from the node set according to the second addressing mode; obtaining the address of the node according to the address carried by the addressing instruction frame currently issued to the node in the addressing instruction sequence; and allocating an address to the node according to the address of the node.

[0125] In summary, based on the computer-readable storage medium of the present invention, the address of a node can be obtained by acquiring the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the frame relation number of the address instruction frame currently issued to the node. This method can achieve precise control over the allocation of node addresses, thereby meeting preset requirements.

[0126] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of computer-readable and computer-unreadable storage media. Computer-readable storage may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static random access memory (SRAM) and dynamic random access memory (DRAM), etc.

[0127] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0128] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0129] Unless otherwise defined, the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used herein is for descriptive purposes only and is not intended to limit the invention. Terms such as “set” appearing herein can refer to either a component being directly attached to another component or a component being attached to another component via an intermediary. A feature described in one embodiment herein may be applied, alone or in combination with other features, to another embodiment, unless that feature is not applicable in that other embodiment or is otherwise stated.

[0130] The present invention has been described through the above embodiments; however, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the present invention to the described embodiments. Those skilled in the art will understand that many variations and modifications can be made based on the teachings of the present invention, and all such variations and modifications fall within the scope of protection claimed by the present invention.

Claims

1. A method for allocating node addresses for vehicles, characterized in that, include: The node whose address is to be assigned is obtained from the node set according to the first addressing method, wherein the node set includes multiple nodes connected to the vehicle's first bus; The address of the node is obtained based on the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the number of the address instruction frames currently issued to the node. Assign addresses to the nodes based on their addresses; The step of obtaining the address of the node based on the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the frame number of the address instruction frame currently issued to the node includes: Obtain a first difference between the number of address instruction frames in the address instruction sequence and the number of address instruction frames currently issued to the node; Obtain a second difference between the address carried in the addressing instruction frame currently issued to the node and the first difference; The address of the node is obtained based on the second difference.

2. The node address allocation method according to claim 1, characterized in that, The node that obtains the current address to be assigned from the node set according to the first addressing method includes: The node search proceeds sequentially from the first node to the last node in the node set. When the first unassigned node is found, the unassigned node is taken as the node to be assigned the current address; or, The node search proceeds sequentially from the tail node to the first node in the node set. When the first unassigned node is found, it is designated as the node for the current address to be assigned.

3. The node address allocation method according to claim 2, characterized in that, The first addressing mode is either LSM addressing mode or BSM addressing mode.

4. The node address allocation method according to claim 1, characterized in that, Also includes: The node whose address is to be assigned is obtained from the node set according to the second addressing method; The address of the node is obtained based on the address carried in the address instruction frame currently issued to the node in the address instruction sequence; Assign addresses to the nodes based on their addresses; The second addressing mode is one of LSM addressing mode and BSM addressing mode, and the second addressing mode is different from the first addressing mode.

5. A vehicle node address allocation device, implementing the vehicle node address allocation method according to any one of claims 1-4, characterized in that, include: A node determination module is used to obtain the node with the current address to be assigned from a node set according to a first addressing mode, wherein the node set includes multiple nodes connected to the vehicle's first bus; The address determination module is used to obtain the address of the node based on the number of address instruction frames in the address instruction sequence, the address carried by the address instruction frame currently issued to the node, and the frame number of the address instruction frame currently issued to the node. The allocation module is used to allocate addresses to the nodes based on their addresses.

6. The vehicle node address allocation device according to claim 5, characterized in that, The address determination module is specifically used for: Obtain a first difference between the number of address instruction frames in the address instruction sequence and the number of address instruction frames currently issued to the node; Obtain a second difference between the address carried in the addressing instruction frame currently issued to the node and the first difference; The address of the node is obtained based on the second difference.

7. A vehicle, characterized in that, include: The node address allocation device for a vehicle according to claim 5 or 6.

8. An electronic device, characterized in that, The system includes a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the program, it implements the node address allocation method for vehicles according to any one of claims 1-4.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the node address allocation method for vehicles according to any one of claims 1-4.

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