A data readout circuit and a resistive switching memory circuit

Abstract

This application discloses a data readout circuit and a resistive switching memory (RSM) storage circuit. The RSM data readout circuit includes: an adaptive sensitive current amplifier and a reference current generator. The adaptive sensitive current amplifier is electrically connected to the RSM and is also electrically connected to the reference current generator. The reference current generator generates a base reference current. The adaptive sensitive current amplifier obtains a reference current based on the base reference current and the bit line current of the RSM. The adaptive sensitive current amplifier compares the magnitude of the reference current with the magnitude of the bit line current to read out the stored data. This improves the problem of data readout errors caused by the high-resistivity degradation of the RSM.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a data readout circuit and a resistive variable memory circuit. Background Technology

[0002] In recent years, resistive random access memory (RRAM) has become a promising embedded non-volatile memory for advanced process nodes due to its good scalability, low power consumption and good compatibility with logic technology. It has been widely used in consumer electronics, autonomous vehicles, industrial control and IoT edge devices.

[0003] However, with the use of resistive random access memory (RRAM), the resistance state of RRAM gradually degrades, that is, the resistance value of the high resistance state decreases significantly or the resistance value of the low resistance state increases significantly. This makes it difficult for the data readout circuit to properly distinguish between the high resistance state and the low resistance state, resulting in data readout errors. Summary of the Invention

[0004] This application provides a data readout circuit and a resistive switching memory circuit, which can improve the problem of data readout errors caused by the high-resistivity degradation of the resistive switching memory.

[0005] In a first aspect, a data readout circuit for a resistive switching memory includes: an adaptive sensitive current amplifier and a reference current generator, wherein the adaptive sensitive current amplifier is used to electrically connect to the resistive switching memory, and the adaptive sensitive current amplifier is electrically connected to the reference current generator.

[0006] The reference current generator is used to generate a base reference current;

[0007] The adaptive sensitive current amplifier is used to obtain a reference current based on the base reference current and the bit line current of the resistive switching memory.

[0008] The adaptive sensitive current amplifier is used to compare the magnitude of the reference current with the bit line current to read out the stored data.

[0009] In one feasible implementation, the adaptive sensitive current amplifier includes: a data readout module and a reference current module;

[0010] The data readout module is electrically connected to the reference current module, and the data readout module is used to be electrically connected to the resistive switching memory. The reference current module is electrically connected to both the resistive switching memory and the reference current generator.

[0011] The reference current module is used to obtain the reference current based on the base reference current and the bit line current;

[0012] The data readout module is used to compare the magnitude of the reference current with the bit line current in order to read the stored data.

[0013] In one feasible implementation, the reference current module includes a feedback unit and multiple amplification units;

[0014] The feedback unit is electrically connected to the resistive switching memory and the amplification unit, respectively, and the amplification unit is electrically connected to the data readout module and the reference current generator, respectively.

[0015] The feedback unit is used to generate an excitation response based on the bit line current of the resistive random access memory, and to control the conduction of the corresponding amplification unit based on the excitation response.

[0016] The amplification unit is used to amplify the basic reference current to obtain the corresponding reference current.

[0017] In one feasible implementation, a plurality of the amplification units are connected in parallel, and each amplification unit corresponds to an amplification factor.

[0018] In one feasible implementation, the amplification unit includes a first MOS transistor, the gate of which is electrically connected to the feedback unit.

[0019] In one feasible implementation, the amplification unit includes a second MOS transistor, and a third MOS transistor is disposed between the second MOS transistor and the reference current generator;

[0020] The channel width-to-length ratio of the third MOS transistor multiplied by the amplification factor is equal to the channel width-to-length ratio of the corresponding second MOS transistor.

[0021] In one feasible implementation, the adaptive sensitive current amplifier includes a pre-protection module;

[0022] The data readout module includes a bit line current input terminal, a reference current input terminal, and a data readout terminal;

[0023] The bit line current input terminal and the reference current input terminal are respectively electrically connected to the pre-protection module.

[0024] In one feasible implementation, the reference current generator includes a replica resistive switching memory module and a current generation module;

[0025] The current generation module is used to generate the base reference current when the replicated resistive variable memory module is in a low-resistance state, wherein the current when the replicated resistive variable memory module is in a low-resistance state is a low-resistance current, which is twice the base reference current.

[0026] In one feasible implementation, the replicated resistive switching memory module includes multiple resistive switching memory cells.

[0027] In a second aspect, a resistive switching memory circuit includes: a resistive switching memory and a data readout circuit for the resistive switching memory as described in any one of the above claims;

[0028] The resistive switching memory includes a resistive switching memory array and a data writing control circuit, wherein the resistive switching memory array is electrically connected to the data writing control circuit.

[0029] The resistive switching memory array is electrically connected to the data readout circuit of the resistive switching memory;

[0030] The resistive switching memory array includes multiple resistive switching memory cells.

[0031] The data readout circuit and resistive switching memory circuit provided in this application embodiment, by setting an adaptive sensitive current amplifier and a reference current generator, can generate a base reference current. The adaptive sensitive current amplifier can adaptively adjust the magnitude of the corresponding reference current according to the magnitude of the bit line current. The reference current and the base reference current have a linear coefficient relationship. By dynamically adjusting the magnitude of the reference current, it can be ensured that the entire reference current is always at the middle position of the bit line current output in the high-resistivity and low-resistivity states, so that the stored data can still be read correctly even when the resistive switching memory experiences high-resistivity degradation. This can improve the accuracy of judging the magnitude of the bit line current and the reference current, and can avoid the problem of data readout errors caused by the resistive switching memory's resistance state degradation leading to a smaller resistive switching memory window. Attached Figure Description

[0032] Figure 1 A schematic block diagram of a data readout circuit for a resistive random access memory provided in an embodiment of this application;

[0033] Figure 2 A schematic block diagram of another data readout circuit for a resistive random access memory provided in an embodiment of this application;

[0034] Figure 3 A schematic block diagram of a data readout circuit for a resistive random access memory provided in an embodiment of this application;

[0035] Figure 4 A schematic structural diagram of another data readout circuit for a resistive random access memory provided in an embodiment of this application;

[0036] Figure 5 A schematic block diagram of a data readout circuit for a resistive random access memory provided in an embodiment of this application;

[0037] Figure 6A schematic structural diagram of another data readout circuit for a resistive random access memory provided in an embodiment of this application;

[0038] Figure 7 This is a schematic block diagram of a resistive switching memory circuit provided in an embodiment of this application. Detailed Implementation

[0039] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.

[0040] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.

[0041] Resistive random access memory (IRRAM) has become a promising embedded non-volatile memory for advanced process nodes due to its excellent scalability, low power consumption, and good compatibility with logic processes. It is widely used in consumer electronics, autonomous vehicles, industrial control, and IoT edge devices. However, with the use of IRRAM, the high-resistivity state of IRRAM gradually degrades, meaning the resistance value of the high-resistivity state decreases significantly. This can make it difficult for data readout circuits to distinguish between the high-resistivity and low-resistivity states, leading to data readout errors.

[0042] In view of this, this application provides a data readout circuit for a resistive random access memory (RRAM), which can improve the problem of data readout errors caused by the high-resistivity degradation of RRAM.

[0043] In one feasible implementation, Figure 1 This is a schematic block diagram of a data readout circuit for a resistive random access memory (RRAM) provided in an embodiment of this application. For example,... Figure 1As shown in the figure, this application provides a data readout circuit for a resistive random access memory (RRAM), including: an adaptive current sense amplifier (CSA) 100 and a reference current generator 200. The adaptive current sense amplifier 100 is electrically connected to the RRAM 300, and the adaptive current sense amplifier 100 is electrically connected to the reference current generator 200. The reference current generator 200 is used to generate a base reference current; the adaptive current sense amplifier 100 is used to obtain a reference current based on the base reference current and the bit line current of the RRAM 300; the adaptive current sense amplifier 100 is used to compare the magnitude of the reference current with the bit line current to read out the stored data.

[0044] For example, in combination Figure 1 The data readout circuit of the resistive random access memory (RRAM) provided in this application embodiment can read the stored data of the RRAM 300. Specifically, the RRAM 300 generates a bit line current I during operation. BL Bit line current I BL It is the current flowing through the resistive random access memory (RRAM). The data readout circuit of the RRAM can determine the bit line current I by... BL With its own generated reference current I ref The size of the resistive random access memory 300 is used to read the stored data. For example, if I... BL >I ref Then the data readout circuit of the resistive random access memory outputs "1", if I BL ref If the data readout circuit of the resistive random access memory (RRAM) outputs "0", then the RRAM outputs "0". For example, when the RRAM 300 is in a high-resistance state, the bit line current I... BL If the current is relatively small, the data readout circuit of the resistive random access memory will output "0"; when the resistive random access memory 300 is in a low-resistance state, the bit line current I... BL If the resistance is relatively large, the data readout circuit of the resistive random access memory will output "1". If the high-resistance state degrades, meaning its resistance decreases significantly, the bit line current I corresponding to the high-resistance state will increase. BL The corresponding increase occurs if the reference current I... ref If it remains unchanged, it is easy to make mistakes when judging the size relationship. BL >I ref ​In this situation, the data readout circuit of the resistive random access memory (RRAM) outputs "1", causing the RRAM 300 to be in a high-resistivity state. This results in a data readout error. The high-resistivity degradation of the RRAM 300 leads to a smaller RRAM window, which in turn increases the data readout error rate. Therefore, in the RRAM data readout circuit provided in this embodiment, the reference current generator 200 generates a base reference current I1, and the adaptive sensitive current amplifier 100 receives the bit line current I1 of the RRAM 300 through its electrical connection to the RRAM 300. BL The adaptive sensitive current amplifier 100 can determine the bit line current I of the resistive random access memory 300 currently being read. BL Whether an offset occurs, for example, when the high-resistance state in the resistive random access memory 300 degrades, that is, the resistance value of the high-resistance state decreases significantly, then the bit line current I corresponding to the high-resistance state will... BL The corresponding increase in size allows the adaptive sensitive current amplifier 100 to adjust according to the current bit line current I. BL Adjust the size of the corresponding reference current I ref Reference current I ref The magnitude adjustment is based on the baseline reference current I1, for example, the reference current I... ref = Adjustment factor × Base reference current I1. The adjustment factor can be preset and is not specifically limited in this application. For example, when the resistance is the same, if the bit line current I... BL If the value is increased, the reference current I can be adjusted accordingly. ref Increase it, if the bit line current I BL If the value is reduced, the reference current I can be adjusted accordingly. ref Reduce it. This is achieved by dynamically adjusting the reference current I. ref The size of the reference current I can guarantee the entire reference current I ref Bit line current I that is always in high impedance and low impedance states BL The middle position ensures that the stored data can still be read correctly even when the resistive random access memory 300 experiences high resistance degradation.

[0045] The data readout circuit of the resistive random access memory provided in this application embodiment, by setting an adaptive sensitive current amplifier 100 and a reference current generator 200, can generate a base reference current I1. The adaptive sensitive current amplifier 100 can adjust the data readout circuit according to the bit line current I1. BL The reference current I is adjusted according to its size. ref Reference current I ref The coefficient relationship is linear with the base reference current I1, and the reference current I is dynamically adjusted. ref The size of the reference current I can guarantee the entire reference current Iref The bit line current is consistently positioned between the high-resistance and low-resistance states, ensuring correct data reading even when the resistive random access memory (RRAM) experiences high-resistance degradation. This improves the performance for bit line current I... BL With reference current I ref The high precision in determining the size can prevent data read errors caused by the shrinking of the resistive variable memory window due to the degradation of the resistive state of the resistive variable memory 300.

[0046] In one feasible implementation, Figure 2 This is a schematic block diagram of another data readout circuit for a resistive random access memory (RANK) provided in an embodiment of this application. Exemplary examples include... Figure 2 As shown, the adaptive sensitive current amplifier 100 includes: a data readout module 110 and a reference current module 120; the data readout module 110 is electrically connected to the reference current module 120, the data readout module 110 is used to be electrically connected to the resistive random access memory 300, and the reference current module 120 is electrically connected to the resistive random access memory 300 and the reference current generator 200 respectively; the reference current module 120 is used to obtain a reference current based on the base reference current and the bit line current; the data readout module 110 is used to compare the magnitude of the reference current and the bit line current to read out the stored data.

[0047] For example, refer to Figure 2 The reference current module 120 can be based on the bit line current I. BL Determine whether the current reference current I needs to be adjusted. ref When it is determined that the current reference current I needs to be adjusted ref At that time, the corresponding reference current I can be obtained based on the base reference current I1. ref This allows for adjustment of the current reference current I. ref The data readout module 110 can be used to compare the bit line current I. BL With the adjusted reference current I ref The size is used to read the stored data.

[0048] The data readout circuit of the resistive random access memory provided in this application embodiment includes a data readout module 110 and a reference current module 120 within the adaptive sensitive current amplifier 100. The reference current module 120 can read data based on a base reference current I1 and a bit line current I. BL Adjust the current reference current I ref The data readout module 110 can compare the reference current I. ref With bit line current I BL The size of the data is used to read the stored data, thereby improving the performance for bit line current I. BL With reference current I refThe high precision in determining the size can prevent data read errors caused by the shrinking of the resistive variable memory window due to the degradation of the resistive state of the resistive variable memory 300.

[0049] In one feasible implementation, Figure 3 This is a schematic block diagram of another data readout circuit for a resistive random access memory (RRAM) provided in an embodiment of this application. For example, as shown... Figure 3 As shown, the reference current module 120 includes a feedback unit 121 and multiple amplification units 122. The feedback unit 121 is electrically connected to the resistive random access memory 300 and the amplification units 122, respectively. The amplification units 122 are electrically connected to the data readout module 110 and the reference current generator 200, respectively. The feedback unit 121 is used to generate an excitation response based on the bit line current of the resistive random access memory 300, and control the conduction of the corresponding amplification unit based on the excitation response. The amplification units 122 are used to amplify the basic reference current to obtain the corresponding reference current.

[0050] In one feasible implementation, multiple amplification units 122 are connected in parallel, and each amplification unit 122 corresponds to an amplification factor, which can correspond to the adjustment factor mentioned in the above embodiments.

[0051] For example, continue to refer to Figure 3 , Figure 3 The amplification unit 122 shown has four units, designated as amplification unit 1, amplification unit 2, amplification unit 3, and amplification unit 4. This is merely illustrative and not intended to limit the scope of this application. The feedback unit 121 can control the bit line current I of the resistive random access memory 300. BL A stimulus response is generated, and the specific amplifier unit 122 that will be turned on can be controlled based on the stimulus response. For example, such as... Figure 3 As shown, if the number of amplification units 122 is 4, the excitation response can be a 4-bit code, such as

[1000] ,

[0100] ,

[0010] , and

[0001] . Excitation response

[1000] can indicate that amplification unit 1 is turned on, and the other amplification units are not turned on; excitation response

[0100] can indicate that amplification unit 2 is turned on, and the other amplification units are not turned on; excitation response

[0010] can indicate that amplification unit 3 is turned on, and the other amplification units are not turned on; excitation response

[0001] can indicate that amplification unit 4 is turned on, and the other amplification units are not turned on. The amplification unit 122 can amplify the basic reference current I1 to obtain the corresponding reference current. For example, each amplification unit 122 corresponds to an amplification factor, which can be any number greater than 0, such as 0.5, 0.8, 1.2, 1.5, 2, 3, 4, or 5, etc., and this application does not impose any specific limitation. Multiplying the base reference current I1 by the amplification factor corresponding to any amplification unit 122 yields the corresponding reference current I. refThat is, the conduction of each amplification unit 122 corresponds to a different reference current I. ref The controlled-on amplifier unit 122 will output the corresponding reference current I. ref Provided to the data reading module 110.

[0052] The data readout circuit of the resistive random access memory provided in this application embodiment, by setting a feedback unit 121, according to the bit line current I... BL An excitation response is generated, and the conduction of amplification unit 122 is selected based on the excitation response. Multiple amplification units 122 are connected in parallel, and each amplification unit 122 corresponds to an amplification coefficient. The coefficient of the basic reference current I1 is amplified by the conduction of the amplification unit 122. The current reference current I1 can be amplified by controlling the conduction of the corresponding amplification unit through the excitation response via the feedback unit 121. ref Adjustments were made to improve the performance of the bit line current I. BL With reference current I ref The high precision in determining the size can prevent data read errors caused by the shrinking of the resistive variable memory window due to the degradation of the resistive state of the resistive variable memory 300.

[0053] In one feasible implementation, Figure 4 This is a schematic structural diagram of another data readout circuit for a resistive random access memory (RRAM) provided in an embodiment of this application. For example,... Figure 4 As shown, the amplification unit 122 includes a first MOS transistor, and the gate of the first MOS transistor is electrically connected to the feedback unit 121. Figure 4 The diagram shows four amplification units 122, each corresponding to a first MOSFET: P0, P1, P2, and P3. The gate of each first MOSFET is electrically connected to a feedback unit 121. Turning on the first MOSFET controls the conduction of the corresponding amplification unit 122, and turning it off controls its disconnection. The feedback unit 121 can supply an electrical signal to the gate of the first MOSFET based on the excitation response to turn it on, thus controlling the conduction of the corresponding amplification unit 122. Using MOSFETs for switching control is highly sensitive and can be implemented using pulse signals or other electrical signals, facilitating control without increasing the circuit's readout delay.

[0054] In one feasible implementation, continue to refer to Figure 4 The amplification unit 122 also includes a second MOS transistor. Figure 4The second MOSFETs corresponding to the amplification units shown are M0, M1, M2, and M3, respectively. A third MOSFET M4 is disposed between the second MOSFETs and the reference current generator 200. The channel width-to-length ratio of the third MOSFET M4 multiplied by the amplification factor is equal to the channel width-to-length ratio of the corresponding second MOSFET, that is, the channel width-to-length ratio of the third MOSFET M4 and the channel width-to-length ratio of the second MOSFET are equal to the amplification factor of the corresponding amplification unit 122. Short-circuiting the source and gate of the third MOSFET M4 allows it to be in a saturated state, and the current flowing through the third MOSFET M4 is always the basic reference current I1. Amplification of the basic reference current I1 is achieved by connecting the gates of the second MOSFET and the third MOSFET M4 in series and by designing different channel width-to-length ratios of the MOSFETs. For example, if the channel width-to-length ratio of the third MOSFET M4 is 1, and the channel width-to-length ratios of the second MOSFETs M0, M1, M2, and M3 are 3, 6, 9, and 12 respectively, then the corresponding currents flowing through the second MOSFETs M0, M1, M2, and M3 are I3 = 3I1, I6 = 6I1, I9 = 9I1, and I... 12 =12I1, therefore, the basic reference current I1 can be amplified to obtain the corresponding reference current I. ref Achieving current amplification by designing different channel dimensions (width-to-length ratio) of the second MOSFET is relatively easy and yields high precision. The channel dimensions of the MOSFET provided in this embodiment are merely illustrative and are not intended to limit the scope of this application.

[0055] Continue to refer to Figure 4 The adaptive sensitive current amplifier 100 includes a pre-protection module 130; the data readout module 110 includes a bit line current input terminal 111, a reference current input terminal 112 and a data readout terminal DQ; the bit line current input terminal 111 and the reference current input terminal 112 are electrically connected to the pre-protection module 130 respectively. Figure 4 The data readout module 110 shown can use a comparator COMP. The two input terminals of the comparator COMP are used as the bit line current input terminal 111 and the reference current input terminal 112, respectively, and the output terminal is used as the data readout terminal DQ. The pre-protection module 130 can play a current limiting protection role. Specifically, it controls the voltages Vmat and Vref to prevent the current flowing through the pre-protection module 130 from being too large, thus avoiding damage to the comparator COMP due to excessive current. Figure 4 The two pre-protection modules 130 are symmetrically arranged relative to the comparator COMP, and the two pre-protection modules 130 have the same circuit structure, which can provide current limiting protection for the two input terminals of the comparator COMP. Figure 4As shown, VDD can represent a high level, and VSS can represent a low level; EN_READN and EN_READ can represent the enable signal terminals of the MOSFET, respectively; Vclamp can represent the voltage input terminal of the clamping circuit; the pre-protection module 130 includes NMOS and PMOS transistors. Figure 4 The circuit structure of the pre-protection module 130 shown is merely illustrative and is not intended to limit the scope of this application. Reference current I ref The bit line current I is input to the reference current input terminal 112 via the pre-protection module 130. BL The current input is obtained through the pre-protection module 130 to the line current input terminal 111.

[0056] In one feasible implementation, Figure 5 This is a schematic structural diagram of a data readout circuit for a resistive random access memory (RRAM) provided in an embodiment of this application. For example,... Figure 5 As shown, the reference current generator 200 includes a replica resistive variable storage module 210 and a current generation module 220; the current generation module 220 is used to generate a base reference current I1 when the replica resistive variable storage module 210 is in a low-resistance state, wherein the current when the replica resistive variable storage module is in a low-resistance state is a low-resistance current, which is twice the base reference current.

[0057] In one feasible implementation, Figure 6 This is a schematic structural diagram of another data readout circuit for a resistive random access memory (RRAM) provided in an embodiment of this application. Exemplary examples include... Figure 6 As shown, the replica resistive variable memory module 210 includes multiple resistive variable memory cells 211, which can be arranged in an array, but this application does not specify a particular arrangement. The current generation module 220 generates a base reference current I1 when all resistive variable memory cells 211 are in a low-resistance state. The current in the replica resistive variable memory module 210 when it is in a low-resistance state is a low-resistance current I0, which is twice the base reference current I1. The current generation module 220 generates the base reference current I1 based on the low-resistance state of the resistive variable memory cells 211, i.e., the current generation module 220 halves the low-resistance current I0 to obtain the base reference current I1. The low-resistance current I0 obtained by replicating the resistive variable memory module 210 is the maximum current of the simulated resistive variable memory. Using half of the low-resistance current I0 as the base reference current I1, subsequent amplification and adjustment of the base reference current I1 can make the reference current I... refThe bit line current is always maintained between the low-resistance state bit line current and the high-resistance state bit line current. The low-resistance state bit line current is the bit line current when the resistive random access memory 300 is in the low-resistance state, and the high-resistance state bit line current is the bit line current when the resistive random access memory 300 is in the high-resistance state. In this way, the high-resistance bit line current is always less than the reference current, and the low-resistance bit line current is always greater than the reference current. This allows the data read circuit output of the resistive random access memory 300 to be "0" when the resistive random access memory 300 is in the high-resistance state, and to be "1" when the resistive random access memory 300 is in the low-resistance state. This improves the performance of the bit line current I. BL With reference current I ref The precision in determining the size can prevent data read errors caused by the shrinking of the resistive storage window due to resistive state degradation of the resistive memory 300. The replicating of the resistive memory module 210 can be directly copied from the resistive storage cells in the resistive memory 300; this application does not impose specific limitations on this.

[0058] Secondly, embodiments of this application provide a resistive switching memory circuit. Figure 7 This is a schematic structural block diagram of a resistive switching memory circuit provided in an embodiment of this application. For example, as shown... Figure 7 As shown, this application provides a resistive random access memory (RRAM) circuit, including: a resistive random access memory (RRAM) and a data readout circuit (CSA) for any of the aforementioned RRAMs; the RRAM includes a RRAM array 310 and a data write control circuit, the RRAM array 310 is electrically connected to the data write control circuit; the RRAM array 310 is electrically connected to the data readout circuit (CSA) of the RRAM; the RRAM array 310 includes a plurality of RRAM cells 311, and the plurality of RRAM cells 311 are arranged in an array.

[0059] For example, such as Figure 7 As shown, the resistive random access memory (RRAM) cell 311 adopts a 1T1R structure, meaning each RRAM cell 311 includes one MOSFET and one resistor. Each row of RRAM cells 311 connected in series is electrically connected to a data readout circuit (CSA) of the RRAM. The replica RRAM module 210 is electrically connected to both the data write control circuit and the current generation module 220. The data write control circuit includes a first data write control circuit 321 and a second data write control circuit 322.

[0060] The resistive switching memory cell 311 conducts electricity through oxygen vacancies in the resistive switching layer. When the gap between these oxygen vacancies changes, the conductivity of the resistive switching memory cell also changes, which can be reflected in changes in current or resistance. During a write operation on the resistive switching memory array 310, a conductive path needs to be formed in the corresponding resistive switching memory cell 311 being written to (this process can be called Form); otherwise, the resistive switching memory cell 311 is in an insulating state. During operation, a large potential difference needs to be formed across the resistive switching memory cell 311. At this time, a suitable voltage is applied to the word line (WL) to saturate the MOSFET, which can limit current and prevent excessive current from damaging the resistive switching memory cell 311. A larger voltage is applied to the bit line (BL), and the source line (SL) is grounded to activate the oxygen vacancies in the resistive switching layer. Under the influence of the electric field, a conductive path is formed, and the resistive switching memory cell 311 changes to a low resistance state (LRS). The process of returning the resistive random access memory (RRAM) cell 311 to a high resistance state (HRS), thus breaking the conductive path of the RRAM cell 311, is called a reset. This operation is the reverse of the form operation. It requires applying a reverse voltage to the RRAM cell 311 to break the conductive filament. Specifically, a voltage is applied to the word line WL to put the MOSFET in a linear state (resistance increases, no current limiting is needed), the bit line BL is grounded, and a voltage is applied to the source line SL. This allows the RRAM cell 311 to change from a low resistance state to a high resistance state. This process is the process of erasing data or writing "0" (Rest). The set operation is similar to the form operation, but the RRAM cell 311 after the form operation does not require a large bit line voltage to form a conductive path. It is easy to understand that changing from a high resistance state to a low resistance state is the process of writing "1". During the erasure and writing process of the resistive switching memory cell 311, the conductive paths will randomly form and break. There are nanoscale gaps between the oxygen vacancies that make up the conductive paths. The unpredictable gap size and random distribution of oxygen vacancies lead to changes in the shape and size of the paths, which in turn leads to changes in the resistance between the resistive switching memory cells 311. This change can be extracted as the response of the Physical Unclonaable Function (PUF). After performing a Form operation on multiple resistive switching memory cells 311, and then through the PUF initialization key generation process of Set and Rest, a suitable reference current is selected. By comparing the reference current and the bit line current through the data readout circuit CSA of the resistive switching memory, the stored data (0 or 1) can be read out. The obtained stored data can be used as the key of the PUF.

[0061] For example, such as Figure 7As shown, the first data write control circuit 321 controls the application of the word line WL voltage according to the clock signal CLK, and the second data write control circuit 322 controls whether the source line SL and bit line BL are grounded or connected to voltage. Typically, the gate of a MOSFET corresponds to the word line WL, the source corresponds to the source line SL, and the drain corresponds to the bit line BL. For example, as... Figure 7 As shown, the same row of resistive switching memory cells 311 corresponds to the same word line WL signal, and the word line signals of the resistive switching memory array 310 are WL... <0> WL <0> ..., WL <30> WL <31> (32-bit); the same source line SL signal corresponds to the same resistive switching memory cell 311 in the same row, and the source line signals of the resistive switching memory array 310 are respectively SL <0> SL <0> , ..., SL <30> SL <31> (32-bit); the same bit line BL current corresponds to the same row of resistive switching memory cells 311, and the bit line currents of the resistive switching memory array 310 are respectively I... BL0 I BL1 ... I BL30 I BL31 (32-bit); the corresponding read storage data are DQ0, DQ1, ..., DQ30, DQ31 (32-bit). The word lines of the replicated resistive memory module 210 are WLR (WLR <0> WLR <0> ..., WLR <30> WLR <31> The source line is SL_R, the bit line is BL_R, and the bit line current is I. BL_R The base reference current I1 is I based on the bit line current. BL_R generate. Figure 7 As shown, the 32-row × 32-column resistive switching memory cells 311 in the resistive switching memory array 310 are merely schematic representations and are not intended to limit the scope of this application.

[0062] The resistive random access memory (RRAM) circuit provided in this application addresses the issue of reduced storage window caused by the degradation of the high-resistivity state of the RRAM cell, which prevents the RRAM readout circuit from properly identifying the low-resistivity and high-resistivity states, leading to readout errors of the stored data. The RRAM circuit provided in this application includes a data readout circuit CSA for the RRAM. It utilizes a replica RRAM module 210 and a current generation module 220 to generate a base reference current I1. An adaptive sensitive current amplifier 100 then adjusts the base reference current I1 based on the bit line current I1. BL The reference current I is adaptively adjusted to the base reference current I1. ref When the bit line current I BL When the high-resistivity state changes due to degradation, the reference current I is adjusted by correspondingly amplifying the base reference current I1. ref The effect is to synchronously and adaptively adjust the bit line current I. BL The reference current I being compared refThis method compensates for the reduced storage window and improves the performance for bit line current I. BL With reference current I ref The precision of size determination avoids data reading errors, ensuring that stored data can still be read correctly even when the resistive variable memory cell experiences high impedance degradation.

[0063] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.

[0064] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.

Claims

1. A data readout circuit for a resistive random access memory (RRAM), characterized in that, include: An adaptive sensitive current amplifier and a reference current generator are provided, wherein the adaptive sensitive current amplifier is used to electrically connect to a resistive switching memory, and the adaptive sensitive current amplifier is electrically connected to the reference current generator. The reference current generator is used to generate a base reference current; The adaptive sensitive current amplifier is used to obtain a reference current based on the base reference current and the bit line current of the resistive switching memory. The adaptive sensitive current amplifier is used to compare the magnitude of the reference current with the bit line current in order to read out the stored data; The adaptive sensitive current amplifier includes: a data readout module and a reference current module; The data readout module is electrically connected to the reference current module, and the data readout module is used to be electrically connected to the resistive switching memory. The reference current module is electrically connected to both the resistive switching memory and the reference current generator. The reference current module is used to obtain the reference current based on the base reference current and the bit line current; The data readout module is used to compare the magnitude of the reference current with the bit line current in order to read out the stored data; The reference current module includes a feedback unit and multiple amplification units; The feedback unit is electrically connected to the resistive switching memory and the amplification unit, respectively, and the amplification unit is electrically connected to the data readout module and the reference current generator, respectively. The feedback unit is used to generate an excitation response based on the bit line current of the resistive random access memory, and to control the conduction of the corresponding amplification unit based on the excitation response. The amplification unit is used to amplify the basic reference current to obtain the corresponding reference current.

2. The data readout circuit of the resistive random access memory according to claim 1, characterized in that, Multiple amplification units are connected in parallel, and each amplification unit corresponds to an amplification factor.

3. The data readout circuit of the resistive random access memory according to claim 2, characterized in that, The amplification unit includes a first MOS transistor, the gate of which is electrically connected to the feedback unit.

4. The data readout circuit of the resistive random access memory according to claim 2, characterized in that, The amplification unit includes a second MOS transistor, and a third MOS transistor is disposed between the second MOS transistor and the reference current generator; The channel width-to-length ratio of the third MOS transistor multiplied by the amplification factor is equal to the channel width-to-length ratio of the corresponding second MOS transistor.

5. The data readout circuit of the resistive random access memory according to claim 1, characterized in that, The adaptive sensitive current amplifier includes a pre-protection module; The data readout module includes a bit line current input terminal, a reference current input terminal, and a data readout terminal; The bit line current input terminal and the reference current input terminal are respectively electrically connected to the pre-protection module.

6. The data readout circuit of the resistive random access memory according to claim 1, characterized in that, The reference current generator includes a replica resistive switching memory module and a current generation module; The current generation module is used to generate the base reference current when the replicated resistive variable memory module is in a low-resistance state, wherein the current when the replicated resistive variable memory module is in a low-resistance state is a low-resistance current, which is twice the base reference current.

7. The data readout circuit of the resistive random access memory according to claim 6, characterized in that, The replicated resistive switching memory module includes multiple resistive switching memory units.

8. A resistive switching memory circuit, characterized in that, include: A resistive random access memory and a data readout circuit for the resistive random access memory as described in any one of claims 1-6; The resistive switching memory includes a resistive switching memory array and a data writing control circuit, wherein the resistive switching memory array is electrically connected to the data writing control circuit. The resistive switching memory array is electrically connected to the data readout circuit of the resistive switching memory; The resistive switching memory array includes multiple resistive switching memory cells.

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