Display substrate and display device

Abstract

A display substrate includes a substrate and a circuit structure layer disposed on the substrate. The substrate includes a display area and a peripheral area located at a periphery of the display area. The display area includes a first display region and a second display region, and the first display region at least partially surrounds the second display region. The circuit structure layer includes a plurality of pixel circuits, a plurality of initial signal lines, and at least one electrostatic conduction line. The plurality of initial signal lines are electrically connected with the plurality of pixel circuits and extend along a first direction, and the electrostatic conduction line extends along a second direction. The plurality of pixel circuits are located in the first display region, and the plurality of initial signal lines are at least located in the first display region. The electrostatic conduction line is electrically connected with at least two initial signal lines.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. Under-display camera technology is a novel technology proposed to improve the screen-to-body ratio of display devices. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] On one hand, this embodiment provides a display substrate, including: a substrate and a circuit structure layer located on the substrate. The substrate includes a display area and a peripheral area located around the display area; the display area includes: a first display area and a second display area, the first display area at least partially surrounding the second display area. The circuit structure layer includes: a plurality of pixel circuits, a plurality of initial signal lines, and at least one electrostatic conduction line. The plurality of initial signal lines are electrically connected to the plurality of pixel circuits and extend along a first direction, the at least one electrostatic conduction line extends along a second direction, and the first and second directions intersect. The plurality of pixel circuits are located in the first display area, the plurality of initial signal lines are at least located in the first display area; the at least one electrostatic conduction line is electrically connected to at least two initial signal lines.

[0006] In some exemplary embodiments, the plurality of pixel circuits arranged along the first direction constitute a row of pixel circuits. The circuit structure layer further includes: a plurality of first signal lines, which extend along the first direction and are electrically connected to the row of pixel circuits. The orthographic projection of the at least one electrostatic conductive line on the substrate overlaps with the orthographic projection of the plurality of first signal lines on the substrate.

[0007] In some exemplary embodiments, the at least one electrostatic conduction line is located on the side of the plurality of first signal lines near the substrate, and the plurality of first signal lines are located on the side of the plurality of initial signal lines near the substrate.

[0008] In some exemplary embodiments, in a direction perpendicular to the display substrate, the circuit structure layer of the first display area includes at least: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on the substrate; the semiconductor layer includes an active layer of transistors of the plurality of pixel circuits; the first conductive layer includes the gate of the transistors of the plurality of pixel circuits and a first capacitor plate of the storage capacitors of the plurality of pixel circuits; the second conductive layer includes a second capacitor plate of the storage capacitors of the plurality of pixel circuits. The at least one electrostatic conduction line is located in the semiconductor layer, the at least two first signal lines are located in the first conductive layer, and the plurality of initial signal lines are located in the second conductive layer.

[0009] In some exemplary embodiments, the plurality of initial signal lines include at least one first initial signal line and at least one second initial signal line. The at least one electrostatic conduction line includes at least one first electrostatic conduction line. The first initial signal line and the second initial signal line electrically connected to the same row of pixel circuitry are electrically connected to the same first electrostatic conduction line.

[0010] In some exemplary embodiments, the first electrostatic conductive line is located on the side of the first initial signal line and the second initial signal line closer to the substrate. One end of the first electrostatic conductive line is electrically connected to the first initial signal line via a first connecting electrode, and the other end is electrically connected to the second initial signal line via a second connecting electrode; the first connecting electrode and the second connecting electrode are of the same layer structure and are located on the side of the first initial signal line and the second initial signal line away from the substrate.

[0011] In some exemplary embodiments, the orthographic projection of the first electrostatic conduction line on the substrate overlaps with the orthographic projection of two first signal lines on the substrate, the two first signal lines including: a first scan line and a light emission control line electrically connected to the same row of pixel circuits.

[0012] In some exemplary embodiments, the plurality of initial signal lines includes: a plurality of first initial signal lines and a plurality of second initial signal lines. The at least one electrostatic conduction line includes: a second electrostatic conduction line and a third electrostatic conduction line. The second electrostatic conduction line is electrically connected to the plurality of first initial signal lines, and the third electrostatic conduction line is electrically connected to the plurality of second initial signal lines.

[0013] In some exemplary embodiments, the second electrostatic conductive line and the third electrostatic conductive line are co-layered and located on the side of the first and second initial signal lines closest to the substrate. The second electrostatic conductive line is electrically connected to the first initial signal line via a third connection electrode, and the third electrostatic conductive line is electrically connected to the second initial signal line via a fourth connection electrode; the third and fourth connection electrodes are co-layered and located on the side of the first and second initial signal lines furthest from the substrate.

[0014] In some exemplary embodiments, the orthographic projection of the second electrostatic conductive line connected between two adjacent first initial signal lines on the substrate overlaps with the orthographic projection of the three first signal lines on the substrate. Similarly, the orthographic projection of the third electrostatic conductive line connected between two adjacent second initial signal lines on the substrate overlaps with the orthographic projection of the three first signal lines on the substrate.

[0015] In some exemplary embodiments, the at least one electrostatic conductive line is located on the side of the plurality of initial signal lines away from the substrate.

[0016] In some exemplary embodiments, the at least one electrostatic conduction line is located in the surrounding area.

[0017] In some exemplary embodiments, the display substrate further includes: a light-emitting structure layer located on the side of the circuit structure layer away from the substrate; the light-emitting structure layer includes: a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits; at least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements, and at least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements.

[0018] In some exemplary embodiments, the light-emitting structure layer includes an anode layer, and the anode layer of the second display area includes an anode of a second light-emitting element; the anode of the second light-emitting element has a bottom and a sidewall extending from the bottom toward the side away from the substrate.

[0019] In some exemplary embodiments, the display substrate further includes at least one first organic insulating layer located between the light-emitting structure layer and the circuit structure layer, wherein the first organic insulating layer of the second display area has at least one first anode recess. The orthogonal projection of the anode of the second light-emitting element onto the substrate covers the orthogonal projection of the first anode recess of the first organic insulating layer onto the substrate. The light-emitting structure layer further includes a pixel definition layer located on the side of the anode layer away from the substrate, wherein the pixel definition layer has pixel openings that expose the surface of the anode of the second light-emitting element. The orthogonal projection of the first anode recess of the first organic insulating layer onto the substrate covers the orthogonal projection of the pixel openings onto the substrate.

[0020] In some exemplary embodiments, the light-emitting structure layer further includes: a pixel definition layer, wherein at least a portion of the anode layer is located on the side of the pixel definition layer away from the substrate; the pixel definition layer has a pixel opening, and the orthogonal projection of the anode of the second light-emitting element onto the substrate covers the orthogonal projection of the pixel opening onto the substrate.

[0021] In some exemplary embodiments, the display substrate further includes a first organic insulating layer located on the side of the anode layer near the substrate and in contact with the anode layer, the first organic insulating layer having at least one annular groove in the second display area. The orthogonal projection of the anode of the second light-emitting element onto the substrate covers the orthogonal projection of the annular groove of the first organic insulating layer onto the substrate.

[0022] In some exemplary embodiments, the first organic insulating layer further has a plurality of auxiliary holes located within the annular groove, and the orthographic projection of the anode of the second light-emitting element onto the substrate covers the orthographic projection of the plurality of auxiliary holes within the annular groove onto the substrate.

[0023] On the other hand, this embodiment provides a display device including a display substrate as described above.

[0024] In some exemplary embodiments, the display device further includes a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor onto the display substrate overlaps with a second display area of ​​the display substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0027] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0028] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0029] Figure 3 for Figure 2 The timing diagram of the pixel circuit shown is shown below.

[0030] Figure 4 This is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0031] Figure 5 for Figure 1 A partially enlarged schematic diagram of the circuit structure layer in the middle region CC;

[0032] Figure 6A for Figure 5 A partial cross-sectional view along the Q-Q' direction;

[0033] Figure 6B for Figure 5 A partial cross-sectional view along the R-R' direction;

[0034] Figure 7A for Figure 5 A schematic diagram of the circuit structure layer after the semiconductor layer is formed.

[0035] Figure 7B for Figure 5 A schematic diagram of the circuit structure layers after the first conductive layer is formed.

[0036] Figure 7C for Figure 5 A schematic diagram of the circuit structure layers after the formation of the second conductive layer;

[0037] Figure 7D for Figure 5 A schematic diagram of the circuit structure layers after the formation of the third insulating layer;

[0038] Figure 7E for Figure 5 A schematic diagram of the circuit structure layers after the formation of the third conductive layer;

[0039] Figure 7F for Figure 7E A schematic diagram of the third conductive layer in the middle;

[0040] Figure 7G for Figure 5 A schematic diagram of the circuit structure layers after the fifth insulating layer is formed.

[0041] Figure 8A for Figure 1 Another enlarged schematic diagram of the circuit structure layer in the middle region CC;

[0042] Figure 8B for Figure 8A A schematic diagram of the circuit structure layer after the semiconductor layer is formed;

[0043] Figure 8C for Figure 8A A schematic diagram of the circuit structure layers after the first conductive layer is formed.

[0044] Figure 8D for Figure 8A A schematic diagram of the circuit structure layers after the formation of the second conductive layer;

[0045] Figure 8E for Figure 8A A schematic diagram of the circuit structure layers after the formation of the third insulating layer;

[0046] Figure 8F for Figure 8A A schematic diagram of the circuit structure layers after the formation of the third conductive layer;

[0047] Figure 9A for Figure 1 Another enlarged schematic diagram of the circuit structure layer in the middle region CC;

[0048] Figure 9B for Figure 9A A schematic diagram of the circuit structure layers after the formation of the third conductive layer;

[0049] Figure 9C for Figure 9B A schematic diagram of the third conductive layer in the middle;

[0050] Figure 10 This is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0051] Figure 11A This is a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0052] Figure 11B for Figure 11A A schematic diagram of the display substrate after the ninth insulating layer has been formed;

[0053] Figure 11C for Figure 11A A schematic diagram of the display substrate after the anode layer has been formed;

[0054] Figure 12 for Figure 11A A partial cross-sectional view along the P-P' direction;

[0055] Figure 13This is another partial cross-sectional schematic diagram of the second display area according to at least one embodiment of the present disclosure;

[0056] Figure 14A This is a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0057] Figure 14B for Figure 14A A schematic diagram of the display substrate after the ninth insulating layer has been formed;

[0058] Figure 14C for Figure 14A A schematic diagram of the display substrate after the anode layer has been formed;

[0059] Figure 15 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0060] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0061] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0062] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0063] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0064] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0065] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional elements.

[0066] In this specification, a transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between its drain (drain terminal, drain region, or drain electrode) and its source (source terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, the channel region refers to the region through which current primarily flows.

[0067] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged. Additionally, the gate can also be called the control terminal.

[0068] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0069] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0070] In this disclosure, "light transmittance" refers to the ability of light to pass through a medium, and is the percentage of light flux passing through a transparent or translucent body relative to the incident light flux.

[0071] In this disclosure, "approximately" and "roughly" refer to situations where there are no strict limits and the process and measurement errors are allowed. In this disclosure, "roughly the same" means that the values ​​differ by no more than 10%.

[0072] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main part of A extends along direction B".

[0073] Static electricity is generated during the manufacturing process of pixel circuits on display substrates. This static electricity tends to accumulate in long conductors, leading to a risk of electrostatic discharge (ESD) in the display area. Display substrates using under-display camera technology, due to space constraints, lack effective static discharge lines in the display area, resulting in severe ESD problems during the manufacturing process of pixel circuits and causing significant yield losses.

[0074] This embodiment provides a display substrate, including a substrate and a circuit structure layer located on the substrate. The substrate includes a display area and a peripheral area surrounding the display area. The display area includes a first display area and a second display area, with the first display area at least partially surrounding the second display area. The circuit structure layer includes a plurality of pixel circuits, a plurality of initial signal lines, and at least one electrostatic conduction line. The plurality of initial signal lines are electrically connected to the plurality of pixel circuits and extend along a first direction, and the at least one electrostatic conduction line extends along a second direction. The plurality of pixel circuits are located in the first display area, and the plurality of initial signal lines are at least located in the first display area. The at least one electrostatic conduction line is electrically connected to at least two initial signal lines.

[0075] The display substrate provided in this embodiment connects at least two initial signal lines by setting electrostatic conduction lines. An electrostatic discharge loop can be formed by the initial signal lines and the electrostatic conduction lines to dissipate the static electricity generated during the manufacturing process, thereby effectively reducing the ESD risk in the display area.

[0076] In some exemplary embodiments, at least one electrostatic conductive line may be located in the peripheral area. This example demonstrates that placing the electrostatic conductive line in the peripheral area does not occupy wiring space in the display area. However, this embodiment is not limited to this. In other examples, at least one electrostatic conductive line may be located in the first display area, for example, close to the peripheral area.

[0077] In some exemplary embodiments, the display substrate may further include a light-emitting structure layer located on the side of the circuit structure layer away from the substrate. The light-emitting structure layer may include a plurality of first light-emitting elements located in a first display area and a plurality of second light-emitting elements located in a second display area. The plurality of pixel circuits include a plurality of first pixel circuits and a plurality of second pixel circuits. At least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements, and at least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements.

[0078] In some exemplary embodiments, the plurality of pixel circuits arranged along the first direction constitute a row of pixel circuits. The circuit structure layer may further include: a plurality of first signal lines, which may extend along the first direction and be electrically connected to the row of pixel circuits. The orthographic projection of at least one electrostatic conduction line on the substrate may overlap with the orthographic projections of the plurality of first signal lines on the substrate. For example, the plurality of first signal lines may extend from the first display area to the peripheral area and overlap with the electrostatic conduction line in the peripheral area. For example, the orthographic projection of at least one electrostatic conduction line on the substrate may overlap with the orthographic projections of two or three first signal lines on the substrate. However, this embodiment is not limited in this respect.

[0079] In some exemplary embodiments, at least one electrostatic conduction line may be located on the side of the plurality of first signal lines near the substrate, and the plurality of first signal lines may be located on the side of the plurality of initial signal lines near the substrate. In some examples, in a direction perpendicular to the display substrate, the circuit structure layer of the first display area may at least include: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on the substrate. The semiconductor layer may include the active layer of transistors of the plurality of pixel circuits; the first conductive layer may include the gate of the transistors of the plurality of pixel circuits and the first capacitor plate of the storage capacitors of the plurality of pixel circuits; the second conductive layer may include: the second capacitor plate of the storage capacitors of the plurality of pixel circuits. At least one electrostatic conduction line may be located in the semiconductor layer, at least two first signal lines may be located in the first conductive layer, and the plurality of initial signal lines may be located in the second conductive layer.

[0080] In some exemplary embodiments, the multiple initial signal lines may include at least one first initial signal line and at least one second initial signal line. At least one electrostatic conduction line may include at least one first electrostatic conduction line. The first and second initial signal lines electrically connected to the same row of pixel circuitry may be electrically connected to the same first electrostatic conduction line. In some examples, the orthographic projection of the first electrostatic conduction line onto the substrate overlaps with the orthographic projection of the two first signal lines onto the substrate. The two first signal lines may include a first scan line and a light emission control line electrically connected to the same row of pixel circuitry. In this example, the first electrostatic conduction line may electrically connect adjacent first and second initial signal lines and overlap with the two first signal lines to form two electrostatic conduction control transistors. During fabrication, when static electricity exists on the two first signal lines, the two electrostatic conduction control transistors are turned on, connecting the first and second initial signal lines to form an electrostatic dissipation loop, allowing static electricity to be dissipated within the loop and preventing burn-out of the transistors.

[0081] In some exemplary embodiments, the multiple initial signal lines may include multiple first initial signal lines and multiple second initial signal lines. At least one electrostatic conduction line may include a second electrostatic conduction line and a third electrostatic conduction line. The second electrostatic conduction line may be electrically connected to the multiple first initial signal lines, and the third electrostatic conduction line may be electrically connected to the multiple second initial signal lines. In some examples, the orthographic projection of the second electrostatic conduction line connected between two adjacent first initial signal lines onto the substrate may overlap with the orthographic projection of the three first signal lines onto the substrate; similarly, the orthographic projection of the third electrostatic conduction line connected between two adjacent second initial signal lines onto the substrate may overlap with the orthographic projection of the three first signal lines onto the substrate. In this example, initial signal lines transmitting the same initial signal may be electrically connected by the same electrostatic conduction line. For example, the electrostatic conduction line may be electrically connected to adjacent initial signal lines transmitting the same signal and overlap with the three first signal lines to form three electrostatic conduction control transistors. During the fabrication process, when there is static electricity on the three first signal lines, all three static electricity conduction control transistors are turned on, which can connect adjacent initial signal lines that transmit the same signal, forming a static electricity dissipation loop. This allows the static electricity to be dissipated in the loop, preventing the transistors from being burned.

[0082] In some exemplary embodiments, at least one electrostatic conduction line may be located on the side of the plurality of initial signal lines away from the substrate. In this example, the electrostatic conduction line may be electrically connected to the plurality of initial signal lines, forming a loop at the tip of the initial signal lines to dissipate static electricity and prevent static buildup.

[0083] The following examples illustrate the solution of this embodiment.

[0084] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 1 As shown, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. The display area AA of the display substrate may include a first display area A1 and a second display area A2. The first display area A1 at least partially surrounds the second display area A2. In this example, the first display area A1 may surround the second display area A2.

[0085] In some examples, such as Figure 1 As shown, the second display area A2 can be a light-transmitting display area, or it can also be called the under-display camera (FDC) area; the first display area A1 can be a normal display area. For example, the orthographic projection of a photosensor (such as a camera) onto the display substrate can be located within the second display area A2 of the display substrate. In some examples, such as... Figure 1As shown, the second display area A2 can be circular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the second display area A2. However, this embodiment is not limited to this. In other examples, the second display area A2 can be rectangular, and the size of the orthographic projection of the photosensor onto the display substrate can be less than or equal to the size of the inscribed circle of the second display area A2.

[0086] In some examples, such as Figure 1 As shown, the second display area A2 can be located at the top center of the display area AA. The first display area A1 can surround the second display area A2. However, this embodiment is not limited in this respect. For example, the second display area A2 can be located at other positions such as the upper left or upper right corner of the display area AA. For example, the first display area A1 can surround at least one side of the second display area A2.

[0087] In some examples, such as Figure 1 As shown, the display area AA can be rectangular, such as a rounded rectangle. The second display area A2 can be circular or elliptical. However, this embodiment is not limited to this. For example, the second display area A2 can be other shapes such as rectangle, semicircle, pentagon, etc.

[0088] In some examples, the display area AA can be configured with multiple sub-pixels. At least one sub-pixel can include pixel circuitry and a light-emitting element. The pixel circuitry is configured to drive the connected light-emitting element. For example, the pixel circuitry is configured to provide drive current to drive the light-emitting element to emit light. The pixel circuitry can include multiple transistors and at least one capacitor; for example, the pixel circuitry can be a 3T1C (i.e., 3 transistors and 1 capacitor) structure, a 7T1C (i.e., 7 transistors and 1 capacitor) structure, a 5T1C (i.e., 5 transistors and 1 capacitor) structure, an 8T1C (i.e., 8 transistors and 1 capacitor) structure, or an 8T2C (i.e., 8 transistors and 2 capacitors) structure, etc.

[0089] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0090] In some examples, a pixel unit of the display area may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0091] In some examples, the shape of the light-emitting element can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement. When a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0092] Figure 2 This is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is described using a 7T1C structure as an example. However, this embodiment is not limited thereto.

[0093] In some exemplary implementations, such as Figure 2 As shown, the pixel circuit of this example may include seven transistors (i.e., first transistor T1 to seventh transistor T7) and a storage capacitor Cst. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0094] In some exemplary embodiments, the seven transistors in the pixel circuit can be either P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve product yield. In some possible implementations, the seven transistors in the pixel circuit may include both P-type and N-type transistors.

[0095] In some exemplary embodiments, the seven transistors of the pixel circuit can be low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OTFTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the OTFT is made of oxide semiconductor. LTPS TFTs offer advantages such as high mobility and fast charging, while OTFTs offer advantages such as low leakage current. Integrating LTPS and OTFTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0096] In some exemplary implementations, such as Figure 2As shown, the display substrate may include: a first scan line GL, a data line DL, a first power line VDD, a second power line VSS, a light emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a second scan line RST1, and a third scan line RST2. In some examples, the first power line VDD may be configured to provide a constant first voltage signal to the pixel circuit, and the second power line VSS may be configured to provide a constant second voltage signal to the pixel circuit, wherein the first voltage signal may be greater than the second voltage signal. The first scan line GL may be configured to provide a scan signal SCAN to the pixel circuit, the data line DL may be configured to provide a data signal DATA to the pixel circuit, the light emission control line EML may be configured to provide a light emission control signal EM to the pixel circuit, the second scan line RST1 may be configured to provide a first reset control signal RESET1 to the pixel circuit, and the third scan line RST2 may be configured to provide a second reset control signal RESET2 to the pixel circuit. In some examples, the second scan line RST1, electrically connected to the nth row pixel circuit, can be electrically connected to the first scan line GL of the (n-1)th row pixel circuit to be input to the scan signal SCAN(n-1), meaning the first reset control signal RESET1(n) and the scan signal SCAN(n-1) can be the same. Similarly, the third scan line RST2 of the nth row pixel circuit can be electrically connected to the first scan line GL of the nth row pixel circuit to be input to the scan signal SCAN(n), meaning the second reset control signal RESET2(n) and the scan signal SCAN(n) can be the same. Here, n is an integer greater than 0. This reduces the number of signal lines on the display substrate, enabling a narrow bezel design. However, this embodiment is not limited to this.

[0097] In some exemplary embodiments, a first initial signal line INIT1 can be configured to provide a first initial signal to the pixel circuit, and a second initial signal line INIT2 can be configured to provide a second initial signal to the pixel circuit. For example, the first initial signal may be different from the second initial signal. The first and second initial signals may be constant voltage signals, the magnitude of which may be, for example, between a first voltage signal and a second voltage signal, but are not limited thereto. In other examples, the first and second initial signals may be the same, and only the first initial signal line may be configured to provide the first initial signal.

[0098] In some exemplary implementations, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The third transistor T3 can also be called a driving transistor. The gate of the fourth transistor T4 is electrically connected to the first scan line GL, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the first terminal of the third transistor T3. The fourth transistor T4 can also be called a data writing transistor. The gate of the second transistor T2 is electrically connected to the first scan line GL, the first terminal of the second transistor T2 is electrically connected to the gate of the third transistor T3, and the second terminal of the second transistor T2 is electrically connected to the second terminal of the third transistor T3. The second transistor T2 can also be called a threshold compensation transistor. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the first terminal of the third transistor T3. The gate of the sixth transistor T6 is electrically connected to the light-emitting control line EML, the first terminal of the sixth transistor T6 is electrically connected to the second terminal of the third transistor T3, and the second terminal of the sixth transistor T6 is electrically connected to the anode of the light-emitting element EL. The fifth transistor T5 and the sixth transistor T6 can also be referred to as light-emitting control transistors. The first transistor T1 is electrically connected to the gate of the third transistor T3 and is configured to reset the gate of the third transistor T3. The seventh transistor T7 is electrically connected to the anode of the light-emitting element EL and is configured to reset the anode of the light-emitting element EL. The gate of the first transistor T1 is electrically connected to the second scan line RST1, the first terminal of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second terminal of the first transistor T1 is electrically connected to the gate of the third transistor T3. The gate of the seventh transistor T7 is electrically connected to the third scan line RST2, the first terminal of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second terminal of the seventh transistor T7 is electrically connected to the anode of the light-emitting element EL. The first transistor T1 and the seventh transistor T7 can also be referred to as reset control transistors. The first capacitor plate of the storage capacitor Cst is electrically connected to the gate of the third transistor T3, and the second capacitor plate of the storage capacitor Cst is electrically connected to the first power supply line VDD.

[0099] In this example, the first node N1 is the connection point of the storage capacitor Cst, the first transistor T1, the third transistor T3, and the second transistor T2; the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, and the third transistor T3; the third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6; and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7, and the light-emitting element EL.

[0100] Figure 3 for Figure 2The timing diagram of the pixel circuit shown is illustrated below. Figure 3 by Figure 2 The pixel circuit shown is illustrated using P-type transistors as an example. The second reset control signal provided by the third scan line RST2 can be the same as the scan signal provided by the first scan line GL.

[0101] In some exemplary embodiments, the operation of the pixel circuit during a frame display period may include: a first stage S1, a second stage S2, and a third stage S3.

[0102] The first stage, S1, is called the reset stage. The first reset control signal RESET1 provided by the second scan line RST1 is a low-level signal, turning on the first transistor T1. The first initial signal provided by the first initial signal line INIT1 is provided to the first node N1 to initialize N1 and clear the original data voltage in the storage capacitor Cst. The scan signal SCAN provided by the first scan line GL is a high-level signal, and the light emission control signal EM provided by the light emission control line EML is a high-level signal, turning off the fourth transistor T4, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. During this stage, the light-emitting element EL does not emit light.

[0103] The second stage, S2, is called the data writing stage or threshold compensation stage. The scan signal SCAN provided by the first scan line GL is low, while the first reset control signal RESET1 provided by the second scan line RST1 and the light emission control signal EM provided by the light emission control line EML are both high. The data line DL outputs a data signal. During this stage, since the first capacitor plate of the storage capacitor Cst is low, the third transistor T3 is turned on. The low scan signal SCAN turns on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. The turn on the second transistor T2 and the fourth transistor T4 allows the data voltage Vdata output by the data line DL to be supplied to the first node N1 via the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage of the first capacitor plate of the storage capacitor Cst (i.e., the first node N1) is Vdata - |Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the anode of the light-emitting element EL. This initializes (resets) the anode of the light-emitting element EL, clearing its internal pre-stored voltage and completing the initialization process, ensuring that the light-emitting element EL does not emit light. The first reset control signal RESET1 provided by the second scan line RST1 is a high-level signal, causing the first transistor T1 to turn off. The light emission control signal EM provided by the light emission control signal line EML is a high-level signal, causing the fifth transistor T5 and the sixth transistor T6 to turn off.

[0104] The third stage, S3, is called the light-emitting stage. The light-emitting control signal EM provided by the light-emitting control line EML is a low-level signal, while the scan signal SCAN provided by the first scan line GL and the first reset control signal RESET1 provided by the second scan line RST1 are high-level signals. When the light-emitting control signal EM provided by the light-emitting control line EML is low, the fifth transistor T5 and the sixth transistor T6 are turned on. The first voltage signal output from the first power line VDD provides a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting element EL to emit light.

[0105] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and first terminal. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0106] I = K × (Vgs - Vth) 2=K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 .

[0107] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the light-emitting element EL, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the first voltage signal output by the first power line VDD.

[0108] As can be seen from the above formula, the current flowing through the light-emitting element EL is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3.

[0109] Figure 4 This is a partial schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as... Figure 4 As shown, the first display area A1 of the display substrate may include a transition area A1a and a non-transition area A1b. The transition area A1a may be located on at least one side outside the second display area A2 (e.g., one side; or, around the perimeter, i.e., including the top and bottom sides and the left and right sides).

[0110] In some examples, the second display area A2 may include a plurality of second light-emitting elements 14 arranged in an array. The transition area A1a may include a plurality of first pixel circuits 11 and a plurality of second pixel circuits 12 arranged in an array, and may also include a plurality of first light-emitting elements. At least one first pixel circuit 11 in the transition area A1a may be electrically connected to at least one first light-emitting element and configured to drive the first light-emitting element to emit light. The orthographic projection of the first light-emitting element on the substrate and the orthographic projection of the electrically connected first pixel circuit 11 on the substrate may at least partially overlap. At least one second pixel circuit 12 may be electrically connected to at least one second light-emitting element 14 disposed in the second display area A2 via a conductive line L (e.g., a transparent conductive line) and configured to drive the second light-emitting element 14 to emit light. For example, one end of the conductive line L may be electrically connected to the second pixel circuit 12 and the other end may be electrically connected to the second light-emitting element 14, and the conductive line L may extend from the transition area A1a to the second display area A2. The orthographic projection of the second pixel circuit 12 on the substrate and the orthographic projection of the electrically connected second light-emitting element 14 on the substrate may not overlap. In this example, each of the second light-emitting elements 14 in the second display area A2 can be electrically connected to the second pixel circuit 12 in the transition area A1a via at least one conductive line L. By placing the second pixel circuit 12 that drives the second light-emitting elements 14 in the transition area A1a, the occlusion of light by the pixel circuit can be reduced, thereby increasing the light transmittance of the second display area A2.

[0111] In some examples, the conductive line L can be made of a transparent conductive material, such as a conductive oxide material, like indium tin oxide (ITO). However, this embodiment is not limited to this.

[0112] In some examples, such as Figure 4 As shown, the non-transition region A1b may include a plurality of first pixel circuits 11 and a plurality of invalid pixel circuits 15 arranged in an array, and may also include a plurality of first light-emitting elements. At least one first pixel circuit 11 in the non-transition region A1b may be electrically connected to at least one first light-emitting element, and the orthographic projection of the first light-emitting element on the substrate and the orthographic projection of the electrically connected first pixel circuit 11 on the substrate may at least partially overlap.

[0113] In some examples, such as Figure 4 As shown, the transition region A1a and the non-transition region A1b may further include multiple invalid pixel circuits 15. By providing invalid pixel circuits, the uniformity of components across multiple film layers during the etching process can be improved. For example, the invalid pixel circuit may have a structure substantially the same as the first and second pixel circuits in its row or column, except that it is not electrically connected to any light-emitting element.

[0114] In some examples, since the first display area A1 is provided with not only a first pixel circuit electrically connected to the first light-emitting element, but also a second pixel circuit electrically connected to the second light-emitting element, the number of pixel circuits in the first display area A1 can be greater than the number of first light-emitting elements. In some examples, such as... Figure 4 As shown, the area for setting the new pixel circuit (including the second pixel circuit and the invalid pixel circuit) can be obtained by reducing the size of the first pixel circuit 11 in the first direction D1. For example, the size of the pixel circuit in the first direction D1 can be smaller than the size of the first light-emitting element in the first direction D1. In this example, as... Figure 4 As shown, the original 'a' column pixel circuits can be compressed along the first direction D1, thereby adding space for one more column of pixel circuits. The space occupied by the 'a' column pixel circuits before compression and the 'a+1' column pixel circuits after compression can be the same. Here, 'a' can be an integer greater than 1. In some examples, 'a' can be equal to 4. However, this embodiment is not limited to this. For example, 'a' can be equal to 2 or 3.

[0115] In other examples, the original b rows of pixel circuits can be compressed along the second direction D2 to add space for a new row of pixel circuits, and the space occupied by the original b rows of pixel circuits and the compressed b+1 rows of pixel circuits is the same. Here, b can be an integer greater than 1. Alternatively, the area for setting the new pixel circuits can be obtained by reducing the size of the first pixel circuits along the first direction D1 and the second direction D2.

[0116] In this embodiment, a row of light-emitting elements can refer to pixel circuits connected to that row of light-emitting elements all being connected to the same gate line (e.g., a scan line). A row of pixel circuits can refer to multiple pixel circuits arranged sequentially along a first direction, and all pixel circuits in a row can be connected to the same gate line. However, this embodiment is not limited in this respect.

[0117] In some examples, such as Figure 1 As shown, the surrounding area BB may include: a left border area and a right border area located on opposite sides of the display area AA along the first direction D1, and a top border area and a bottom border area located on opposite sides of the display area AA along the second direction D2. The structures within the left border area and the right border area can be roughly the same; the following example uses the structure within the left border area as an example for illustration.

[0118] In some examples, the bottom bezel area may include: a fan-out area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area AA. The fan-out area, connected to the display area AA, may include multiple data leads configured to connect to the data lines of the display area AA in a fan-out routing manner. The bending area, connected to the fan-out area, may include a composite insulating layer with grooves, configured to bend the driver chip area and bonding pin area to the back of the display area AA. The driver chip area may house an integrated circuit (IC), which may be configured to connect to the multiple data fan-out lines. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0119] In some examples, the left bezel area may include a circuit area, a power line area, a dam area, and a cut area arranged sequentially along a direction away from the display area AA. The circuit area may be connected to the display area AA and may include at least a gate drive circuit, a first initial peripheral trace, and a second initial peripheral trace. The first initial peripheral trace may be configured to transmit a first initial signal, and the second initial peripheral trace may be configured to transmit a second initial signal. The gate drive circuit may be located on the side of the second initial peripheral trace away from the display area AA, and the first initial peripheral trace may be located on the side of the second initial peripheral trace closer to the display area AA. The first and second initial peripheral traces may extend from the left bezel area to the lower bezel area, for example, they may be electrically connected to bonding pads in a bonding pin area to receive the first and second initial signals, respectively. The gate drive circuit may be electrically connected to scan lines and light-emitting control lines connected to pixel circuits in the display area AA. The power line area may be connected to the circuit area and may include at least bezel power leads, which may extend along a direction parallel to the edge of the display area and be electrically connected to the cathode of the light-emitting element in the display area AA. The crack dam area can be connected to the power line area and can include at least multiple cracks formed on the composite insulating layer. The cutting area can be connected to the crack dam area and can include at least a cutting groove formed on the composite insulating layer, the cutting groove being configured so that, after all film layers of the display substrate have been prepared, the cutting equipment cuts along the cutting groove respectively.

[0120] In some examples, both the first initial peripheral trace and the second initial peripheral trace can be double-layered traces. The first initial peripheral trace may include a first initial sub-trace and a third initial sub-trace that are stacked and electrically connected to each other, and the second initial peripheral trace may include a second initial sub-trace and a fourth initial sub-trace that are stacked and electrically connected to each other. However, this embodiment is not limited to this. For example, the first initial peripheral trace and the second initial peripheral trace may be single-layered traces.

[0121] Figure 5 for Figure 1 A partially enlarged schematic diagram of the circuit structure layer in the middle region CC. Figure 6A for Figure 5 A partial cross-sectional view along the Q-Q' direction. Figure 6B for Figure 5 A partial cross-sectional view along the R-R' direction.

[0122] In some examples, such as Figure 5As shown, the first display area A1 may include a first circuit area A11 and a second circuit area A12 arranged at intervals in the first direction D1. The first circuit area A11 may be provided with multiple columns of first pixel circuits (e.g., three columns of first pixel circuits), and the second circuit area A12 may be provided with a column of invalid pixel circuits (e.g., including multiple invalid pixel circuits) or a column of pixel circuits including invalid pixel circuits and second pixel circuits. In the following examples, the first pixel circuit of the first circuit area A11 of the first display area A1 is used as an example for illustration and explanation, and the film structure and fabrication process of the gate driving circuit in the peripheral area are omitted in the following examples.

[0123] In some examples, such as Figure 5 , Figure 6A and Figure 6B As shown, in the direction perpendicular to the display substrate, the circuit structure layer of the display substrate of the first display area A1 may include: a semiconductor layer 20, a first conductive layer 21, a second conductive layer 22, a third conductive layer 23, and a fourth conductive layer 24 sequentially disposed on the substrate 100. A first insulating layer 101 may be disposed between the semiconductor layer 20 and the first conductive layer 21; a second insulating layer 102 may be disposed between the first conductive layer 21 and the second conductive layer 22; a third insulating layer 103 may be disposed between the second conductive layer 22 and the third conductive layer 23; and a fourth insulating layer 104 and a fifth insulating layer 105 may be disposed between the third conductive layer 23 and the fourth conductive layer 24. In some examples, the first insulating layer 101 to the fourth insulating layer 104 may all be inorganic insulating layers, and the fifth insulating layer 105 may be an organic insulating layer. The first conductive layer 21 may also be called a first gate metal layer, the second conductive layer 22 may also be called a second gate metal layer, the third conductive layer 23 may also be called a first source / drain metal layer, and the fourth conductive layer 24 may also be called a second source / drain metal layer. However, this embodiment is not limited in this respect. In some other examples, only a fifth insulating layer may be provided between the third conductive layer 23 and the fourth conductive layer 24.

[0124] The following reference Figures 5 to 7GThe fabrication process of the display substrate is illustrated by way of example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0125] In some exemplary embodiments, the fabrication process of the display substrate may include the following operations.

[0126] (1) Providing a substrate. In some examples, the substrate 100 can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, etc. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen.

[0127] (2) Forming a semiconductor layer. In some examples, a semiconductor thin film is deposited on the substrate 100, and the semiconductor thin film is patterned by a patterning process, forming a semiconductor layer 20 between the first display area A1 and the surrounding area BB. In some examples, the material of the semiconductor layer 20 may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene.

[0128] Figure 7A for Figure 5 A schematic diagram of the circuit structure layer after the semiconductor layer has been formed. In some examples, such as... Figure 7AAs shown, the semiconductor layer 20 of the first display area A1 may include at least: active layers of multiple transistors of multiple pixel circuits (e.g., including: a first active layer 310 of the first transistor of the first pixel circuit, a second active layer 320 of the second transistor, a third active layer 330 of the third transistor, a fourth active layer 340 of the fourth transistor, a fifth active layer 350 of the fifth transistor, a sixth active layer 360 of the sixth transistor, and a seventh active layer 370 of the seventh transistor). The first active layer 310 of the first transistor of a first pixel circuit to the seventh active layer 370 of the seventh transistor can be an integral structure interconnected.

[0129] In some examples, such as Figure 7A As shown, the first active layer 310, the second active layer 320 and the fourth active layer 340 of the first pixel circuit can be located on one side of the second direction D2 of the third active layer 330 of the first pixel circuit, and the fifth active layer 350, the sixth active layer 360 and the seventh active layer 370 can be located on the other side of the second direction D2 of the third active layer 330 of the first pixel circuit.

[0130] In some examples, such as Figure 7A As shown, the first active layer 310 of the first pixel circuit can be roughly U-shaped, the second active layer 320, the fifth active layer 350 and the sixth active layer 360 can be roughly L-shaped, the third active layer 330 can be roughly n-shaped, and the fourth active layer 340 and the seventh active layer 370 can be roughly I-shaped. However, this embodiment is not limited in this respect.

[0131] In some examples, such as Figure 7A As shown, the first active layer 310 of the first transistor 31 to the seventh active layer 370 of the seventh transistor 37 in the first pixel circuit may each include: a first region, a second region, and a channel region located between the first and second regions. In some examples, the first and second regions of the active layer can be interpreted as the source or drain electrodes of the transistor. The portion of the active layer between the transistors can be interpreted as doped wiring that can be used to electrically connect the transistors. The channel region may be undoped and have semiconductor characteristics. The first and second regions located on both sides of the channel region may be doped with impurities and thus have conductivity. The impurities may vary depending on the type of transistor. However, this embodiment is not limited in this respect.

[0132] In some examples, such as Figure 7AAs shown, the first region 340-1 of the fourth active layer 340, the first region 350-1 of the fifth active layer 350, and the first region 370-1 of the seventh active layer 370 can be configured independently. The second region 310-2 of the first active layer 310 can simultaneously serve as the first region 320-1 of the second active layer 320. The second region 320-2 of the second active layer 320 can simultaneously serve as the second region 330-2 of the third active layer 330 and the first region 360-1 of the sixth active layer 360. The first region 330-1 of the third active layer 330 can simultaneously serve as the second region 340-2 of the fourth active layer 340 and the second region 350-2 of the fifth active layer 350. The second region 360-2 of the sixth active layer 360 can simultaneously serve as the second region 370-2 of the seventh active layer 370.

[0133] In some examples, such as Figure 7A As shown, the semiconductor layer 20 of the peripheral region BB may include at least a plurality of first electrostatic conduction lines 201. The plurality of first electrostatic conduction lines 201 may extend along the second direction D2 and be arranged sequentially along the second direction D2. The plurality of first electrostatic conduction lines 201 may be adjacent to the pixel circuit of the first display area A1 in the first direction D1.

[0134] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate 100 on which the aforementioned structure is formed. The first conductive film is patterned by a patterning process to form a first insulating layer 101 covering the semiconductor layer 20, and a first conductive layer 21 disposed on the first insulating layer 101.

[0135] Figure 7B for Figure 5 A schematic diagram of the circuit structure layers after the first conductive layer has been formed. In some examples, such as... Figure 7BAs shown, the first conductive layer 21 of the first display area A1 may include at least: the gates of multiple transistors of multiple pixel circuits and the first capacitor plate of the storage capacitor (e.g., the gates of multiple transistors of the first pixel circuit and the first capacitor plate 381 of the storage capacitor), a first scan line (e.g., GL(n-1), GL(n), and GL(n+1)), a light emission control line (e.g., EML(n-1) and EML(n)), and a second scan line (e.g., RST1(n-1), RST1(n), and RST1(n+1)). Here, n is a positive integer. The first scan line, the second scan line, and the light emission control line may all be line shapes extending along the first direction D1 of the main body portion. The ends of the first scan line, the second scan line, and the light emission control line may extend into the peripheral area BB. The first scan line electrically connected to a row of pixel circuits may be located between the second scan line and the light emission control line electrically connected to that row of pixel circuits. In this example, the third scan line electrically connected to a row of pixel circuits is the second scan line electrically connected to the next row of pixel circuits.

[0136] In some examples, such as Figure 7B As shown, taking the first pixel circuit in the nth row as an example, the overlapping area of ​​the second scan line RST1(n) and the first active layer 310 of the first transistor T1 in the first pixel circuit of this row can serve as the gate of the first transistor T1. The overlapping area of ​​the first scan line GL(n) and the second active layer 320 of the second transistor T2 in the first pixel circuit of this row can serve as the gate of the second transistor T2. The overlapping area of ​​the first scan line GL(n) and the fourth active layer 340 of the fourth transistor T4 in the first pixel circuit of this row can serve as the gate of the fourth transistor T4. The overlapping area of ​​the light emission control line EML(n) and the fifth active layer 350 of the fifth transistor T5 in the first pixel circuit of this row can serve as the gate of the fifth transistor T5. The overlapping area of ​​the light emission control line EML(n) and the sixth active layer 360 of the sixth transistor T6 in the first pixel circuit of this row can serve as the gate of the sixth transistor T6. The overlapping region between the second scan line RST1(n+1) and the seventh active layer 370 of the seventh transistor T7 of the first pixel circuit in this row can serve as the gate of the seventh transistor T7.

[0137] In some examples, such as Figure 7B As shown, the first capacitor plate 381 of the storage capacitor in the first pixel circuit can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the first capacitor plate 381 onto the substrate overlaps with the orthographic projection of the third active layer 330 of the third transistor T3 of the first pixel circuit onto the substrate. The first capacitor plate 381 of the first pixel circuit can simultaneously serve as one plate of the storage capacitor and the gate of the third transistor T3.

[0138] In some examples, after the first conductive layer 21 is formed, it can be used as a shield to conduct the semiconductor layer 20. The semiconductor layer 20 in the area shielded by the first conductive layer 21 can form the channel region of the transistor, and the semiconductor layer 20 in the area not shielded by the first conductive layer 21 can be conducted. For example, the first and second regions of the active layer of the seven transistors in the pixel circuit are both conducted.

[0139] In some examples, such as Figure 7B As shown, the first conductive layer 21 of the surrounding area BB may include at least: a plurality of first initial transition electrodes 211 and a plurality of second initial transition electrodes 212. The first initial transition electrodes 211 and the second initial transition electrodes 212 may be arranged at intervals in the second direction D2 and may be aligned in the second direction D2.

[0140] In some examples, such as Figure 7B As shown, the ends of the first scan line and the light-emitting control line can extend to the peripheral region BB. The orthographic projection of the first electrostatic conduction line 201 on the substrate overlaps with the orthographic projections of a first scan line and a light-emitting control line on the substrate. The overlapping region of the first electrostatic conduction line 201 and the orthographic projection of a first scan line (e.g., GL(n)) on the substrate can serve as the channel region of the first electrostatic conduction control transistor M1, and the overlapping region of the first scan line and the first electrostatic conduction line 201 can serve as the gate of the first electrostatic conduction control transistor M1. The overlapping region of the first electrostatic conduction line 201 and the orthographic projection of a light-emitting control line (e.g., EML(n)) on the substrate can serve as the channel region of the second electrostatic conduction control transistor M2, and the overlapping region of the light-emitting control line and the orthographic projection of the first electrostatic conduction line 201 on the substrate can serve as the gate of the second electrostatic conduction control transistor M2. The first electrostatic conduction control transistor M1 can be adjacent to the second transistor T2 of the pixel circuit of the first display area A1 in the first direction D1, and the second electrostatic conduction control transistor M2 can be adjacent to the sixth transistor T6 of the pixel circuit of the first display area A1 in the first direction D1.

[0141] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate 100 on which the aforementioned structure is formed, and the second conductive film is patterned by a patterning process to form a second insulating layer 102 and a second conductive layer 22 disposed on the second insulating layer 102.

[0142] Figure 7C for Figure 5 A schematic diagram of the circuit structure layers after the formation of the second conductive layer. In some examples, such as... Figure 7CAs shown, the second conductive layer 22 of the first display area A1 may include at least: second capacitor plates of storage capacitors for multiple pixel circuits (e.g., second capacitor plate 382 of the first pixel circuit), multiple first initial signal lines INIT1, and multiple second initial signal lines INIT2. The shapes of the first initial signal lines INIT1 and INIT2 may be line shapes whose main body extends along the first direction D1. The orthographic projection of the first initial signal line INIT1 onto the substrate may be located between the orthographic projections of the light emission control line and the first scan line onto the substrate, and the orthographic projection of the second initial signal line INIT2 onto the substrate may be located between the orthographic projections of the light emission control line and the first scan line onto the substrate. The ends of the first initial signal lines INIT1 and INIT2 may extend to the peripheral area BB. The orthographic projection of the second capacitor plate 382 of the first pixel circuit onto the substrate may overlap with the orthographic projection of the first capacitor plate 381 onto the substrate. The second capacitor plate 382 may have a hollow structure, and the orthographic projection of the hollow structure onto the substrate may be located within the orthographic projection range of the first capacitor plate 381 onto the substrate. In some examples, in a row of pixel circuits, the second capacitor plates of the storage capacitors of adjacent pixel circuits can be electrically connected to each other, for example, forming an interconnected integrated structure. The second capacitor plates of the integrated structure can be reused as power signal connection lines, ensuring that multiple second capacitor plates in a row of pixel circuits have the same potential. This helps improve the uniformity of the display substrate, avoids display defects, and ensures the display effect of the display substrate.

[0143] In some examples, such as Figure 7C As shown, the second conductive layer 22 in the surrounding area BB may include at least: multiple scan output lines 221 and multiple light emission control output lines 222. The scan output lines 221 may be configured to connect the first scan line to the scan signal output terminal of the corresponding gate drive circuit. The light emission control output lines 222 may be configured to connect the light emission control line to the light emission control signal output terminal of the corresponding gate drive circuit. One scan output line 211 and one light emission control output line 222 are adjacent in the second direction D2. However, this embodiment is not limited in this respect. For example, the scan output lines and light emission control output lines may be located in the first conductive layer.

[0144] In some examples, such as Figure 7C As shown, the ends of the first initial signal line INIT1 and the second initial signal line INT2 can extend to the peripheral region BB. The orthographic projections of the first initial signal line INIT1 and the second initial signal line INIT2 onto the substrate may not overlap with the orthographic projection of the first electrostatic conduction line 201 onto the substrate. The two ends of the first electrostatic conduction line 201 along the second direction D2 may be adjacent to the first initial signal line INIT1 and the second initial signal line INIT2, respectively.

[0145] (5) Forming a third insulating layer. In some examples, a third insulating film is deposited on the substrate 100 on which the aforementioned pattern is formed, and the third insulating film is patterned by a patterning process to form a third insulating layer 103. The third insulating layer 103 may have multiple vias, for example, multiple vias may expose the surfaces of the semiconductor layer 20, the first conductive layer 21 and the second conductive layer 22 respectively.

[0146] Figure 7D for Figure 5 A schematic diagram of the circuit structure layers after the formation of the third insulating layer. In some examples, such as... Figure 7D As shown, the third insulating layer 103 of the first display area A1 can have multiple vias, for example, it may include: first via V1 to tenth via V10. The third insulating layer 103, second insulating layer 102, and first insulating layer 101 within the first via V1 to sixth via V6 are removed, exposing the surface of the semiconductor layer 20. The third insulating layer 103 and second insulating layer 102 within the seventh via V7 are removed, exposing the surface of the first conductive layer 21. The third insulating layer 103 within the eighth via V8 to tenth via V10 is removed, exposing the surface of the second conductive layer 22.

[0147] In some examples, such as Figure 7DAs shown, the third insulating layer 103 of the peripheral region BB can have multiple vias, for example, it can include eleventh via V11 to twenty-sixth via V26. The third insulating layer 103, second insulating layer 102, and first insulating layer 101 within the eleventh via V11 and twelfth via V12 are removed, exposing the surface of the electrostatic conduction line 201 located in the semiconductor layer 20. The third insulating layer 103 and second insulating layer 102 within the thirteenth via V13 and sixteenth via V16 are removed, exposing the surface of the second scan line located in the first conductive layer 21. The third insulating layer 103 and second insulating layer 102 within the fourteenth via V14 are removed, exposing the surface of the first scan line located in the first conductive layer 21. The third insulating layer 103 and second insulating layer 102 within the fifteenth via V15 are removed, exposing the surface of the light-emitting control line located in the first conductive layer 21. The third insulating layer 103 and the second insulating layer 102 in the seventeenth via V17 and the eighteenth via V18 are removed, exposing the surface of the first initial transfer electrode 211 located in the first conductive layer 21. The third insulating layer 103 and the second insulating layer 102 in the nineteenth via V19 and the twentieth via V20 are removed, exposing the surface of the second initial transfer electrode 212 located in the first conductive layer 21. The third insulating layer 103 in the twenty-second via V22 and the twenty-first via V21 is removed, exposing the surface of the first initial signal line INIT1 located in the second conductive layer 22. The third insulating layer 103 in the twenty-fourth via V24 and the twenty-third via V23 is removed, exposing the surface of the second initial signal line INIT2 located in the second conductive layer 22. The third insulating layer 103 in the twenty-sixth via V26 is removed, exposing the surface of the scan output line 221 located in the second conductive layer 22. The third insulating layer 103 inside the twenty-fifth via V25 is removed, exposing the surface of the light-emitting control output line 222 located in the second conductive layer 22.

[0148] (6) Forming a third conductive layer. In some examples, a third conductive film is deposited on the substrate 100 on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer 23 on the third insulating layer 103.

[0149] Figure 7E for Figure 5 A schematic diagram of the circuit structure layer after the formation of the third conductive layer. Figure 7F for Figure 7E A schematic diagram of the third conductive layer. In some examples, such as... Figure 7E and Figure 7F As shown, the third conductive layer 23 of the first display area A1 may include: a plurality of pixel connection electrodes (e.g., including: first pixel connection electrode 231 to sixth pixel connection electrode 236). Figures 7D to 7FAs shown, the first pixel connection electrode 231 can be electrically connected to the first region 310-1 of the first active layer 310 of the first transistor T1 of the first pixel circuit through the first via V1, and can also be electrically connected to the first initial signal line INIT1 through the eighth via V8. The second pixel connection electrode 232 can be electrically connected to the second region 310-2 of the first active layer 310 of the first transistor T1 of the first pixel circuit through the second via V2, and can also be electrically connected to the first capacitor plate 381 through the seventh via V7. The third pixel connection electrode 233 can be electrically connected to the first region 340-1 of the fourth active layer 340 of the fourth transistor T4 of the first pixel circuit through the third via V3. The fourth pixel connection electrode 234 can be electrically connected to the first region 350-1 of the fifth active layer 350 of the fifth transistor T5 of the first pixel circuit through the fourth via V4, and can also be electrically connected to the second capacitor plate 382 through the ninth via V9. The fifth pixel connection electrode 235 can be electrically connected to the second region 360-2 of the sixth active layer 360 of the sixth transistor T6 of the first pixel circuit through the fifth via V5. The sixth pixel connection electrode 236 can be electrically connected to the first region 370-1 of the seventh active layer 370 of the seventh transistor T7 of the first pixel circuit through the sixth via V6, and can also be electrically connected to the second initial signal line INIT2 through the tenth via V10.

[0150] In some examples, such as Figure 7E and Figure 7F As shown, the third conductive layer 23 of the surrounding area BB may include: a first connecting electrode 237, a second connecting electrode 238, a plurality of output transition electrodes (e.g., including a first output transition electrode 251 to a ninth output transition electrode 259), a first initial sub-trace 261 and a second initial sub-trace 262.

[0151] In some examples, such as Figures 7D to 7F As shown, the first initial sub-trace 261 and the second initial sub-trace 262 can extend along the second direction D2. In the first direction D1, the first initial sub-trace 261 can be located on the side of the second initial sub-trace 262 closer to the first display area A1. The first initial sub-trace 261 can be electrically connected to the first initial adapter electrode 211 through two vertically arranged eighteenth vias V18. The second initial sub-trace 262 can be electrically connected to the second initial adapter electrode 212 through two vertically arranged twentieth vias V20.

[0152] In some examples, such as Figures 7D to 7FAs shown, the first output transition electrode 251 can be electrically connected to the second scan line (e.g., RST1(n)) through two thirteenth vias V13 arranged side-by-side, and can also be electrically connected to the first scan line (e.g., GL(n-1)) electrically connected to the previous row of pixel circuits. The second output transition electrode 252 can be electrically connected to the first initial signal line INIT1 through two twenty-second vias V22 arranged vertically. The third output transition electrode 253 can be electrically connected to the first scan line (e.g., GL(n)) through two fourteenth vias V14 arranged vertically, and can also be electrically connected to the second scan line (e.g., RST1(n+1)) electrically connected to the next row of pixel circuits through two sixteenth vias V16 arranged side-by-side. The fourth output transition electrode 254 can be electrically connected to the light emission control line (e.g., EML(n)) through two fifteenth vias V15 arranged vertically. The fifth output transition electrode 255 can be electrically connected to the second initial signal line INIT2 through two twenty-fourth vias V24 arranged vertically. The sixth output adapter electrode 256 can be electrically connected to the first initial adapter electrode 211 through two vertically arranged seventeenth vias V17. The seventh output adapter electrode 257 can be electrically connected to the scan output connection line 221 through two vertically arranged twenty-sixth vias V26. The eighth output adapter electrode 258 can be electrically connected to the light emission control output connection line 222 through two vertically arranged twenty-fifth vias V25. The ninth output adapter electrode 259 can be electrically connected to the second initial adapter electrode 212 through two vertically arranged nineteenth vias V19.

[0153] In this disclosure, side-by-side arrangement means arranged along the first direction D1, and vertical arrangement means arranged along the second direction D2.

[0154] In some examples, such as Figures 7D to 7FAs shown, the first connection electrode 237 can be electrically connected to one end of the first electrostatic conduction line 201 through the eleventh via V11, and can also be electrically connected to the first initial signal line INIT1 through the twenty-first via V21. The second connection electrode 238 can be electrically connected to the other end of the first electrostatic conduction line 201 through the twelfth via V12, and can also be electrically connected to the second initial signal line INIT2 through the twenty-third via V23. In this example, the first terminal of the first electrostatic conduction control transistor M1 can be electrically connected to the first initial signal line INIT1, the second terminal can be electrically connected to the first terminal of the second electrostatic conduction control transistor M2, and the second terminal of the second electrostatic conduction control transistor M2 can be electrically connected to the second initial signal line INIT2. When the first electrostatic conduction control transistor M1 and the second electrostatic conduction control transistor M2 are both turned on, the first initial signal line INIT1 and the second initial signal line INIT2 can be connected; when at least one of the first electrostatic conduction control transistor M1 and the second electrostatic conduction control transistor M2 is turned off, the first initial signal line INIT1 and the second initial signal line INIT2 are disconnected.

[0155] In some implementations, before the third conductive layer is fabricated, the long conductive lines of the first and second conductive layers easily accumulate static electricity because there is no way to transfer to other signal traces. When the first and second conductive layers are connected to the active layer of the transistor through the third conductive layer, the static electricity easily dissipates at the resistance change point due to the change in resistance at the channel formed by the active layer, potentially damaging the transistor. In this example, a static electricity dissipation loop is controlled by setting a first static electricity conduction line in the peripheral area and forming a first static electricity conduction control transistor M1 and a second static electricity conduction control transistor M2 with the first scan line and the light emission control line. In some examples, when there is no static electricity accumulation on the first scan line and the light emission control line, both the first static electricity conduction control transistor M1 and the second static electricity conduction control transistor M2 are disconnected, and the first initial signal line INIT1 and the second initial signal line INIT2 are also disconnected. When there is static electricity accumulation on the first scan line and the light emission control line, the first static electricity conduction control transistor M1 and the second static electricity conduction control transistor M2 are turned on, and the first initial signal line INIT1 and the second initial signal line INIT2 are connected, which can form a static electricity dissipation loop. This makes it difficult for static electricity to accumulate at the tip of the initial signal line, but it is consumed in the static electricity dissipation loop. This prevents the static electricity accumulated on the long wires of the second conductive layer from being conducted to the semiconductor layer through the third conductive layer and burning the transistor.

[0156] In this example, the static electricity generated before the fabrication of the fourth conductive layer can be dissipated through the static electricity dissipation loop formed by the first electrostatic conduction control transistor M1 and the second electrostatic conduction control transistor M2. During normal display after the fabrication process is complete, according to the pixel circuit timing, the scan signal provided by the first scan line and the light emission control signal provided by the light emission control line are not simultaneously at a low level. Therefore, the first electrostatic conduction control transistor M1 and the second electrostatic conduction control transistor M2 will not be simultaneously turned on during normal display. During normal display, the first initial signal line INIT1 and the second initial signal line INIT2 will not be connected, thus preventing a short circuit and ensuring normal display functionality.

[0157] (7) Forming the fourth and fifth insulating layers. In some examples, a fourth insulating film is deposited on the substrate 100 on which the aforementioned pattern is formed to form a fourth insulating layer 104; subsequently, a fifth insulating film is coated and patterned by a patterning process to form a fifth insulating layer 105. In some examples, after forming vias or grooves in the fifth insulating layer 105, the fourth insulating layer 104 may be etched to form vias or grooves in the fourth insulating layer 104 to expose the surface of the third conductive layer 23.

[0158] Figure 7G for Figure 5 A schematic diagram of the circuit structure layers after the fifth insulating layer has been formed. In some examples, such as... Figure 7G As shown, the fifth insulating layer 105 of the first display area A1 may have multiple vias, such as the thirty-first via V31 to the thirty-third via V33. The fifth insulating layer 105 and the fourth insulating layer 104 in the thirty-first via V31 are removed, exposing the surface of the third pixel connection electrode 233 located in the third conductive layer 23. The fifth insulating layer 105 and the fourth insulating layer 104 in the thirty-second via V32 are removed, exposing the surface of the fourth pixel connection electrode 234 located in the third conductive layer 23. The fifth insulating layer 105 and the fourth insulating layer 104 in the thirty-third via V33 are removed, exposing the surface of the fifth pixel connection electrode 235 located in the third conductive layer 23.

[0159] In some examples, such as Figure 7GAs shown, the fifth insulating layer 105 of the peripheral region BB can have multiple vias and multiple grooves, for example, it can include the thirty-fourth via V34 to the forty-first via V41 and the first groove V42 and the second groove V43. The fifth insulating layer 105 and the fourth insulating layer 104 in the thirty-fourth via V34 to the forty-first via V41 are removed, exposing the surface of the output transition electrode located in the third conductive layer 23. The fifth insulating layer 105 and the fourth insulating layer 104 in the first groove V42 are removed, exposing the surface of the first initial sub-trace 261 located in the third conductive layer 23. The fifth insulating layer 105 and the fourth insulating layer 104 in the second groove V43 are removed, exposing the surface of the second initial sub-trace 262 located in the third conductive layer 23.

[0160] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate 100 on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer 24.

[0161] In some examples, such as Figure 5 As shown, the fourth conductive layer 24 of the first display area A1 may include: multiple anode connection electrodes (e.g., a first anode connection electrode 241), multiple first power lines 242, and multiple data lines 243. The first power lines 242 and data lines 243 may both extend along the second direction D2 and may be adjacent in the first direction D1. The first anode connection electrode 241 may be electrically connected to the fifth pixel connection electrode 235 through a thirty-third via V33, thereby achieving electrical connection to the second electrode of the sixth transistor of the first pixel circuit. The data lines 243 may be electrically connected to the third pixel connection electrode 233 through a thirty-first via V31, thereby achieving electrical connection to the first electrode of the fourth transistor of the first pixel circuit. The first power lines 242 may be electrically connected to the fourth pixel connection electrode 234 through a thirty-second via V32, thereby achieving electrical connection to the first electrode of the fifth transistor of the first pixel circuit and the second capacitor plate of the storage capacitor. For example, the first power lines 242 may extend along the second direction D2 to the lower frame area and be electrically connected to the peripheral power traces provided in the lower frame area to be configured to transmit a first voltage signal.

[0162] In some examples, such as Figure 5As shown, the fourth conductive layer 24 of the peripheral region BB may include: a third initial sub-trace 263, a fourth initial sub-trace 264, and multiple output adapter lines (e.g., including the first output adapter line 271 to the fourth output adapter line 274). The third initial sub-trace 263 and the fourth initial sub-trace 264 may extend along the second direction D2. In the first direction D1, the third initial sub-trace 263 may be located on the side of the fourth initial sub-trace 264 closer to the first display area A1. The orthographic projection of the third initial sub-trace 263 onto the substrate may overlap with the orthographic projection of the first initial sub-trace 261 onto the substrate. The third initial sub-trace 263 may be electrically connected to the first initial sub-trace 261 through the first groove V42. The orthographic projection of the fourth initial sub-trace 264 onto the substrate may overlap with the orthographic projection of the second initial sub-trace 262 onto the substrate. The fourth initial sub-trace 264 may be electrically connected to the second initial sub-trace 262 through the second groove V43. In this example, the first initial peripheral routing can be a two-layer routing, including a first initial sub-routing 261 and a third initial sub-routing 263; the second initial peripheral routing can be a two-layer routing, including a second initial sub-routing 262 and a fourth initial sub-routing 264.

[0163] In some examples, such as Figure 7F , Figure 7G and Figure 5 As shown, the first output adapter cable 271 can be electrically connected to the second output adapter electrode 252 through the thirty-fourth via V34, and can also be electrically connected to the sixth output adapter electrode 256 through the thirty-eighth via V38, thereby realizing the electrical connection between the first initial signal line INIT1 and the first initial peripheral trace. The second output adapter cable 272 can be electrically connected to the third output adapter electrode 253 through the thirty-fifth via V35, and can also be electrically connected to the seventh output adapter electrode 257 through the thirty-ninth via V39, thereby realizing the electrical connection between the scan output line and the first scan line (e.g., GL(n)) and the second scan line (e.g., RST1(n+1)). The third output adapter cable 273 can be electrically connected to the fourth output adapter electrode 254 through the thirty-sixth via V36, and can also be electrically connected to the eighth output adapter electrode 258 through the fortieth via V40, thereby realizing the electrical connection between the light emission control output line and the light emission control line (e.g., EML(n)). The fourth output adapter cable 274 can be electrically connected to the fifth output adapter electrode 255 through the thirty-seventh via V37, and can also be electrically connected to the ninth output adapter electrode 259 through the forty-first via V41, thereby realizing the electrical connection between the second initial signal line INIT2 and the second initial peripheral trace. However, this embodiment is not limited to this. In other examples, the first output adapter cable to the fourth output adapter cable can be disposed on the third conductive layer.

[0164] At this point, the circuit structure layer of the display substrate is complete. The second display area A2 may include a substrate 100 and a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, and a fifth insulating layer 105 stacked on the substrate 100. In some examples, the film structure of the second pixel circuit and the invalid pixel circuit of the second circuit area A12 of the first display area A1 may be similar to the film structure of the first pixel circuit, and therefore will not be described further here.

[0165] (9) At least one transparent conductive layer and a light-emitting structure layer are formed in sequence. The light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode layer.

[0166] In some exemplary embodiments, a transparent conductive layer is used as an example. A first planarization film is coated on a substrate with the aforementioned pattern, and the first planarization film is patterned using a patterning process to form a first planarization layer. A transparent conductive film is deposited on the substrate with the aforementioned pattern, and the transparent conductive film is patterned using a patterning process to form a transparent conductive layer. The transparent conductive layer may include multiple transparent conductive lines electrically connecting a second pixel circuit of a first display area and a second light-emitting element of a second display area. Subsequently, a second planarization film is coated on the substrate with the aforementioned pattern, and the second planarization film is patterned using a patterning process to form a second planarization layer. Subsequently, an anode film is deposited on the substrate with the aforementioned pattern, and the anode film is patterned using a patterning process to form an anode layer. Subsequently, a pixel definition film is coated on the substrate with the aforementioned pattern, and a pixel definition layer is formed using a masking, exposure, and development process. The pixel definition layer has multiple pixel openings exposing the anode layer. Subsequently, an organic light-emitting layer is formed within the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode thin film is deposited, and the cathode thin film is patterned using a patterning process to form a cathode layer. The cathode layer is electrically connected to the organic light-emitting layer and the second power line. In some examples, an encapsulation structure layer is formed on the cathode layer, which may include a stacked structure of inorganic / organic / inorganic materials. In other examples, multiple transparent conductive layers (e.g., three transparent conductive layers) may be provided, and multiple transparent conductive lines may be arranged in the multiple transparent conductive layers. At least one planarization layer may be provided between adjacent transparent conductive layers.

[0167] In some exemplary embodiments, the first conductive layer 21, the second conductive layer 22, the third conductive layer 23, and the fourth conductive layer 24 can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The first insulating layer 101 and the second insulating layer 102 can be referred to as gate insulating (GI) layers, the third insulating layer 103 can be referred to as interlayer insulating (ILD) layers, and the fourth insulating layer 104 can be referred to as passivation layers. The fifth insulating layer 105, the first planarization layer, and the second planarization layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer can be made of reflective materials such as metal, and the cathode layer can be made of transparent conductive materials. However, this embodiment is not limited in this respect.

[0168] The structure and fabrication process of the display substrate in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with existing fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0169] The display substrate provided in this embodiment has a first electrostatic conduction line in the peripheral area, and the first electrostatic conduction line is located in the semiconductor layer, requiring no additional fabrication steps. The first electrostatic conduction line can cooperate with the first scan line and the light-emitting control line to form an electrostatic conduction control transistor, without occupying the original wiring space of the display substrate. It can utilize the original wiring to form an electrostatic dissipation loop, and electrostatic dissipation only occurs when static electricity is present. This can reduce the incidence of electrostatic discharge defects in the display area, improve the product yield of the display substrate, and not affect the normal display of the display substrate.

[0170] Figure 8A for Figure 1 Another enlarged schematic diagram of the circuit structure layer in the middle region CC. Figure 8B for Figure 8A A schematic diagram of the circuit structure layer after the semiconductor layer is formed. Figure 8C for Figure 8A A schematic diagram of the circuit structure layers after the first conductive layer is formed. Figure 8D for Figure 8A A schematic diagram of the circuit structure layer after the formation of the second conductive layer. Figure 8E for Figure 8A A schematic diagram of the circuit structure layer after the formation of the third insulating layer. Figure 8F for Figure 8A A schematic diagram of the circuit structure layer after the formation of the third conductive layer.

[0171] In some examples, such as Figure 8A and Figure 8B As shown, the semiconductor layer 20 of the peripheral region BB may include at least a second electrostatic conduction line 202 and a third electrostatic conduction line 203. Both the second electrostatic conduction line 202 and the third electrostatic conduction line 203 extend along the second direction D2. In the first direction D1, the second electrostatic conduction line 202 is located on the side of the third electrostatic conduction line 203 away from the first display area A1.

[0172] In some examples, such as Figure 8CAs shown, the ends of the first scan line, the second scan line, and the light-emitting control line can extend to the peripheral region BB. The orthographic projection of the second electrostatic conduction line 202 onto the substrate can overlap with the orthographic projections of at least one first scan line, at least one second scan line, and at least one light-emitting control line onto the substrate. The orthographic projection of the third electrostatic conduction line 203 onto the substrate can overlap with the orthographic projections of at least one first scan line, at least one second scan line, and at least one light-emitting control line onto the substrate. The overlapping region of the second electrostatic conduction line 202 and the orthographic projection of a second scan line (e.g., RST1(n)) onto the substrate can serve as the channel region of the third electrostatic conduction control transistor M3, and the overlapping region of the second scan line and the second electrostatic conduction line 202 can serve as the gate of the third electrostatic conduction control transistor M3. The overlapping region of the second electrostatic conduction line 202 and the orthographic projection of a first scan line (e.g., GL(n)) onto the substrate can serve as the channel region of the fourth electrostatic conduction control transistor M4, and the overlapping region of the first scan line and the second electrostatic conduction line 202 can serve as the gate of the fourth electrostatic conduction control transistor M4. The overlapping region of the second electrostatic conduction line 202 and a light-emitting control line (e.g., EML(n)) projected onto the substrate can serve as the channel region of the fifth electrostatic conduction control transistor M5, and the overlapping region of the light-emitting control line and the second electrostatic conduction line 202 can serve as the gate of the fifth electrostatic conduction control transistor M5. Similarly, the third electrostatic conduction line 203 can overlap with a second scan line (e.g., RST1(n)) to form the channel region of the sixth electrostatic conduction control transistor M6; the third electrostatic conduction line 203 can overlap with a first scan line (e.g., GL(n)) to form the channel region of the seventh electrostatic conduction control transistor M7; and the third electrostatic conduction line 203 can overlap with a light-emitting control line (e.g., EML(n)) to form the channel region of the eighth electrostatic conduction control transistor M8.

[0173] In some examples, such as Figure 8D As shown, the first initial signal line INIT1 and the second initial signal line INIT2 located in the second conductive layer can extend to the surrounding area BB. The orthographic projection of the second electrostatic conduction line 202 on the substrate may overlap with the orthographic projections of the first initial signal line INIT1 and the second initial signal line INIT2 on the substrate, and the orthographic projection of the third electrostatic conduction line 203 on the substrate may overlap with the orthographic projections of the first initial signal line INIT1 and the second initial signal line INIT2 on the substrate.

[0174] In some examples, such as Figure 8EAs shown, the third insulating layer of the peripheral region BB can have multiple vias, for example, it can include vias 27 to 29 V29. The third, second, and first insulating layers within the 27th via V27 are removed, exposing the surface of the third electrostatic conductive line 203 located in the semiconductor layer 20. The third, second, and first insulating layers within the 28th via V28 are removed, exposing the surface of the second electrostatic conductive line 202 located in the semiconductor layer 20. The third insulating layer within the 29th via V29 is removed, exposing the surface of the first initial signal line INIT1 located in the second conductive layer 22.

[0175] In some examples, such as Figure 8E and Figure 8F As shown, the third conductive layer of the peripheral region BB may include a third connecting electrode 239 and a fourth connecting electrode 240. The third connecting electrode 239 can be electrically connected to the second electrostatic conduction line 202 through the twenty-eighth via V28, and can also be electrically connected to the first initial signal line INIT1 through the twenty-ninth via V29. In this example, at least two first initial signal lines INIT1 can be electrically connected to the second electrostatic conduction line 202. The second electrostatic conduction line 202 connecting two adjacent first initial signal lines INIT1 can form three electrostatic conduction control transistors (i.e., M3 to M5). During the fabrication of the display substrate, the same static electricity accumulates on the first scan line (e.g., GL(n)), the second scan line (e.g., RST1(n)), and the light emission control line (e.g., EML(n)), so that when the third electrostatic conduction control transistor M3 to the fifth electrostatic conduction control transistor M5 are simultaneously turned on, at least two second initial signal lines can be connected, thereby forming an electrostatic dissipation loop to dissipate static electricity. During normal display, due to the differences in signals transmitted by the first scan line, the second scan line, and the light-emitting control line, the third electrostatic conduction control transistor M3 to the fifth electrostatic conduction control transistor M5 will not be turned on simultaneously. Therefore, at least two first initial signal lines will not be connected. In addition, multiple first initial signal lines INIT1 transmit the same signal, and even if they are connected to each other, it will not affect the display.

[0176] In some examples, such as Figure 8E and Figure 8FAs shown, the sixth pixel connection electrode 236 of the third conductive layer of the first display area A1 can be electrically connected to the first region of the seventh active layer of the seventh transistor through the sixth via V6, and can also be electrically connected to the second initial signal line INIT2 through the tenth via V10. The fourth connection electrode 240 can be electrically connected to the third electrostatic conduction line 203 through the twenty-seventh via V27. The sixth pixel connection electrode 236 and the fourth connection electrode 240 can be an integral structure. In this example, at least two second initial signal lines INIT2 can be electrically connected to the third electrostatic conduction line 203. The third electrostatic conduction line 203 connecting two adjacent second initial signal lines INIT2 forms three electrostatic conduction control transistors (i.e., M6 to M8). During the fabrication of the display substrate, the same static electricity accumulates on the first scan line (e.g., GL(n)), the second scan line (e.g., RST1(n)), and the light-emitting control line (e.g., EML(n)). This allows at least two second initial signal lines to be connected when the sixth to eighth static conduction control transistors M6 to M8 are simultaneously turned on, thus forming a static electricity dissipation loop to dissipate the static electricity. During normal display, due to the differences in signals transmitted by the first scan line, the second scan line, and the light-emitting control line, the sixth to eighth static conduction control transistors M6 to M8 will not be turned on simultaneously, therefore at least two second initial signal lines will not be connected. Furthermore, multiple second initial signal lines INIT2 transmit the same signal, and even if they are interconnected, it will not affect the display.

[0177] The remaining film layer structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0178] Figure 9A for Figure 1 Another enlarged schematic diagram of the circuit structure layer in the middle region CC. Figure 9B for Figure 9A A schematic diagram of the circuit structure layer after the formation of the third conductive layer. Figure 9C for Figure 9B A schematic diagram of the third conductive layer.

[0179] In some examples, such as Figures 9A to 9CAs shown, the third conductive layer of the surrounding area BB may include a fourth electrostatic conductive line 204 and a fifth electrostatic conductive line 205. The fourth electrostatic conductive line 204 and the fifth electrostatic conductive line 205 may extend along the second direction D2, and the fifth electrostatic conductive line 205 may be located on the side of the fourth electrostatic conductive line 204 closer to the first display area A1 in the first direction D1. One fourth electrostatic conductive line 204 may connect to an adjacent second output transition electrode 252, thereby achieving an electrical connection to an adjacent first initial signal line INIT1. Multiple fourth electrostatic conductive lines 204 and multiple second output transition electrodes 252 may be an integral structure. One fifth electrostatic conductive line 205 may connect to an adjacent sixth pixel connection electrode 236, thereby achieving an electrical connection to an adjacent second initial signal line INIT2. Multiple fifth electrostatic conductive lines 205 and multiple sixth pixel connection electrodes 236 may be an integral structure.

[0180] In this example, at least two first initial signal lines INIT1 can be electrically connected via the fourth electrostatic conduction line 204 to form an electrostatic dissipation loop; at least two second initial signal lines INIT2 can be electrically connected via the fifth electrostatic conduction line 205 to form an electrostatic dissipation loop. In this way, the static electricity accumulated on the first and second initial signal lines will not accumulate at the trace tips, but can be dissipated through the electrostatic dissipation loop, thereby dissipating the static electricity generated during the manufacturing process and effectively reducing the ESD risk in the display area.

[0181] The remaining film layer structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0182] In other examples, the above embodiments can be combined with each other. For example, at least two of the first to fifth electrostatic conductive lines can be provided in the peripheral area of ​​the display substrate. For instance, the first electrostatic conductive line can be provided in the left frame area of ​​the display substrate, and the second and third electrostatic conductive lines can be provided in the right frame area; or, the second and third electrostatic conductive lines can be provided in the left frame area, and the fourth and fifth electrostatic conductive lines can be provided in the right frame area. However, this embodiment is not limited in this respect.

[0183] Figure 10 This is a partial cross-sectional schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, such as Figure 10As shown, in a direction perpendicular to the display substrate, the first display area A1 may include: a substrate 100, and a circuit structure layer 200, three transparent conductive layers (e.g., a first transparent conductive layer 31, a second transparent conductive layer 32, and a third transparent conductive layer 33), a light-emitting structure layer 400, and an encapsulation structure layer 500 sequentially disposed on the substrate 100. The circuit structure layer 200 may include a semiconductor layer 20, a first insulating layer 101, a first conductive layer 21, a second insulating layer 102, a second conductive layer 22, a third insulating layer 103, a third conductive layer 23, a fourth insulating layer 104, a fifth insulating layer 105, and a fourth conductive layer 24 sequentially disposed on the substrate 100. A sixth insulating layer 106 is disposed between the first transparent conductive layer 31 and the circuit structure layer 200, a seventh insulating layer 107 is disposed between the first transparent conductive layer 31 and the second transparent conductive layer 32, and an eighth insulating layer 108 is disposed between the second transparent conductive layer 32 and the third transparent conductive layer 33. A ninth insulating layer 109 is disposed between the third transparent conductive layer 33 and the light-emitting structure layer 400. The second display area A2 may include: a substrate 100, and a first insulating layer 101 to a sixth insulating layer 106, a first transparent conductive layer 31, a seventh insulating layer 107, a second transparent conductive layer 32, an eighth insulating layer 108, a third transparent conductive layer 33, a ninth insulating layer 109, a light-emitting structure layer 400, and an encapsulation structure layer 500 sequentially disposed on the substrate 100. In some examples, the first insulating layer 101 to the fourth insulating layer 104 may be inorganic insulating layers, and the fifth insulating layer 105 to the ninth insulating layer 109 may be organic insulating layers, for example, they may be called planarization layers.

[0184] In some examples, the first transparent conductive layer 31 may include a second anode connection electrode located in the first display area A1 and multiple first conductive lines. The first conductive lines can extend from the first display area A1 to the second display area A2 to electrically connect to the second pixel circuit and the second light-emitting element. The second anode connection electrode in the first display area A1 can be electrically connected to the first anode connection electrode of the fourth conductive layer. The second transparent conductive layer 32 may include multiple third anode connection electrodes and multiple second conductive lines. The third anode connection electrode in the first display area A1 can be electrically connected to the second anode connection electrode. The third anode connection electrode in the second display area A2 can be electrically connected to the first conductive lines. The third transparent conductive layer 33 may include multiple fourth anode connection electrodes and multiple third conductive lines. The fourth anode connection electrode in the first display area A1 can be electrically connected to the third anode connection electrode. The fourth anode connection electrode in the second display area A2 can be electrically connected to the second conductive lines. The light-emitting structure layer 400 may include: an anode layer 41 (e.g., the anode 41a of the first light-emitting element and the anode 41b of the second light-emitting element), an organic light-emitting layer 42 (e.g., the organic light-emitting layer 42a of the first light-emitting element and the organic light-emitting layer 42b of the second light-emitting element), a cathode layer 43, and a pixel definition layer 44. The anode 41a of the first light-emitting element may be electrically connected to the fourth anode connection electrode of the third transparent conductive layer 33. The anode 41b of the second light-emitting element may be electrically connected to the third conductive line of the third transparent conductive layer 33 or the fourth anode connection electrode of the second display area A2.

[0185] In some examples, such as Figure 10 As shown, since the second display area A2 is a light-transmitting area, all areas within the second display area A2 except for the anode layer are translucent. Furthermore, the anode layer has a flat surface. The second display area A2 emits both self-emissive light and external light (such as...) Figure 10 (As shown by the dashed line) After refraction and reflection, the light reaches the interface between substrate 100 and air. At the interface between substrate 100 and air, total internal reflection occurs, and the totally internalized light (such as...) Figure 10 (As shown by the dashed line) will reach the first display area A1, causing some sub-pixels in the first display area A1 to experience light leakage, which causes the corresponding sub-pixels to darken, forming a progressive dark ring.

[0186] In some exemplary embodiments, the anode of the second light-emitting element may have a bottom and sidewalls extending from the bottom toward the side away from the substrate. In this example, the anode of the second light-emitting element may be groove-shaped, thereby reflecting the emitted light from the second light-emitting element through the sidewalls of the anode, reducing refracted light toward the non-display side, and improving the progressive dark ring problem. The shape of the anode of the first light-emitting element may be similar to that of the anode of the second light-emitting element, or the anode of the first light-emitting element may have a flat surface. This embodiment is not limited in this respect.

[0187] In some exemplary embodiments, at least one first organic insulating layer located between the light-emitting structure layer and the circuit structure layer may have at least one first anode groove. The orthogonal projection of the anode of the second light-emitting element onto the substrate may cover the orthogonal projection of the first anode groove of the first organic insulating layer onto the substrate. The pixel defining layer may be located on the side of the anode layer away from the substrate and has pixel openings that expose the surface of the anode of the second light-emitting element. The orthogonal projection of the first anode groove of the first organic insulating layer onto the substrate covers the orthogonal projection of the pixel openings onto the substrate. In some examples, the first organic insulating layer may include at least one of a fifth to a ninth insulating layer. In this example, the first anode groove formed by the first organic insulating layer may be used to give the anode of the second light-emitting element a groove shape.

[0188] The following explanation uses the example of the first organic insulating layer being the ninth insulating layer. Figure 11A This is a partial top view of a display substrate according to at least one embodiment of the present disclosure. Figure 11B for Figure 11A A schematic diagram of the display substrate after the ninth insulating layer has been formed. Figure 11C for Figure 11A A schematic diagram of the display substrate after the anode layer has been formed. Figure 12 for Figure 11A A partial cross-sectional view along the P-P' direction.

[0189] In some examples, such as Figure 11A As shown, the first light-emitting elements of the first display area A1 may include: a first light-emitting element 11a emitting a first color light, a first light-emitting element 11b emitting a second color light, and first light-emitting elements 11c and 11d emitting a third color light. The first light-emitting elements 11a and 11b emitting the first color light can be arranged in a row along a first direction D1, and in a column along a second direction D2. The first light-emitting elements 11c and 11d emitting the third color light can be arranged in a row along the first direction D1, and in a column along the second direction D2. A row of first light-emitting elements 11c and 11d emitting the third color light is located between the two rows of first light-emitting elements 11a and 11b emitting the first color light in the second direction D2. A column of first light-emitting elements 11c and 11d emitting the third color light is located between the two columns of first light-emitting elements 11a and 11b emitting the first color light in the first direction D2. In some examples, the light-emitting areas of the first light-emitting elements 11a, 11b, 11c, and 11d can be rectangles of different sizes, such as rounded rectangles. In some examples, the first color light can be blue light, the second color light can be red light, and the third color light can be green light. However, this embodiment is not limited in this respect.

[0190] In some examples, such as Figure 11A As shown, the second light-emitting element of the second display area A2 may include: a second light-emitting element 12a emitting a first color light, a second light-emitting element 12b emitting a second color light, and second light-emitting elements 12c and 12d emitting a third color light. The arrangement of the second light-emitting elements is the same as that of the first light-emitting elements, and therefore will not be described again here. The light-emitting areas of the second light-emitting elements 12a, 12c, and 12d can be circular or elliptical of different sizes, and the light-emitting area of ​​the second light-emitting element 12b can be teardrop-shaped. However, this embodiment is not limited in this respect.

[0191] In some examples, a first light-emitting element 11a emitting light of the first color and a second light-emitting element 12a emitting light of the first color will be used as examples for illustration. Figure 11B and Figure 12 As shown, the ninth insulating layer 109 of the first display area A1 may have a first anode via K1. The ninth insulating layer 109 within the first anode via K1 can be removed, exposing the fourth anode connection electrode. The ninth insulating layer 109 of the second display area A2 may have a second anode via K2 and a first anode groove K3. The second anode via K2 and the first anode groove K3 corresponding to the second light-emitting element 12a emitting the first color light can be connected. The second anode via and the first anode groove corresponding to the second light-emitting element emitting the third color light may not be connected. The ninth insulating layer 109 within the second anode via K2 can be removed, exposing the surface of the third transparent conductive layer. The ninth insulating layer 109 within the first anode groove K3 can be completely removed, exposing the surface of the eighth insulating layer 108, or it can be partially removed. The bottom surface of the first anode groove K3 can be a flat surface, so that the anode formed within the first anode groove K3 can remain flat. However, this embodiment is not limited in this respect.

[0192] In some examples, the angle between the side of the first anode recess K3 and the plane of the substrate is α. For example, α can be greater than or equal to 30 degrees. By increasing the value of α, light reflection can be increased, and the amount of light reaching the non-display side of the display substrate can be minimized.

[0193] In some examples, such as Figure 11CAs shown, the anode layer of the first display area A1 may include at least the anode 111 of the first light-emitting element 11a. The anode 111 of the first light-emitting element 11a can be electrically connected to the fourth anode connection electrode of the third transparent conductive layer through the first anode via K1. The anode layer of the second display area A2 may include at least the anode 121 of the second light-emitting element 12a. The anode 121 of the second light-emitting element 12a can be electrically connected to the fourth anode connection electrode or the third transparent conductive line located in the third transparent conductive layer through the second anode via K2. The orthogonal projection of the anode 121 of the second light-emitting element 12a onto the substrate can cover the orthogonal projections of the second anode via K2 and the first anode groove K3 onto the substrate.

[0194] In some examples, such as Figure 11A As shown, the pixel definition layer of the first display area A1 has a first pixel opening OP1. The pixel definition layer within the first pixel opening OP1 is removed, exposing the surface of the anode 111. The pixel definition layer of the second display area A2 has a second pixel opening OP2. The pixel definition layer within the second pixel opening OP2 is removed, exposing the surface of the anode 121. The orthographic projection of the second pixel opening OP2 onto the substrate can be located within the orthographic projection range of the first anode groove K3 onto the substrate.

[0195] In some examples, such as Figure 12 As shown, the anode 121 of the second light-emitting element 12a can be formed into a groove shape, so that the light emitted from the second light-emitting element 12a will not be refracted to the substrate of the display substrate after encountering the side wall of the anode 121, but will be reflected to the display side, thereby avoiding affecting the transistor characteristics of the circuit structure layer of the first display area and improving the progressive dark ring.

[0196] The display substrate in this example requires no additional processing steps, thus not increasing costs. Furthermore, by creating a groove in the first organic insulating layer below the anode, the overall transmittance of the second display area is not affected, nor is normal light transmission impeded. While reducing light propagation on the non-display side, the light emission on the display side can be increased, thereby increasing the luminous efficiency and brightness of the second display area.

[0197] Figure 13 This is another partial cross-sectional schematic diagram of the second display area according to at least one embodiment of the present disclosure. In some examples, such as Figure 13As shown, the anode layer of the light-emitting structure layer is located on the side of the pixel definition layer 44 away from the substrate 100. For example, the anode 121 of the second light-emitting element 12a can be located within the pixel opening formed by the pixel definition layer 44, and the orthographic projection of the anode 121 of the second light-emitting element 12a onto the substrate 100 can cover the orthographic projection of the pixel opening onto the substrate 100, so that the anode 121 can have a groove shape. The sidewall of the anode 121 covering the side of the pixel opening can serve as a reflective layer to reflect the light emitted from the second light-emitting element 12a, so that the emitted light is reflected to the display side and is not refracted to the non-display side, thereby improving the progressive dark ring. While reducing the light propagation on the non-display side, the amount of light emitted on the display side can be increased, thereby increasing the luminous efficiency and brightness of the second display area. The remaining structure of the display substrate of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0198] Figure 14A This is a partial top view of a display substrate according to at least one embodiment of the present disclosure. Figure 14B for Figure 14A A schematic diagram of the display substrate after the ninth insulating layer has been formed. Figure 14C for Figure 14A A schematic diagram of the display substrate after the anode layer has been formed. In this example, the first organic insulating layer can be the ninth insulating layer.

[0199] In some examples, a first light-emitting element 11a emitting light of the first color and a second light-emitting element 12a emitting light of the first color will be used as examples for illustration. Figure 14B As shown, the ninth insulating layer of the first display area A1 may have a first anode via K1. The ninth insulating layer within the first anode via K1 can be removed, exposing the fourth anode connection electrode. The ninth insulating layer of the second display area A2 may have a second anode via K2 and an annular groove K4. The second anode via K2 and the annular groove K4 corresponding to the second light-emitting element may not be connected. The ninth insulating layer within the second anode via K2 may be removed, exposing the surface of the third transparent conductive layer. The ninth insulating layer within the annular groove K4 may be completely removed, exposing the surface of the eighth insulating layer, or it may be partially removed.

[0200] In some examples, the ninth insulating layer of the second display area A2 may also have multiple auxiliary holes K5. These auxiliary holes K5 may be located within the annular groove K4. For example, the multiple auxiliary holes K5 may be evenly distributed within the annular groove K4. This example does not limit the number of auxiliary holes K5 within the annular groove K4.

[0201] In some examples, such as Figure 14CAs shown, the anode layer of the first display area A1 may include at least the anode 111 of the first light-emitting element 11a. The anode 111 of the first light-emitting element 11a can be electrically connected to the fourth anode connection electrode of the third transparent conductive layer through the first anode via K1. The anode layer of the second display area A2 may include at least the anode 121 of the second light-emitting element 12a. The anode 121 of the second light-emitting element 12a can be electrically connected to the fourth anode connection electrode or the third transparent conductive line located in the third transparent conductive layer through the second anode via K2. The orthogonal projection of the anode 121 of the second light-emitting element 12a onto the substrate can cover the orthogonal projection of the second anode via K2, the annular groove K4, and the plurality of auxiliary holes K5 located in the annular groove K4 onto the substrate.

[0202] In some examples, such as Figure 14A As shown, the pixel definition layer of the first display area A1 has a first pixel opening OP1. The pixel definition layer within the first pixel opening OP1 is removed, exposing the surface of the anode 111. The pixel definition layer of the second display area A2 has a second pixel opening OP2. The pixel definition layer within the second pixel opening OP2 is removed, exposing the surface of the anode 121. The orthographic projection of the second pixel opening OP2 onto the substrate may overlap with the orthographic projection of the annular groove K4 onto the substrate. The orthographic projection of the second pixel opening OP2 onto the substrate may cover the orthographic projections of the multiple auxiliary holes K5 within the annular groove K4 onto the substrate.

[0203] This example demonstrates how setting an annular groove and auxiliary holes in the ninth insulating layer of the second display area can reduce the refraction of light emitted by the second light-emitting element by the ninth insulating layer, which is beneficial for the light emitted by the second light-emitting element to exit from the display side, thereby improving the luminous efficiency and brightness of the second display area.

[0204] The remaining film layer structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0205] At least one embodiment of this disclosure also provides a display device, including the display substrate described above.

[0206] Figure 15 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 15 As shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 is located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 overlaps with the second display area A2.

[0207] In some exemplary embodiments, the display substrate 91 can be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device can be a product with image (including still images or moving images, where the moving images can be video) display capabilities. For example, the display device can be any of the following products: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, drawing screen, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc. Furthermore, the display device can also be any of the following products: microdisplay, VR device or AR device containing a microdisplay, etc.

[0208] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of the technical solutions of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, characterized in that, include: The substrate includes a display area and a peripheral area located around the display area; The display area includes: a first display area and a second display area, wherein the first display area at least partially surrounds the second display area; A circuit structure layer, located on the substrate, includes: multiple pixel circuits, multiple initial signal lines, and at least one electrostatic conduction line. The multiple initial signal lines are electrically connected to the multiple pixel circuits and extend along a first direction, and the at least one electrostatic conduction line extends along a second direction, wherein the first direction and the second direction intersect. The multiple pixel circuits are located in the first display area, and the multiple initial signal lines are located at least in the first display area. The at least one electrostatic conduction line is electrically connected to at least two initial signal lines. Multiple pixel circuits arranged along the first direction constitute a row of pixel circuits; The circuit structure layer further includes: a plurality of first signal lines, the plurality of first signal lines extending along the first direction and electrically connected to the row of pixel circuits; the orthographic projection of the at least one electrostatic conduction line on the substrate overlaps with the orthographic projection of the plurality of first signal lines on the substrate; In a direction perpendicular to the display substrate, the circuit structure layer of the first display area includes at least: a semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on the substrate; the semiconductor layer includes the active layer of the transistors of the plurality of pixel circuits; the first conductive layer includes the gate of the transistors of the plurality of pixel circuits and the first capacitor plate of the storage capacitor of the plurality of pixel circuits; the second conductive layer includes the second capacitor plate of the storage capacitor of the plurality of pixel circuits. The at least one electrostatic conduction line is located in the semiconductor layer, the plurality of initial signal lines are located in the second conductive layer, and the at least two first signal lines are located in the first conductive layer.

2. The display substrate according to claim 1, characterized in that, The at least one electrostatic conduction line is located on the side of the plurality of first signal lines close to the substrate, and the plurality of first signal lines are located on the side of the plurality of initial signal lines close to the substrate.

3. The display substrate according to claim 1, characterized in that, The plurality of initial signal lines include: at least one first initial signal line and at least one second initial signal line; The at least one electrostatic conduction line includes: at least one first electrostatic conduction line; The first initial signal line and the second initial signal line, which are electrically connected to the same row of pixel circuits, are electrically connected to the same first electrostatic conduction line.

4. The display substrate according to claim 3, characterized in that, The first electrostatic conduction line is located on the side of the first initial signal line and the second initial signal line that is closer to the substrate; One end of the first electrostatic conduction line is electrically connected to the first initial signal line through a first connecting electrode, and the other end is electrically connected to the second initial signal line through a second connecting electrode; the first connecting electrode and the second connecting electrode are of the same layer structure and are located on the side of the first initial signal line and the second initial signal line away from the substrate.

5. The display substrate according to claim 3, characterized in that, The orthographic projection of the first electrostatic conduction line on the substrate overlaps with the orthographic projection of the two first signal lines on the substrate. The two first signal lines include a first scan line and a light emission control line electrically connected to the same row of pixel circuits.

6. The display substrate according to claim 1, characterized in that, The plurality of initial signal lines include: a plurality of first initial signal lines and a plurality of second initial signal lines; The at least one electrostatic conduction line includes: a second electrostatic conduction line and a third electrostatic conduction line; The second electrostatic conduction line is electrically connected to the plurality of first initial signal lines, and the third electrostatic conduction line is electrically connected to the plurality of second initial signal lines.

7. The display substrate according to claim 6, characterized in that, The second electrostatic conduction line and the third electrostatic conduction line are in the same layer and are located on the side of the first initial signal line and the second initial signal line that are closer to the substrate; The second electrostatic conduction line is electrically connected to the first initial signal line through a third connecting electrode, and the third electrostatic conduction line is electrically connected to the second initial signal line through a fourth connecting electrode; the third connecting electrode and the fourth connecting electrode are of the same layer structure and are located on the side of the first initial signal line and the second initial signal line away from the substrate.

8. The display substrate according to claim 6, characterized in that, The orthographic projection of the second electrostatic conduction line connecting two adjacent first initial signal lines on the substrate overlaps with the orthographic projection of the three first signal lines on the substrate. The orthographic projection of the third electrostatic conduction line connecting two adjacent second initial signal lines on the substrate overlaps with the orthographic projection of the three first signal lines on the substrate.

9. The display substrate according to claim 1, characterized in that, The at least one electrostatic conductive line is located on the side of the plurality of initial signal lines away from the substrate.

10. The display substrate according to any one of claims 1 to 9, characterized in that, The at least one electrostatic conduction line is located in the surrounding area.

11. The display substrate according to any one of claims 1 to 9, characterized in that, The display substrate further includes: a light-emitting structure layer located on the side of the circuit structure layer away from the substrate; the light-emitting structure layer includes: a plurality of first light-emitting elements located in the first display area and a plurality of second light-emitting elements located in the second display area; the plurality of pixel circuits include: a plurality of first pixel circuits and a plurality of second pixel circuits; at least one of the plurality of first pixel circuits is electrically connected to at least one of the plurality of first light-emitting elements, and at least one of the plurality of second pixel circuits is electrically connected to at least one of the plurality of second light-emitting elements.

12. The display substrate according to claim 11, characterized in that, The light-emitting structure layer includes an anode layer, and the anode layer of the second display area includes an anode of a second light-emitting element; the anode of the second light-emitting element has a bottom and a sidewall extending from the bottom toward the side away from the substrate.

13. The display substrate according to claim 12, characterized in that, The display substrate further includes: at least one first organic insulating layer located between the light-emitting structure layer and the circuit structure layer, wherein the first organic insulating layer of the second display area has at least one first anode groove; The orthogonal projection of the anode of the second light-emitting element onto the substrate covers the orthogonal projection of the first anode groove of the first organic insulating layer onto the substrate; The light-emitting structure layer further includes: a pixel definition layer located on the side of the anode layer away from the substrate, wherein the pixel definition layer has pixel openings that expose the surface of the anode of the second light-emitting element; The first anode groove of the first organic insulating layer, in its orthogonal projection onto the substrate, covers the orthogonal projection of the pixel opening onto the substrate.

14. The display substrate according to claim 12, characterized in that, The light-emitting structure layer further includes: a pixel definition layer, wherein at least a portion of the anode layer is located on the side of the pixel definition layer away from the substrate; the pixel definition layer has a pixel opening, and the orthogonal projection of the anode of the second light-emitting element onto the substrate covers the orthogonal projection of the pixel opening onto the substrate.

15. The display substrate according to claim 12, characterized in that, The display substrate further includes: a first organic insulating layer located on the side of the anode layer near the substrate and in contact with the anode layer, wherein the first organic insulating layer has at least one annular groove in the second display area; The orthogonal projection of the anode of the second light-emitting element onto the substrate covers the orthogonal projection of the annular groove of the first organic insulating layer onto the substrate.

16. The display substrate according to claim 15, characterized in that, The first organic insulating layer also has a plurality of auxiliary holes located within the annular groove, and the orthographic projection of the anode of the second light-emitting element onto the substrate covers the orthographic projection of the plurality of auxiliary holes within the annular groove onto the substrate.

17. A display device, characterized in that, include: The display substrate as described in any one of claims 1 to 16.

18. The display device according to claim 17, characterized in that, The display device further includes a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor on the display substrate overlaps with the second display area of ​​the display substrate.

Images