Display substrate, method for preparing same, and display device

Abstract

The present disclosure provides a display substrate, a method for manufacturing the same, and a display device, belonging to the field of display technology. The display substrate has an island region, a via region, and a bridge region; the display substrate includes a substrate, and a circuit layer disposed on the substrate; the circuit layer includes a driving circuit located in the island region and a via located in the via region; the circuit layer further includes at least one photoelectric sensor electrically connected to the driving circuit; the photoelectric sensor includes a first electrode layer, a photoelectric structure layer, and a second electrode layer stacked; the photoelectric sensor is located in the island region, and the first electrode layer, the photoelectric structure layer, and the second electrode layer of the photoelectric sensor are sequentially disposed along the direction from the island region to the bridge region; and / or, the photoelectric sensor is located in the bridge region, and the first electrode layer, the photoelectric structure layer, and the second electrode layer of the photoelectric sensor are sequentially disposed along the direction from the bridge region to the island region.

Description

Technical Field

[0001] The present disclosure relates to the technical field of displays, and particularly to a display substrate, a preparation method thereof, and a display device. Background Art

[0002] An Organic-Photo-Diode (OPD) is integrated in a display device, and the OPD is used to detect the light change in the application environment to determine the current state of the display device. Taking "electronic skin" as an example, the OPD detects the light change when the display device is stretched, determines the stretching state of the display device, and further determines the change state of the human skin. However, the traditional integration method of the OPD occupies a relatively large display area and aperture ratio of the display device, thereby reducing the overall resolution of the display device. Summary of the Invention

[0003] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a display substrate, a preparation method thereof, and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a display substrate, which has an island region, a hole region, and a bridge region; the display substrate includes a substrate, and a circuit layer disposed on the substrate;

[0005] The circuit layer includes a driving circuit located in the island region, and vias located in the hole region; the circuit layer further includes at least one photosensor electrically connected to the driving circuit; the photosensor includes a first electrode layer, a photo structure layer, and a second electrode layer stacked;

[0006] The photosensor is located in the island region, and the first electrode layer, the photo structure layer, and the second electrode layer of the photosensor are sequentially disposed along the direction from the island region to the bridge region; and / or, the photosensor is located in the bridge region, and the first electrode layer, the photo structure layer, and the second electrode layer of the photosensor are sequentially disposed along the direction from the bridge region to the island region.

[0007] In some examples, the driving circuit includes a first thin film transistor for driving the photosensor, a drain of the first thin film transistor is electrically connected to the first electrode layer of the photosensor, and the drain of the first thin film transistor is multiplexed as the first electrode layer.

[0008] In some examples, the driving circuit includes a first thin film transistor for driving the photosensor, a gate of the first thin film transistor is electrically connected to the first electrode layer of the photosensor, and the gate of the first thin film transistor is multiplexed as the first electrode layer.

[0009] In some examples, a light-emitting device is disposed on a side of the circuit layer facing away from the substrate; the light-emitting device includes a third electrode layer, a fourth electrode layer, and a light-emitting layer disposed between the third electrode layer and the fourth electrode layer;

[0010] The third electrode layer is reused as the first electrode layer, and the fourth electrode layer is reused as the second electrode layer.

[0011] In some examples, the photosensor is located in the island region; the circuit layer includes a first thin-film transistor located in the island region, a buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer that are located in the island region and are sequentially disposed on the substrate;

[0012] The first thin-film transistor includes an active layer, a gate, a source, and a drain; the active layer is disposed on a side of the buffer layer facing away from the substrate; the gate is disposed on a side of the first insulating layer facing away from the substrate, and the gate and the active layer overlap at least partially in a front projection on the substrate; the source and the drain are disposed on a side of the second insulating layer facing away from the substrate, the source is electrically connected to the source region of the active layer through a first connection via, and the drain is electrically connected to the drain region of the active layer through a second connection via;

[0013] The photosensor is on the same layer as any one of the first insulating layer, the second insulating layer, or the third insulating layer; or, the photosensor is located between any two adjacent layers of the first insulating layer, the second insulating layer, and the third insulating layer.

[0014] In some examples, the first electrode layer includes a first sub-structure, a second sub-structure, and a third sub-structure connecting the first sub-structure and the second sub-structure;

[0015] The first sub-structure, the third sub-structure, and the second sub-structure are sequentially disposed along the direction from the substrate to the circuit layer.

[0016] In some examples, the first sub-structure and the second sub-structure are trapezoidal structures; the third sub-structure is a rectangular structure.

[0017] In some examples, the second sub-structure and the third sub-structure are electrically connected to the drain of the first thin-film transistor, and the drain of the first thin-film transistor is reused as the second sub-structure and the third sub-structure; the first sub-structure is electrically connected to the third electrode layer, and the third electrode layer is reused as the first sub-structure.

[0018] In some examples, the first electrode layer is disposed as a rectangular structure.

[0019] In some examples, the photoelectric sensor is located in the bridge area; the circuit layer includes a buffer layer, a first insulating layer, and a third insulating layer that are located in the bridge area and are sequentially disposed on the substrate.

[0020] The photoelectric sensor is on the same layer as the first insulating layer or the third insulating layer; alternatively, the photoelectric sensor is located between the first insulating layer and the third insulating layer.

[0021] In some examples, the driving circuit includes a first thin-film transistor for driving the photoelectric sensor; a third connection via is provided on the first insulating layer.

[0022] The drain of the first thin-film transistor is electrically connected to the first electrode layer through the third connection via, and the drain of the first thin-film transistor is multiplexed as the first electrode layer; alternatively, the gate of the first thin-film transistor is electrically connected to the first electrode layer through the third connection via, and the gate of the first thin-film transistor is multiplexed as the first electrode layer.

[0023] In some examples, the via in the via area is located between the island area and the bridge area; the photoelectric sensor is located on the sidewalls of the respective film layers between the island area and the bridge area; the sidewalls form a preset inclination angle with the substrate.

[0024] In some examples, the via in the via area is located between the island area and the bridge area; the photoelectric sensor includes a multi-stage photoelectric structure; the multi-stage photoelectric structure is located on the sidewalls of the respective film layers between the island area and the bridge area.

[0025] The first sub-photoelectric structure of the i-th stage photoelectric structure is connected to the second sub-photoelectric structure of the (i - 1)-th stage photoelectric structure; the second sub-photoelectric structure of the i-th stage photoelectric structure is connected to the first sub-photoelectric structure of the (i + 1)-th stage photoelectric structure; 0 < i ≤ N, and N is a positive integer greater than or equal to 2.

[0026] The included angle range between the first sub-photoelectric structure of the i-th stage photoelectric structure and the second sub-photoelectric structure of the (i - 1)-th stage photoelectric structure is between 85° and 105°; the included angle range between the second sub-photoelectric structure of the i-th stage photoelectric structure and the first sub-photoelectric structure of the (i + 1)-th stage photoelectric structure is between 85° and 105°; the included angle range between the first sub-photoelectric structure of the i-th stage photoelectric structure and the second sub-photoelectric structure of the i-th stage photoelectric structure is between 85° and 105°.

[0027] In a second aspect, an embodiment of the present disclosure further provides a method for manufacturing a display substrate. The display substrate has an island area, a via area, and a bridge area. The method for manufacturing the display substrate includes:

[0028] A circuit layer is formed on a substrate; a driving circuit located in the island region and vias located in the hole region are formed on the circuit layer;

[0029] At least one photosensor electrically connected to the driving circuit is further formed on the circuit layer; the photosensor includes a first electrode layer, a photo - electric structure layer, and a second electrode layer which are stacked;

[0030] The photosensor is located in the island region, and the first electrode layer, the photo - electric structure layer, and the second electrode layer of the photosensor are sequentially arranged along the direction from the island region to the bridge region; and / or, the photosensor is located in the bridge region, and the first electrode layer, the photo - electric structure layer, and the second electrode layer of the photosensor are sequentially arranged along the direction from the bridge region to the island region.

[0031] In a third aspect, an embodiment of the present disclosure further provides a display device, which includes a display substrate as described in any one of the examples in the first aspect. Description of the Drawings

[0032] Figure 1 It is a schematic diagram of the structures of each region of a display substrate provided by an embodiment of the present disclosure;

[0033] Figure 2 It is a schematic diagram of a photosensor located in the island region provided by an embodiment of the present disclosure;

[0034] Figure 3 It is a schematic diagram of a photosensor located in the bridge region provided by an embodiment of the present disclosure;

[0035] Figure 4 It is a schematic diagram of the structures of each film layer of the display substrate when the photosensor is located in the island region provided by an embodiment of the present disclosure;

[0036] Figure 5 It is a schematic diagram of a driving circuit of a photosensor provided by an embodiment of the present disclosure;

[0037] Figure 6 It is a schematic diagram of the connection structure between the drain of the first thin - film transistor and the photosensor when the photosensor is located in the island region provided by an embodiment of the present disclosure;

[0038] Figure 7 It is another schematic diagram of a driving circuit of a photosensor provided by an embodiment of the present disclosure;

[0039] Figure 8 It is a schematic diagram of the connection structure between the gate of the first thin - film transistor and the photosensor when the photosensor is located in the island region provided by an embodiment of the present disclosure;

[0040] Figure 9Schematic diagram of the connection structure between the light-emitting device and the photosensor when the photosensor provided by the embodiment of the present disclosure is located in the island region;

[0041] Figure 10 Schematic diagram of the structure of each film layer of the display substrate when the photosensor provided by the embodiment of the present disclosure is located in the bridge region;

[0042] Figure 11 Schematic diagram of the specific structure of a first electrode layer provided by the embodiment of the present disclosure;

[0043] Figure 12 Schematic diagram of the sidewall structure of each film layer when the photosensor provided by the embodiment of the present disclosure is located between the island region and the bridge region;

[0044] Figure 13 Schematic diagram of the sidewall structure of each film layer when the photosensor provided by the embodiment of the present disclosure is located between the island region and the bridge region in another way;

[0045] Figures 14a to 14o Schematic diagram of the preparation process of the display substrate provided by the embodiment of the present disclosure.

[0046] Wherein the reference numerals are: display substrate 100; substrate substrate 01; circuit layer 02; photosensor 03; first electrode layer 31; first sub-structure 311; second sub-structure 312; third sub-structure 313; optoelectronic structure layer 32; second electrode layer 33; first thin-film transistor T1; via Via0 in the hole region; buffer layer 21; first insulating layer 22; second insulating layer 23; third insulating layer 24; active layer T11 of the first thin-film transistor T1; gate T12 of the first thin-film transistor T1; source T13 of the first thin-film transistor T1; drain T14 of the first thin-film transistor T1; source region T11a of the active layer T11 of the first thin-film transistor T1; drain region T11b of the active layer T11 of the first thin-film transistor T1; first connection via Via1; second connection via Via2; glass sub-substrate 11; flexible sub-substrate 12; modulus material 13; light-emitting device 04; third electrode layer 41; light-emitting layer 42; fourth electrode layer 43; active layer T21 of the second thin-film transistor T2; gate T22 of the second thin-film transistor T2; source T23 of the second thin-film transistor T2; drain T24 of the second thin-film transistor T2; source region T21a of the active layer T21 of the second thin-film transistor T2; drain region T21b of the active layer T21 of the first thin-film transistor T2; fourth connection via Via4; fifth connection via Via5; sixth connection via Via6; encapsulation film layer 05. Detailed implementation manners

[0047] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0048] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, the terms such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. The terms such as "comprising" or "including" mean that the elements or objects appearing before this term cover the elements or objects listed after this term and their equivalents, without excluding other elements or objects. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0049] It should be noted that in this disclosure, the "same-layer setting" of two structures means that they are formed by the same material layer. Therefore, they are in the same layer in the stacking relationship, but it does not mean that the distances between them and the substrate are equal, nor does it mean that the other layer structures between them and the substrate are completely the same.

[0050] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0051] Figure 1 It is a schematic diagram of the structure of each region of a display substrate provided by an embodiment of the present disclosure. Figure 2 It is a schematic diagram of a photoelectric sensor located in an island region provided by an embodiment of the present disclosure. Figure 3 It is a schematic diagram of a photoelectric sensor located in a bridge region provided by an embodiment of the present disclosure; as Figure 1 、 Figure 2 and Figure 3 shown, the display substrate has an island region, a via region and a bridge region; the display substrate 100 includes a substrate 01 and a circuit layer 02 provided on the substrate 01.

[0052] The display substrate provided by the embodiment of the present disclosure is a stretchable display substrate 100. The stretchable display substrate is provided with a series of microporous structures, that is, vias Via0 located in the via region. The via Via0 divides the stretchable display substrate 100 into an island region and a bridge region. The island region is used for image display; the via Via0 is used to provide a deformation space when the display substrate 100 is stretched, and at the same time, it is also used to transmit light; the bridge region is used for routing and transmitting tensile force. AsFigure 1 As shown in the figure, the driving circuits of the OLED and the photoelectric sensor are located in the island region. When an external force is applied along the direction perpendicular to the stretchable display panel 100, the bridge region deforms to achieve certain stretchability, and at the same time, the light passing through the via hole Via0 changes.

[0053] The circuit layer 02 includes a driving circuit located in the island region and a via hole Via0 located in the hole region; the circuit layer 02 further includes at least one photoelectric sensor 03 electrically connected to the driving circuit; the photoelectric sensor 03 includes a first electrode layer 31, a photoelectric structure layer 32, and a second electrode layer 33 arranged in a stacked manner.

[0054] As Figure 2 shown, the photoelectric sensor 03 is located in the island region, and the first electrode layer 31, the photoelectric structure layer 32, and the second electrode layer 33 of the photoelectric sensor 03 are sequentially arranged along the direction from the island region to the bridge region.

[0055] As Figure 3 shown, the photoelectric sensor 03 is located in the bridge region, and the first electrode layer 31, the photoelectric structure layer 32, and the second electrode layer 33 of the photoelectric sensor 03 are sequentially arranged along the direction from the bridge region to the island region.

[0056] It should be noted that the via hole Via0 in the hole region is located between the island region and the bridge region, and the via hole Via0 in the hole region penetrates the circuit layer 02 along the direction perpendicular to the substrate 01. The photoelectric sensor 03 is located near the hole region in the circuit layer 02, and the first electrode layer 31, the photoelectric structure layer 32, and the second electrode layer 33 are sequentially close to the via hole Via0 in the hole region. Exemplarily, the photoelectric sensor 03 can be an Organic-Photo-Diode (OPD). The first electrode layer 31 is the anode of the photoelectric sensor 03, the second electrode layer 33 is the cathode of the photoelectric sensor 03, and the second electrode layer 33 is a transparent electrode layer, and the light from the via hole Via0 in the hole region can be received through the second electrode layer 33.

[0057] In the embodiment of the present disclosure, the photoelectric sensor 03 is integrated into the stretchable display substrate 100 located in the stretchable island region and / or the bridge region. The photoelectric sensor 03 can utilize the light change after stretching of the via hole Via0 in the hole region to realize the monitoring of the stretching state, and can be used for stretchable display, electronic skin and other displays. In addition, the first electrode layer 31, the photoelectric structure layer 32, and the second electrode layer 33 in the photoelectric sensor 03 are stacked along the direction between the island region and the bridge region, that is, the structures of the photoelectric sensor 03 are arranged horizontally. This can not only be applicable to the stretchable backplane, but also reduce the occupied area. Compared with the traditional OPD integration method (usually the OPD is arranged on the same layer as the Organic Light-Emitting Diode (OLED)), it can improve the display resolution and the aperture ratio.

[0058] Under the condition that the second electrode layer 33 can receive the light of the via Via0 in the via region, the photosensor 03 can be arranged at any position in the island region or the bridge region. However, in order to more fully reduce the occupied area and improve the sensitivity of the optical sensor, the photosensor 03 is arranged at a position of the circuit layer 02 close to the via region, and can be embedded or laid on the side walls of each film layer located in the island region or the bridge region, etc.

[0059] In the embodiments of the present disclosure, the photosensor 03 arranged on the display substrate 100 can be prepared by different methods. In a possible implementation manner, taking the photosensor 03 prepared by the solution method as an example, the following will describe in detail each structure of the display substrate 100 provided by the embodiments of the present disclosure.

[0060] In some examples, since the island region is not easily deformed and is provided with a variety of different thin film transistors, which is convenient for circuit connection, the photosensor 03 is arranged on the circuit layer 02 located in the island region. Figure 4 For the photosensor provided by the embodiments of the present disclosure when it is located in the island region, the schematic diagram of the structures of each film layer of the display substrate is as Figure 4 shown, the photosensor 03 is located in the island region; the circuit layer 02 includes a first thin film transistor T1 located in the island region, a buffer layer 21, a first insulating layer 22, a second insulating layer 23, and a third insulating layer 24 that are located in the island region and are sequentially arranged on the substrate 01. The first thin film transistor T1 includes an active layer T11, a gate T12, a source T13, and a drain T14; the active layer T11 is arranged on the side of the buffer layer 21 facing away from the substrate 01; the gate T12 is arranged on the side of the first insulating layer 22 facing away from the substrate 01, and the gate T12 and the active layer T11 overlap at least partially in the orthographic projection on the substrate 01; the source T13 and the drain T14 are arranged on the side of the second insulating layer 23 facing away from the substrate 01, and the source T13 is electrically connected to the source region T11a of the active layer T11 through a first connection via Via1, and the drain T11b is electrically connected to the drain region T11b of the active layer T11 through a second connection via Via2.

[0061] The material of the active layer of the first thin film transistor T1 provided by the embodiments of the present disclosure can be a semiconductor material, for example, it can include low temperature polysilicon, or oxide, etc., and can be limited according to requirements in actual applications, and the embodiments of the present disclosure do not make specific limitations.

[0062] The photosensor 03 is on the same layer as any one of the first insulating layer 22, the second insulating layer 23, or the third insulating layer 24; or, the photosensor 03 is located between any two adjacent layers of the first insulating layer 22, the second insulating layer 23, and the third insulating layer 24. Among them, Figure 4Only a schematic diagram showing that the optoelectronic sensor 03 is on the same layer as the first insulating layer 22 is shown.

[0063] The substrate 01 provided by the embodiment of the present disclosure may be a flexible substrate. The substrate 01 may adopt a single-layer substrate or a multi-layer substrate. If a multi-layer substrate is adopted, the substrate 01 includes a glass sub-substrate 11 and a flexible sub-substrate 12 (a substrate made of a flexible material, thermoplastic polyimide (PI)) arranged in a stacked manner.

[0064] In one example, in addition to penetrating the circuit layer 02, the via Via0 in the via region also penetrates the buffer layer 21 and the flexible sub-substrate 12 of the substrate 01. In another example, as Figure 4 shown, in addition to penetrating the circuit layer 02, the via Via0 in the via region also penetrates the buffer layer 21 and the flexible sub-substrate 12 of the substrate 01, and a low-modulus material 13 is filled at the via of the flexible sub-substrate 12, which can improve the stretching performance of the display substrate 100.

[0065] The buffer layer 21 is usually made of an inorganic material, such as silicon oxide, silicon nitride and other materials, to achieve the effects of water and oxygen resistance and alkaline ion blocking. Therefore, the buffer layer 21 has a relatively high hardness and a relatively large thickness. When the display substrate 100 is stretched, the buffer layer 21 is relatively difficult to be stretched, and the buffer layer 21 has a relatively large stress, especially cracks are likely to occur at the edges of the buffer layer 21 corresponding to the island region and the bridge region. If the number of cracks is large, the buffer layer 21 will be damaged, resulting in damage to the display substrate 100. The display substrate 100 provided by the embodiment of the present disclosure aims to set an opening on the buffer layer 21 through the via Via0, which can release the stress accumulated by the buffer layer 21 during stretching, avoid cracks in the buffer layer 21 caused by stretching, thereby avoiding damage to the display substrate 100 and improving the stretchability of the display substrate 100.

[0066] The material of the first insulating layer 22 only needs to be a material that can satisfy the insulation between the active layer T11 and the gate T12 of the first thin-film transistor T1, and the embodiment of the present disclosure does not specifically limit it. The first insulating layer 22 may be a first gate insulation (Gate Insulator, abbreviated as GI) layer GI1.

[0067] The second insulating layer 23 is used to protect the insulation between the gate T12 of the first thin-film transistor T1 and other metal structures (such as the source T13 and the drain T14 of the first thin-film transistor T1). The second insulating layer 23 may adopt a single-layer insulating layer, such as the second gate insulating layer GI2; or, it may also adopt sub-insulating layers arranged in a multi-layer stacked manner, such as the second gate insulating layer GI2 and an inter-layer dielectric (Inter-Layer Dielectric, abbreviated as ILD) layer arranged in a stacked manner. The material of the second insulating layer 23 is not specifically limited in the embodiment of the present disclosure.

[0068] The third insulating layer 24 is used to protect the source T13 and the drain T14 of the first thin-film transistor T1. The third insulating layer 24 can adopt two insulating layers, such as a passivation (PVX) layer and a first planarization layer PLN1 arranged in a stacked manner; alternatively, it can also adopt sub-insulating layers arranged in multiple layers in a stacked manner, such as a passivation layer PVX, a first plain (PLN) layer PLN1, and a second planarization layer PLN2 arranged in a stacked manner.

[0069] It should be noted that different photoelectric sensors 03 can be on the same layer as different insulating layers. Multiple photoelectric sensors 03 receive the light after transformation in the stretching hole area, which can improve the detection accuracy. The placement heights of different photoelectric sensors 03 can be staggered to detect the light at different positions of the via Via0 in the hole area.

[0070] In some examples, the driving circuit includes a first thin-film transistor for driving the photoelectric sensor 03. Figure 5 Schematic diagram of a driving circuit for a photoelectric sensor provided by an embodiment of the present disclosure, as Figure 5 shown, wherein the source T13 of the first thin-film transistor T1 is electrically connected to an external signal source (not shown in Figure 5 , and this external signal source can be a signal source capable of providing a fixed voltage). The drain T14 of the first thin-film transistor T1 is electrically connected to the first electrode layer 31 of the photoelectric sensor 03. The photoelectric structure layer 32 of the photoelectric sensor 03 includes a photodiode PIN and a capacitor C. The photodiode PIN and the capacitor C are connected in parallel, and the first end N1 of the parallel connection is connected to the first electrode layer 31, and the second end N2 of the parallel connection is connected to the second electrode layer 33. Exemplarily, the first electrode layer 31 is the anode of the photoelectric sensor 03, and the second electrode layer 33 is the cathode of the photoelectric sensor 03, and a low power supply voltage VSS is connected.

[0071] Figure 6 Schematic diagram of the connection structure between the drain of the first thin-film transistor and the photoelectric sensor when the photoelectric sensor provided by the embodiment of the present disclosure is located in the island area, as Figure 6 shown, the drain of the first thin-film transistor is electrically connected to the first electrode layer 31 of the photoelectric sensor 03, and the drain of the first thin-film transistor is multiplexed as the first electrode layer 31.

[0072] Exemplarily, the material of the drain of the first thin-film transistor is a titanium Ti-aluminum Al-titanium Ti metal composite layer, that is, the material of the first electrode layer 31 is a titanium Ti-aluminum Al-titanium Ti metal composite layer. Of course, the embodiment of the present disclosure does not limit the material of the drain of the first thin-film transistor. In addition to being a titanium Ti-aluminum Al-titanium Ti metal composite layer, it can also be other feasible materials, which can be specifically limited according to experience and actual scenarios, and the embodiment of the present disclosure does not list them one by one.

[0073] Here, since the drain of the first thin film transistor can be directly reused as the first electrode layer 31 of the photoelectric sensor 03, a metal electrode layer can be directly prepared in the process preparation stage, which can improve the preparation efficiency.

[0074] It should be noted that the photoelectric sensor 03 and the drain electrode of the first thin film transistor can be arranged in the same layer, such as Figure 6 As shown, the photoelectric sensor 03 is arranged on the side of the first flat layer PLN1 in the third insulating layer 24 away from the base substrate 01, that is, the second flat layer PLN2 in the third insulating layer 24. Of course, the photoelectric sensor 03 can also be in the same layer with other layers except the second flat layer PLN2, such as the first insulating layer 22, the second gate insulating layer GI2 in the second insulating layer 23, the interlayer insulating layer ILD in the second insulating layer 23, the passivation layer PVN in the third insulating layer 24, and any one of the first flat layer PLN1, and other ways of setting the same layer are not listed one by one in the embodiments of the present disclosure. Alternatively, the photoelectric sensor 03 can also be located between any two adjacent layers of the first insulating layer 22, the second gate insulating layer GI2 in the second insulating layer 23, the interlayer insulating layer ILD in the second insulating layer 23, the passivation layer PVX in the third insulating layer 24, the first flat layer PLN1 in the third insulating layer 24, and the second flat layer PLN2 in the third insulating layer 24, and the embodiments of the present disclosure are not listed one by one. When the photoelectric sensor 03 and the drain electrode of the first thin film transistor are in different layers, as Figure 4 As shown, the drain electrode T14 of the first thin film transistor T1 can be electrically connected to the first electrode layer 31 of the photosensor 03 through a connecting via hole.

[0075] In some examples, the driving circuit includes a first thin film transistor for driving the photosensor 03, Figure 7 A schematic diagram of another driving circuit of a photoelectric sensor provided in an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, the source electrode T13 and the drain electrode T14 of the first thin film transistor T1 are electrically connected to an external signal source (not shown). Figure 7 As shown in FIG. 1 , the external signal source may be a signal source capable of providing a fixed voltage), the gate T12 of the first thin film transistor T1 is electrically connected to the first electrode layer 31 of the photoelectric sensor 03, and the photoelectric structure layer 32 of the photoelectric sensor 03 includes a photodiode PIN and a capacitor C, the photodiode PIN and the capacitor C are connected in parallel, and the first parallel terminal N1 is connected to the first electrode layer 31, and the second parallel terminal N2 is connected to the second electrode layer 33. Exemplarily, the first electrode layer 31 is the anode of the photoelectric sensor 03, and the second electrode layer 33 is the cathode of the photoelectric sensor 03, which is connected to the low power supply voltage VSS.

[0076] Figure 8When the photoelectric sensor provided by the embodiment of the present disclosure is located in the island region, the schematic connection structure between the gate of the first thin film transistor and the photoelectric sensor is as follows Figure 8 As shown, the gate T12 of the first thin film transistor T1 is electrically connected to the first electrode layer 31 of the photoelectric sensor 03, and the gate of the first thin film transistor is multiplexed as the first electrode layer 31. Figure 8 It is a schematic diagram of the connection relationship between the gate T12 of the first thin film transistor T1 and the photoelectric sensor 03. Figure 8 The specific connection structure between the gate T12 of the first thin film transistor T1 and the first electrode layer 31 is not shown.

[0077] Exemplarily, the material of the gate of the first thin film transistor can be molybdenum Mo, or other feasible materials, and the embodiments of the present disclosure do not specifically limit this.

[0078] Here, since the gate T12 of the first thin film transistor T1 can be directly multiplexed as the first electrode layer 31 of the photoelectric sensor 03, therefore, in the process preparation stage, a gate layer can be directly prepared, which can improve the preparation efficiency.

[0079] It should be noted that the photoelectric sensor 03 and the gate T12 of the first thin film transistor T1 can be arranged in the same layer. As Figure 8 shown, the photoelectric sensor 03 is arranged on the side of the first insulating layer 22 away from the substrate 01, that is, the second gate insulating layer GI2 in the second insulating layer 23. Of course, the photoelectric sensor 03 can also be in the same layer as other layers except the second gate insulating layer GI2 in the second insulating layer 23, such as any one of the first insulating layer 22, the interlayer insulating layer ILD in the second insulating layer 23, the passivation layer PVX in the third insulating layer 24, the first planarization layer PLN1 in the third insulating layer 24, and the second planarization layer PLN2 in the third insulating layer 24. The other ways of being arranged in the same layer are not listed one by one in the embodiments of the present disclosure. Or, the photoelectric sensor 03 can also be located between any two adjacent layers among the first insulating layer 22, the second gate insulating layer GI2 in the second insulating layer 23, the interlayer insulating layer ILD in the second insulating layer 23, the passivation layer PVX in the third insulating layer 24, the first planarization layer PLN1 in the third insulating layer 24, and the second planarization layer PLN2 in the third insulating layer 24. The embodiments of the present disclosure do not list them one by one here. When the photoelectric sensor 03 and the gate T12 of the first thin film transistor T1 are not in the same layer, the gate T12 of the first thin film transistor T1 can be electrically connected to the first electrode layer 31 of the photoelectric sensor 03 through a connection via.

[0080] In some examples, Figure 9 When the photoelectric sensor provided by the embodiment of the present disclosure is located in the island region, the schematic connection structure between the light emitting device and the photoelectric sensor is as follows. As Figure 9As shown, a light-emitting device 04 is provided on the side of the circuit layer 02 facing away from the substrate 01; the light-emitting device 04 includes a third electrode layer 41, a fourth electrode layer 43, and a light-emitting layer 42 disposed between the third electrode layer 41 and the fourth electrode layer 43; the third electrode layer 41 is multiplexed as the first electrode layer 31, and the fourth electrode layer 43 is multiplexed as the second electrode layer 33.

[0081] The third electrode layer 41 is the anode AND of the light-emitting device 04, and the fourth electrode layer 43 is the cathode of the light-emitting device 04. The material of the third electrode layer 41 is an indium tin oxide ITO-silver Ag-indium tin oxide ITO composite layer, that is, the material of the first electrode layer 31 is an indium tin oxide ITO-silver Ag-indium tin oxide ITO composite layer. The material of the fourth electrode layer 43 is magnesium Mg or silver Ag, that is, the material of the second electrode layer 33 is magnesium Mg or silver Ag.

[0082] The light-emitting layer 42 includes a first hole transport layer HTL1 and a first exciton blocking layer ETL1.

[0083] A pixel definition layer (Pixel Definition Layer, PDL) is provided on the circuit layer 02 facing away from the substrate 01, and the light-emitting layer 42 and the fourth electrode layer 43 are sequentially provided on the side of the pixel definition layer PDL facing away from the substrate 01.

[0084] The driving circuit further includes a second thin-film transistor T2 for driving the light-emitting device. The source T23 of the second thin-film transistor T2 is electrically connected to the third electrode layer 41. The active layer T21 of the second thin-film transistor T2 is disposed on the side of the buffer layer 21 facing away from the substrate 01. The gate T22 of the second thin-film transistor T2 is disposed on the side of the first insulating layer 22 facing away from the substrate 01, and the gate T22 of the second thin-film transistor T2 and the active layer T1 of the second thin-film transistor T2 overlap at least partially in the orthographic projection on the substrate 01; the source T23 and the drain T24 of the second thin-film transistor T2 are disposed on the side of the second insulating layer 23 facing away from the substrate 01. The first end of the source T23 of the second thin-film transistor T2 is electrically connected to the source region T21a of the active layer T21 of the second thin-film crystal T2 through a fourth connection via Via4. The drain T24 of the second thin-film transistor T2 is electrically connected to the drain region T21b of the active layer T21 of the second thin-film transistor T2 through a fifth connection via Via5; the second end of the source T23 of the second thin-film transistor T2 is electrically connected to the third electrode layer 41 through a sixth connection via Via6.

[0085] Here, since the third electrode layer 41 can be directly reused as the first electrode layer 31 of the photoelectric sensor 03, and the fourth electrode layer 43 can be directly reused as the second electrode layer 33 of the photoelectric sensor 03, therefore, in the process preparation stage, the mutually reused electrode layers can be directly prepared into one layer, which can improve the preparation efficiency. Of course, the first electrode layer 31 and the second electrode layer 33 can also be prepared separately without reusing the third electrode layer 41 and the fourth electrode layer 43 of the light-emitting device.

[0086] It should be noted that as Figure 9 shown, the photoelectric sensor 03 and the pixel defining layer PDL can be arranged on the same layer, that is, the photoelectric sensor 03 is arranged on the side of the third insulating layer 24 away from the substrate 01. Compared with the case of layered arrangement where connection vias need to be opened, the same-layer arrangement can improve the preparation efficiency and save material costs. Of course, the photoelectric sensor 03 can also be on the same layer as different insulating layers, and the embodiments of the present disclosure do not make specific limitations.

[0087] It should be noted that the materials of the second thin-film transistor active layer, source electrode, drain electrode, and gate electrode can refer to the description of the specific materials of each structure of the above first thin-film transistor, and the repeated parts will not be elaborated.

[0088] In some examples, the first electrode layer 31 is arranged in a rectangular structure, which can enhance the signal, prevent the signal light from dispersing up and down, and increase the signal-to-noise ratio.

[0089] In some examples, since most of the wiring in the bridge area is the driving lines of the source electrode and the drain electrode, there are fewer gate driving lines, and the noise of the OPD wiring is small, and the OPD material is flexible and can withstand the deformation of the bridge area. Therefore, the photoelectric sensor 03 can be arranged on the circuit layer 02 located in the bridge area. Taking Figure 5 the driving circuit shown as an example, Figure 10 FIG. is a schematic structural diagram of each film layer of the display substrate when the photoelectric sensor provided by the embodiment of the present disclosure is located in the bridge area. As Figure 10 shown, the photoelectric sensor 03 is located in the bridge area; the circuit layer 02 includes a buffer layer 21, a first insulating layer 22, and a third insulating layer 24 that are located in the bridge area and are sequentially arranged on the substrate 01.

[0090] The photoelectric sensor 03 is on the same layer as the first insulating layer 22 or the third insulating layer 24; or, the photoelectric sensor 03 is located between the first insulating layer 22 and the third insulating layer 24. Figure 10 FIG. shows a schematic diagram of the photoelectric sensor 03 on the same layer as the first insulating layer 22.

[0091] Here, the buffer layer 21 has the same material and function as the buffer layer 21 in the above Figure 4 example; the first insulating layer 22 has the same material and function as the first insulating layer 22 in the above Figure 4 example; the third insulating layer 24 has the same material as the third insulating layer 24 in the aboveFigure 4 The materials and functions of the third insulating layer 24 in the examples are the same, and the repeated parts will not be described here again.

[0092] In some examples, at least one third connection via Via3 is provided in the first insulating layer 22 located in the bridge area, as Figure 10 shown. If the drain T14 of the first thin-film transistor T1 is provided at the third connection via Via3, at this time, the drain T14 of the first thin-film transistor T1 is on the same layer as the first insulating layer 22 located in the bridge area, the first electrode layer 31 of the photosensor 03 is electrically connected to the drain T14 of the first thin-film transistor T1, and the drain T14 of the first thin-film transistor T1 is reused as the first electrode layer 31 of the photosensor 03.

[0093] If the gate of the first thin-film transistor is provided at the third connection via, at this time, the gate of the first thin-film transistor is on the same layer as the first insulating layer 22 located in the bridge area, the first electrode layer 31 of the photosensor 03 can be electrically connected to the gate T12 of the first thin-film transistor T1, and the gate T12 of the first thin-film transistor T1 is reused as the first electrode layer 31 of the photosensor 03.

[0094] In some examples, Figure 11 is a schematic structural diagram of a first electrode layer provided by an embodiment of the present disclosure. As Figure 11 shown, taking the photosensor 03 being on the same layer as the third insulating layer 24 as the preferred setting method and being provided between the first planar layer PLN1 and the second planar layer PLN2 as an example, the third insulating layer 24 here can be either the third insulating layer 24 located in the island area or the third insulating layer 24 located in the bridge area. The first electrode layer 31 includes a first sub-structure 311, a second sub-structure 312, and a third sub-structure 313 connecting the first sub-structure 311 and the second sub-structure 312; the first sub-structure 311, the third sub-structure 313, and the second sub-structure 312 are arranged in sequence along the direction from the substrate 01 to the circuit layer 02.

[0095] Among them, the first sub-structure 311 and the second sub-structure 312 are trapezoidal structures; the third sub-structure 313 is a rectangular structure, which can enhance the signal, prevent the signal light from being scattered up and down, and increase the signal-to-noise ratio. Specifically, after the first planar layer PLN1 and the second planar layer PLN2 are etched into trapezoidal structures by exposure, trapezoidal first and second sub-structures are deposited and formed.

[0096] Example 1: The second sub-structure 312 and the third sub-structure 313 are electrically connected to the drain T14 of the first thin-film transistor T1, and the drain T14 of the first thin-film transistor T1 is multiplexed as the second sub-structure 312 and the third sub-structure 313. The first sub-structure 311 is electrically connected to the third electrode layer 41, and the third electrode layer 41 is multiplexed as the first sub-structure 311. Example 2: The first sub-structure 311, the second sub-structure 312, and the third sub-structure 313 are all electrically connected to the third electrode layer 41, and the third electrode layer 41 is simultaneously multiplexed as the first sub-structure 311, the second sub-structure 312, and the third sub-structure 313. Example 3: The drain T14 of the first thin-film transistor T1 is simultaneously multiplexed as the first sub-structure 311, the second sub-structure 312, and the third sub-structure 313.

[0097] In the embodiments of the present disclosure, in addition to the respective structures of the display substrate 100 obtained by preparing the photoelectric sensor 03 using the solution method as described above, in another possible implementation manner, taking the photoelectric sensor 03 prepared by the evaporation method as an example, the respective structures of the display substrate 100 provided by the embodiments of the present disclosure will be described in detail below.

[0098] In some examples, Figure 12 is a schematic structural diagram of the sidewalls of the respective film layers of a photoelectric sensor provided by an embodiment of the present disclosure located between the island region and the bridge region. As Figure 12 shown, the via Via0 in the via region is located between the island region and the bridge region; the photoelectric sensor 03 is located on the sidewalls of the respective film layers between the island region and the bridge region; the sidewalls form a preset inclination angle with the substrate 01.

[0099] Here, the preset inclination angle can be set according to experience, and the embodiments of the present disclosure do not make specific limitations.

[0100] It should be noted that the sidewalls of the respective film layers between the island region and the bridge region include the sidewalls of the respective film layers in the island region and the sidewalls of the respective film layers in the bridge region.

[0101] On the sidewalls of the respective film layers in the island region, the first electrode layer 31, the optoelectronic structure layer 32, and the second electrode layer 33 are sequentially stacked in the direction from the island region to the bridge region, and / or, on the sidewalls of the respective film layers in the bridge region, the first electrode layer 31, the optoelectronic structure layer 32, and the second electrode layer 33 are sequentially stacked in the direction from the bridge region to the island region.

[0102] In the embodiments of the present disclosure, the drain T14 of the first thin-film transistor T1 can be multiplexed as the first electrode layer 31; or, the gate T12 of the first thin-film transistor T1 can be multiplexed as the first electrode layer 31; or, the third electrode layer 41 can be multiplexed as the first electrode layer 31. For specific structural connection examples, reference can be made to the respective structures of the display substrate 100 corresponding to the solution method described above, and the repeated parts will not be elaborated again.

[0103] As Figure 12As shown in Figure 5 Taking the driving circuit shown as an example, the drain T14 of the first thin-film transistor T1 is electrically connected to the first electrode layer 31, and the drain T14 of the first thin-film transistor T1 is multiplexed as the first electrode layer 31.

[0104] In some examples, Figure 13 FIG. is a schematic structural diagram of side walls of each film layer between the island region and the bridge region of another photoelectric sensor provided by an embodiment of the present disclosure. As Figure 13 shown, the vias in the hole region are located between the island region and the bridge region; the photoelectric sensor 03 includes a multi-stage photoelectric structure; the multi-stage photoelectric structure is located on the side walls of each film layer between the island region and the bridge region; the first sub-photoelectric structure of the i-th stage photoelectric structure is connected to the second sub-photoelectric structure of the (i-1)-th stage photoelectric structure; the second sub-photoelectric structure of the i-th stage photoelectric structure is connected to the first sub-photoelectric structure of the (i+1)-th stage photoelectric structure; 0 < i ≤ N, where N is a positive integer greater than or equal to 2; the included angle between the first sub-photoelectric structure of the i-th stage photoelectric structure and the second sub-photoelectric structure of the (i-1)-th stage photoelectric structure is between 85° and 105°; the included angle range between the second sub-photoelectric structure of the i-th stage photoelectric structure and the first sub-photoelectric structure of the (i+1)-th stage photoelectric structure is between 85° and 105°; the included angle between the first sub-photoelectric structure of the i-th stage photoelectric structure and the second sub-photoelectric structure of the i-th stage photoelectric structure is between 85° and 105°.

[0105] Exemplarily, for the convenience of preparation, the included angle between the first sub-photoelectric structure and the second sub-structure can be set to 90°. Of course, those skilled in the art should know that the corners formed between the sub-photoelectric structures can be within the allowable error range of the 90° corner.

[0106] The multi-stage photoelectric structure forms a stepped photoelectric structure. At this time, the side walls of each film layer between the island region and the bridge region are also set as a stepped structure to adapt to the stepped multi-stage photoelectric structure.

[0107] In the embodiment of the present disclosure, having a large slope or a stepped shape on the side walls of each film layer between the island region and the bridge region can increase the area of the photoelectric sensor 03, increase the signal intensity, and does not occupy the area of the circuit layer 02, thereby improving the display resolution and aperture ratio.

[0108] In some examples, a light-emitting layer is provided on the side of the circuit layer 02 away from the substrate 01; the light-emitting layer includes a first hole transport layer HTL1 and a first exciton blocking layer ETL1; the optoelectronic structure layer 32 includes a second hole transport layer HTL2, a second exciton blocking layer ETL2, and an optoelectronic material layer (i.e., an OPD material layer) that are sequentially stacked along the direction from the first electrode layer 31 to the second electrode layer 33; the first hole transport layer HTL1 is connected to the second hole transport layer HTL2, and the first hole transport layer HTL1 is reused as the second hole transport layer HTL2; the first exciton blocking layer ETL1 is connected to the second exciton blocking layer ETL2, and the first exciton blocking layer ETL1 is reused as the second exciton blocking layer ETL2.

[0109] The first hole transport layer HTL1 and the first exciton blocking layer ETL1 in the light-emitting layer are sequentially stacked along the direction from the third electrode layer to the fourth electrode layer.

[0110] As Figure 12 shown, the second hole transport layer HTL2, the second exciton blocking layer ETL2, and the optoelectronic material layer in the optoelectronic structure layer 32 together form a photodiode PIN and a capacitor C.

[0111] Here, the first hole transport layer HTL1 being reused as the second hole transport layer HTL2 and the first exciton blocking layer ETL1 being reused as the second exciton blocking layer ETL2 can save costs such as equipment and materials.

[0112] In some examples, an encapsulation film layer 05 is provided on the outer side of the display substrate 100, that is, on the outer walls of each film layer located in the island region and the bridge region. The encapsulation film layer 05 is, for example, a film layer made of tetrafluoroethylene TFE material.

[0113] Based on the same inventive concept, an embodiment of the present disclosure also provides a method for manufacturing a display substrate 100. Since the principle of the problem solved by the method for manufacturing the display substrate 100 in the embodiment of the present disclosure is similar to that of the above-mentioned display substrate 100 in the embodiment of the present disclosure, each structure of the display substrate 100 in the method for manufacturing the display substrate 100 can refer to the above-mentioned display substrate 100 provided in the embodiment, and repeated parts will not be described again.

[0114] A method for preparing a display substrate 100, wherein the display substrate 100 has an island region, a via region, and a bridge region. The method for preparing the display substrate 100 includes: forming a circuit layer 02 on a substrate 01; forming a driving circuit located in the island region and vias located in the via region on the circuit layer 02; further forming at least one photosensor 03 electrically connected to the driving circuit on the circuit layer 02; the photosensor 03 includes a first electrode layer 31, a photo - electric structure layer 32, and a second electrode layer 33 which are stacked; the photosensor 03 is located in the island region, and the first electrode layer 31, the photo - electric structure layer 32, and the second electrode layer 33 of the photosensor 03 are sequentially arranged along the direction from the island region to the bridge region; and / or, the photosensor 03 is located in the bridge region, and the first electrode layer 31, the photo - electric structure layer 32, and the second electrode layer 33 of the photosensor 03 are sequentially arranged along the direction from the bridge region to the island region.

[0115] In an embodiment of the present disclosure, the photosensor 03 is integrated into the display substrate 100 located in the stretchable island region and / or the bridge region. When the display substrate 100 is stretched, the photosensor 03 can utilize the change in light intensity of the via Via0 in the via region after stretching to monitor the stretching state, and can be used for stretchable displays, electronic skins, etc. In addition, the first electrode layer 31, the photo - electric structure layer 32, and the second electrode layer 33 in the photosensor 03 are stacked along the direction between the island region and the bridge region, that is, the structures of the photosensor 03 are arranged horizontally, which can reduce the occupied area, thereby improving the display resolution and the aperture ratio.

[0116] In some examples, the photosensor 03 is prepared by a solution method. For a more clear description of the preparation of each film layer, taking Figure 5 the driving circuit as an example, the following will be elaborated in detail with steps S1 - S15. Figures 14a to 14o The following is a schematic diagram of the preparation process of the display substrate provided by the embodiment of the present disclosure:

[0117] S1. Form a buffer layer 21 on the substrate 01, and etch the buffer layer 21 located in the via region to form a via Via0 penetrating the buffer layer 21, as Figure 14a shown.

[0118] In some examples, the substrate 01 includes a glass sub - substrate 11 and a flexible sub - substrate 12. In the region where the positive projection of the via region on the substrate 01 is located, a via penetrating the flexible sub - substrate 12 is formed, and a low - modulus material 13 is filled in the via penetrating the flexible sub - substrate.

[0119] The buffer layer 21 can be deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0120] It should be noted that on the substrate 01, the buffer layer 21 located in the island region and the bridge region is prepared simultaneously.

[0121] S2. Form the active layer T11 of the first thin-film transistor T1 and the active layer T21 of the second thin-film transistor T2 on the side of the buffer layer 21 facing away from the substrate 01, as Figure 14b shown.

[0122] Specifically, first, deposit a semiconductor layer on the substrate 01; then, coat a photoresist on the side of the semiconductor layer facing away from the substrate 01 and perform processes such as exposure, development, etching, and stripping to obtain the active layer T11 of the first thin-film transistor T1 and the active layer T21 of the second thin-film transistor T2. The semiconductor layer can be deposited on the substrate 01 by means of CVD or ALD.

[0123] S3. Form a first insulating layer 22 (i.e., the first gate insulating layer) on the side of the active layer T11 of the first thin-film transistor T1 facing away from the substrate 01, and form a first connection via Via1 and a second connection via Via2 penetrating the first insulating layer 22 in the regions where the source region T11a and the drain region T11b of the active layer T11 of the first thin-film transistor T1 are orthogonally projected; form a fourth connection via Via4 and a fifth connection via Via5 penetrating the first insulating layer 22 in the regions where the source region T21a and the drain region T21b of the active layer T21 of the second thin-film transistor T2 are orthogonally projected, as Figure 14c shown.

[0124] The first insulating layer 22 can be the first gate insulating layer GI1, which is used to protect the active layer T11 of the first thin-film transistor T1.

[0125] Since the multi-layer insulating layer has a relatively deep depth, it is difficult to punch holes through the multi-layer insulating layer at one time. Therefore, in the embodiments of the present disclosure, the same connection via is punched in batches. In one case, in order to reduce the difficulty of the punching process, when each insulating layer is deposited, a sub-connection via penetrating the insulating layer is formed. For example, after depositing a first gate insulating layer GI1, a first connection via Via1 and a second connection via Via2 penetrating the first insulating layer 22 are formed in the regions where the source region T11a and the drain region T11b of the active layer T11 of the first thin-film transistor T1 are orthogonally projected. In another case, for the connection via penetrating the multi-layer insulating layer, in order to reduce the difficulty of the punching process, and at the same time, to reduce the number of punching times and improve the preparation efficiency of the display substrate 100. After depositing two or more insulating layers, the punching preparation process is performed. The specific punching preparation process can refer to the punching process performed when each insulating layer is deposited.

[0126] It should be noted that on the substrate 01, the first insulating layer 22 located in the island region and the bridge region is prepared simultaneously.

[0127] S4. On the side of the first insulating layer 22 facing away from the substrate 01, form the gate T12 of the first thin-film transistor T1 and the gate T22 of the second thin-film transistor T2, and the gate T12 of the first thin-film transistor T1 overlaps with the positive projection of the active layer T11 of the first thin-film transistor T1 on the substrate 01; the gate T22 of the second thin-film transistor T2 overlaps with the positive projection of the active layer T21 of the second thin-film transistor T2 on the substrate 01, as Figure 14d .

[0128] For the implementation of depositing the gate of the first thin-film transistor T1 in this step, refer to the implementation of depositing the active layer T11 of the first thin-film transistor T1 in S2, and the specific preparation principle will not be elaborated here.

[0129] S5. On the side of the gate T12 of the first thin-film transistor T1 facing away from the substrate 01, form the second gate insulating layer GI2, and in the regions where the source region T11a and the drain region T11b of the active layer T11 of the first thin-film transistor T1 are projected orthographically, form the first connection via Via1 and the second connection via Via2 that penetrate the second gate insulating layer GI2; in the regions where the source region T21a and the drain region T21b of the active layer T21 of the second thin-film transistor T2 are projected orthographically, form the fourth connection via Via4 and the fifth connection via Via5 that penetrate the second gate insulating layer GI2, as Figure 14e shown.

[0130] The second gate insulating layer GI2 is used to protect the gate T12 of the first thin-film transistor T1 and the gate T22 of the second thin-film transistor T2.

[0131] S6. On the side of the second gate insulating layer GI2 facing away from the substrate 01, form the interlayer insulating layer ILD, and in the regions where the source region T11a and the drain region T11b of the active layer T11 of the first thin-film transistor T1 are projected orthographically, form the first connection via Via1 and the second connection via Via2 that penetrate the interlayer insulating layer ILD; in the regions where the source region T21a and the drain region T21b of the active layer T21 of the second thin-film transistor T2 are projected orthographically, form the fourth connection via Via4 and the fifth connection via Via5 that penetrate the interlayer insulating layer ILD, as Figure 14f shown.

[0132] S7. On the side of the interlayer insulating layer ILD facing away from the substrate 01, form the source electrode T13 and the drain electrode T14 of the first thin-film transistor T1, and form the source electrode T23 and the drain electrode T24 of the second thin-film transistor T2. Among them, the source electrode T13 of the first thin-film transistor T1 is electrically connected to the source region T11a of the first thin-film transistor T1 through the first connection via Via1, and the drain electrode T14 of the first thin-film transistor T1 is electrically connected to the drain region T11b of the first thin-film transistor T1 through the second connection via Via2; the source electrode T23 of the second thin-film transistor T2 is electrically connected to the source region T21a of the second thin-film transistor T2 through the fourth connection via Via4, and the drain electrode T24 of the second thin-film transistor T2 is electrically connected to the drain region T21b of the second thin-film transistor T2 through the fifth connection via Via5, as Figure 14g shown.

[0133] For the implementation of depositing the source electrode T13 and the drain electrode T14 of the first thin-film transistor T1 in this step, refer to the implementation of depositing the active layer T11 of the first thin-film transistor T1 in S2, and the specific preparation principle will not be elaborated here.

[0134] S8. On the side of the source electrode T13 and the drain electrode T14 of the first thin-film transistor T1 facing away from the substrate 01, form a passivation layer PVX, as Figure 14h shown.

[0135] The passivation layer PVX is used to protect the source electrode T13 and the drain electrode T14 of the first thin-film transistor T1.

[0136] S9. On the side of the passivation layer PVX facing away from the substrate 01, form a first planarization layer PLN1, and in the region where the positive projections of the source electrode T13 and the drain electrode T14 of the first thin-film transistor T1 are located, form a first connection via Via1 and a second connection via Via2 that penetrate the first planarization layer PLN1, as Figure 14i shown.

[0137] It should be noted that on the substrate 01, the first planarization layer PLN1 in the island region and the bridge region is prepared simultaneously.

[0138] S10. On the side of the first planarization layer PLN1 facing away from the substrate 01, form the source electrode T13 and the drain electrode T14 of the first thin-film transistor T1. Among them, the source electrode T13 of the first thin-film transistor T1 is electrically connected to the source electrode T13 of the first thin-film transistor T1 located at the passivation layer PVX through the first connection via Via1, and the drain electrode T14 of the first thin-film transistor T1 is electrically connected to the drain electrode T14 of the first thin-film transistor T1 located at the passivation layer PVX through the second connection via Via2; in addition, the drain electrode T14 of the first thin-film transistor T1 is reused as the first electrode layer 31 of the photosensor 03.

[0139] At this time, the photoelectric sensor 03 is located on the side of the first flat layer PLN1 away from the substrate 01, that is, on the same layer as the following second flat layer PLN2, as Figure 14j shown.

[0140] S11. Form a second flat layer PLN2 on the side of the source electrode T13 and the drain electrode T14 of the first thin-film transistor T1 prepared in S10 away from the substrate 01. After patterning and typesetting by exposure and etching on the second flat layer PLN2, leave a via 321 for the optoelectronic structure layer 32 to be coated of the photoelectric sensor 03 and a via 331 for the second electrode layer 33, as Figure 14k shown.

[0141] While fabricating the light-emitting device in S14, coat the optoelectronic structure layer 32 of the photoelectric sensor 03 in the reserved vias. The optoelectronic structure layer 32 includes a second hole transport layer HTL2, an optoelectronic material layer (OPD material), and a second exciton blocking layer ETL2. Among them, the second exciton blocking layer can also be an ink material and can be directly typeset by ink printing. Then, apply photoresist tape, perform oxygen etching typesetting, and finally deposit ITO or Mg or Ag material as the second electrode layer 33.

[0142] It should be noted that on the substrate 01, the second flat layer PLN2 in the island region and the bridge region is fabricated simultaneously; meanwhile, the photoelectric sensor 03 is fabricated in the island region and the bridge region respectively.

[0143] S12. Form a sixth connection via Via6 penetrating the second flat layer PLN2 in the region where the positive projection of the source electrode T23 of the second thin-film transistor T2 prepared in S10 is located, and form a third electrode layer 41 of the light-emitting device on the side of the second flat layer PLN2 away from the substrate 01. The third electrode layer 41 is electrically connected to the source electrode T23 of the second thin-film transistor T2 through the sixth connection via Via6, as Figure 14l shown.

[0144] S13. Form a pixel defining layer PDL on the side of the second flat layer PLN2 away from the substrate 01, and form a slot at a set position, as Figure 14m shown.

[0145] It should be noted that the pixel defining layer PDL is only formed on the side of the second flat layer PLN2 in the island region away from the substrate 01.

[0146] S14. Form a light-emitting layer 42 of the light-emitting device on the side of the pixel defining layer PDL away from the substrate 01, as Figure 14n shown.

[0147] The light-emitting device 04 includes a third electrode layer 41, a fourth electrode layer 43, and a light-emitting layer 42. The third electrode layer 41 is an anode, the fourth electrode layer 43 is a cathode, and the light-emitting layer 42 includes a first hole transport layer HTL1 and a first exciton blocking layer ETL1. Among them, on the side of the pixel defining layer PDL facing away from the substrate 01, the first hole transport layer HTL1, the first exciton blocking layer ETL1, and the fourth electrode layer 43 are sequentially deposited. The first hole transport layer HTL1 is multiplexed as the second hole transport layer HTL2, and the first exciton blocking layer ETL1 is multiplexed as the second exciton blocking layer ETL2. For the specific connection structure that is multiplexed, Figure 14n is not shown.

[0148] It should be noted that when preparing the first hole transport layer HTL1, the first exciton blocking layer ETL1, and the fourth electrode layer 43, the optoelectronic structure layer 32 and the second electrode layer 33 of the optoelectronic sensor 03 are coated simultaneously. The specific preparation process is as in S11.

[0149] S15. Form a packaging film layer 05 on the outer walls of the respective film layers located in the island region and the bridge region, as Figure 14o shown.

[0150] In some examples, as Figure 12 shown, the optoelectronic sensor 03 is prepared by evaporation. To further clearly describe the preparation of each film layer, taking Figure 5 the driving circuit as an example, after preparing the first thin-film transistor T1, the second thin-film transistor T2, and the light-emitting device 04 according to the preparation process of steps S1 to S14, the optoelectronic sensor 03 is evaporated on the side walls of the respective film layers located between the island region and the bridge region. For the optoelectronic sensor 03 located in the island region, the first electrode layer 31, the second hole transport layer HTL2 (such as HTL material), the optoelectronic material layer (such as OPD light-emitting material), the second exciton blocking layer ETL2 (such as ETL material), and the second electrode layer 33 are sequentially stacked along the direction from the island region to the bridge region. For the optoelectronic sensor 03 located in the bridge region, the first electrode layer 31, the second hole transport layer HTL2, the optoelectronic material layer, the second exciton blocking layer ETL2, and the second electrode layer 33 are sequentially stacked along the direction from the bridge region to the island region.

[0151] Among them, the drain T14 of the first thin-film transistor T1 is multiplexed as the first electrode layer 31 (anode) of the optoelectronic sensor 03, the first hole transport layer HTL1 of the light-emitting device 04 is multiplexed as the first hole transport layer HTL1 of the optoelectronic sensor 03, the optoelectronic material layer is deposited on the side of the first hole transport layer HTL1 close to the via hole in the hole region, the first exciton blocking layer ETL1 of the light-emitting device 03 is multiplexed as the second exciton blocking layer ETL2 of the optoelectronic sensor 03, and the fourth electrode layer 43 of the light-emitting device 03 is multiplexed as the second electrode layer 33.

[0152] If the sidewalls of the film layers located between the island region and the bridge region form a preset inclination angle with the substrate 01, the formed photoelectric sensor 03 by evaporation is in a large slope shape; if the sidewalls of the film layers located between the island region and the bridge region are stepped, the formed photoelectric sensor 03 by evaporation is stepped. Specifically, reference can be made to the embodiment in which the photoelectric sensor 03 is in a stepped structure in the above embodiment, specifically as Figure 13 shown.

[0153] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, including the display substrate 100 in the above embodiment. Since the principle of the problem solved by the display device in the embodiment of the present disclosure is similar to that of the above display substrate 100 in the embodiment of the present disclosure, the structures of the display substrate 100 included in the display device can refer to the display substrate 100 provided in the above embodiment, and the repeated parts will not be described again.

[0154] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure. However, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A display substrate having an island region, a hole region, and a bridge region, with the hole region located between the island region and the bridge region; the display substrate includes a substrate and a circuit layer disposed on the substrate. The circuit layer includes a driving circuit located in the island region and vias located in the hole region; the circuit layer further includes at least one photosensor electrically connected to the driving circuit, and the photosensor is positioned near the hole region in the circuit layer; the photosensor includes a first electrode layer, a photo - electric structure layer, and a second electrode layer stacked on top of each other. The photosensor is located in the island region, and the first electrode layer, the photo - electric structure layer, and the second electrode layer of the photosensor are sequentially arranged along the direction from the island region to the bridge region; and / or, the photosensor is located in the bridge region, and the first electrode layer, the photo - electric structure layer, and the second electrode layer of the photosensor are sequentially arranged along the direction from the bridge region to the island region.

2. The display substrate according to claim 1, wherein, The driving circuit includes a first thin - film transistor for driving the photosensor, the drain of the first thin - film transistor is electrically connected to the first electrode layer of the photosensor, and the drain of the first thin - film transistor is multiplexed as the first electrode layer.

3. The display substrate according to claim 1, wherein, The driving circuit includes a first thin - film transistor for driving the photosensor, the gate of the first thin - film transistor is electrically connected to the first electrode layer of the photosensor, and the gate of the first thin - film transistor is multiplexed as the first electrode layer.

4. The display substrate according to claim 1, wherein, A light - emitting device is disposed on the side of the circuit layer away from the substrate; the light - emitting device includes a third electrode layer, a fourth electrode layer, and a light - emitting layer disposed between the third electrode layer and the fourth electrode layer. The third electrode layer is multiplexed as the first electrode layer, and the fourth electrode layer is multiplexed as the second electrode layer.

5. The display substrate according to any one of claims 1-4, wherein, The photosensor is located in the island region; the circuit layer includes a first thin - film transistor located in the island region, a buffer layer, a first insulating layer, a second insulating layer, and a third insulating layer that are located in the island region and are sequentially disposed on the substrate. The first thin - film transistor includes an active layer, a gate, a source, and a drain; the active layer is disposed on the side of the buffer layer away from the substrate; the gate is disposed on the side of the first insulating layer away from the substrate, and the gate and the active layer overlap at least partially in the orthographic projection on the substrate; the source and the drain are disposed on the side of the second insulating layer away from the substrate, the source is electrically connected to the source region of the active layer through a first connection via, and the drain is electrically connected to the drain region of the active layer through a second connection via. The photosensor is on the same layer as any one of the first insulating layer, the second insulating layer, or the third insulating layer. Alternatively, the photosensor is located between any two adjacent layers of the first insulating layer, the second insulating layer, and the third insulating layer.

6. The display substrate according to claim 5, wherein, The first electrode layer includes a first sub - structure, a second sub - structure, and a third sub - structure connecting the first sub - structure and the second sub - structure. The first sub-structure, the third sub-structure, and the second sub-structure are sequentially arranged along the direction from the substrate to the circuit layer.

7. The display substrate according to claim 6, wherein The first sub-structure and the second sub-structure are trapezoidal structures; the third sub-structure is a rectangular structure.

8. The display substrate according to claim 6, wherein, The second sub-structure and the third sub-structure are electrically connected to the drain of the first thin-film transistor, and the drain of the first thin-film transistor is multiplexed as the second sub-structure and the third sub-structure; the first sub-structure is electrically connected to the third electrode layer, and the third electrode layer is multiplexed as the first sub-structure.

9. The display substrate according to claim 5, wherein, The first electrode layer is arranged as a rectangular structure.

10. The display substrate according to any one of claims 1-3, wherein, The photoelectric sensor is located in the bridge area; the circuit layer includes a buffer layer, a first insulating layer, and a third insulating layer that are located in the bridge area and are sequentially arranged on the substrate. The photoelectric sensor is on the same layer as the first insulating layer or the third insulating layer. Alternatively, the photoelectric sensor is located between the first insulating layer and the third insulating layer.

11. The display substrate according to claim 10, wherein, The driving circuit includes a first thin-film transistor for driving the photoelectric sensor; a third connection via is provided on the first insulating layer. The drain of the first thin-film transistor is electrically connected to the first electrode layer through the third connection via, and the drain of the first thin-film transistor is multiplexed as the first electrode layer; or, the gate of the first thin-film transistor is electrically connected to the first electrode layer through the third connection via, and the gate of the first thin-film transistor is multiplexed as the first electrode layer.

12. The display substrate according to any one of claims 1-4, wherein The via in the via area is located between the island area and the bridge area; the photoelectric sensor is located on the sidewalls of the film layers between the island area and the bridge area; the sidewalls form a preset inclination angle with the substrate.

13. The display substrate according to any one of claims 1-4, wherein The via in the via area is located between the island area and the bridge area; the photoelectric sensor includes a multi-stage photoelectric structure; the multi-stage photoelectric structure is located on the sidewalls of the film layers between the island area and the bridge area. The first sub-photoelectric structure of the i-th stage photoelectric structure is connected to the second sub-photoelectric structure of the (i - 1)-th stage photoelectric structure; the second sub-photoelectric structure of the i-th stage photoelectric structure is connected to the first sub-photoelectric structure of the (i + 1)-th stage photoelectric structure; 0 < i ≤ N, and N is a positive integer greater than or equal to 2. The included angle range between the first sub-photoelectric structure of the i-th stage photoelectric structure and the second sub-photoelectric structure of the (i - 1)-th stage photoelectric structure is between 85° and 105°; the included angle range between the second sub-photoelectric structure of the i-th stage photoelectric structure and the first sub-photoelectric structure of the (i + 1)-th stage photoelectric structure is between 85° and 105°; the included angle range between the first sub-photoelectric structure and the second sub-photoelectric structure of the i-th stage photoelectric structure is between 85° and 105°.

14. A method for preparing a display substrate, wherein, The display substrate has an island area, a via area, and a bridge area, and the via area is located between the island area and the bridge area; the manufacturing method of the display substrate includes: Forming a circuit layer on the substrate; forming a driving circuit located in the island area and a via located in the via area on the circuit layer. At least one photosensor electrically connected to the driving circuit is further formed on the circuit layer, and the position of the photosensor on the circuit layer is close to the hole region; the photosensor includes a first electrode layer, a photo structure layer, and a second electrode layer which are stacked. The photosensor is located in the island region, and the first electrode layer, the photo structure layer, and the second electrode layer of the photosensor are sequentially arranged along the direction from the island region to the bridge region; and / or, the photosensor is located in the bridge region, and the first electrode layer, the photo structure layer, and the second electrode layer of the photosensor are sequentially arranged along the direction from the bridge region to the island region.

15. A display device, wherein, A display substrate includes any one of claims 1 to 13.

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