Sub-pixel driving circuit and display device including the same capable of operating in low-quality mode and high-quality mode using the same pixel memory

Abstract

A sub-pixel driving circuit and a display device including the same are disclosed. The sub-pixel driving circuit can include a light emitting element driving line connected between a light emitting element and a positive power source or between the light emitting element and a negative power source, a first transistor connected in series on the light emitting element driving line and turned on according to a PWM signal, a first current driving part and a second current driving part connected in series on the light emitting element driving line and connected in parallel to each other, and a second transistor connected between a reference voltage source and the second current driving part and turned on or off according to a display mode selection signal, wherein the reference voltage source is connected to apply a reference voltage to the first current driving part and the second current driving part.

Description

Technical Field

[0001] The present invention relates to displays, and more specifically, to a display device capable of operating in both low-resolution and high-resolution modes using the same pixel memory. Background Technology

[0002] This application claims priority to Korean Patent Application No. 10-2020-0040501, filed on April 2, 2020, the contents of which are incorporated herein by reference.

[0003] An active matrix liquid crystal display (LCD) remains illuminated throughout the information updates of all different pixels. In a digital format, where each pixel includes internal memory, data related to the light emitted by the pixel during one frame is stored, and brightness is controlled using PWM (Pulse Width Modulation). Generally, if a pixel contains three or four light-emitting elements (e.g., LEDs), each light-emitting element is called a sub-pixel.

[0004] Figure 9 This is a circuit diagram of the driving circuit for sub-pixels in previous technologies.

[0005] Reference Figure 9 This allows us to confirm the driving circuit diagram and signal timing of the sub-pixels. For pixels driven by digital PWM, image data is stored in the pixel memory for a predetermined time (pixel programming). Furthermore, based on the image data stored in the pixel memory, the sub-pixels emit light during their on-duty period within one frame. At this time, the brightness of the sub-pixels is controlled according to the PWM method. The gray clock signal used for PWM control is as follows... Figure 9 As shown in the example, the input is to the driving circuit of the sub-pixel. The number of grayscale clock signals (MSB, MSB-1, MSB-2, ..., LSB) is determined according to the number of bits of the image data. The PWM control unit outputs the grayscale clock signals to the light-emitting element (LED) based on the image data stored in the pixel's built-in memory. As a result, the light-emitting element (LED) emits light during its on-duty period within one frame.

[0006] The color depth of the monitor The depth and the light-emitting element (LED) can be precisely adjusted during one frame. The degree of on-duty time is related to the color depth of a display. Therefore, the color depth of a display varies depending on the number of bits of memory built into each pixel.

[0007] On the other hand, typical pixel-based internal memory consists of SRAM (Static Random-Access Memory) cells corresponding to the number of bits. Therefore, to achieve high-quality displays, the more SRAM cells there are, the higher the power consumption, the larger the pixel circuitry, and the more power and circuitry are required to control the data transmission process. Summary of the Invention

[0008] Technical issues

[0009] The purpose of this specification is to provide a sub-pixel driving circuit that can operate in low-resolution and high-resolution modes using the same pixel memory, and a display device including the same.

[0010] This specification does not include, but is not limited to, the topics mentioned above. Other topics not mentioned are those that can be clearly understood by a person skilled in the art from the following description.

[0011] Technical solution

[0012] To address the aforementioned technical challenges, the sub-pixel driving circuit of this specification may include: a light-emitting element driving line, which connects the light-emitting element to a positive power supply or the light-emitting element to a negative power supply; a first transistor, which is connected in series on the light-emitting element driving line and is turned on according to a PWM signal; a first current driving unit and a second current driving unit, which are connected in series on the light-emitting element driving line and electrically connected in parallel; and a second transistor, which is connected between a reference voltage source and the second current driving unit and is turned on or off according to a display mode selection signal, wherein the reference voltage source is configured to supply a reference voltage to the first current driving unit and the second current driving unit.

[0013] According to one embodiment of this specification, the first current driving unit may include: a third transistor connected in series on the light-emitting element driving line, which is turned on according to the positive power supply; and a fourth transistor connected in series on the light-emitting element driving line, which is turned on according to a reference voltage. Furthermore, according to one embodiment of this specification, the second current driving unit may include: a fifth transistor connected in series on the light-emitting element driving line, which is turned on according to the positive power supply; and a sixth transistor connected in series on the light-emitting element driving line, which is turned on according to the reference voltage when the second transistor is turned on.

[0014] At this time, the second transistor can be connected between the reference voltage source and the sixth transistor.

[0015] The sub-pixel driving circuit of this specification may further include a seventh transistor, which is connected between the positive power supply and the sixth transistor, and is turned on or off according to the display mode selection signal.

[0016] According to one embodiment of this specification, the first transistor, the fourth transistor, the sixth transistor, and the seventh transistor can be P-type MOSFETs, and the second transistor, the third transistor, and the fifth transistor can be N-type MOSFETs.

[0017] The sub-pixel driving circuit according to this specification can be a component of a sub-pixel circuit, wherein the sub-pixel circuit includes: a sub-pixel driving circuit; a light-emitting element; a pixel memory, the pixel memory storing data related to driving the light-emitting element; and

[0018] A PWM control unit processes signals for controlling the brightness of the light-emitting element.

[0019] At this time, the pixel memory can be five static random-access memory (SRAM) units used to store five bits of data related to the driving of the light-emitting element.

[0020] To address the aforementioned issues, the display device described in this specification may include: a display panel comprising a plurality of sub-pixel circuits; a scan driving circuit that sequentially drives sub-pixel circuits arranged in a row direction among a plurality of scan lines connected to the pixel memory of each sub-pixel circuit; a data driving circuit that outputs signals related to the driving of each light-emitting element to each pixel memory via a plurality of data lines connected to the pixel memory of each sub-pixel circuit; a grayscale clock signal output circuit that outputs a width-adjusted pulse signal (hereinafter referred to as "grayscale clock signal") to the PWM control unit included in each sub-pixel circuit to adjust the brightness of the sub-pixel; and a timing control circuit that outputs signals for controlling the scan driving circuit, the data driving circuit, and the grayscale clock signal output circuit, and outputs a display mode selection signal to the second transistor included in the plurality of sub-pixel circuits.

[0021] According to one embodiment of this specification, the timing control circuit can output the display mode selection signal to turn on the second transistor within a 1-frame interval when the first mode is the default image quality mode, and output the display mode selection signal to turn on the second transistor within any one of the two sub-frames included in the 1-frame interval when the second mode is the high image quality mode, and turn off the second transistor within the remaining sub-frame interval.

[0022] According to one embodiment of this specification, the timing control circuit can output a control signal to the grayscale clock signal output circuit in the first mode to output the grayscale clock signal during a preset time (T), and in the second mode, output a control signal to the grayscale clock signal output circuit to output the grayscale clock signal within each subframe interval. The grayscale clock signal is output during period T.

[0023] According to one embodiment of this specification, the timing control circuit can output a control signal in the first mode to cause the grayscale clock signal output circuit to output a grayscale clock signal. The grayscale clock signal, where k is the number of bits stored in the pixel memory, is used in the second mode to output a control signal so that the grayscale clock signal output circuit outputs a grayscale clock signal. The grayscale clock signal, where k is the number of bits stored in the pixel memory.

[0024] According to one embodiment of this specification, the timing control circuit can output a control signal in the first mode to cause the data driving circuit to output a signal related to the driving of each light-emitting element to each pixel memory once, and in the second mode, output a control signal to cause the data driving circuit to output two signals related to the driving of each light-emitting element to each pixel memory corresponding to each subframe interval.

[0025] The display device described in this specification can be a component of a wearable device, wherein the wearable device includes: a display device; a first power supply that supplies power to the display device; and a communication module that receives image data from a main device and provides it to the timing control circuit, wherein the main device transmits data related to the image displayed on the display device (hereinafter referred to as "image data").

[0026] At this time, the communication module can receive image data wirelessly with the main device. Additionally, the main device can receive power from a second power supply.

[0027] Other specific aspects of the invention are contained in the detailed description and accompanying drawings.

[0028] Invention Effects

[0029] According to one aspect of this specification, a display device is provided that can operate in both low-resolution and high-resolution modes using the same pixel memory.

[0030] According to another aspect of this specification, compared to conventional display panels that provide the same image quality, a display panel with a smaller pixel memory footprint can be provided.

[0031] According to another aspect of this specification, operation is optional, only required when high-quality images are needed, thus reducing power consumption compared to conventional display panels. Therefore, more efficient power management can be achieved in wearable devices that require a display but have limited battery capacity.

[0032] The effects of the present invention are not limited to those mentioned above, and other effects not mentioned are clearly understood by those skilled in the art from the following description. Attached Figure Description

[0033] Figure 1 This is a circuit diagram of a sub-pixel driving circuit according to an embodiment of this specification.

[0034] Figure 2 This is a circuit diagram showing the operation when the display mode selection signal is at a logic high level.

[0035] Figure 3 This is a circuit diagram showing the operation when the display mode selection signal is at a logic low level.

[0036] Figure 4 This is a block diagram that briefly illustrates the structure of the sub-pixel circuit in this specification.

[0037] Figure 5 This is a block diagram that briefly illustrates the configuration of a display device according to an embodiment of this specification.

[0038] Figure 6 This is a reference diagram showing the emission time of the light-emitting element in both the first and second modes.

[0039] Figure 7 This is a schematic diagram of a wearable device including the display device 100 described in this specification.

[0040] Figure 8 This is a schematic diagram illustrating smart glasses operating in both the first and second modes.

[0041] Figure 9 This is a circuit diagram of the driving circuit for sub-pixels in previous technologies. Detailed Implementation

[0042] If you refer to the following and appendix Figure 1As described in detail, the advantages, features, and methods of achieving the invention disclosed herein will become clear. However, this specification is not limited to the embodiments disclosed below and may be embodied in many different forms. These embodiments are provided only to make the disclosure of this specification more complete and to fully inform those skilled in the art of this specification (hereinafter referred to as "the art practitioner") of the scope of this specification. The scope of this specification is defined only by the scope of the claims.

[0043] The terminology used in this specification is for describing embodiments and is not intended to limit the scope of this specification. In this specification, the singular includes the plural unless otherwise specifically mentioned. The terms "comprises" and / or "comprising" as used in this specification do not exclude the presence or addition of one or more other constituent elements besides those mentioned.

[0044] Throughout this specification, the same reference numerals refer to the same constituent elements, and "and / or" includes each of the mentioned constituent elements and all combinations thereof. Although terms such as "first," "second," etc., are used to describe multiple constituent elements, these constituent elements are not limited by these terms. These terms are only used to distinguish one constituent element from others. Therefore, the first constituent element mentioned below can, within the technical concept of this invention, also be a second constituent element.

[0045] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) shall be interpreted in a meaning commonly understood by one of ordinary skill in the art to which this specification pertains. Furthermore, terms defined in commonly used dictionaries shall not be over- or over-interpreted unless explicitly and specifically defined.

[0046] In the following embodiments, "on" as used for element states can refer to the active state of the element, and "off" can refer to the inactive state of the element. "On" as used for signals received by the element can refer to the signal that activates the element, and "off" can refer to the signal that deactivates the element. Elements can be activated by high or low voltages. For example, a P-type transistor is activated by a low voltage, and an N-type transistor is activated by a high voltage. Therefore, the "on" voltage for P-type and N-type transistors should be understood as opposite (low to high) voltage levels.

[0047] When referring to one element as "connected to" or "coupled to" another element, it includes both direct connection or coupling to the other element and cases where other elements are inserted in between. Conversely, when referring to one element as "directly connected to" or "directly coupled to" another element, it indicates that no other elements are present in between. Embodiments of the invention are described below with reference to the accompanying drawings.

[0048] Figure 1 This is a circuit diagram of a sub-pixel driving circuit according to an embodiment of this specification.

[0049] Reference Figure 1 The light-emitting element (LED) can be identified. Typically, a pixel includes 3 or 4 light-emitting elements (e.g., LEDs), and each light-emitting element is called a sub-pixel. The sub-pixel driving circuit 10 in this specification is a circuit used to operate the light-emitting elements (LEDs). The sub-pixel driving circuit 10 in this specification may include light-emitting element driving lines connecting the light-emitting element (LED) to a positive power supply (VDD) or to a negative power supply (VEE). Figure 1 In the example shown, the sub-pixel driving circuit 10 is a light-emitting element driving line connecting the light-emitting element (LED) and the positive power supply (VDD).

[0050] The sub-pixel driving circuit 10 in this specification may include a first transistor T1, a first current driving unit 11, a second current driving unit 12, and a second transistor T2. The first transistor T1 may be connected in series on the light-emitting element driving line and is turned on according to a PWM signal. The first current driving unit 11 and the second current driving unit 12 may be connected in series on the light-emitting element driving line and electrically connected in parallel with each other. The second transistor T2 may be connected between a reference voltage source (not shown) and the second current driving unit 12, and is activated according to a display mode selection signal V. MODE The reference voltage source can be connected to apply a reference voltage V to the first current drive unit 11 and the second current drive unit 12. REF .

[0051] According to one embodiment of this specification, the first current driving unit 11 may include a third transistor T3 and a fourth transistor T4. The third transistor T3 may be connected in series on the light-emitting element driving line and is turned on according to the positive power supply (VDD). The fourth transistor T4 may be connected in series on the light-emitting element driving line and is turned on according to a reference voltage. On the other hand, the reference voltage VDD... REF A voltage value that can be applied to the gate terminal of the fourth transistor T4 to turn the fourth transistor T4 on is provided.

[0052] According to one embodiment of this specification, the second current driving unit 12 may include a fifth transistor T5 and a sixth transistor T6. The fifth transistor T5 may be connected in series on the light-emitting element driving line and is turned on according to the positive power supply (VDD). The sixth transistor T6 may be connected in series on the light-emitting element driving line and, when the second transistor T2 is turned on, is turned on according to the reference voltage VDD. REF Turn on. At this time, the second transistor T2 can be connected between the reference voltage source and the sixth transistor T6. On the other hand, the reference voltage V... REF A voltage value that can be applied to the gate terminal of the sixth transistor T6 to turn the sixth transistor T6 on is provided.

[0053] In one embodiment of this specification, the sub-pixel driving circuit 10 may further include a seventh transistor T7. The seventh transistor T7 may be connected between the positive power supply (VDD) and the sixth transistor T6, according to the display mode selection signal V. MODE Turn it on or off.

[0054] The description is based on an embodiment in which the first transistor T1, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 are P-type MOSFETs, and the second transistor T2, the third transistor T3, and the fifth transistor T5 are N-type MOSFETs, so as to provide a more specific understanding of the operation of a sub-pixel driving circuit 10 according to an embodiment of this specification.

[0055] The sub-pixel driving circuit 10 described in the specification can operate in two modes. The first mode is a "default image quality mode," and the second mode is a "high image quality mode." The default image quality mode is the mode that operates when displaying a relatively low-quality image compared to the high image quality mode. In the first mode, the display mode selection signal V... MODEA logic high signal can be input. In the second mode, the display mode selection signal V... MODE It can input logic high and logic low signals.

[0056] First, the display mode selection signal V is input from a logic high level. MODE The description begins at that time. Figure 2 This is a circuit reference diagram showing the operation when the display mode selection signal is at a logic high level. The first transistor T1 can operate under the PWM signal V. PWM The display mode selection signal V is enabled (on) or disabled (off) when the logic level is high or low. MODE The voltage level is logic high, therefore the second transistor T2 is in the on state. The gate terminal of the third transistor T3 is connected to the positive power supply (VDD), therefore the third transistor T3 is in the on state according to the positive power supply (VDD). The reference voltage V REF The voltage applied to the gate terminal of the fourth transistor T4 causes the fourth transistor T4 to be in the on state according to the reference voltage. The gate terminal of the fifth transistor T5 is connected to the positive power supply (VDD), and therefore the fifth transistor T5 is in the on state according to the positive power supply (VDD). The gate terminal of the sixth transistor T6 is connected to the second transistor T2, and the second transistor T2 is in the on state, therefore the reference voltage VDD is applied to the gate terminal of the fourth transistor T4, causing the fourth transistor T4 to be in the on state. REF An application is made to the gate terminal of the sixth transistor T6, turning the sixth transistor T6 into the on state. This is due to the display mode selection signal V. MODE The logic level is high, therefore the seventh transistor T7 is off. In summary, the third transistor T3, fourth transistor T4, fifth transistor T5, and sixth transistor T6 are all on. Therefore, driving current flows into both the first current driving section 11 and the second current driving section 12. When the current flowing into the first current driving section 11 is referred to as "I1" and the current flowing into the second current driving section 12 as "I2", the current applied to the light-emitting element (LED) is "I Total =I1+I2.

[0057] Then, the display mode selection signal V is input from a logic low level. MODE The description begins at that time. Figure 3This is a circuit reference diagram showing the operation when the display mode selection signal is at a logic low level. The first transistor T1 can operate under the PWM signal V. PWM The display mode selection signal V is enabled (on) or disabled (off) when the logic level is high or low. MODE The voltage level is logic low, therefore the second transistor T2 is in the off state. The gate terminal of the third transistor T3 is connected to the positive power supply (VDD), therefore the third transistor T3 is in the on state according to the positive power supply (VDD). Because the reference voltage V... REF The reference voltage V is applied to the gate terminal of the fourth transistor T4, thus turning the fourth transistor T4 on according to the reference voltage. The gate terminal of the fifth transistor T5 is connected to the positive power supply (VDD), thus turning the fifth transistor T5 on according to the positive power supply (VDD). The gate terminal of the sixth transistor T6 is connected to the second transistor T2, which is off, therefore the reference voltage V is not applied to the gate terminal of the sixth transistor T6. REF The sixth transistor T6 is turned off. This is due to the display mode selection signal V. MODE The voltage level is logic low, therefore the seventh transistor T7 is in the on state. Because the seventh transistor T7 is on, the positive power supply (VDD) can be applied to the gate terminal of the sixth transistor T6, thus the gate terminal voltage of the sixth transistor T6 does not float, reliably turning the sixth transistor T6 off. In summary, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are on, but the sixth transistor T6 is off. Therefore, only the first current drive section 11 receives the drive current I1, and no drive current I2 flows into the second current drive section 12. The current applied to the light-emitting element (LED) becomes "I Total =I1".

[0058] As briefly mentioned above, in the first mode, the display mode selection signal V MODE Input a logic high signal. Therefore, during operation in the first mode, "I Total A current of "=I1+I2" can be applied to the light-emitting element (LED). Furthermore, in the second mode, the display mode selection signal V... MODEIt can accept logic high and logic low signals. Therefore, during operation in the second mode, "I Total =I1+I2” and “I Total A current of I1 can be applied to the light-emitting element (LED). If the transistors constituting the first current drive unit 11 and the second current drive unit 12 have the same physical characteristics, then the first current drive unit 11 and the second current drive unit 12 can be applied with the same reference voltage V. REF Therefore, "I1 = I2". Thus, the first mode is where the current flows into the same "I" at a constant rate over a given time period. Total =2I1” current pattern. Moreover, the second pattern flows into the same “I” current during a predetermined time period. Total After "=2I1", it flows into "I" again within a predetermined time period. Total =I1” current, that is, the mode of current change. The characteristics of the first mode and the characteristics of the second mode can be used to provide the basic principle of a display that operates in two image quality modes (low image quality / high image quality).

[0059] On the other hand, the sub-pixel driving circuit 10 in this specification can be a component of the sub-pixel circuit.

[0060] Figure 4 This is a block diagram that briefly illustrates the structure of the sub-pixel circuit in this specification.

[0061] Reference Figure 4 The sub-pixel circuit 40 in this specification may include a sub-pixel driving circuit 10, a light-emitting element (LED), a pixel memory 20, and a PWM control unit 30.

[0062] The sub-pixel driving circuit 10 has been previously referred to. Figures 1 to 3 Since it has already been described, I will not repeat it here.

[0063] The light-emitting element (LED) can be a light-emitting diode (LED). The LED can be red (R), green (G), blue (B), or white (W), and can have many other colors. Furthermore, the LED can be a micro LED (typically an LED with a width of 1–100 μm) or an OLED. The type of light-emitting element does not constitute a limitation on the sub-pixel circuit 40 described in this specification.

[0064] The pixel memory 20 can store data related to driving the light-emitting element (LED). The PWM control unit 30 can process signals for controlling the brightness of the light-emitting element (LED). The sub-pixel circuit 40 in this specification, as a MIP (Memory-In-Pixel) pixel with internal memory, is a sub-pixel of an active matrix display panel used to make the light-emitting element emit light according to the brightness determined by the data stored in the pixel memory during one frame. In this case, the brightness of the sub-pixel is controlled according to the PWM signal. The PWM control algorithm is well-known to those skilled in the art and will not be described in detail here.

[0065] According to one embodiment of this specification, the pixel memory 20 may include five static random-access memory (SRAM) cells for storing five bits of data related to driving the light-emitting element (LED). The color depth of the display varies depending on the number of bits in the pixel memory. A commonly used 256-color display typically has an 8-bit pixel memory. A 16-bit memory is also used for high resolution, and a 10-bit memory can be used for gamma correction occurring in 8-bit displays. In this specification, a display panel using half the number of bits of memory, i.e., a 5-bit memory, will be described as an example, compared to a display panel using a 10-bit memory. How to achieve the same image quality as a display panel using a 10-bit memory, and how to minimize power consumption, despite the half-sized memory, will be described.

[0066] Figure 5 This is a block diagram that briefly illustrates the configuration of a display device according to an embodiment of this specification.

[0067] Reference Figure 5 The display device 100 in this specification may include a display panel 110, a scan driving circuit 120, a data driving circuit 130, a grayscale clock signal output circuit 140, and a timing control circuit 150.

[0068] The display panel 110 may include multiple sub-pixel circuits 40 as described in this specification. Three or more... These 4 sub-pixels Circuit 40 can be aggregated to form a pixel (PX). The multiple pixels... Each pixel (PX) can be arranged in a matrix shape by arranging m×n (m and n are natural numbers). However, the pattern of the multiple pixels can be arranged into various patterns, such as a Z-shape, depending on the embodiment.

[0069] The display panel 110 can be implemented as one of the following: LCD (liquid crystal display), LED (light emitting diode) display, OLED (organic LED) display, AMOLED (active-matrix OLED) display, ECD (electrochromic display), DMD (digital mirror device), AMD (actuated mirror device), GLV (grating light valve), PDP (plasma display panel), ELD (electroluminescent display), and VFD (vacuum fluorescent display), or as other types of flat panel displays or flexible displays. In this specification, an LED display panel will be described as an example.

[0070] Each pixel (PX) may include a pixel circuit that drives multiple sub-pixels. The pixel circuit can drive the sub-pixel circuit 40 to start or stop based on control signals output by the scan driving circuit 120 and / or the data driving circuit 130. The sub-pixel circuit 40 may include at least one thin-film transistor, implemented in a stacked structure on a semiconductor wafer.

[0071] The display panel 110 may include scan lines SL1 to SL2 arranged in a raw direction. m And the data lines DL1 to DL2 arranged in the column direction n Pixels (PX) can be located on scan lines SL1 to SL2. m With data cable DL1~DL n The intersection point. Each pixel (PX) can intersect with any scan line SL. k and any data cable DL k Connection. The scan lines SL1 to SL m The data lines DL1 to DL2 can be connected to the scan drive circuit 120. n It can be connected to the data drive circuit 130.

[0072] The scan drive circuit 120 can drive the scan lines SL1 to SL2. mThis causes the sub-pixel circuits arranged along the row direction in multiple scan lines connected to the pixel memory of each sub-pixel circuit to be driven sequentially. For example, during the first scan driving time, the pixel connected to the first scan line SL1 can be driven, and during the second scan driving time, the pixel connected to the second scan line SL2 can be driven. The operation of the scan driving circuit 120 in this specification will be described in more detail later.

[0073] The data driving circuit 130 can be connected via the data lines DL1 to DL2 n Multiple data lines connected to the pixel memory of each sub-pixel circuit output signals (grayscale correlation signals) related to the driving of each light-emitting element to each pixel memory. A data line connects to multiple pixels along the vertical direction, but grayscale correlation signals can be input only to pixels connected to the scan line selected by the scan driving circuit 120.

[0074] The grayscale clock signal output circuit 140 can output a pulse signal with width adjustment (hereinafter referred to as "grayscale clock signal") to the PWM control unit 30 included in each sub-pixel circuit to adjust the brightness of the sub-pixel.

[0075] The timing control circuit 150 can output signals to control the scan drive circuit 120, the data drive circuit 130, and the grayscale clock signal output circuit 140. The operating algorithms of the timing control circuit 150, the scan drive circuit 120, the data drive circuit 130, and the grayscale clock signal output circuit 140 are well-known to those skilled in the art and will not be described in detail here. Unlike conventional display devices, the timing control circuit 150 can output a display mode selection signal (V) to the second transistor T2 included in the plurality of sub-pixel circuits 40. MODE ).

[0076] According to one embodiment of this specification, the display mode selection signal (V) MODE This can be a first mode signal as the default image quality mode and a second mode signal as a high image quality mode. In this specification, "high image quality mode" refers to an image quality with a deeper color depth compared to the default image quality mode.

[0077] Figure 6 This is a reference diagram showing the emission time of the light-emitting element in both the first and second modes.

[0078] Figure 6 (a) is a timing diagram showing the on-time operation of the light-emitting elements in the first mode (default image quality mode). Figure 6 (b) is a timing diagram of the on-time of the light-emitting element in the second mode (high-definition mode).

[0079] The first mode and the second mode can have the same frame interval. In this case, the second mode can be composed of two subframes SF that comprise one frame. The two subframes SF are referred to as "first subframe SF1" and "second subframe SF2" respectively.

[0080] The timing control circuit 150 described in this specification can output the display mode selection signal (V) when the first mode is used as the default image quality mode. MODE This allows the second transistor T2 to be turned on within a one-frame interval. Furthermore, the timing control circuit 150 described in this specification can output the display mode selection signal (V) when the second mode is used as a high-quality mode. MODE So that the second transistor T2 is turned on in either of the two subframes (e.g., SF1) of a frame, and turned off in the remaining subframe (e.g., SF2).

[0081] Furthermore, the timing control circuit 150 can output a control signal to the grayscale clock signal output circuit 140 in the first mode to output the grayscale clock signals GC1 to GC5 during a preset time T. Moreover, the timing control circuit 150 can output a control signal to the grayscale clock signal output circuit 140 in the second mode to output the grayscale clock signals within each subframe interval. The grayscale clock signals GC1 to GC5 are output during period T. For reference, if all grayscale clock signals GC1 to GC5 are concentrated, it becomes the on-time of the light-emitting element.

[0082] According to the control algorithm of the timing control circuit 150, the amount of charge Q flowing into the light-emitting element (LED) during one frame in the first mode (default image quality mode) and the second mode (high image quality mode) will be known. First, in the first mode, the second transistor T2 is turned on, so the current flowing into the light-emitting element (LED) is "2I1". Furthermore, in the first mode, the on-time of the light-emitting element (LED) is "T". Therefore, in the first mode, the amount of charge Q flowing into the light-emitting element (LED) during one frame is "2I1 × T". Conversely, in the second mode, within the first subframe interval, the on-time of the light-emitting element (LED) is "2I1 × T". At this time, the current flowing into the light-emitting element (LED) is "2I1". In the second mode, within the second subframe interval, the on-time of the light-emitting element (LED) is "T". At this point, the current flowing into the light-emitting element (LED) is "I1". Therefore, in the second mode, the amount of charge Q flowing into the light-emitting element (LED) during one frame is "T". That is, in both the first and second modes, the amount of charge Q flowing into the light-emitting element (LED) during one frame is the same. However, in the second mode, i.e., the high-quality mode, more diverse brightness can be represented through two subframes SF, and images with deeper color depth can be output. In other words, both low-quality and high-quality images can be represented using the same pixel memory 20.

[0083] Therefore, the timing control circuit 150 can output a control signal in the first mode. To make the grayscale The clock signal output circuit 140 outputs the following: (k is the pixel memory storage) The grayscale clock signals GC1 to GC5 (number of bits) are provided. Furthermore, the timing control circuit 150 can output a control signal in the second mode to cause the grayscale clock signal output circuit 140 to output a grayscale clock signal. Grayscale clock signals GC1 to GC5 (where k is the number of bits stored in the pixel memory).

[0084] Furthermore, in the first mode, the timing control circuit 150 can output a control signal to cause the data driving circuit 130 to output a signal related to the driving of each light-emitting element to each pixel memory 20 once. Moreover, in the second mode, the timing control circuit 150 can output a control signal to cause the data driving circuit 130 to output two signals related to the driving of each light-emitting element to each pixel memory 20 for each subframe interval.

[0085] The display device 100 described in this specification can not only display both low-definition and high-definition images using the same size pixel memory 20, but also reduces the manufacturing cost of the display panel. For example, it goes without saying that manufacturing a display panel with a pixel circuit having half the number of memory units (5 bits) compared to manufacturing a pixel circuit with 10 memory units is more cost-effective. Not only is cost reduced, but the manufacturing process of the display panel can also be further simplified.

[0086] Furthermore, low-power operation can be achieved depending on the environment in which the display device is used. For example, consider an environment where low-resolution images are mostly output, with occasional high-resolution output. There's no need to excessively size the memory cells for outputting relatively infrequently used high-resolution images, thus preventing unnecessary power consumption. Therefore, it can be used more efficiently in environments where the display device's power supply is limited.

[0087] The display device operates in environments where power supply is limited, such as portable devices that rely on batteries for power. In particular, for wearable devices where battery size or weight is a significant constraint, the display device 100 described in this manual can be more efficient.

[0088] Figure 7 This is a schematic diagram of a wearable device including the display device 100 described in this specification.

[0089] Reference Figure 7 The image confirms the presence of "smart glasses," a wearable device that can be worn on the face like glasses. As a wearable device, smart glasses are limited by their battery power. Especially compared to wearable devices worn on the wrist or waist, smart glasses, due to their face-worn nature, face significantly greater constraints on battery size and weight. Furthermore, because they need to provide information to the user in visual form via a display device, they require more power than other wearable devices.

[0090] Therefore, considering the characteristics of the information displayed on the screen, the first mode described in this manual is used when sufficient information can be provided to the user even when the image is output in low quality, and the second mode described in this manual is used when high quality is required, thereby enabling efficient control of power consumption.

[0091] Figure 8 This is a schematic diagram illustrating smart glasses operating in both the first and second modes.

[0092] Figure 8 (a) describes the scenario where smart glasses provide navigation information. When providing navigation information, the variation between frames is small, and sufficient information can be provided even if the color depth of the information displayed by the pixels is relatively shallow. Therefore, in this case, the display device can operate in the first mode. Conversely, Figure 8 (b) describes the scenario where the smart glasses output photos or videos. Unlike navigation, photos require high-quality images. Therefore, in this case, the display device can operate in a second mode.

[0093] Refer again Figure 7 The wearable device 200 in this specification may include: a display device 100; a first power supply 210 that supplies power to the display device 100; and a communication module 220 that receives image data from a main device 300 and provides it to the timing control circuit 150, wherein the main device 300 transmits data related to the image displayed on the display device 100 (hereinafter referred to as "image data").

[0094] The wearable device 200 includes a display device 100 that has been previously passed through. Figure 6The description has already been provided and will not be repeated here. The communication module 220 is used to send and receive data with the main device 300, and can receive image data wirelessly. Although wireless communication is shown as an example in the accompanying drawings, it is not limited to wireless communication and can also be wired communication. In addition, in this specification, the term "first power supply 210" is only a name used to distinguish it from the second power supply 330 included in the main device 300, and can be various power supplies such as a rechargeable battery. Therefore, the main device 300 can receive power from the second power supply 330.

[0095] On the other hand, Figure 7 In this context, the main device 300 is shown as a smartphone, but the main device 300 can also be a laptop computer, a digital broadcasting terminal, or a PDA (personal digital assistant). PMP (portable) multimedia player, then Portable multimedia player), navigator, Touchscreen tablet PCs, tablet PCs, ultrabooks, etc.

[0096] Additionally, the main device 300 may include an image processing module 320. To output an image from the display device, various preprocessing operations are required. For example, operations such as de-mura, dead pixel compensation, and gamma correction are needed, and the processed image needs to be stored in the frame buffer's storage space. Furthermore, the display device in this specification has a first mode and a second mode, thus requiring the input image to be converted into image data according to either the first or second mode. This operation requires a higher-performance image data processing processor and consumes a significant amount of power. Therefore, it can be designed so that operations prior to generating image data, which the timing control circuit 150 can directly provide to the data driving circuit 130, are processed in the image processing module 320 included in the main device 300, allowing the display device 100 to use only a minimal amount of power.

[0097] On the other hand, in addition to the control actions described in this specification, the timing control circuit 150 can also control the overall operation of the display device 100. For example, in addition to the image data RGB, it can receive a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a clock signal CLK, and a data enable signal DE from the main device 300, and control the scan drive circuit 120, the data drive circuit 130, and the grayscale clock signal output circuit 140 based on the received signals.

[0098] To execute the aforementioned control actions and various control logics, the timing control circuit 150 may include processors, ASICs (application-specific integrated circuits), other chip sets, logic circuits, registers, communication modems, data processing devices, etc., known in the technical field of this invention. Furthermore, when the aforementioned control logic is implemented in software, the timing control circuit 150 may be implemented as a set of program modules. In this case, the program modules may be stored in a storage device and executed by the processor.

[0099] To enable the computer to read and run the program-implemented method, the computer program may include code encoded in computer languages ​​such as C / C++, C#, JAVA, Python, and machine learning, which can be read by the computer's processor (CPU) through the computer device interface. This code may include functional code, such as functions defining the necessary features for running the method, and control code related to the execution steps required for the computer processor to run the function according to predetermined steps. Additionally, this code may include code specifying the memory location (address) from which additional information or media required for the computer processor to run the function should be referenced. Furthermore, when the computer's processor needs to communicate with a remote computer or server to run the function, the code may also include communication-related code, such as how to use the computer's communication module to communicate with the remote computer or server, and what information or media needs to be sent and received during communication.

[0100] The storage medium is not a medium that can temporarily store data like registers, caches, or memory, but rather a medium that stores data semi-permanently and can be read by a device. Specifically, the storage medium includes, but is not limited to, ROM, RAM, CD-ROM, magnetic tape, floppy disks, and optical data storage devices. That is, the program can be stored on various recording media on various servers accessible to the computer or on various recording media on the user's computer. Furthermore, the medium can be distributed across a network-connected computer system to store computer-readable code in a distributed manner.

[0101] The embodiments of this specification have been described above with reference to the accompanying drawings. Those skilled in the art will understand that the present invention can be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood in all respects as exemplary rather than restrictive.

[0102] Figure Labels

[0103] 10: Sub-pixel driving circuit

[0104] 11: First current drive unit; 12: Second current drive unit

[0105] 20: Pixel memory; 30: PWM control unit

[0106] 40: Sub-pixel circuit; 100: Display device

[0107] 110: Display panel; 120: Scan drive circuit

[0108] 130: Data driving circuit; 140: Grayscale clock signal output circuit

[0109] 150: Timing control circuit

Claims

1. A sub-pixel driving circuit, comprising: A light-emitting element driving line, wherein the light-emitting element driving line is connected between the output terminal of the first transistor and the positive power supply or between the output terminal of the first transistor and the negative power supply; The first transistor is connected in series on the light-emitting element driving line and is turned on according to the PWM signal; The first current driving unit and the second current driving unit are connected in series on the light-emitting element driving line and are electrically connected in parallel to each other. and The second transistor is connected between the reference voltage source and the second current drive unit, wherein the reference voltage source is configured to supply a reference voltage to the first current drive unit and the second current drive unit; When operating in the first mode, the first current driving unit and the second current driving unit are turned on; and when operating in the second mode, a frame interval includes a first subframe interval and a second subframe interval, the first current driving unit is turned on in the frame interval, and the second transistor is connected to turn on the second current driving unit during the first subframe and turn off the second current driving unit during the second subframe. The second mode has higher image quality than the first mode; The first current driving unit includes: A third transistor, connected in series on the light-emitting element driving line, is turned on according to the positive power supply; and The fourth transistor is connected in series on the light-emitting element driving line and is turned on according to the reference voltage; The second current drive unit includes: The fifth transistor, connected in series on the light-emitting element driving line, is turned on according to the positive power supply; and The sixth transistor is connected in series on the light-emitting element driving line, and when the second transistor is turned on, it is turned on according to the reference voltage.

2. The sub-pixel driving circuit according to claim 1, characterized in that, The second transistor is connected between the reference voltage source and the sixth transistor.

3. The sub-pixel driving circuit according to claim 1, wherein, It also includes a seventh transistor, which is connected between the positive power supply and the sixth transistor, and selects whether to turn the signal on or off according to the display mode.

4. The sub-pixel driving circuit according to claim 3, wherein, The first, fourth, sixth, and seventh transistors are P-type MOSFETs. The second, third, and fifth transistors are N-type MOSFETs.

5. A sub-pixel circuit, comprising: Sub-pixel driving circuit according to any one of claims 1 to 4; Light-emitting elements; A pixel memory that stores data related to driving the light-emitting element; and A PWM control unit processes signals for controlling the brightness of the light-emitting element.

6. The sub-pixel circuit according to claim 5, characterized in that, The pixel memory consists of five static random access memory units used to store five bits of data related to the driving of the light-emitting element.

7. A display device, comprising: The display panel includes a plurality of sub-pixel circuits as described in claim 5; A scan driving circuit, wherein the scan driving circuit sequentially drives the sub-pixel circuits arranged along the row direction in a plurality of scan lines connected to the pixel memory of each sub-pixel circuit; The data driving circuit outputs signals related to the driving of each light-emitting element to each pixel memory through multiple data lines connected to the pixel memory of each sub-pixel circuit. A grayscale clock signal output circuit outputs a width-adjusted pulse signal to the PWM control unit included in each sub-pixel circuit to adjust the brightness of the sub-pixel. The width-adjusted pulse signal is hereinafter referred to as the "grayscale clock signal". and A timing control circuit outputs signals for controlling the scan drive circuit, the data drive circuit, and the grayscale clock signal output circuit, and outputs a display mode selection signal to the second transistors included in the plurality of sub-pixel circuits.

8. The display device according to claim 7, characterized in that, When the timing control circuit operates in the first mode (default image quality mode), it outputs the display mode selection signal to enable the second transistor within a one-frame interval. In the second mode, which is a high-quality mode, the display mode selection signal is output to turn on the second transistor in any one of the two subframes included in a frame, and turn off the second transistor in the remaining subframes.

9. The display device according to claim 8, characterized in that, In the first mode, the timing control circuit outputs a control signal to the grayscale clock signal output circuit so as to output the grayscale clock signal during a preset time T. In the second mode, a control signal is output to the grayscale clock signal output circuit to enable control within each subframe interval. The grayscale clock signal is output during period T.

10. The display device according to claim 9, characterized in that, In the first mode, the timing control circuit outputs a control signal to cause the grayscale clock signal output circuit to output as... The grayscale clock signal, where k is the number of bits stored in the pixel memory. In the second mode, the output control signal causes the grayscale clock signal output circuit to output as... The grayscale clock signal, where k is the number of bits stored in the pixel memory.

11. The display device according to claim 9, characterized in that, In the first mode, the timing control circuit outputs a control signal to cause the data driving circuit to output a signal related to the driving of each light-emitting element to each pixel memory. In the second mode, a control signal is output to make the data driving circuit output two signals related to the driving of each light-emitting element to each pixel memory, corresponding to each sub-frame interval.

12. A wearable device, comprising: The display device according to claim 7; A first power supply, which supplies power to the display device; and A communication module receives image data from a master device and provides it to the timing control circuit, wherein the master device transmits data related to the image displayed on the display device.

13. The wearable device according to claim 12, characterized in that, The communication module receives image data wirelessly with the main device.

14. The wearable device according to claim 12, characterized in that, The main device receives power from the second power supply.

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