Display substrate and display device

Abstract

A display substrate has a plurality of sub-pixels, and each column of sub-pixels includes a first sub-pixel and a second sub-pixel arranged alternately. The display substrate includes a substrate, a second source-drain metal layer, and a first source-drain metal layer arranged in sequence. The first source-drain metal layer includes a first data line and a second data line arranged alternately. The second source-drain metal layer includes a first connection portion and a second connection portion. The first end of each first connection portion is electrically connected to the corresponding first data line, and the second end is electrically connected to the corresponding first sub-pixel. The first end of each second connection portion is electrically connected to the corresponding second data line, and the second end is electrically connected to the corresponding second sub-pixel. In the same column of sub-pixels, a first connection line between the second end of the first connection portion and the second end of the second connection portion is substantially parallel to a second direction, the first end of the first connection portion is located on a first side of the first connection line, and the first end of the second connection portion is located on a second side of the first connection line.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] The refresh rate of a display device (also called vertical refresh rate or vertical scanning rate) refers to the number of times a display screen can display a new image per second. For example, a display screen can display a new image 60 times per second at a refresh rate of 60Hz. When the refresh rate of a display device is high, such as 75Hz, 90Hz, 120Hz or higher, it can avoid blurring and smearing when displaying high-speed moving images, thereby improving image quality and user visual experience. Summary of the invention

[0003] On the one hand, a display substrate is provided. The display substrate has a plurality of sub-pixels arranged in an array, each column of sub-pixels includes a plurality of first sub-pixels and second sub-pixels, and the first sub-pixels and the second sub-pixels are arranged alternately along a second direction. The display substrate includes: a substrate, a first source-drain metal layer disposed on the substrate, and a second source-drain metal layer disposed between the substrate and the first source-drain metal layer. The first source-drain metal layer includes a plurality of first data lines and a plurality of second data lines, the first data lines and the second data lines are arranged alternately along a first direction, and a first data line and a second data line are disposed between each two adjacent columns of sub-pixels; along the first direction, a column of sub-pixels corresponds to a first data line and a second data line located on both sides thereof, respectively, each first sub-pixel of the column of sub-pixels is electrically connected to the corresponding first data line, and each second sub-pixel of the column of sub-pixels is electrically connected to the corresponding second data line. The second source-drain metal layer includes a plurality of first connection portions and a plurality of second connection portions. Each first sub-pixel is electrically connected to the corresponding first data line through a first connection portion; the first end of each first connection portion is electrically connected to the corresponding first data line, and the second end is electrically connected to the pixel driving circuit of the corresponding first sub-pixel. Each second sub-pixel is electrically connected to the corresponding second data line through a second connection portion; the first end of each second connection portion is electrically connected to the corresponding second data line, and the second end is electrically connected to the pixel driving circuit of the corresponding second sub-pixel. In the same column of sub-pixels, a first connection line between the second end of the first connection portion and the second end of the second connection portion is substantially parallel to the second direction, the first end of the first connection portion is located on the first side of the first connection line, and the first end of the second connection portion is located on the second side of the first connection line.

[0004] In some embodiments, the display substrate further includes an active layer disposed between the substrate and the second source-drain metal layer. Each sub-pixel further includes a write transistor, the write transistor including a fourth active pattern disposed in the active layer; along the first direction, the spacing between the fourth active patterns of the write transistors in each two adjacent sub-pixels is approximately equal, and along the second direction, the spacing between the fourth active patterns of the write transistors in each two adjacent sub-pixels is approximately equal. In each first sub-pixel, the second end of the first connection portion is electrically connected to the fourth active pattern of the corresponding write transistor; in each second sub-pixel, the second end of the second connection portion is electrically connected to the fourth active pattern of the corresponding write transistor.

[0005] In some embodiments, each row of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels, and the first sub-pixels and the second sub-pixels are alternately arranged along the first direction. In the same row of sub-pixels, a second connection line between the second end of the first connection portion and the second end of the second connection portion is substantially parallel to the first direction; the first end of the first connection portion is located on a side of the second connection line away from the corresponding fourth active pattern, and the first end of the second connection portion is located on a side of the second connection line close to the corresponding fourth active pattern.

[0006] In some embodiments, the display substrate further comprises a first insulating layer disposed between the second source-drain metal layer and the active layer, wherein a plurality of first via holes and a plurality of second via holes are disposed in the first insulating layer. In each first sub-pixel, the second end of the first connecting portion is electrically connected to the fourth active pattern of the corresponding write transistor through a corresponding first via hole; in each second sub-pixel, the second end of the second connecting portion is electrically connected to the fourth active pattern of the corresponding write transistor through a corresponding second via hole.

[0007] In some embodiments, the first insulating layer includes a first sub-insulating layer and a second sub-insulating layer, the second sub-insulating layer is disposed between the first sub-insulating layer and the substrate, and the display substrate further includes a second gate metal layer disposed between the first sub-insulating layer and the second sub-insulating layer; the second gate metal layer includes a plurality of first shielding portions and a plurality of second shielding portions, and each sub-pixel is provided with a first shielding portion and a second shielding portion. In each first sub-pixel, the orthographic projections of the first connecting portion and the second shielding portion on the substrate have an overlapping area, the orthographic projections of the first connecting portion and the first shielding portion on the substrate do not have an overlapping area, and the second end of the first connecting portion and the orthographic projection of the second shielding portion on the substrate do not have an overlapping area; in each second sub-pixel, the orthographic projections of the second connecting portion and the first shielding portion on the substrate have an overlapping area, the orthographic projections of the second connecting portion and the second shielding portion on the substrate do not have an overlapping area, and the second end of the second connecting portion and the first shielding portion do not have an overlapping area.

[0008] In some embodiments, along the first direction, in the same row of sub-pixels, the first blocking portions and the second blocking portions are alternately arranged, and adjacent first blocking portions and second blocking portions respectively located in different sub-pixels are integrally formed.

[0009] In some embodiments, the maximum dimension of each first connection portion in the extension direction thereof is greater than the maximum dimension of each second connection portion in the extension direction thereof.

[0010] In some embodiments, the area of ​​the first end of each first connection portion is larger than the area of ​​the second end thereof, and / or the area of ​​the first end of each second connection portion is larger than the area of ​​the second end thereof.

[0011] In some embodiments, each first data line includes a first body and a plurality of fifth connection parts; the plurality of fifth connection parts are disposed on a side of the first body close to the corresponding first sub-pixel and arranged along the second direction; each fifth connection part is electrically connected between the first body and the first end of the corresponding first connection part. Each second data line includes a second body and a plurality of sixth connection parts; the plurality of sixth connection parts are disposed on a side of the second body close to the corresponding second sub-pixel and arranged along the second direction; each sixth connection part is electrically connected between the second body and the first end of the corresponding second connection part.

[0012] In some embodiments, the display substrate further includes a second insulating layer disposed between the first source-drain metal layer and the second source-drain metal layer, and a plurality of third vias and a plurality of fourth vias are disposed in the second insulating layer. Each fifth connection portion is electrically connected to a first end of a corresponding first connection portion through a corresponding third via, and each sixth connection portion is electrically connected to a first end of a corresponding second connection portion through a corresponding fourth via.

[0013] In some embodiments, the display substrate further includes a plurality of first voltage signal lines, the orthographic projection of each first voltage signal line on the substrate being located between the orthographic projections of the first data line and the second data line between each two adjacent columns of sub-pixels on the substrate, and the first voltage signal line is electrically connected to at least one column of sub-pixels. The first voltage signal line includes: a first sub-voltage signal line disposed in the first source-drain metal layer, and a second sub-voltage signal line disposed in the second source-drain metal layer, and the first sub-voltage signal line is electrically connected to the second sub-voltage signal line.

[0014] In some embodiments, when the display substrate includes a second insulating layer, a plurality of fifth vias are provided in the second insulating layer; the first sub-voltage signal line and the second sub-voltage signal line are electrically connected through at least one fifth via among the plurality of fifth vias; wherein, among the first data line, the second data line and the first sub-voltage signal line located between two adjacent columns of sub-pixels, the portion of the first data line adjacent to the fifth via is bent in a direction away from the fifth via to form a first bending portion, and the portion of the second data line adjacent to the fifth via is bent in a direction away from the fifth via to form a second bending portion. The first bending portion and the second bending portion are opposite to each other to form a receiving area, the first sub-voltage signal line includes a conductive portion passing through the fifth via, and the conductive portion is located in the receiving area; along the first direction, the size of the conductive portion is greater than the width of the first sub-voltage signal line.

[0015] In some embodiments, in the first data line and the second data line adjacent to a column of sub-pixels and located on both sides of the column of sub-pixels along the first direction, a seventh connecting portion is arranged between the first bending portion and the second bending portion, and the seventh connecting portion is arranged on the same layer as the first sub-voltage signal line.

[0016] In some embodiments, the display substrate further comprises an anode layer disposed on a side of the first source-drain metal layer away from the substrate. Each sub-pixel further comprises a first light emission control transistor, the first light emission control transistor comprises a sixth active pattern disposed in the active layer, the sixth active pattern comprises a first conductor portion; the seventh connection portion is electrically connected to the first conductor portion and the anode layer.

[0017] In some embodiments, the first side of the first connection line is a side of the first connection line close to the first data line corresponding to the column of sub-pixels, and the second side of the first connection line is a side of the first connection line close to the second data line corresponding to the column of sub-pixels.

[0018] In another aspect, a display device is provided, comprising the display substrate as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0020] Figure 1 is an equivalent circuit diagram of a 7T1C pixel driving circuit according to some embodiments;

[0021] Figure 2 for Figure 1 The signal timing diagram of the pixel driving circuit shown;

[0022] Figure 3 A schematic diagram of a driving architecture in some embodiments;

[0023] Figure 4 for Figure 3 The signal timing diagram of the drive architecture shown;

[0024] Figure 5 is a schematic structural diagram of another driving system in some embodiments;

[0025] Figure 6 for Figure 5 The signal timing diagram of the drive system shown;

[0026] Figure 7 is a schematic top view of a display substrate according to some embodiments;

[0027] Figures 8A to 8H for Figure 7 A schematic top view of each film layer of the display substrate shown;

[0028] Fig. 9A is a schematic diagram of a sub-pixel structure according to some embodiments;

[0029] Fig. 9B for Fig. 9AA schematic cross-sectional view of a sub-pixel along dotted line AA';

[0030] Fig. 10A is a schematic diagram of the structure of another sub-pixel according to some embodiments;

[0031] Fig. 10B for Fig. 10A A schematic cross-sectional view of a sub-pixel along dotted line BB';

[0032] Fig.11 for Figure 7 An equivalent circuit diagram of a portion of a display substrate in region S is shown;

[0033] Fig.12 for Figure 7 A partial enlarged view of a portion within the region S' of the display substrate shown;

[0034] Figures 13A to 13F It is a schematic diagram of the connection relationship between film layers of a display substrate according to some embodiments. DETAILED DESCRIPTION

[0035] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0036] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and other forms thereof, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open, inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0037] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0038] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other, or to indicate that two or more components are indirectly physically or electrically connected to each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0039] It should be understood that, in the description of the present disclosure, the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0040] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0041] As used herein, "about" or "approximately" includes the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0042] When the display device operates at a higher refresh rate (e.g., 75Hz, 90Hz, 120Hz or higher), the displayed image quality and the user's visual experience can be improved. However, a higher refresh rate will bring about the problem of shortening the data writing and compensation time of each sub-pixel in the display device, which may lead to insufficient charging rate of each sub-pixel and reduced threshold voltage compensation effect, thereby reducing the display effect of the display device.

[0043] like Figure 1As shown, taking a display device including a pixel driving circuit of a 7T1C structure as an example, the display device includes a plurality of sub-pixels, each of which has a pixel driving circuit of the 7T1C structure, and the pixel driving circuit includes seven transistors (a first transistor T1 to a seventh transistor T7) and a capacitor Cst. The seven transistors may be P-type transistors, that is, they are turned on when the gate receives a low-level signal and are turned off when a high-level signal is received; the seven transistors may also be N-type transistors, that is, they are turned on when the gate receives a high-level signal and are turned off when a low-level signal is received.

[0044] In order to conveniently introduce the pixel driving circuit of 7T1C, the electrical connection point between the second electrode of the first transistor T1, the second electrode plate B1 of the capacitor Cst and the gate of the third transistor T3 is called the first node N1, and the voltages of the first node N1, the second electrode plate B1 of the capacitor Cst and the gate of the third transistor T3 are equal; the electrical connection point between the second electrode of the fifth transistor T5, the second electrode of the fourth transistor T4 and the first electrode of the third transistor T3 is called the second node N2; the electrical connection node between the second electrode of the third transistor T3, the first electrode of the second transistor T2 and the first electrode of the sixth transistor T6 is called the third node N3. It should be noted that the third transistor T3 is used as a driving transistor in the pixel driving circuit.

[0045] It is worth noting that the channel width-to-length ratio of the driving transistor is usually greater than the channel width-to-length ratio of other switching transistors, that is, the channel width-to-length ratio of the third transistor T3 is usually greater than the channel width-to-length ratio of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In addition, taking the electroluminescent device as an example, the luminous brightness of the light-emitting device E corresponding to each sub-pixel is related to the size of the driving current I flowing through it. According to the formula I = K (Vgs-Vth) 2 It can be seen that the driving current I is related to the gate-source voltage difference Vgs of the driving transistor and the threshold voltage Vth of the driving transistor, that is, when the voltage difference Vgs is constant, the luminous brightness of each light-emitting device E will be mainly affected by the threshold voltage Vth of the corresponding driving transistor. In this way, when the threshold voltages Vth of the driving transistors in the sub-pixels of the display device are not equal, for example, when the threshold voltage Vth of the driving transistor drifts as the working time increases, the display device may have uneven display brightness.

[0046] The components of the above-mentioned 7T1C pixel driving circuit and the connection relationship between the components are introduced below. Here, the transistors included in the pixel driving circuit are taken as an example as P-type transistors, that is, the first transistor T1 to the seventh transistor T7 are turned on when the signal received by the gate is a low level, and are turned off when the signal received by the gate is a high level.

[0047] The gate of the first transistor T1 (also referred to as the first reset transistor) is electrically connected to the reset signal terminal RESET, the first electrode is electrically connected to the initialization voltage signal terminal INIT, and the second electrode is electrically connected to the first node N1. The gate of the second transistor T2 (also referred to as the compensation transistor) is electrically connected to the scan signal terminal GATE, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the first node N1. The gate of the third transistor T3 (also referred to as the drive transistor) is electrically connected to the first node N1, the first electrode is electrically connected to the second node N2, and the second electrode is electrically connected to the third node N3. The gate of the fourth transistor T4 (also referred to as the write transistor) is electrically connected to the scan signal terminal GATE, the first electrode is electrically connected to the data signal terminal DATA, and the second electrode is electrically connected to the second node N2. The gate of the fifth transistor T5 (also referred to as the second light emitting control transistor) is electrically connected to the light emitting signal terminal EM, the first electrode is electrically connected to the first voltage signal terminal VDD, and the second electrode is electrically connected to the second node N2. The gate of the sixth transistor T6 (also referred to as the first light-emitting control transistor) is electrically connected to the light-emitting signal terminal EM, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the anode of the sub-pixel light-emitting device E. The gate of the seventh transistor T7 (also referred to as the second reset transistor) is electrically connected to the reset signal terminal RESET, the first electrode is electrically connected to the initialization voltage signal terminal INIT, and the second electrode is electrically connected to the anode of the sub-pixel light-emitting device E. The first plate A1 of the capacitor Cst is electrically connected to the first voltage signal terminal VDD, and the second plate B1 is electrically connected to the first node N1.

[0048] In addition, the anode of the light emitting device E of the sub-pixel is electrically connected to the above-mentioned pixel driving circuit, and the cathode is electrically connected to the second voltage signal terminal VSS.

[0049] Combine the following Figure 2 The signal timing diagram shown introduces the working process of the above-mentioned 7T1C pixel driving circuit. In one frame time, the working process of the pixel driving circuit includes a reset phase P1, a writing and compensation phase P2 and a light emitting phase P3.

[0050] In the reset phase P1, the reset signal Vre transmitted from the reset signal terminal RESET to the gate of the first transistor T1 and the gate of the seventh transistor T7 is at a low level, and the first transistor T1 and the seventh transistor T7 are turned on. The first transistor T1 transmits the initialization voltage signal Vinit from the initialization voltage signal terminal INIT to the first node N1 to reset the voltage of the second plate B1 of the capacitor Cst and the gate of the third transistor T3 (also referred to as the driving transistor T3), and the voltage of the second plate B1 is equal to the voltage Vi of the initialization voltage signal Vinit. The seventh transistor T7 transmits the initialization voltage signal Vinit from the initialization voltage signal terminal INIT to the anode of the light emitting device E to reset the anode voltage of the light emitting device E.

[0051] Here, the initialization voltage signal Vinit is at a low level in the reset phase P1, and the voltage of the first node N1 is a low voltage, so the third transistor T3 whose gate is electrically connected to the first node N1 is turned on. Exemplarily, the initialization voltage signal Vinit may be a constant low voltage signal.

[0052] In the writing and compensation phase P2, the reset signal Vre is high, the first transistor T1 and the seventh transistor T7 are turned off, the voltage of the first node N1 is equal to the voltage of the second plate B1 of the capacitor Cst, that is, the voltage of the first node N1 is still low, and the third transistor T3 remains turned on.

[0053] The scanning signal Vgate transmitted from the scanning signal terminal GATE to the gate of the fourth transistor T4 and the gate of the second transistor T2 is at a low level, and the fourth transistor T4 and the second transistor T2 are turned on. The fourth transistor T4 transmits the data signal Vdata from the data signal terminal DATA to the third transistor T3. The data signal Vdata is transmitted to the second transistor T2 through the turned-on third transistor T3, and then transmitted to the first node N1 through the turned-on second transistor T2, so as to be written into the capacitor Cst. The process of the data signal Vdata being written into the capacitor Cst is actually the charging process of the second plate B1 of the capacitor Cst (i.e., the process of the voltage of the second plate B1 gradually increasing). The voltage of the first node N1 gradually increases from Vi in the previous stage (i.e., the reset stage P1) until the voltage of the first node N1 rises to Vdata+Vth, and the third transistor T3 is turned off, where Vth is the threshold voltage value of the third transistor T3. At this time, the voltage of the second plate B1 of the capacitor Cst is equal to Vdata+Vth, so that the threshold voltage value Vth of the third transistor T3 is compensated to the data signal written into the capacitor Cst.

[0054] It should be noted that the duration 1H of the effective level of the scanning signal Vgate (ie, the level that turns on the corresponding transistor) is the time required for a row of sub-pixels to complete the writing of the data signal Vdata.

[0055] In the light-emitting stage P3, the light-emitting signal Vem transmitted to the gate of the fifth transistor T5 and the gate of the sixth transistor T6 of the light-emitting signal terminal EM is at a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on. The source voltage Vs of the third transistor T3 is equal to the first voltage Vdd of the first voltage signal terminal VDD, and the gate voltage Vg of the third transistor T3 is equal to Vdata+Vth, where the first voltage Vdd is greater than Vdata+Vth, so the third transistor T3 is turned on. In this way, a current path is formed between the first voltage signal terminal VDD and the second voltage signal terminal VSS, so that the light-emitting device E can emit light.

[0056] It should be noted that the driving current I flowing through the light emitting device E in the light emitting stage P3 is I=K(Vgs-Vth) 2 =K(Vdata+Vth-Vdd-Vth) 2 =K(Vdata-Vdd) 2 In this way, the magnitude of the driving current I is independent of the threshold voltage value Vth of the third transistor T3, thereby avoiding the influence of the threshold voltage drift of the third transistor T3 on the driving current I, and making the light emitting brightness of the display device more uniform.

[0057] When the display device needs to be refreshed at a faster frequency, the time of each frame is shortened due to the large number of new images displayed per second, resulting in a corresponding shortening of the writing and compensation phase P2 within a frame, that is, the duration of the effective level of the scanning signal is shortened. This may cause the data writing time (i.e., the charging time of the sub-pixel) and the threshold voltage compensation time of the display device to be shorter, resulting in insufficient charging rate of the sub-pixel and poor threshold voltage compensation effect, affecting the image quality of the display device and the visual experience of the user.

[0058] To solve the above problem, two data lines DL can be set to provide a data signal Vdata to a column of sub-pixels. Figures 3 to 6 , the display device with the 7T1C pixel driving circuit mentioned above adopts the driving method scheme to exemplarily introduce.

[0059] like Figure 3 and 5As shown, the display device includes a plurality of sub-pixels PX, a plurality of data lines DL (e.g., DL1 to DL8) and a plurality of gate lines GL (e.g., GL1 to GL4), and these sub-pixels PX can be arranged in an array. Each column of sub-pixels corresponds to two data lines DL, and the two data lines DL are respectively arranged on the left and right sides of the column of sub-pixels. In the sub-pixels located in the same column, each two adjacent sub-pixels PX are respectively electrically connected to different data lines DL in the left and right data lines DL, that is, along the extension direction of the column of sub-pixels, the sub-pixels PX located in the same column are alternately electrically connected to the left and right data lines DL. The sub-pixels located in the same row can be electrically connected to the same gate line GL, where the gate line GL can provide a scanning signal Vgate to a row of sub-pixels electrically connected thereto, so that the data signal Vdata from the data line DL is transmitted to the corresponding sub-pixel PX, and the data signal Vdata is written. The data writing process of each sub-pixel PX can refer to the description of the writing and compensation stage P2 above, which will not be repeated here.

[0060] It should be noted that, along the extension direction of each row of sub-pixels, the sub-pixels PX located in the same row can be alternately electrically connected to the data lines DL on the left and right sides thereof (eg Figure 3 and Figure 5 As shown), they may also be electrically connected to the data line DL located on the left side or the right side thereof.

[0061] The display device may further include a plurality of source drive signal lines S (e.g., S1 to S4) and a source driver 100, and the plurality of source drive signal lines S are electrically connected to the source driver 100. The source driver 100 is used to provide data signals Vdata of images to be displayed by the display device, and these data signals Vdata may be provided to each sub-pixel PX through the source drive signal lines S and the data lines DL.

[0062] Each adjacent plurality of data lines DL is electrically connected to the same source drive signal line S. In this way, the source driver 100 can transmit the data signal Vdata to the plurality of data lines DL electrically connected to the source drive signal line S through the source drive signal line S, thereby reducing the number of interfaces for outputting the data signal Vdata provided on the source driver 100. A switch SW is provided between each data line DL and its corresponding source drive signal line S. In this way, by controlling the opening and closing of the corresponding switch SW, the source drive signal line S can be time-division multiplexed. Here, the control electrodes of the switches SW corresponding to the same source drive signal line S and located on the left side of a column of sub-pixels are all connected to the same control signal line MUX (for example, Figure 3The control signal line MUX is electrically connected to the MUX1 or MUX2 in the source drive signal line S, and the switch SW corresponding to the data line DL can be controlled to be turned on and off through the control signal line MUX, thereby controlling the data signal Vdata from the source drive signal line S in a certain frame to be transmitted to a specific data line DL, so that the data signal Vdata can be controlled to be written into the corresponding sub-pixel PX.

[0063] Here, the switch SW may include an N-type or P-type transistor. In the case where the switch SW includes an N-type transistor, the switch SW is turned on when the signal from the control signal line MUX is at a high level, and is turned off when the signal is at a low level. In the case where the switch SW includes a P-type transistor, the switch SW is turned on when the signal from the control signal line MUX is at a low level, and is turned off when the signal is at a high level.

[0064] The following will be Figure 2 and Figure 4 As an example, the structure of the display device shown in FIG. 1 is used to introduce the driving process of the display device. The pixel driving circuit in the sub-pixel of the display device can refer to Figure 1 Here, the second transistor T2 and the fourth transistor T4 in the pixel driving circuit and the switch SW are P-type transistors as an example, and along the extension direction of a row of sub-pixels, the sub-pixels PX in the same row are alternately electrically connected to the data lines DL on the left and right sides thereof.

[0065] For some examples, see Figure 3 , every two adjacent data lines DL are electrically connected to the same source driving signal line S. For example, the source driving signal line S1 is electrically connected to the data line DL1 and the data line DL2, that is, the source driver 100 can provide the data signal Vdata to the first column of sub-pixels PC1 through the source driving signal line S1, the data line DL1 and the data line DL2. Similarly, the source drive signal line S2 is electrically connected to the data line DL3 and the data line DL4, and the source driver 100 can provide the data signal Vdata to the second column sub-pixel PC2 through the source drive signal line S2, the data line DL3 and the data line DL4; the source drive signal line S3 is electrically connected to the data line DL5 and the data line DL6, and the source driver 100 can provide the data signal Vdata to the third column sub-pixel PC3 through the source drive signal line S3, the data line DL5 and the data line DL6; the source drive signal line S4 is electrically connected to the data line DL7 and the data line DL8, and the source driver 100 can provide the data signal Vdata to the fourth column sub-pixel PC4 through the source drive signal line S4, the data line DL7 and the data line DL8.

[0066] In the two data lines DL corresponding to the same source driving signal line S, in each switch SW electrically connected to each data line DL located on the left side of the corresponding column sub-pixel, the gate of the thin film transistor is electrically connected to the control signal line MUX1; in the switch SW corresponding to each data line DL located on the right side of the corresponding column sub-pixel, the gate of the thin film transistor is electrically connected to the control signal line MUX2. For example, the gate of the thin film transistor in each switch SW electrically connected to the data lines DL1, DL3, DL5 and DL7 is electrically connected to the control signal line MUX1, and the gate of the thin film transistor in the switch SW corresponding to the data lines DL2, DL4, DL6 and DL8 is electrically connected to the control signal line MUX2.

[0067] Thus, by transmitting signals of different levels to the thin film transistors in different switches SW, different data lines DL can be selected to transmit the data signal Vdata to the corresponding sub-pixels PX. In this way, the source driver 100 can transmit the data signal Vdata to two data lines DL electrically connected to the source drive signal line S through one source drive signal line S.

[0068] In this case, see Figure 4 In the first stage T11, the control signal Vumx1 transmitted via the control signal line MUX1 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX1 is turned on; the control signal Vumx2 transmitted via the control signal line MUX2 is at a high level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX2 is turned off. The scanning signal Vgate1 transmitted via the scanning signal line GL1 is at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 are turned on; the scanning signal Vgate2 transmitted via the scanning signal line GL2 is at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the second sub-pixel row PR2 are turned off. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located in the first row sub-pixel PR1 and the first column sub-pixel PC1, and the data signal Vdata transmitted via the source drive signal line S3 is written into the sub-pixel located in the first row sub-pixel PR1 and the third column sub-pixel PC3.

[0069] In the second stage T12, the control signal Vumx1 transmitted through the control signal line MUX1 is at a high level, and each switch SW electrically connected to the control signal line MUX1 is closed; the control signal Vumx2 transmitted through the control signal line MUX2 is at a low level, and each switch SW electrically connected to the control signal line MUX2 is opened. The scanning signal Vgate1 transmitted through the scanning signal line GL1 and the scanning signal Vgate2 transmitted through the scanning signal line GL2 are both at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first row of sub-pixels PR1 and the second row of sub-pixels PR2 are both turned on. In this way, although the fourth transistor T4 of each sub-pixel in the first row of sub-pixels PR1 and the second row of sub-pixels PR2 are all turned on, since the switches SW corresponding to the data lines DL1, DL3, DL5 and DL7 are all closed, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixels located in the second row of sub-pixels PR2 and the first column of sub-pixels PC1 by the data line DL2, the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixels located in the first row of sub-pixels PR1 and the second column of sub-pixels PC2 by the data line DL4, the data signal Vdata transmitted via the source drive signal line S3 is written into the sub-pixels located in the second row of sub-pixels PR2 and the third column of sub-pixels PC3 by the data line DL6, and the data signal Vdata transmitted via the source drive signal line S4 is written into the sub-pixels located in the first row of sub-pixels PR1 and the fourth column of sub-pixels PC4 by the data line DL8.

[0070] It should be noted that in the above driving mode, the duration of the effective level of the scanning signal Vgate of each sub-pixel PX is 2H, that is, the duration of the effective level of the scanning signal Vgate of each sub-pixel PX is equal to the time required for two rows of sub-pixels to complete the writing of the data signal Vdata. In this way, the time of the writing and compensation phase P2 can be increased, so that the charging time of the sub-pixel PX is sufficient and the threshold voltage compensation effect is improved, thereby improving the display effect of the display device at a high refresh rate.

[0071] In some embodiments, see Figure 5 Every four adjacent data lines DL are electrically connected to the same source driving signal line S. For example, the source driving signal line S1 is electrically connected to the data lines DL1 to DL4, and the source data line S2 is electrically connected to the data lines DL5 to DL8.

[0072] From left to right along the extension direction of a row of sub-pixels, in every 4 data lines DL corresponding to the same source drive signal line S, the gates of the thin film transistors in each switch SW electrically connected to each data line DL numbered 1 are electrically connected to the control signal line MUX1, the gates of the thin film transistors in each switch SW electrically connected to each data line DL numbered 2 are electrically connected to the control signal line MUX2, the gates of the thin film transistors in each switch SW electrically connected to each data line DL numbered 3 are electrically connected to the control signal line MUX3, and the gates of the thin film transistors in each switch SW electrically connected to each data line DL numbered 4 are electrically connected to the control signal line MUX4.

[0073] Similarly, by transmitting signals of different levels to the thin film transistors in different switches SW, different data lines DL can be selected to transmit the data signal Vdata to the corresponding sub-pixels PX. In this way, by time-division multiplexing the source drive signal line S, the source driver 100 can transmit the data signal Vdata to the four data lines DL electrically connected to the source drive signal line S through the same source drive signal line S, so that the corresponding four columns of sub-pixels can realize the writing of the data signal Vdata.

[0074] In this case, see Figure 6 In the first stage T21, the control signal Vumx1 transmitted via the control signal line MUX1 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX1 is turned on; the control signals Vumx2 to Vumx4 transmitted via the control signal lines MUX2 to MUX4 are all at a high level, and the thin film transistors in the switch SW electrically connected to the control signal lines MUX2 to MUX4 are all turned off. The scanning signal Vgate1 transmitted via the scanning signal line GL1 is at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 are turned on; the scanning signals Vgate2 to Vgate4 transmitted via the scanning signal lines GL2 to GL4 are all at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the second pixel row PR2 to the fourth pixel row PR4 are all turned off. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located in the first row of sub-pixel PR1 and the first column of sub-pixel PC1, and the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixel located in the first row of sub-pixel PR1 and the third column of sub-pixel PC3.

[0075] In the second stage T22, the control signal Vumx2 transmitted via the control signal line MUX2 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX2 is turned on; the control signals Vumx1, Vumx3 and Vumx4 transmitted via the control signal lines MUX1, MUX3 and MUX4 are all at a high level, and the thin film transistors in the switch SW electrically connected to the control signal lines MUX1, MUX3 and MUX4 are all turned off. The scanning signals Vgate1 and Vgate2 transmitted via the scanning signal lines GL1 and GL2 are at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 and the second sub-pixel row PR2 are turned on; the scanning signals Vgate3 and Vgate4 transmitted via the scanning signal lines GL3 and GL4 are both at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the third pixel row PR3 and the fourth pixel row PR4 are all turned off. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located in the second row sub-image PR2 and the first column sub-pixel PC1, and the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixel located in the second row sub-image PR2 and the third column sub-pixel PC3.

[0076] In the third stage T3, the control signal Vumx3 transmitted via the control signal line MUX3 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX3 is turned on; the control signals Vumx1, Vumx2 and Vumx4 transmitted via the control signal lines MUX1, MUX2 and MUX4 are all at a high level, and the thin film transistors in the switch SW electrically connected to the control signal lines MUX1, MUX2 and MUX4 are all turned off. The scanning signals Vgate1 to Vgate3 transmitted via the scanning signal lines GL1 to GL3 are at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 to the third sub-pixel row PR3 are turned on; the scanning signal Vgate4 transmitted via the scanning signal line GL4 is at a high level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the fourth pixel row PR4 are all turned off. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located in the second row sub-pixel PR2 and the second column sub-pixel PC2, and the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixel located in the second row sub-pixel PR2 and the fourth column sub-pixel PC4.

[0077] In the fourth stage T4, the control signal Vumx4 transmitted via the control signal line MUX4 is at a low level, and the thin film transistor in the switch SW electrically connected to the control signal line MUX4 is turned on; the control signals Vumx1 to Vumx3 transmitted via the control signal lines MUX1 to MUX3 are all at a high level, and the thin film transistors in the switch SW electrically connected to the control signal lines MUX1 to MUX3 are all turned off. The scanning signals Vgate1 to Vgate4 transmitted via the scanning signal lines GL1 to GL4 are all at a low level, and the second transistor T2 and the fourth transistor T4 in each sub-pixel PX located in the first sub-pixel row PR1 to the fourth sub-pixel row PR4 are all turned on. In this way, the data signal Vdata transmitted via the source drive signal line S1 is written into the sub-pixel located at the first row sub-image PR2 and the second column sub-pixel PC2 and the sub-pixel located at the third row sub-image PR3 and the second column sub-pixel PC2, and the data signal Vdata transmitted via the source drive signal line S2 is written into the sub-pixel located at the first row sub-image PR1 and the fourth column sub-pixel PC4 and the sub-pixel located at the third row sub-image PR3 and the fourth column sub-pixel PC4.

[0078] Here, the duration of the effective level of the scanning signal Vgate of each sub-pixel PX is 2H, and the time of the writing and compensation stage P2 can also be increased to ensure sufficient charging time for the sub-pixel PX and improve the threshold voltage compensation effect, thereby improving the display effect of the display device at a high refresh rate.

[0079] It should be noted that in the fourth stage T4, the data signal Vdata written into the sub-pixel located in the third row sub-image PR3 and the second column sub-pixel PC2, and the data signal Vdata written into the sub-pixel located in the third row sub-image PR3 and the fourth column sub-pixel PC4 are not the data signals actually required in the light-emitting stage. When the duration of the effective level of the scanning signal is 2H, before the effective level of the scanning signal Vgate3 corresponding to the above two sub-pixels ends, the two sub-pixels will be written with new data signals Vdata again, and the newly written data signals Vdata are the data signals required in the light-emitting stage.

[0080] However, when the display device adopts the above-mentioned driving method of providing a data signal Vdata to a column of sub-pixels through two data lines DL, the number of data lines DL provided in the display device will double, and the distribution density of the data lines DL will increase, so that the spacing between the sub-pixel and the two corresponding data lines (i.e., the two data lines adjacent to the pixel and located on both sides thereof) will decrease, which may cause the data line that is not electrically connected to the sub-pixel in the two corresponding data lines to generate a large parasitic capacitance with the pixel driving circuit in the sub-pixel. This may affect the luminescence of the sub-pixel, thereby possibly reducing the display effect of the display device.

[0081] Some embodiments of the present disclosure provide a display substrate, see Figure 7 and 9A 10B, the display substrate 1000 includes a substrate 10 and a plurality of sub-pixels arranged in an array on the substrate 10. Here, for ease of description, a direction perpendicular or substantially perpendicular to the extension direction of a column of sub-pixels is defined as a first direction OU, that is, the first direction OU is the row direction of the plurality of sub-pixels arranged in an array, and a direction parallel or substantially parallel to the extension direction of a column of sub-pixels is defined as a second direction OV, that is, the second direction OV is the column direction of the plurality of sub-pixels arranged in an array. Each column of sub-pixels includes a plurality of first sub-pixels 31 and second sub-pixels 32, and the first sub-pixels 31 and the second sub-pixels 32 are alternately arranged along the second direction OV.

[0082] Fig.11 for Figure 7 The equivalent circuit diagram of the portion of the display substrate 1000 located in the region S is shown. Here, the display substrate 1000 includes two first sub-pixels 31 and two second sub-pixels 32 arranged in a matrix in the region S as an example for explanation. Each first sub-pixel 31 and each second sub-pixel 32 has a pixel driving circuit of a 7T1C structure, and the pixel driving circuit includes a first transistor T1 to a seventh transistor T7 and a capacitor Cst. The electrical connection relationship between the components inside the pixel driving circuit and the working process of the driving circuit can refer to the above description, and will not be repeated here.

[0083] The following will Figure 7 The structure of each component in the pixel driving circuit of the sub-pixel in the display panel 1000 is exemplarily introduced. Along the thickness direction of the substrate 10, the display panel 1000 includes an active layer L disposed on the substrate 10 in sequence. A , the first gate metal layer L G1 , the second gate metal layer L G2 and the first source-drain metal layer L SD1 It should be noted that Figures 8A to 8F Middle area S P1 is an area where the first sub-pixel 31 is located, and area S P2 is a region where a second sub-pixel 32 is located.

[0084] like Fig. 8A , 9B , 10B and 13A, the active layer L A The active pattern 71 includes an active pattern 71 of a first transistor T1 , an active pattern 72 of a second transistor T2 , an active pattern 73 of a third transistor T3 , an active pattern 74 of a fourth transistor T4 , an active pattern 75 of a fifth transistor T5 , an active pattern 76 of a sixth transistor T6 , and an active pattern 77 of a seventh transistor T7 .

[0085] like Figure 8B , 9B , 10B and 13B, the first gate metal layer L G1 The first gate metal layer L includes a gate G1 of the first transistor T1, a gate G2 of the second transistor T2, a gate G3 of the third transistor T3, a gate G4 of the fourth transistor T4, a gate G5 of the fifth transistor T5, a gate G6 of the sixth transistor T6, and a gate G7 of the seventh transistor T7. G1 The present invention also includes a second electrode plate B1 of the capacitor Cst, a reset signal line RL, a gate line GL, and a light-emitting signal line EML. Here, the reset signal line RL is configured to transmit a reset signal Vre from a reset signal terminal RESET to a corresponding sub-pixel, the gate line GL is configured to transmit a scan signal Vgate from a scan signal terminal GATE to a corresponding sub-pixel, and the light-emitting signal line EML is configured to transmit a light-emitting signal Vem from a light-emitting signal terminal EM to a corresponding sub-pixel.

[0086] It should be noted that see Fig. 13B , the first gate metal layer L G1 The overlapped portion with the positive projection of the active pattern 71 of the first transistor T1 on the substrate 10 can be used as the gate G1 of the first transistor T1. G1 The overlapped portion with the positive projection of the active pattern 72 of the second transistor T2 on the substrate 10 can be used as the gate G2 of the second transistor T2. G1 The overlapped portion with the positive projection of the active pattern 73 of the third transistor T3 on the substrate 10 can be used as the gate G3 of the third transistor T3. G1 The overlapped portion with the positive projection of the active pattern 74 of the fourth transistor T4 on the substrate 10 can be used as the gate G4 of the fourth transistor T4. G1 The overlapped portion with the positive projection of the active pattern 75 of the fifth transistor T5 on the substrate 10 can be used as the gate G5 of the fifth transistor T5. G1 The overlapped portion with the positive projection of the active pattern 76 of the sixth transistor T6 on the substrate 10 can be used as the gate G6 of the sixth transistor T6. G1 The overlapping portion with the orthographic projection of the active pattern 77 of the seventh transistor T7 on the substrate 10 may serve as the gate G7 of the seventh transistor T7.

[0087] like Figure 8C , 9B , 10B and 13C, the second gate metal layer L G2The first electrode A1 of the capacitor Cst and the initialization voltage signal line IL are included. The initialization voltage signal line IL is configured to transmit the initialization voltage signal Vin from the initialization voltage signal terminal INIT to the corresponding sub-pixel.

[0088] like Figure 8G , 9B , 10B and 13F, the first source and drain metal layer L SD1 The plurality of first data lines 21 and the plurality of second data lines 22 are alternately arranged along the first direction OU, and one first data line 21 and one second data line 22 are arranged between each two adjacent columns of sub-pixels. Along the first direction OU, one column of sub-pixels corresponds to one first data line 21 and one second data line 22 located on both sides thereof, respectively, and each first sub-pixel 31 of the column of sub-pixels is electrically connected to the corresponding first data line 21, and each second sub-pixel 32 of the column of sub-pixels is electrically connected to the corresponding second data line 22.

[0089] Refer to the following Fig.11 , an exemplary description is given of the connection relationship between the pixel driving circuit of each sub-pixel and the signal line in the display substrate 1000.

[0090] In the same column of sub-pixels, the fourth transistor T4 of the first sub-pixel 31 is electrically connected to the same first data line 21, and the fourth transistor T4 of the second sub-pixel 32 is electrically connected to the same second data line 22. That is, the first sub-pixel 31 receives the data signal Vdata through the first data line 21, and the second sub-pixel 32 receives the data signal Vdata through the second data line 22.

[0091] The gates of the second transistor T2 and the fourth transistor T4 of the sub-pixels in the same row are electrically connected to the same level scanning signal terminal GATE (for example, the Nth level scanning signal terminal GATE) through the same gate line GL. N Or the (N+1)th level scanning signal terminal GATA N+1 ).

[0092] The gates of the fifth transistor T5 and the sixth transistor T6 of the sub-pixels in the same row are electrically connected to the same-level light emitting signal terminal EM (for example, the Nth-level light emitting signal terminal EM) through the same light emitting signal line EML. N Or the (N+1)th luminous signal terminal EM N+1 ).

[0093] The gates of the first transistor T1 and the seventh transistor T7 of the sub-pixel in the same row are electrically connected to the previous scanning signal terminal GATE through the same reset signal line RL. It should be noted that the scanning signal Vgate output by the previous scanning signal terminal GATE is used as the reset signal Vre, that is, the previous scanning signal terminal GATE is used as the reset signal terminal RESET of the current sub-pixel. For example, Fig.11 In the Nth level, the scan signal terminal GATE N The output scanning signal Vgate is used as the second transistor T2 and the fourth transistor T4 to connect to the (N+1)th stage scanning signal terminal GATA. N+1 Reset signal Vre of the electrically connected sub-pixel.

[0094] The first electrodes of the first transistor T1 and the seventh transistor T7 of the sub-pixel in the same row are electrically connected to the initialization voltage signal terminal INIT through the same initialization voltage signal line IL. Here, the initialization voltage signal Vin output by the initialization voltage signal terminal INIT may be a constant voltage signal, for example, Fig.11 The initialization voltage signal Vin in can be a constant low voltage signal.

[0095] In some embodiments, see 7, Fig. 8E , 9A 10B and 13E, the display substrate 1000 further includes a first source-drain metal layer L disposed between the substrate 10 and the first source-drain metal layer L SD1 The second source-drain metal layer L SD2 For example, the display substrate 1000 includes a second gate metal layer L G2 In this case, the second source-drain metal layer L SD2 Set on the second gate metal layer L G2 and the first source-drain metal layer L SD1 between.

[0096] The second source and drain metal layer L SD2 The first connecting portion 131 includes a plurality of first connecting portions 131 and a plurality of second connecting portions 132. Here, the first connecting portion 131 is disposed in the first region S where the first sub-pixel 31 is located. P1 In the embodiment, the second connecting portion 132 is disposed in the first region S where the second sub-pixel 32 is located. P2 See Fig. 9A and 9BEach first sub-pixel 31 is electrically connected to the corresponding first data line 21 through a first connection portion 131, a first end 1311 of each first connection portion 131 is electrically connected to the corresponding first data line 21, and a second end 1312 of the first connection portion 131 is electrically connected to the pixel driving circuit of the corresponding first sub-pixel 31. Each second sub-pixel 32 is electrically connected to the corresponding second data line 22 through a second connection portion 132, a first end 1321 of each second connection portion 132 is electrically connected to the corresponding second data line 22, and a second end 1322 of the second connection portion 132 is electrically connected to the pixel driving circuit of the corresponding second sub-pixel 32. In the same column of sub-pixels, the first connection line CD between the second end 1312 of the first connection portion 131 and the second end 1322 of the second connection portion 132 is approximately parallel to the second direction OV, the first end 1311 of the first connection portion 131 is located on a first side of the first connection line CD, which may be, for example, a side of the first connection line CD close to the first data line 21 corresponding to the sub-pixels in the column, and the first end 1321 of the second connection portion 132 is located on a second side of the first connection line CD, which may be, for example, a side of the first connection line CD close to the second data line 22 corresponding to the sub-pixels in the column.

[0097] For the first sub-pixel 31, the first connection portion 131 is located in the second source-drain metal layer L SD2 The second data line 22 adjacent to the first sub-pixel 31 is located in the first source-drain metal layer L SD1 Therefore, the first connection portion 131 and the second data line 22 are located in different film layers. In this way, even if the second end 1312 of the first connection portion 131 is close to the orthographic projection distance of the second data line 22 on the substrate 10, since the first connection portion 131 and the second data line 22 are located in different film layers, the parasitic capacitance generated between the two is small. The first end 1311 of the first connection portion 131 is far away from the second data line 22, so the electrical connection between the first end 1311 of the first connection portion 131 and the first data line 21 adjacent to the first sub-pixel 31 is far away from the second data line 22, so that a large parasitic capacitance will not be generated between the first end 1311 of the first connection portion 131 and the electrical connection and the second data line 22.

[0098] Similarly, for the second sub-pixel 32, the second connecting portion 32 is located on the second source-drain metal layer L SD2 , the first data line 21 adjacent to the second sub-pixel 32 is located in the first source-drain metal layer L SDTherefore, the second connection portion 132 and the first data line 21 are located in different film layers. In this way, even if the second end 1322 of the second connection portion 132 is close to the orthographic projection distance of the first data line 21 on the substrate 10, since the second connection portion 132 and the first data line 21 are located in different film layers, the parasitic capacitance generated between the two is small. The first end 1321 of the second connection portion 132 is far away from the second data line 22, so the electrical connection between the first end 1321 of the second connection portion 132 and the second data line 22 adjacent to the second sub-pixel 32 is far away from the first data line 21, so that no large parasitic capacitance is generated between the first end 1321 of the second connection portion 132 and the electrical connection and the first data line 21.

[0099] In this way, in the above-mentioned display substrate 1000, for a certain sub-pixel, the parasitic capacitance between the data line that is not electrically connected to the sub-pixel and the pixel driving circuit in the sub-pixel can be reduced, thereby reducing the influence of the parasitic capacitance on the luminescence of the sub-pixel, thereby improving the display effect of the display device.

[0100] For example, see Fig. 9B and 10B The display substrate 1000 includes a substrate 10 and a second source / drain metal layer L disposed on the substrate 10. SD2 The active layer L A In the case of the display substrate 1000, the display substrate 1000 further includes a substrate 10 and an active layer L disposed between the substrate 10 and the active layer L A There is an inorganic buffer layer 11 in between. The inorganic buffer layer 11 may be a single-layer structure or a multi-layer stacked structure, for example, a stacked structure in which inorganic film layers and organic film layers are alternately arranged.

[0101] In some embodiments, see Figure 7 , 8A , 9A to 10B and 11, in the case where each sub-pixel includes a fourth transistor T4 (which can be called a write transistor), along the first direction OU, the spacing between the fourth active patterns 74 of the fourth transistors T4 in each two adjacent sub-pixels is substantially equal, and along the second direction OV, the spacing between the fourth active patterns 74 of the fourth transistors T4 in each two adjacent sub-pixels is substantially equal. That is, each fourth active pattern 74 is located in the area S where the corresponding sub-pixel is located. P In each first sub-pixel 31, the second end 1312 of the first connection portion 131 is electrically connected to the fourth active pattern 74 of the corresponding fourth transistor T4; in each second sub-pixel 32, the second end 1322 of the second connection portion 132 is electrically connected to the fourth active pattern 74 of the corresponding fourth transistor T4.

[0102] For example, see Figures 9A to 10B, along the second direction OV, in each first sub-pixel 31, relative to the first end 1311 of the first connection portion 131 in the active layer L A The second end 1312 of the first connecting portion 131 is projected on the active layer L A The positive projection on the active layer L is closer to the corresponding fourth active pattern 74; in each second sub-pixel 32, relative to the second end 1322 of the second connecting portion 132, A The first end 1321 of the second connecting portion 132 is on the active layer L A The orthographic projection on is closer to the corresponding fourth active pattern 74 .

[0103] In some embodiments, see Fig. 8A , 8E , 9A and 10A, the second source and drain metal layer L SD2 It also includes a plurality of third connection parts 110 and a plurality of fourth connection parts 120. In each sub-pixel, the active pattern 71 of the first transistor T1 and the active pattern 77 of the seventh transistor T7 are electrically connected to the initialization voltage signal line IL through a corresponding third connection part 110, thereby realizing the electrical connection between the first transistor T1 and the seventh transistor T7 and the initialization voltage signal line IL.

[0104] In some embodiments, see Figure 7 Each row of sub-pixels includes a plurality of first sub-pixels 31 and a plurality of second sub-pixels 32 , and along the first direction OU, the first sub-pixels 31 and the second sub-pixels 32 are alternately arranged.

[0105] In the same row of sub-pixels, the second connection line EF between the second end 1312 of the first connection portion 131 and the second end 1322 of the second connection portion 132 is substantially parallel to the first direction OU. The first end 1311 of the first connection portion 131 is located on a side of the second connection line EF away from the corresponding fourth active pattern 74, and the first end 1321 of the second connection portion 132 is located on a side of the second connection line EF close to the corresponding fourth active pattern 74.

[0106] In this way, in the first sub-pixel 31, the distance between the first connection portion 131 and the fourth connection portion 120 can be increased, and in the second sub-pixel 32, the risk of short circuit of the pixel driving circuit in the first sub-pixel 31 can be reduced. In the second sub-pixel 32, the distance between the second connection portion 132 and the third connection portion 110 can be increased, and the risk of short circuit of the pixel driving circuit in the second sub-pixel 32 can be reduced.

[0107] In some embodiments, see Fig.8D and 9A 10B, the display substrate 1000 further includes a second source-drain metal layer L SD2 and the active layer LA The first insulating layer IS1 is provided with a plurality of first via holes 701 and a plurality of second via holes 702. In each first sub-pixel 31, the second end 1312 of the first connecting portion 131 is electrically connected to the fourth active pattern 74 of the corresponding fourth transistor T4 through a corresponding first via hole 701. In each second sub-pixel 32, the second end 1322 of the second connecting portion 132 is electrically connected to the fourth active pattern 74 of the corresponding fourth transistor T4 through a corresponding second via hole 702.

[0108] For example, see Fig. 8A , 9A 10B, the first insulating layer IS1 includes a first sub-insulating layer IS11 and a second sub-insulating layer IS12 , and the second sub-insulating layer IS12 is disposed on a side of the first sub-insulating layer IS11 close to the substrate 10 .

[0109] Active layer L A The first active connection portion 711, the second active connection portion 712 and the third active connection portion 713 are also included. In each first sub-pixel 31, the fourth active pattern 74 of the fourth transistor T4 is electrically connected to the second end 1312 of the first connection portion 131 through a corresponding first active connection portion 711; in each second sub-pixel 32, the fourth active pattern 74 of the fourth transistor T4 is electrically connected to the second end 1322 of the second connection portion 132 through a corresponding first active connection portion 711. In each sub-pixel, the first active pattern 71 of the first transistor T1 (which may be referred to as the first reset transistor) and the second active pattern 72 of the second transistor T2 (which may be referred to as the compensation transistor) are electrically connected through a corresponding second active connection portion 712, and a corresponding third active connection portion 713 is connected between the first active pattern 71 of the first transistor T1 and the seventh active pattern 77 of the seventh transistor T7.

[0110] The display substrate 1000 includes a second gate metal layer L G2 In the case of the second gate metal layer L G2 It is disposed between the first sub-insulating layer IS11 and the second sub-insulating layer IS12. Fig. 8A , 8C and 13C, the second gate metal layer L G2It also includes a plurality of first shielding portions 1021 and a plurality of second shielding portions 1022, and each sub-pixel is provided with a first shielding portion 1021 and a second shielding portion 1022. In each sub-pixel, the first shielding portion 1021 and the orthographic projection of the corresponding first active connection portion 711 on the substrate 10 have an overlapping area, the second shielding portion 1022 and the orthographic projection of the corresponding third active connection portion 713 on the substrate 10 have an overlapping area, and the second shielding portion 1022 and the orthographic projection of the corresponding second active connection portion 712 on the substrate 10 have an overlapping area.

[0111] Here, when a display device including the display substrate 1000 displays an image, the first connection portion 131 can shield the corresponding first active connection portion 711 and the third active connection portion 713 from light, thereby reducing the leakage current of the first transistor T1, the second transistor T2 and the seventh transistor T7; the second blocking portion 1022 can shield the corresponding second active connection portion 712 from light, thereby reducing the leakage current of the fourth transistor T4.

[0112] Based on this, in each first sub-pixel 31, the orthographic projections of the first connection portion 131 and the second blocking portion 1022 on the substrate 10 have an overlapping area, the orthographic projections of the first connection portion 131 and the first blocking portion 1021 on the substrate 10 do not have an overlapping area, and the second end 1312 of the first connection portion 131 and the orthographic projections of the second blocking portion 1022 on the substrate 10 do not have an overlapping area. In each second sub-pixel 32, the orthographic projections of the second connection portion 132 and the first blocking portion 1021 on the substrate 10 have an overlapping area, the orthographic projections of the second connection portion 132 and the second blocking portion 1022 on the substrate 10 do not have an overlapping area, and the second end 1322 of the second connection portion 132 and the first blocking portion 1021 do not have an overlapping area.

[0113] In this way, in the first sub-pixel 31, the first blocking portion 1021 and the second blocking portion 1022 can avoid the first via hole 701 set in the first insulating layer IS1, thereby avoiding the first blocking portion 1021 and the second blocking portion 1022 from affecting the electrical connection between the first connecting portion 131 and the corresponding fourth active pattern 74; in the second sub-pixel 32, the second blocking portion 1022 can avoid the second via hole 702 set in the first insulating layer IS1, thereby avoiding the first blocking portion 1021 and the second blocking portion 1022 from affecting the electrical connection between the second connecting portion 132 and the corresponding fourth active pattern 74.

[0114] Here, the first blocking portion 1021 and the second blocking portion 1022 may be formed of the same material and through the same patterning process, thereby simplifying the manufacturing process.

[0115] Illustratively, along the first direction OU, in the same row of sub-pixels, the first blocking portions 1021 and the second blocking portions 1022 are alternately arranged, and the adjacent first blocking portions 1021 and the second blocking portions 1022 respectively located in different sub-pixels are integrally formed.

[0116] In some embodiments, see Fig. 9B and 10B The first insulating layer IS1 further includes a third sub-insulating layer IS13 disposed on a side of the second sub-insulating layer IS12 close to the substrate 10. In this case, the first gate metal layer L G1 Disposed between the second sub-insulating layer IS12 and the third sub-insulating layer IS13.

[0117] For example, see Fig.8D , 13D and 13E, a seventh via 510 (for example, including 510A and 510B) is further provided in the first insulating layer IS1, an eighth via 513 is provided in the first sub-insulating layer IS11, and a ninth via 514 is provided through the first sub-insulating layer IS11 and the second sub-insulating layer IS12 (i.e., the ninth via 514 penetrates the first sub-insulating layer IS11 and the second sub-insulating layer IS12). One end of the third connecting portion 110 is electrically connected to the active pattern 77 of the seventh transistor T7 through the seventh via 510A, and the other end of the third connecting portion 110 is electrically connected to the initialization voltage signal line IL through the eighth via 513. One end of the fourth connecting portion 120 is electrically connected to the active pattern 71 of the first transistor T1 and the second active pattern 72 of the second transistor T2 through the seventh via 510B, and the other end of the fourth connecting portion 120 is electrically connected to the third active pattern 73 of the third transistor T3 (which can be called a driving transistor) through the ninth via 514.

[0118] In some embodiments, see Figure 7 and 8E , the maximum dimension of each first connection portion 131 in its extending direction is greater than the maximum dimension of each second connection portion 132 in its extending direction.

[0119] In some embodiments, see Figure 7 , 8E , 9A and 10A, the area of ​​the first end 1311 of each first connection portion 131 is larger than the area of ​​the second end 1312 thereof, and / or the area of ​​the first end 1321 of each second connection portion 132 is larger than the area of ​​the second end 1322 thereof. This facilitates the electrical connection between the first connection portion 131 and the corresponding first data line 21, and facilitates the electrical connection between the second connection portion 132 and the corresponding second data line 22.

[0120] In some embodiments, each first connection portion 131 also includes a first transition sub-portion 1313, which is connected between the first end 1311 and the second end 1312 of the first connection portion 131, and the dimension of the first transition sub-portion 1313 along the direction perpendicular to the extension direction of the first connection portion 131 is smaller than the dimension of the first end 1311 and the second end 1312 of the first connection portion 131 along the direction perpendicular to the extension direction of the first connection portion 131.

[0121] Exemplarily, each second connection portion 132 also includes a second transition sub-portion 1323, which is connected between the first end 1321 and the second end 1322 of the second connection portion 132, and the dimension of the second transition sub-portion 1323 along the direction perpendicular to the extension direction of the second connection portion 132 is smaller than the dimension of the first end 1321 and the second end 1322 of the second connection portion 132 along the direction perpendicular to the extension direction of the first connection portion 132.

[0122] In some embodiments, see Figure 7 , 8G 9A to 10B, each first data line 21 includes a first body 211 and a plurality of fifth connection portions 212. The plurality of fifth connection portions 212 are disposed on a side of the first body 211 close to the corresponding first sub-pixel 31 and arranged along the second direction OV, and each fifth connection portion 212 is electrically connected between the first body 211 and the first end 1311 of the corresponding first connection portion 131.

[0123] Each second data line 22 includes a second body 221 and a plurality of sixth connection portions 222. The plurality of sixth connection portions 222 are disposed on a side of the second body 221 close to the corresponding second sub-pixel 32 and arranged along the second direction OV, and each sixth connection portion 222 is electrically connected between the second body 221 and the first end 1321 of the corresponding second connection portion 132.

[0124] Here, the first data line 21 is electrically connected to the corresponding first connection part 131 through the plurality of fifth connection parts 212, which can increase the electrical contact area between the first data line 21 and the first connection part 131, which is beneficial to the electrical connection between the two. Similarly, the second data line 22 is electrically connected to the corresponding second connection part 132 through the plurality of sixth connection parts 222, which can increase the electrical contact area between the second data line 22 and the second connection part 132, which is beneficial to the electrical connection between the two.

[0125] For example, see Figures 9A to 10B The display substrate 1000 also includes a first source-drain metal layer L SD1 and the second source-drain metal layer L SD2The second insulating layer IS2 is provided with a plurality of third via holes 801 and a plurality of fourth via holes 802. Each fifth connection portion 212 is electrically connected to the first end 1311 of the corresponding first connection portion 131 through a corresponding third via hole 801, and each sixth connection portion 222 is electrically connected to the first end 1321 of the corresponding second connection portion 132 through a corresponding fourth via hole 802.

[0126] In some embodiments, see Figure 7 and 11 The display substrate 1000 also includes a plurality of first voltage signal lines 40 arranged on the substrate 10, and the positive projection of each first voltage signal line 40 on the substrate 10 is between the positive projections of the first data line 21 and the second data line 22 between each two adjacent columns of sub-pixels on the substrate 10, and each first voltage signal line 40 is electrically connected to at least one column of sub-pixels.

[0127] The first electrodes of the fifth transistors T5 of the sub-pixels in the same column can be electrically connected to the first voltage signal terminal VDD through the same first voltage signal line 40. Here, the first voltage signal line 40 can be used to transmit the first voltage signal Vdd from the first voltage signal terminal VDD to the sub-pixels electrically connected thereto.

[0128] For example, see Figure 7 , 8E 8F and 12, each first voltage signal line 40 includes a first source and drain metal layer L SD1 The first sub-voltage signal line 41 in the second source-drain metal layer L SD2 The first sub-voltage signal line 41 is electrically connected to the second sub-voltage signal line 42. For example, a plurality of fifth vias 501 are provided in the second insulating layer IS2, and the first sub-voltage signal line 41 and the second sub-voltage signal line 42 are electrically connected through at least one fifth via 501 among the plurality of fifth vias 501.

[0129] It should be noted that the first voltage signal line 40 can transmit a first voltage signal Vdd which is a constant voltage signal to the sub-pixel electrically connected thereto, that is, the voltages on the first sub-voltage signal line 41 and the second sub-voltage signal line 42 can both be stable voltages. When the display device including the above-mentioned display substrate 1000 displays a picture, the first sub-voltage signal line 41 which is arranged in the same layer as the first data line 21 and the second data line 22 and is located between the two can shield the data signal Vdata transmitted on the first data line 21 and the second data line 22 because it has a stable voltage. In this way, during the display process of the display device, the parasitic capacitance between the adjacent first data line 21 and the second data line 22 can be reduced by the first self-voltage signal line 41 arranged between the two, thereby reducing the crosstalk between the data signals Vdata and improving the display effect of the display device.

[0130] Exemplarily, the first sub-voltage signal line 41, the first data line 21 and the second data line 22 may be formed by the same patterning process so that they are disposed in the same layer.

[0131] Exemplarily, the orthographic projections of the first sub-voltage signal line 41 and the second sub-voltage signal line 42 on the substrate 10 overlap or partially overlap. Thus, the first via 501 can be disposed in the overlapped or overlapping region of the orthographic projections of the two, so that the two can be connected through the first via 501.

[0132] Based on this, in some embodiments, see Figure 7 , 8G and 12, among the first data line 21, the second data line 22 and the first sub voltage signal line 40 located between two adjacent columns of sub-pixels, the portion of the first data line 21 adjacent to the fifth via hole 501 is bent in a direction away from the fifth via hole 501 to form a first bent portion 213; the portion of the second data line 22 adjacent to the fifth via hole 501 is bent in a direction away from the fifth via hole 501 to form a second bent portion 223. The first bent portion 213 and the second bent portion 223 are opposite to each other to form an accommodation area A. The first sub voltage signal line 41 includes a conductive portion 411 passing through the fifth via hole 501, and the conductive portion 411 is located in the accommodation area A.

[0133] Here, along the first direction OU, the size D1 of the conductive part 411 can be larger than the width D0 of the first sub-voltage signal line 41, so that the first via 501 has a larger size along the first direction OU, thereby ensuring good electrical contact between the first sub-voltage signal line 41 and the second sub-voltage signal line 41.

[0134] In some embodiments, in the first data line 21 and the second data line 22 adjacent to a column of sub-pixels and located on both sides of the column of sub-pixels along the first direction OU, the first bent portion 213 and the second bent portion 223 are arranged opposite to each other. The display substrate 1000 further includes a seventh connecting portion 60 arranged between the first bent portion 213 and the second bent portion 223 arranged opposite to each other, and the seventh connecting portion 60 is arranged on the first source-drain metal layer L SD1 The seventh connection portion 60 is configured to shield the data signal Vdata of the first data line 21 and the second data line 22 adjacent to the column of sub-pixels and located on both sides of the column of sub-pixels along the first direction OU. The orthographic projection of the seventh connection portion 60 on the substrate 10 can be a regular pattern or an irregular pattern.

[0135] Exemplarily, the display substrate 1000 further includes a first source-drain metal layer L SD1 The anode layer is located away from the substrate 10, and the anode pattern of each sub-pixel can be arranged in the anode layer. Fig.11 and 12 In the case where the pixel driving circuit of each sub-pixel includes a sixth transistor T6 (which can be called a first light-emitting transistor), the sixth active pattern 76 of the sixth transistor T6 includes a first conductor portion, and the seventh connecting portion 60 is electrically connected to the first conductor portion of the corresponding active pattern 76 and the corresponding anode pattern.

[0136] Exemplarily, the display substrate 1000 further includes a light emitting device E disposed in each sub-pixel, and the light emitting device E further includes a cathode pattern, and a light emitting functional layer disposed between the anode pattern and the cathode pattern.

[0137] See also Fig.11 , the anode pattern of the light emitting device E can be electrically connected to the second voltage signal terminal VSS. For example, when the display substrate 1000 further includes a second voltage signal line 50, the anode pattern of the light emitting device E can be electrically connected to the second voltage signal terminal VSS through the second voltage signal line 50 to receive the second voltage signal Vss from the second voltage signal terminal VSS.

[0138] The light-emitting functional layer includes a light-emitting material layer, and further, may include at least one of an election transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), or a hole injection layer (HIL). The light-emitting material layer may be an organic light-emitting material layer, in which case the display device including the display substrate 200 is an OLED (Organic Light-Emitting Diode) display device. The light-emitting material layer may also be a quantum dot light-emitting material layer, in which case the display device including the display substrate 200 is a QLED (Quantum Dot Light-Emitting Diode) display device.

[0139] Here, the sixth active pattern 76 of the sixth transistor T6 may include a first conductor portion, a channel portion, and a second conductor portion, the first conductor portion and the second conductor portion being connected through the channel portion. The first conductor portion and the second conductor portion may serve as one of the source and the drain of the sixth transistor T6, and the second conductor portion may serve as the other of the source and the drain. For example, see Fig.11 In the case where the sixth transistor T6 is a P-type transistor, the first conductive portion connected to the anode layer 90 serves as the drain of the sixth transistor T6, and the second conductive portion serves as the source of the sixth transistor T6.

[0140] In the above-mentioned display substrate 1000, the seventh connection portion 60 is electrically connected to the light-emitting device E, and the light-emitting device E is electrically connected to the second voltage signal terminal VSS. Therefore, in the process of displaying an image by the display device including the display substrate 200, the seventh connection portion 60 can shield the data signal Vdata on the first signal line 21 and the second signal line 22 located between two columns of pixels due to its stable voltage, thereby reducing the crosstalk between the data signals Vdata and improving the display effect of the display device.

[0141] It should also be noted that since the seventh connecting portion 60 in the above-mentioned display substrate 200 is arranged on the same layer as the first sub-voltage signal line 41, the first data line 21 and the second data line 22, the seventh connecting portion 60 can be formed to reduce the crosstalk between the data signal Vdata of the first data line 21 and the second data line 22 without adding an additional composition process.

[0142] For example, see Figure 8H , 9A 10A, the display substrate 1000 also includes a first source and drain metal layer LSD1 The third insulating layer IS3 is located away from the substrate 10 , and a tenth via hole 504 is provided in the third insulating layer IS3 . The seventh connecting portion 60 is electrically connected to the anode pattern of the light emitting device E through the tenth via hole 504 .

[0143] In some embodiments, see Fig. 8E , 9A , 10A and 13D to 13F, the display substrate 1000 further includes an eighth connection portion 80 disposed in the second source-drain metal layer LSD2. An eleventh via hole 508 is further disposed in the first insulating layer IS1, and a twelfth via hole 505 is further disposed in the second insulating layer IS2. One end of the eighth connection portion 80 is electrically connected to the sixth active pattern 76 of the sixth transistor T6 through the eleventh via hole 508, and the other end of the eighth connection portion 80 is electrically connected to the seventh connection portion 60 through the twelfth via hole 505, so that the sixth active pattern 76 of the sixth transistor T6 and the anode pattern of the light-emitting device E can be electrically connected.

[0144] In some embodiments of the present disclosure, a display device is further provided, comprising the display substrate 1000. The beneficial effects of the display device are the same as those of the display substrate 1000, which will not be described in detail herein.

[0145] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate having a plurality of sub-pixels arranged in an array, each column of sub-pixels comprising a plurality of first sub-pixels and second sub-pixels, the first sub-pixels and the second sub-pixels being alternately arranged along a second direction; the display substrate comprising: substrate; A first source-drain metal layer is disposed on the substrate, wherein the first source-drain metal layer includes a plurality of first data lines and a plurality of second data lines; wherein, The first data lines and the second data lines are alternately arranged along a first direction, and one first data line and one second data line are arranged between every two adjacent columns of sub-pixels; Along the first direction, a column of sub-pixels corresponds to a first data line and a second data line respectively located on two sides thereof, each first sub-pixel in the column of sub-pixels is electrically connected to the corresponding first data line, and each second sub-pixel in the column of sub-pixels is electrically connected to the corresponding second data line; A second source-drain metal layer is disposed between the substrate and the first source-drain metal layer, wherein the second source-drain metal layer comprises: a plurality of first connection parts, each first sub-pixel is electrically connected to the corresponding first data line through a first connection part; a first end of each first connection part is electrically connected to the corresponding first data line, and a second end is electrically connected to the pixel driving circuit of the corresponding first sub-pixel; and A plurality of second connection parts, each second sub-pixel is electrically connected to the corresponding second data line through a second connection part; a first end of each second connection part is electrically connected to the corresponding second data line, and a second end is electrically connected to the pixel driving circuit of the corresponding second sub-pixel; wherein, In the same column of sub-pixels, a first line connecting the second end of the first connecting portion and the second end of the second connecting portion is substantially parallel to the second direction, the first end of the first connecting portion is located on a first side of the first line, and the first end of the second connecting portion is located on a second side of the first line.

2. The display substrate according to claim 1, wherein: The display substrate further includes an active layer disposed between the substrate and the second source-drain metal layer; Each sub-pixel further includes a write transistor, the write transistor including a fourth active pattern disposed in the active layer; along the first direction, the spacing between the fourth active patterns of the write transistors in each two adjacent sub-pixels is substantially equal, and along the second direction, the spacing between the fourth active patterns of the write transistors in each two adjacent sub-pixels is substantially equal; In each first sub-pixel, the second end of the first connection portion is electrically connected to the fourth active pattern of the corresponding write transistor; in each second sub-pixel, the second end of the second connection portion is electrically connected to the fourth active pattern of the corresponding write transistor.

3. The display substrate according to claim 2, wherein: Each row of sub-pixels includes a plurality of first sub-pixels and a plurality of second sub-pixels, and along the first direction, the first sub-pixels and the second sub-pixels are alternately arranged; In the same row of sub-pixels, the second line between the second end of the first connection portion and the second end of the second connection portion is roughly parallel to the first direction; the first end of the first connection portion is located on the side of the second connection portion away from the corresponding fourth active pattern, and the first end of the second connection portion is located on the side of the second connection portion close to the corresponding fourth active pattern.

4. The display substrate according to claim 2, further comprising a first insulating layer disposed between the second source-drain metal layer and the active layer, wherein a plurality of first via holes and a plurality of second via holes are disposed in the first insulating layer; In each first sub-pixel, the second end of the first connection portion is electrically connected to the fourth active pattern of the corresponding write transistor through a corresponding first via hole; in each second sub-pixel, the second end of the second connection portion is electrically connected to the fourth active pattern of the corresponding write transistor through a corresponding second via hole.

5. The display substrate according to claim 4, wherein: The first insulating layer includes a first sub-insulating layer and a second sub-insulating layer, the second sub-insulating layer is arranged between the first sub-insulating layer and the substrate, the display substrate also includes a second gate metal layer arranged between the first sub-insulating layer and the second sub-insulating layer; the second gate metal layer includes a plurality of first shielding parts and a plurality of second shielding parts, and each sub-pixel is provided with a first shielding part and a second shielding part; In each first sub-pixel, the orthographic projections of the first connecting portion and the second blocking portion on the substrate have an overlapping area, the orthographic projections of the first connecting portion and the first blocking portion on the substrate do not have an overlapping area, and the second end of the first connecting portion and the orthographic projection of the second blocking portion on the substrate do not have an overlapping area; In each second sub-pixel, the second connecting portion and the first blocking portion have an overlapping area in their orthographic projections on the substrate, the second connecting portion and the second blocking portion have no overlapping area in their orthographic projections on the substrate, and the second end of the second connecting portion and the first blocking portion have no overlapping area.

6. The display substrate according to claim 5, wherein: Along the first direction, in the same row of sub-pixels, the first shielding parts and the second shielding parts are arranged alternately, and the adjacent ones and the second shielding parts are located in different sub-pixels. The first shielding part and the second shielding part in the element are integrally formed.

7. The display substrate according to any one of claims 1 to 6, wherein: The maximum dimension of each first connection portion in the extending direction thereof is greater than the maximum dimension of each second connection portion in the extending direction thereof.

8. The display substrate according to any one of claims 1 to 6, wherein: The area of ​​the first end of each first connection portion is larger than the area of ​​the second end thereof, and / or the area of ​​the first end of each second connection portion is larger than the area of ​​the second end thereof.

9. The display substrate according to any one of claims 1 to 6, wherein: Each first data line includes a first body and a plurality of fifth connection portions; the plurality of fifth connection portions are disposed on a side of the first body close to the corresponding first sub-pixel and arranged along the second direction; each fifth connection portion is electrically connected between the first body and a first end of the corresponding first connection portion; Each second data line includes a second body and a plurality of sixth connection portions; the plurality of sixth connection portions are arranged on one side of the second body close to the corresponding second sub-pixel and arranged along the second direction; each sixth connection portion is electrically connected between the second body and the first end of the corresponding second connection portion.

10. The display substrate according to claim 9, further comprising a second insulating layer disposed between the first source-drain metal layer and the second source-drain metal layer, wherein a plurality of third via holes and a plurality of fourth via holes are disposed in the second insulating layer; Each fifth connection portion is electrically connected to the first end of the corresponding first connection portion through a corresponding third via hole, and each sixth connection portion is electrically connected to the first end of the corresponding second connection portion through a corresponding fourth via hole.

11. The display substrate according to any one of claims 1 to 6, further comprising a plurality of first voltage signal lines, wherein the orthographic projection of each first voltage signal line on the substrate is located between the orthographic projections of the first data line and the second data line between each two adjacent columns of sub-pixels on the substrate, and the first voltage signal line is electrically connected to at least one column of sub-pixels; The first voltage signal line comprises: A first sub-voltage signal line is disposed in the first source-drain metal layer, and a second sub-voltage signal line is disposed in the second source-drain metal layer, wherein the first sub-voltage signal line is electrically connected to the second sub-voltage signal line.

12. The display substrate according to claim 11, wherein: When the display substrate includes a second insulating layer, a plurality of fifth via holes are provided in the second insulating layer; the first sub-voltage signal line and the second sub-voltage signal line are electrically connected through at least one fifth via hole among the plurality of fifth via holes; wherein, among the first data line, the second data line and the first sub-voltage signal line located between two adjacent columns of sub-pixels, A portion of the first data line adjacent to the fifth via hole is bent in a direction away from the fifth via hole to form a first bent portion; A portion of the second data line adjacent to the fifth via hole is bent in a direction away from the fifth via hole to form a second bent portion; The first curved portion and the second curved portion are opposite to each other to form a receiving area; The first sub-voltage signal line includes a conductive portion passing through the fifth via hole, and the conductive portion is located in the accommodating area; along the first direction, the size of the conductive portion is greater than the width of the first sub-voltage signal line.

13. The display substrate according to claim 12, wherein: In the first data line and the second data line adjacent to a column of sub-pixels and located on both sides of the column of sub-pixels along the first direction, a seventh connecting portion is arranged between the first bending portion and the second bending portion, and the seventh connecting portion is arranged in the same layer as the first sub-voltage signal line.

14. The display substrate according to claim 13, further comprising an anode layer disposed on a side of the first source-drain metal layer away from the substrate; Each sub-pixel further includes a first light emission control transistor, which includes a sixth active pattern disposed in the active layer, and the sixth active pattern includes a first conductor portion; the seventh connection portion is electrically connected to the first conductor portion and the anode layer.

15. The display substrate according to claim 1, wherein: The first side of the first connection line is a side of the first connection line close to the first data line corresponding to the column of sub-pixels, and the second side of the first connection line is a side of the first connection line close to the second data line corresponding to the column of sub-pixels.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

Images