Display panel and manufacturing method thereof, and display device

Abstract

Disclosed is a display panel (10), wherein a second cathode layer (109) of a second display area (101b) has a hollowed-out area, and thus does not entirely cover the second display area (101b). Compared with the second cathode layer (109) entirely covering the second display area (101b), the influence on light transmittance can be reduced, and the imaging effect of a camera located in the second display area (101b) is better. Also disclosed are a method for preparing the display panel (10) and a display device comprising the display panel (10).

Description

[0001] This application claims priority to patent application No. PCT / CN2021 / 075839, filed on February 7, 2021, with invention name “Display substrate, display panel and display device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same, and a display device. Background Art

[0003] Organic light-emitting diode (OLED) display panels have been widely used due to their advantages such as self-luminescence, low driving voltage, and fast response speed.

[0004] In the related art, in order to improve the screen-to-body ratio of the display panel, the camera of the display device can be set in the display area of ​​the display panel. The display area of ​​the display panel includes: an anode layer, a light-emitting layer, and a cathode layer stacked in sequence in a direction away from the base substrate. The camera is set on the side of the anode layer away from the light-emitting layer.

[0005] However, since the cathode layer affects the transmittance, the imaging effect of the camera disposed in the display area of ​​the display panel is poor. Summary of the invention

[0006] The present application provides a display panel and a method for manufacturing the same, and a display device, which can solve the problem of poor imaging effect of a camera in a display panel in the related art. The technical solution is as follows:

[0007] In one aspect, a display panel is provided, the display panel comprising:

[0008] A base substrate, wherein the base substrate has a first display area and a second display area;

[0009] A first auxiliary electrode layer, a first anode layer, a first light-emitting layer and a first cathode layer are located in the first display area and are sequentially stacked in a direction away from the base substrate;

[0010] A second auxiliary electrode layer, a second anode layer, a second light emitting layer and a second cathode layer are located in the second display area and are sequentially stacked in a direction away from the base substrate;

[0011] Wherein, the first auxiliary electrode layer is connected to the first cathode layer, the second auxiliary electrode layer is connected to the first auxiliary electrode layer, the second cathode layer is connected to the first cathode layer, and the second cathode layer has at least one hollow area;

[0012] The display panel also includes a plurality of pixel circuits located in the second display area, each of the pixel circuits including at least one layer of opaque pattern; wherein the second auxiliary electrode layer includes: a plurality of electrically connected auxiliary electrode patterns, at least 50% of the orthographic projection area of ​​at least one layer of opaque pattern in at least one of the pixel circuits on the base substrate overlaps with the orthographic projection area of ​​the auxiliary electrode pattern on the base substrate.

[0013] Optionally, the orthographic projection of the auxiliary electrode pattern on the base substrate covers the orthographic projection of at least one layer of opaque pattern in at least one of the pixel circuits on the base substrate.

[0014] Optionally, at least a portion of an edge of an orthographic projection of the auxiliary electrode pattern on the base substrate is arc-shaped.

[0015] Optionally, the auxiliary electrode pattern includes: a first pattern and a second pattern;

[0016] The orthographic projection of the first pattern on the base substrate overlaps with more than 50% of the orthographic projection area of ​​at least one layer of opaque pattern in at least one pixel circuit on the base substrate;

[0017] The second pattern is used to be electrically connected to the adjacent auxiliary electrode pattern.

[0018] Optionally, the shape of the orthographic projection of the first pattern on the base substrate is a circle.

[0019] Optionally, the base substrate further has a peripheral area surrounding the first display area and the second display area;

[0020] The first auxiliary electrode layer and the first cathode layer are also located in the peripheral region, and a portion of the first auxiliary electrode layer located in the peripheral region is electrically connected to a portion of the first cathode layer located in the peripheral region.

[0021] Optionally, the orthographic projection of the first auxiliary electrode layer on the base substrate covers the first display area;

[0022] The peripheral area includes: a first area and a second area arranged opposite to and in parallel, and a third area and a fourth area arranged opposite to and in parallel, the extension direction of the first area is perpendicular to the extension direction of the third area, and the distance between the second display area and the first area is smaller than the distance between the second display area and the second area;

[0023] The portion of the first auxiliary electrode layer located in the first region is connected to the portion of the first cathode layer located in the first region, the portion of the first auxiliary electrode layer located in the third region is connected to the portion of the first cathode layer located in the third region, and the portion of the first auxiliary electrode layer located in the fourth region is connected to the portion of the first cathode layer located in the fourth region;

[0024] A portion of the first auxiliary electrode layer located in the second region is not connected to a portion of the first cathode layer located in the second region.

[0025] Optionally, a plurality of the auxiliary electrode patterns overlap each other.

[0026] Optionally, the display panel further includes: a plurality of first connecting electrodes located in the second display area, and the plurality of auxiliary electrode patterns are electrically connected via the plurality of first connecting electrodes.

[0027] Optionally, the display panel further includes: an active layer, a buffer layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, and a first source and drain layer, which are located in the first display area and the second display area and are sequentially stacked in a direction away from the base substrate;

[0028] The first source-drain electrode layer includes a plurality of first source-drain electrode layer patterns corresponding to the respective pixel circuits; the active layer includes a plurality of active patterns corresponding to the respective pixel circuits; the first gate layer includes a plurality of first gate layer patterns corresponding to the respective pixel circuits; and the second gate layer includes a plurality of second gate layer patterns corresponding to the respective pixel circuits;

[0029] The at least one layer of opaque patterns of the pixel circuit includes: a group of the first source and drain layer patterns located in the first source and drain layer, a group of the active patterns located in the active layer, a group of the first gate patterns located in the first gate layer, and a group of the second gate patterns located in the second gate layer.

[0030] Optionally, the display panel further includes: a first conductive layer located in the same layer as the first source and drain electrode layer, and a second conductive layer located in the same layer as the second gate layer; a buffer layer, a first gate insulating layer, a second gate insulating layer, and the interlayer dielectric layer all have a first via hole; the second conductive layer and the first conductive layer are electrically connected to the auxiliary electrode pattern through the first via hole;

[0031] The display panel further comprises a passivation layer and a first planarization layer located on a side of the first source and drain electrode layer away from the base substrate, and a plurality of first connection electrodes located between the passivation layer and the first planarization layer;

[0032] The passivation layer has a second via hole, at least a portion of the first connecting electrode is located in the second via hole and connected to the first conductive layer; the plurality of first connecting electrodes are used to connect the plurality of auxiliary electrode patterns.

[0033] Optionally, the display panel further includes: a passivation layer and a first planarization layer located on a side of the first source and drain electrode layer away from the base substrate, a plurality of second connection electrodes located between the passivation layer and the first planarization layer, a first signal transmission layer located on the same layer as the first source and drain electrode layer, and a third conductive layer located on the same layer as the first gate layer;

[0034] The first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer all have a third via hole; the first signal transmission layer is electrically connected to the third conductive layer through the third via hole;

[0035] The passivation layer has a fourth via hole, and at least a portion of the second connection electrode is located in the fourth via hole and connected to the first signal transmission layer.

[0036] Optionally, the third conductive layer includes: a plurality of first signal line segments, a plurality of second signal line segments, and a plurality of third signal line segments;

[0037] Wherein, each of the plurality of first signal line segments, the plurality of second signal line segments, and the plurality of third signal line segments is connected to one pixel circuit;

[0038] The plurality of second connecting electrodes include: a plurality of first-type second connecting electrodes connected to the plurality of first signal line segments, a plurality of second-type second connecting electrodes connected to the plurality of second signal line segments, and a plurality of third-type second connecting electrodes connected to the plurality of third signal line segments.

[0039] Optionally, the multiple first signal line segments are gate signal line segments for transmitting gate signals, the multiple second signal line segments are reset control signal line segments for transmitting reset control signals, and the multiple third signal line segments are light-emitting control signal line segments for transmitting light-emitting control signals.

[0040] Optionally, the display panel further includes: a plurality of third connection electrodes, and a fourth conductive layer; the fourth conductive layer includes a plurality of fourth signal line segments;

[0041] Each of the fourth signal line segments is connected to at least one of the pixel circuits, and at least some of the fourth signal line segments among the plurality of fourth signal line segments are electrically connected via at least some of the third connection electrodes.

[0042] Optionally, the display panel further includes a passivation layer and a first flat layer located on a side of the first source and drain electrode layer away from the base substrate, and a second source and drain electrode layer located on the first flat layer away from the first source and drain electrode layer; the fourth conductive layer and the first source and drain electrode layer are located on the same layer, and the plurality of third connection electrodes are located between the passivation layer and the first flat layer; the display panel further includes: a fifth conductive layer located on the same layer as the second source and drain electrode layer, the fifth conductive layer including a plurality of fifth signal line segments; the passivation layer has a fifth via hole;

[0043] At least a portion of the third connection electrode is located in the fifth via hole and connected to the fourth signal line segment. The first planar layer has a sixth via hole. At least a portion of the fifth signal line segment is located in the sixth via hole and connected to the third connection electrode.

[0044] Optionally, the plurality of fourth signal line segments and the plurality of fifth signal line segments are all positive power signal line segments for transmitting positive power signals.

[0045] Optionally, the fourth conductive layer and the first source and drain electrode layer are located in the same layer, the plurality of third connection electrodes are located between the passivation layer and the first planar layer; the passivation layer has a seventh via hole;

[0046] At least a portion of the third connection electrode is located in the seventh via hole and connected to the fourth signal line segment.

[0047] Optionally, the plurality of fourth signal line segments are data signal line segments for transmitting data signals.

[0048] Optionally, the fourth conductive layer and the second gate layer are located in the same layer, and the plurality of third connection electrodes are located between the passivation layer and the first flat layer; the display panel further comprises: a second signal transmission layer located in the same layer as the first source and drain layer; an eighth via hole is provided in the second gate insulating layer and the interlayer dielectric layer; the second signal transmission layer is located in the eighth via hole, and the second signal transmission layer is connected to the fourth signal line segment;

[0049] The passivation layer has a ninth via hole, and at least a portion of the third connection electrode is located in the ninth via hole and connected to the second signal transmission layer.

[0050] Optionally, the plurality of fourth signal line segments are initialization signal line segments, which are used to transmit initialization signals.

[0051] Optionally, the display panel further includes: an active layer, a buffer layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source and drain layer, a passivation layer and a first planar layer located in the first display area and the second display area and stacked in sequence in a direction away from the base substrate, and the display panel further includes a plurality of connecting electrodes located between the passivation layer and the first planar layer; at least part of the plurality of connecting electrodes is used to electrically connect the first gate layer, the second gate layer and at least one of the first source and drain layer in the first display area and the first gate layer, the second gate layer and at least one of the first source and drain layer in the second display area, and / or, at least part of the plurality of connecting electrodes is used to electrically connect at least two of the auxiliary electrode patterns located in the second display area, and / or, at least part of the plurality of connecting electrodes is used to connect at least one layer of an opaque pattern in at least two of the pixel circuits in the second display area;

[0052] Among them, the multiple connecting electrodes have multiple connecting points, and the connecting points include connecting vias or overlapping structures corresponding to the respective patterns connected to the multiple connecting electrodes, and the orthographic projection of the auxiliary electrode pattern on the base substrate has an overlapping area with the orthographic projection of at least one of the connecting points on the base substrate.

[0053] Optionally, an orthographic projection of the auxiliary electrode pattern on the base substrate covers an orthographic projection of at least one of the connection points on the base substrate.

[0054] Optionally, the second anode layer includes a plurality of anode patterns arranged at intervals; the display panel further includes: a pixel defining layer located on a side of the second anode layer away from the base substrate;

[0055] The pixel defining layer has a plurality of tenth via holes, and the tenth via holes expose the corresponding anode pattern; the second light-emitting layer includes: a plurality of light-emitting layer patterns, and the light-emitting layer patterns are at least partially located in the tenth via holes;

[0056] The second cathode layer at least partially covers the tenth via hole, and the at least one hollow region of the second cathode layer does not overlap with the tenth via hole.

[0057] Optionally, a boundary of the at least one hollow area at least partially comprises an arc shape.

[0058] Optionally, the first cathode layer and the second cathode layer are an integrated structure.

[0059] Optionally, an area of ​​an overlapping portion of an orthographic projection of the hollow region on the base substrate and an orthographic projection of the auxiliary electrode pattern on the base substrate is less than 10% of an area of ​​the hollow region.

[0060] In another aspect, a method for preparing a display panel is provided, the method comprising:

[0061] Providing a base substrate, the base substrate having a first display area and a second display area;

[0062] Forming a first auxiliary electrode layer, a first anode layer, a first light emitting layer, and a first cathode layer stacked in sequence in the first display area;

[0063] Forming a second auxiliary electrode layer, a second anode layer, a second light emitting layer, and a second cathode layer stacked in sequence in the second display area;

[0064] forming a plurality of pixel circuits in the second display area;

[0065] Among them, the first auxiliary electrode layer is connected to the first cathode layer, the second auxiliary electrode layer is connected to the first auxiliary electrode layer, the second cathode layer is connected to the first cathode layer, and the second cathode layer has at least one hollow area; the second auxiliary electrode layer includes: a plurality of electrically connected auxiliary electrode patterns; at least 50% of the orthographic projection area of ​​at least one layer of opaque pattern in at least one of the pixel circuits on the base substrate overlaps with the orthographic projection area of ​​one of the auxiliary electrode patterns on the base substrate.

[0066] In yet another aspect, a display device is provided, the display device comprising: an image sensor and the display panel as described in the above aspect;

[0067] The image sensor is located on a side of the base substrate in the display panel away from the second anode layer, and overlaps with the second display area of ​​the base substrate.

[0068] The beneficial effects of the technical solution provided by this application include at least:

[0069] The present application provides a display panel and a method for manufacturing the same, and a display device, wherein the second cathode layer included in the display panel has a hollow area, so the second cathode layer does not cover the second display area in its entirety. Compared with a cathode layer that covers the second display area in its entirety, the influence on light transmittance can be effectively reduced, and the imaging effect of a camera located in the second display area is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0071] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0072] Figure 2 is a top view of a substrate provided in an embodiment of the present application;

[0073] Figure 3 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application;

[0074] Figure 4 is a top view of a display panel provided in an embodiment of the present application;

[0075] Figure 5 yes Figure 4 A schematic diagram of the structure of the auxiliary electrode pattern;

[0076] Figure 6 is a top view of a display panel provided by an embodiment of the present application without an auxiliary electrode pattern;

[0077] Figure 7 Yes Figure 6 Schematic diagram of a display panel undergoing a diffraction simulation test;

[0078] Figure 8 Yes Figure 4 Schematic diagram of a display panel undergoing a diffraction simulation test;

[0079] Fig. 9 is a cross-sectional view of a display panel provided in an embodiment of the present application;

[0080] Fig.10 is a cross-sectional view of another display panel provided in an embodiment of the present application;

[0081] Fig.11 is a cross-sectional view of another display panel provided in an embodiment of the present application;

[0082] Fig.12 is a cross-sectional view of another display panel provided in an embodiment of the present application;

[0083] Fig.13 is a cross-sectional view of another display panel provided in an embodiment of the present application;

[0084] Fig.14 is a top view of another display panel provided in an embodiment of the present application;

[0085] Fig.15 is a cross-sectional view of another display panel provided in an embodiment of the present application;

[0086] Fig.16 is a schematic diagram of an auxiliary electrode pattern and a second cathode layer provided in an embodiment of the present application;

[0087] Fig.17 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application;

[0088] Fig.18 is a plan view of a sub-pixel in a first display area provided by an embodiment of the present application;

[0089] Fig.19 yes Fig.18 A plan view of an active layer of a sub-pixel included in one repeating unit;

[0090] Fig. 20 yes Fig.18 A plan view of a combination of an active layer of a sub-pixel and a first gate layer included in one repeating unit;

[0091] Fig.21 yes Fig.18 A plan view of a combination of an active layer of a sub-pixel and a first gate layer included in one repeating unit;

[0092] Fig. 22 yes Fig.18 A plan view of a combination of a sub-pixel active layer, a first gate layer, a second gate layer and a first source and drain electrode layer included in one repeating unit;

[0093] Fig.23 yes Fig.18 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a sub-pixel included in one repeating unit;

[0094] Fig.24 yes Fig.18 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a sub-pixel included in one repeating unit;

[0095] Fig.25 yes Fig.18 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a second source-drain electrode layer and a first anode layer of a sub-pixel included in one repeating unit;

[0096] Fig.26 is an equivalent circuit diagram of another pixel circuit provided in an embodiment of the present application;

[0097] Fig. 27 is a plan view of a sub-pixel in a second display area provided by an embodiment of the present application;

[0098] Fig.28 yes Fig. 27 A plan view of an active layer of a sub-pixel included in one repeating unit;

[0099] Fig.29 yes Fig. 27 A plan view of a combination of an active layer of a sub-pixel and a first gate layer included in one repeating unit;

[0100] Fig.30 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, and a second gate layer of a sub-pixel included in one repeating unit;

[0101] Fig.31 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer and a first source and drain electrode layer of a sub-pixel included in one repeating unit;

[0102] Fig.32 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer and a connecting electrode film layer of a sub-pixel included in one repeating unit;

[0103] Fig.33 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer and a connecting electrode film layer of three sub-pixels included in one repeating unit;

[0104] Fig.34 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a connecting electrode film layer, and a second source-drain electrode layer of a sub-pixel included in one repeating unit;

[0105] Fig.35 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a connecting electrode film layer, a second source-drain electrode layer, and a second anode layer of a sub-pixel included in one repeating unit;

[0106] Fig.36 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a connecting electrode film layer, a second source-drain electrode layer, and a second anode layer of another sub-pixel included in one repeating unit;

[0107] Fig.37 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a connecting electrode film layer, a second source-drain electrode layer, and a second anode layer of another sub-pixel included in a repeating unit;

[0108] Fig.38is a flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0109] Fig.39 is a flow chart of another method for preparing a display panel provided in an embodiment of the present application;

[0110] Fig.40 is a schematic diagram of a first auxiliary electrode layer and a second auxiliary electrode layer provided in an embodiment of the present application;

[0111] Fig.41 is a schematic structural diagram of an active layer provided in an embodiment of the present application;

[0112] Fig.42 is a schematic diagram of forming an active layer in a second display area provided by an embodiment of the present application;

[0113] Fig.43 is a schematic diagram of forming an active layer in a first display area provided by an embodiment of the present application;

[0114] Fig.44 is a schematic diagram of forming an active layer in a first display area and a second display area provided by an embodiment of the present application;

[0115] Fig.45 is a schematic structural diagram of a first gate layer provided in an embodiment of the present application;

[0116] Fig.46 is a schematic diagram of forming a first gate layer in a second display area provided by an embodiment of the present application;

[0117] Fig.47 is a schematic diagram of forming a first gate layer in a first display area provided by an embodiment of the present application;

[0118] Fig.48 is a schematic diagram of forming a first gate layer in a first display area and a second display area provided by an embodiment of the present application;

[0119] Fig.49 is a schematic structural diagram of a first gate insulating layer provided in an embodiment of the present application;

[0120] Fig.50 is a schematic diagram of forming a first gate insulating layer in a second display area provided by an embodiment of the present application;

[0121] Fig.51 is a schematic diagram of forming a first gate insulating layer in a first display area and a second display area provided by an embodiment of the present application;

[0122] Fig.52 is a schematic structural diagram of a second gate layer provided in an embodiment of the present application;

[0123] Fig.53 is a schematic diagram of forming a second gate layer in a second display area provided by an embodiment of the present application;

[0124] Fig.54 is a schematic diagram of forming a second gate layer in a first display area provided by an embodiment of the present application;

[0125] Fig.55 is a schematic diagram of forming a second gate layer in a first display area and a second display area provided by an embodiment of the present application;

[0126] Fig.56 is a schematic diagram of the structure of an interlayer dielectric layer provided in an embodiment of the present application;

[0127] Fig.57 is a schematic diagram of forming an interlayer dielectric layer in the second display area provided by an embodiment of the present application;

[0128] Fig.58 is a schematic diagram of forming an interlayer dielectric layer in a first display area provided by an embodiment of the present application;

[0129] Fig.59 is a schematic diagram of forming an interlayer dielectric layer in a first display area and a second display area provided by an embodiment of the present application;

[0130] Fig.60 is a schematic structural diagram of a first source and drain layer provided in an embodiment of the present application;

[0131] Fig.61 is a schematic diagram of forming a first source and drain electrode layer in a second display area provided by an embodiment of the present application;

[0132] Fig.62 is a schematic diagram of forming a first source and drain electrode layer in a first display area provided by an embodiment of the present application;

[0133] Fig.63 is a schematic diagram of forming a first source-drain electrode layer in a first display area and a second display area provided by an embodiment of the present application;

[0134] Fig.64 is a schematic structural diagram of a passivation layer provided in an embodiment of the present application;

[0135] Fig.65 is a schematic diagram of forming a passivation layer in a second display area provided by an embodiment of the present application;

[0136] Fig.66 is a schematic diagram of forming a passivation layer in a first display area provided by an embodiment of the present application;

[0137] Fig.67 is a schematic diagram of forming a passivation layer in a first display area and a second display area provided by an embodiment of the present application;

[0138] Fig.68 is a schematic diagram of the structure of a connecting electrode film layer provided in an embodiment of the present application;

[0139] Fig.69 is a schematic diagram of forming a connecting electrode film layer in a second display area provided by an embodiment of the present application;

[0140] Fig.70 This is a schematic diagram of forming a connecting electrode film layer in a first display area provided by an embodiment of the present application;

[0141] Fig.71 is a schematic diagram of forming a connecting electrode film layer in a first display area and a second display area provided by an embodiment of the present application;

[0142] Fig.72 is a schematic structural diagram of a first flat layer provided in an embodiment of the present application;

[0143] Fig.73 is a schematic diagram of forming a first flat layer in a second display area provided by an embodiment of the present application;

[0144] Fig.74 is a schematic diagram of forming a first flat layer in a first display area provided by an embodiment of the present application;

[0145] Fig.75 is a schematic diagram of forming a first flat layer in a first display area and a second display area provided by an embodiment of the present application;

[0146] Fig.76 is a schematic structural diagram of a second source and drain layer provided in an embodiment of the present application;

[0147] Fig.77 is a schematic diagram of forming a second source-drain electrode layer in a second display area provided by an embodiment of the present application;

[0148] Fig.78 is a schematic diagram of forming a second source and drain electrode layer in a first display area provided by an embodiment of the present application;

[0149] Fig.79 is a schematic diagram of forming a second source-drain electrode layer in a first display area and a second display area provided by an embodiment of the present application;

[0150] Fig.80 is a schematic structural diagram of a second flat layer provided in an embodiment of the present application;

[0151] Fig.81is a schematic diagram of forming a second flat layer in a second display area provided by an embodiment of the present application;

[0152] Fig.82 is a schematic diagram of forming a second flat layer in a first display area provided by an embodiment of the present application;

[0153] Fig.83 is a schematic diagram of forming a second flat layer in a first display area and a second display area provided by an embodiment of the present application;

[0154] Fig.84 is a schematic diagram of a first anode layer and a second anode layer provided in an embodiment of the present application;

[0155] Fig.85 is a schematic diagram of forming a second anode layer in a second display area provided by an embodiment of the present application;

[0156] Fig.86 A schematic diagram of forming a first anode layer in a first display area provided by an embodiment of the present application;

[0157] Fig.87 is a schematic diagram of forming a first anode layer in a first display area and forming a second anode layer in a second display area provided by an embodiment of the present application;

[0158] Fig.88 is a structural schematic diagram of a pixel definition layer provided in an embodiment of the present application;

[0159] Fig.89 is a schematic diagram of forming a pixel defining layer in a second display area provided by an embodiment of the present application;

[0160] Fig.90 is a schematic diagram of forming a pixel defining layer in a first display area provided by an embodiment of the present application;

[0161] Fig.91 is a schematic diagram of forming a pixel defining layer in a first display area and a second display area provided by an embodiment of the present application;

[0162] Fig.92 This is a schematic diagram of the structure of a first cathode layer and a second cathode layer provided in an embodiment of the present application;

[0163] Fig.93 is a schematic diagram of forming a second cathode layer in a second display area provided by an embodiment of the present application;

[0164] Fig.94 is a schematic diagram of forming a first cathode layer in a first display area provided by an embodiment of the present application;

[0165] Fig.95It is a schematic diagram of forming a first cathode layer in a first display area and forming a second cathode layer in a second display area provided by an embodiment of the present application;

[0166] Fig.96 It is a structural schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0167] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0168] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application. Figure 1 It can be seen that the display panel 10 may include: a base substrate 101, a first auxiliary electrode layer 102, a first anode layer 103, a first light-emitting layer 104, a first cathode layer 105, a second auxiliary electrode layer 106, a second anode layer 107, a second light-emitting layer 108, and a second cathode layer 109.

[0169] Figure 2 FIG. 1 is a top view of a substrate 101 provided in an embodiment of the present application. Figure 1 and Figure 2 The base substrate 101 may have a first display region 101a and a second display region 101b. The first auxiliary electrode layer 102, the first anode layer 103, the first light-emitting layer 104, and the first cathode layer 105 may be located in the first display region 101a and stacked in sequence in a direction away from the base substrate 101. The second auxiliary electrode layer 106, the second anode layer 107, the second light-emitting layer 108, and the second cathode layer 109 may be located in the second display region 101b and stacked in sequence in a direction away from the base substrate 101. The second cathode layer 109 may have at least one hollow region.

[0170] Since the second cathode layer 109 included in the display panel 10 has at least one hollow area, the second cathode layer 109 does not cover the second display area 101b in its entirety. Compared with the cathode layer that covers the second display area 101b in its entirety, the influence on light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area 101b is better.

[0171] In the embodiment of the present application, the first auxiliary electrode layer 102 may be connected to the first cathode layer 105, the second auxiliary electrode layer 106 may be connected to the first auxiliary electrode layer 102, and the second cathode layer 109 may be connected to the first cathode layer 105. That is, the first auxiliary electrode layer 102, the first cathode layer 105, the second auxiliary electrode layer 106, and the second cathode layer 109 are interconnected, and the signals transmitted in the first auxiliary electrode layer 102, the first cathode layer 105, the second auxiliary electrode layer 106, and the second cathode layer 109 may be the same.

[0172] Since the first auxiliary electrode layer 102, the first cathode layer 105, the second auxiliary electrode layer 106, and the second cathode layer 109 are all connected, the voltage difference between the power signals received by the first cathode layer 105 and the second cathode layer 109 can be made small, thereby ensuring the brightness uniformity of the display panel 10 and providing a better display effect of the display panel 10.

[0173] Figure 3 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Figure 3 In the embodiment of the present application, the display panel 10 may further include: a pixel circuit 110 ( Figure 3 1 shows a pixel circuit 110). Each pixel circuit 110 may include at least one layer of opaque pattern b. Figure 1 The film layer a in the embodiment includes at least one layer of opaque pattern b of the pixel circuit 110 .

[0174] refer to Figure 1 and Figure 3 It can also be seen that the second auxiliary electrode layer 106 may include: a plurality of electrically connected auxiliary electrode patterns 1061. Since the plurality of auxiliary electrode patterns 1061 can be electrically connected, the plurality of auxiliary electrode patterns 1061 can be interconnected, thereby ensuring the reliability of signal transmission by the plurality of auxiliary electrode patterns 1061.

[0175] Furthermore, at least 50% of the area of ​​the orthographic projection of at least one layer of the opaque pattern b in at least one pixel circuit 110 on the base substrate 101 overlaps with the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101. Alternatively, at least a portion of the boundary of at least one layer of the opaque pattern b in at least one pixel circuit 110 is located within the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101.

[0176] Thus, the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 can largely cover at least one layer of opaque pattern b in at least one pixel circuit 110. The diffraction effect of the pixel circuit 110 on the camera arranged in the second display area 101b can be small, and the display effect of the display panel 10 can be guaranteed. Among them, the opaque pattern can be a pattern in a film layer whose transmittance is less than a transmittance threshold. For example, the transmittance threshold is 10%.

[0177] Optionally, at least 50% of the area of ​​the orthographic projection of at least one layer of opaque pattern b in at least one pixel circuit 110 on the base substrate 101 overlaps with the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101, which may mean that a target ratio of the orthographic projection area of ​​at least one layer of opaque pattern b in at least one pixel circuit 110 on the base substrate 101 overlaps with the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101. The target ratio may be 60%, 65%, 70%, 75%, 80%, 85%, 90% or 100%.

[0178] In summary, the embodiment of the present application provides a display panel, wherein the second cathode layer included in the display panel has a hollow area, so the second cathode layer does not cover the second display area in its entirety. Compared with a cathode layer that covers the second display area in its entirety, the influence on light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area is better.

[0179] Optionally, the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may include metal. For example, the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may be molybdenum (Mo), or the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may be aluminum alloy.

[0180] The materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may be the same or different, which is not limited in the embodiment of the present application.

[0181] In the embodiment of the present application, the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 can cover the orthographic projection of at least one layer of opaque pattern b in at least one pixel circuit 110 on the base substrate 101. The plurality of pixel circuits 110 can be located on a side of the second anode layer 107 close to the base substrate 101.

[0182] Since the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 covers the orthographic projection of at least one layer of opaque pattern b in at least one pixel circuit 110 on the base substrate 101, the diffraction effect of the pixel circuit 110 on the camera set in the second display area 101b can be avoided, and the display effect of the display panel 10 is better.

[0183] refer to Figure 3 It can also be seen that the display panel 10 may further include: an active layer 112, a buffer layer 111, a first gate layer 113, a first gate insulating layer 114, a second gate layer 115 ( Figure 3 (not shown), a second gate insulating layer 116, an interlayer dielectric layer 117, a first source and drain electrode layer 118, a passivation layer 119, a first planarization layer 120, and a second source and drain electrode layer 121 ( Figure 3 The display panel 10 may further include another buffer layer 123 located on a side of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 close to the base substrate 101 .

[0184] The first source-drain electrode layer 118 includes a plurality of first source-drain electrode layer patterns corresponding to each pixel circuit 110. Each first source-drain electrode layer pattern includes a source electrode 1181 and a drain electrode 1182. The second source-drain electrode layer 121 includes a plurality of second source-drain electrode layer patterns corresponding to each pixel circuit 110. The active layer 112 includes a plurality of active patterns 1131 corresponding to each pixel circuit 110, the first gate electrode layer 113 includes a plurality of first gate patterns 1151 corresponding to each pixel circuit 110, and the second gate electrode layer 115 includes a plurality of second gate patterns corresponding to each pixel circuit 110. The source electrode 1181 and the drain electrode 1182 may be connected to one active pattern 1131. The drain electrode 1182 may also be connected to the second anode layer 107.

[0185] refer to Figure 3 , at least one layer of opaque pattern b of each pixel circuit 110 includes: a group of first source and drain electrode layer patterns located in the first source and drain electrode layer 118, a group of active patterns 1151 located in the active layer 112, a group of first gate patterns 1151 located in the first gate layer 113, and a group of second gate patterns located in the second gate layer 115. That is, each pixel circuit 110 may include multiple layers of opaque patterns. The transmittance of each layer of opaque pattern is less than the transmittance threshold.

[0186] Among them, a group of first source-drain layer patterns located in the first source-drain layer 118 are patterns belonging to the same pixel circuit 110. For example, a group of first source-drain layer patterns in the first source-drain layer 118 include: a source 1181 and a drain 1182 belonging to a transistor in the same pixel circuit 110. In addition, the first source-drain layer pattern also includes a switching pattern. A group of active patterns 1151 located in the active layer 112 include active layers of transistors in each pixel circuit 110. A group of first gate patterns 1151 located in the first gate layer 113 include gates of transistors in each pixel circuit 110. A group of second gate patterns located in the second gate layer 115 include capacitor plates.

[0187] refer to Figure 4 , the multi-layer opaque pattern b may include an overlapping portion c1 and a non-overlapping portion c2. The orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 covers the orthographic projection of at least one layer of the opaque pattern b in at least one pixel circuit 110 on the base substrate 101, which can be used to indicate that: the orthographic projection of at least part of the overlapping portion c1 on the base substrate 101 is located within the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101. Moreover, the orthographic projection of at least part of the non-overlapping portion c2 on the base substrate 101 is located within the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101.

[0188] Due to the limitation of the manufacturing process, the auxiliary electrode pattern 1061 may not completely cover the orthographic projection of the pixel circuit 110 on the base substrate 101, that is, it may not completely cover the orthographic projection of the multi-layer opaque pattern b included in the pixel circuit 110 on the base substrate 101. Therefore, in order to avoid the pixel circuit 110 having too large a diffraction effect on the camera arranged in the second display area 101b, the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 can be made to cover the orthographic projection of the overlapping portion c1 of the multi-layer opaque pattern b on the base substrate 101 as much as possible. That is, the portion that the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 cannot cover is mainly the non-overlapping portion c2 of the multi-layer opaque pattern b. For example, the orthographic projection of only a partial area of ​​the active pattern 1131 included in the multi-layer opaque pattern on the base substrate 101 cannot be covered by the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101.

[0189] In the embodiment of the present application, the second anode layer 107, the second light-emitting layer 108 and the second cathode layer 109 can be divided into a plurality of light-emitting units of the first sub-pixel. The orthographic projection of the light-emitting area of ​​the light-emitting unit of the first sub-pixel on the base substrate 101 can be located in the overlapping area of ​​the auxiliary electrode pattern 1061 and the second cathode layer 109. In addition to the light-emitting unit, each first sub-pixel also includes a pixel circuit 110 disposed in the second display area 101b.

[0190] refer to Figure 1 , the second anode layer 107 may include: a plurality of anode patterns 1071 arranged at intervals. The second light-emitting layer 108 may include: a plurality of light-emitting layer patterns 1081. And, the plurality of anode patterns 1071 and the plurality of light-emitting layer patterns 1081 may correspond. Each anode pattern 1071, together with a corresponding light-emitting layer pattern 1081 and the second cathode layer 109, constitutes a light-emitting unit of a first sub-pixel. Among them, two adjacent anode patterns 1081 may be located on the same side of a hollow area of ​​the second cathode layer 109, or may be located on both sides of a hollow area, which is not limited in the embodiment of the present application.

[0191] In the embodiment of the present application, the first anode layer 103, the first light-emitting layer 104 and the first cathode layer 105 can be divided into a plurality of light-emitting units of the second sub-pixel. The orthographic projection of the light-emitting region of the light-emitting unit of the second sub-pixel on the base substrate 101 can be located within the orthographic projection of the first cathode layer 105 on the base substrate 101.

[0192] The first anode layer 103 may also include: a plurality of anode patterns (not shown in the figure). The first light-emitting layer 104 may include: a plurality of light-emitting layer patterns (not shown in the figure). The plurality of anode patterns correspond to the plurality of light-emitting layer patterns one by one. Each anode pattern and a corresponding light-emitting layer pattern and the first cathode layer 105 may constitute a light-emitting unit of a second sub-pixel.

[0193] In the embodiment of the present application, the display panel 10 may further include: a pixel circuit located in the first display area 101a. In addition to the light emitting unit, each second sub-pixel also includes a pixel circuit located in the first display area 101a.

[0194] Figure 4 is a top view of a display panel provided in an embodiment of the present application. Figure 4 It can be seen that at least a portion of the edge of the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 may be arc-shaped.

[0195] Optionally, the edge of the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 may include an arc segment, wherein the ratio of the length of the arc segment to the perimeter of the edge may be greater than or equal to 50%.

[0196] For example, the ratio of the length of the arc segment to the perimeter of the edge may be 100%, that is, the edges of the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 may all be arc segments.

[0197] In order to avoid the diffraction effect of the pixel circuit 110 of the first sub-pixel on the camera disposed in the second display area 101b, the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 can cover the orthographic projection of at least one layer of opaque pattern b in the pixel circuit 110 of the first sub-pixel on the base substrate 101. That is, the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 can cover the orthographic projection of at least one layer of opaque pattern in a pixel circuit 110 on the base substrate 101.

[0198] Figure 5 yes Figure 4 Schematic diagram of the structure of the auxiliary electrode pattern 1061. Figure 5 It can be seen that the auxiliary electrode pattern 1061 may include: a first pattern 10611 and a second pattern 10612. The orthographic projection of the first pattern 10611 on the base substrate 101 overlaps with more than 50% of the orthographic projection area of ​​at least one layer of opaque pattern b in at least one pixel circuit 110 on the base substrate 101. The second pattern 10612 may be used to electrically connect to an adjacent auxiliary electrode pattern 1061. For example, the orthographic projection of the first pattern 10611 on the base substrate 101 may cover the orthographic projection of at least one layer of opaque pattern b in a pixel circuit 110 on the base substrate 101.

[0199] It should be noted that the edge of at least one layer of opaque pattern b included in the pixel circuit 110 includes at least two sub-edges and at least one corner located between the at least two sub-edges. The angle between the two sub-edges is less than 150 degrees. That is, the edge of at least one layer of opaque pattern b included in the pixel circuit 110 can be a broken line segment.

[0200] In the embodiment of the present application, the display panel (eg Figure 6 ), and a display panel provided with an auxiliary electrode pattern 1061 are respectively subjected to diffraction simulation tests. The steps of the diffraction simulation test may include: respectively arranging a point light source and a charge coupled device (CCD) on both sides of the display panel, and when the point light source emits light, using the CCD to test the scattering of the light emitted by the point light source after passing through the display panel. Figure 7 and Figure 8 The central bright spot can be used to represent the center of the point light source. The brighter the brightness of the surrounding bright spots, the more divergent the energy of the point light source is after passing through the display panel, and the more serious the diffraction is.

[0201] refer to Figure 7 and Figure 8 It can be seen that Figure 7The test image shown in FIG. 1 shows that the diffraction effect of the display panel without the auxiliary electrode pattern 1061 is stronger (the brightness of the peripheral bright spot is brighter), while Figure 8 The test image shows that the diffraction effect of the display panel with the auxiliary electrode pattern 1061 on the surface is weak (the brightness of the peripheral bright spots is weak).

[0202] In the embodiment of the present application, first patterns 10611 of different shapes are set in multiple display panels, and diffraction simulation tests are performed on multiple display panels with first patterns 10611 of different shapes. According to the test results, it can be determined that when the shape of the orthographic projection of the first pattern 10611 on the base substrate 101 is a circle, the diffraction effect of the display panel is the weakest, that is, the effect of reducing diffraction is the best compared to the display panel without the auxiliary electrode pattern 1061. Therefore, reference Figure 5 It can be seen that the shape of the orthographic projection of the first pattern 10611 in the auxiliary electrode pattern 1061 on the base substrate 101 can be a circle.

[0203] As an optional implementation, refer to Figure 1 The plurality of auxiliary electrode patterns 1061 overlap each other to achieve electrical connection of the plurality of auxiliary electrode patterns 1061. For example, the second pattern 10612 of a certain auxiliary electrode pattern 1061 may overlap the second pattern 10612 of another adjacent auxiliary electrode pattern 1061.

[0204] That is, for two adjacent auxiliary electrode patterns 1061 among the plurality of auxiliary electrode patterns 1061, the orthographic projection of one auxiliary electrode pattern 1061 on the base substrate 101 has an overlapping region with the orthographic projection of another auxiliary electrode pattern 1061 on the base substrate 101. The ratio of the area of ​​the overlapping region to the area of ​​the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate is in a range of 5% to 10%.

[0205] As another optional implementation, refer to Figure 3 The display panel 10 may further include: a plurality of first connection electrodes 124 located in the second display area 101 b , and the plurality of auxiliary electrode patterns 1061 are electrically connected via the plurality of first connection electrodes 124 .

[0206] refer to Fig. 9 The display panel 10 further includes: a first conductive layer 125 located at the same layer as the first source and drain electrode layer 118, and a second conductive layer 126 located at the same layer as the second gate layer 115. The buffer layer 111, the first gate insulating layer 114, the second gate insulating layer 116, and the interlayer dielectric layer 117 all have first via holes. The second conductive layer 126 and the first conductive layer 125 can be electrically connected to the auxiliary electrode pattern 1061 through the first via holes.

[0207] Furthermore, the plurality of first connection electrodes 124 are located between the passivation layer 119 and the first planar layer 120 . The passivation layer 119 may have a second via hole. At least a portion of the first connection electrode 124 is located in the second via hole and connected to the first conductive layer 125 .

[0208] refer to Fig. 9 , Fig. 9 , two auxiliary electrode patterns 1061, two first conductive patterns 1251 included in the first conductive layer 125, two second conductive patterns 1261 included in the second conductive layer 126, and a first connecting electrode 124 are shown. Among them, the buffer layer 111, the first gate insulating layer 114, the second gate insulating layer 116, and the interlayer dielectric layer 117 each have two first vias. The two second conductive patterns 1261 correspond to the two first conductive patterns 1251 one by one. The passivation layer 119 may have two second vias. One end of the first connecting electrode 124 is located in a second via and connected to a first conductive pattern 1251, and the other end of the first connecting electrode 124 is located in another second via and connected to another first conductive pattern 1251. Thus, the two auxiliary electrode patterns 1061 can be connected to the first connecting electrode 124 through the first conductive pattern 1251 and the second conductive pattern 1261, thereby realizing signal transmission of the two auxiliary electrode patterns 1061.

[0209] In the embodiment of the present application, the connection mode between the first auxiliary electrode layer 102 and the auxiliary electrode pattern 1061 in the second auxiliary electrode layer 106 may include two types. For example, the first auxiliary electrode layer 102 overlaps the auxiliary electrode pattern 1061 in the second display area 101b close to the first display area 101a. Alternatively, the first auxiliary electrode layer 102 and the auxiliary electrode pattern 1061 in the second display area 101b close to the first display area 101a are connected through the first connection electrode 124. In addition, the connection mode thereof can refer to the connection mode between the auxiliary electrode patterns 1061 in the second display area 101b, and the embodiment of the present application will not be repeated here.

[0210] In the examples of this application, refer to Fig.10 The display panel 10 may further include: a plurality of second connection electrodes 127 located between the passivation layer 119 and the first planar layer 120 , a first signal transmission layer 128 located on the same layer as the first source and drain layer 118 , and a third conductive layer 129 located on the same layer as the first gate layer 113 .

[0211] The first gate insulating layer 114, the second gate insulating layer 116, and the interlayer dielectric layer 117 all have third via holes. The first signal transmission layer 128 is connected to the third conductive layer 129 through the third via hole. The passivation layer 119 has a fourth via hole, and at least a portion of the second connection electrode 127 is located in the fourth via hole and connected to the first signal transmission layer 128.

[0212] In the embodiment of the present application, the third conductive layer 129 may include: a plurality of first signal line segments, a plurality of second signal line segments, and a plurality of third signal line segments, wherein each signal line segment 1291 of the plurality of first signal line segments, the plurality of second signal line segments, and the plurality of third signal line segments is connected to a pixel circuit 110 .

[0213] The plurality of second connection electrodes 127 include: a plurality of first-type second connection electrodes 127 connected to a plurality of first signal line segments, a plurality of second-type second connection electrodes 127 connected to a plurality of second signal line segments, and a plurality of third-type second connection electrodes 127 connected to a plurality of third signal line segments.

[0214] Assumptions Fig.10 The two signal line segments 1291 shown in FIG. 1 are both first signal line segments. Fig.10 The second connection electrode 127 in is a first type of second connection electrode 127. Assume that Fig.10 The two signal line segments 1291 shown in FIG. 1 are both second signal line segments. Fig.10 The second connection electrode 127 in is a second type of second connection electrode 127. Assume that Fig.10 The two signal line segments 1291 shown in FIG. 1 are both third signal line segments. Fig.10 The second connecting electrode 127 in FIG. 1 is a second connecting electrode 127 of the third type.

[0215] by Fig.10 The two signal line segments 1291 shown in the figure are both first signal line segments. The first gate insulating layer 114, the second gate insulating layer 116, and the interlayer dielectric layer 117 each have two third vias. And, Fig.10 1 shows two first signal transmission patterns 1281 of the first signal transmission layer 128, each of which is connected to the first signal line segment 1291 through a third via hole. The passivation layer 119 has two fourth via holes. One end of the second connection electrode 127 is located in one fourth via hole and connected to one first signal transmission pattern 1281. The other end of the second connection electrode 127 is located in another fourth via hole and connected to another first signal transmission pattern 1281. Thus, the two first signal line segments 1291 can be connected to the second connection electrode 127 through the two first signal transmission patterns 128, thereby realizing signal transmission of the two first signal line segments 1291.

[0216] Among them, the multiple first signal segments can all be gate signal segments, the multiple second signal segments can all be reset control signal segments, and the multiple third signal segments can all be emission control (EM) signal segments. That is, the multiple gate signal segments can be connected through multiple first-type second connection electrodes 127 to achieve the transmission of gate signals of multiple gate signal segments. The multiple reset control signal segments can be connected through multiple second-type second connection electrodes 127 to achieve the transmission of reset control signals of multiple reset control signal segments. The multiple emission control signal segments can be connected through multiple third-type second connection electrodes 127 to achieve the transmission of emission control signals of multiple emission control signal segments.

[0217] In the embodiment of the present application, the first display area 101a includes a gate signal line, which can be connected to the gate signal line segment of the second display area 101b close to the first display area 101a through the second connection electrode 127. In addition, the connection method can refer to the connection method between the various gate signal line segments in the second display area 101b, and the embodiment of the present application will not be repeated here. The first display area 101a includes a reset control signal line, which can be connected to the reset control signal line of the second display area 101b close to the first display area 101a through the second connection electrode 127. In addition, the connection method can refer to the connection method between the various reset control signal line segments in the second display area 101b, and the embodiment of the present application will not be repeated here. The first display area 101a includes a light-emitting control signal line, which can be connected to the light-emitting control signal line segment of the second display area 101b close to the first display area 101a through the second connection electrode 127. Moreover, the connection method thereof may refer to the connection method between the light emitting control signal line segments in the second display area 101 b , and the embodiments of the present application will not be described in detail here.

[0218] As a possible situation, in the embodiment of the present application, refer to Fig.11 The display panel 10 may further include: a plurality of third connection electrodes 130 , a fourth conductive layer 131 and a fifth conductive layer 132 . The plurality of third connection electrodes 130 may be located between the passivation layer 119 and the second planar layer 122 .

[0219] The fourth conductive layer 131 may be located at the same layer as the first source-drain electrode layer 118, and the fourth conductive layer 131 may include a plurality of fourth signal line segments 1311. The fifth conductive layer 132 may be located at the same layer as the second source-drain electrode layer 121, and the fifth conductive layer 132 may include a plurality of fifth signal line segments 1321. Each of the plurality of fourth signal line segments 1311 and the plurality of fifth signal line segments 1321 is connected to one pixel circuit 110, and the plurality of fourth signal line segments 1311 are electrically connected via a plurality of third connection electrodes 130, and the plurality of fifth signal line segments 1321 are electrically connected via a plurality of third connection electrodes 130.

[0220] refer to Fig.11 The passivation layer 119 has a fifth via hole. At least a portion of the third connection electrode 130 is located in the fifth via hole and connected to the fourth signal line segment 1311. The first planar layer 120 has a sixth via hole. At least a portion of the fifth signal line segment 1321 is located in the sixth via hole and connected to the third connection electrode 130.

[0221] Fig.11 1 and 2. The passivation layer 119 has two fifth via holes. One end of the third connection electrode 130 is located in one of the fifth via holes and connected to one of the fourth signal line segments 1311. The other end of the third connection electrode 130 is located in another of the fifth via holes and connected to another of the fourth signal line segments 1311. In addition, the first flat layer 120 has two sixth via holes, and at least a portion of each of the fifth signal line segments 1321 is located in one of the sixth via holes and connected to one of the third connection electrodes 130. Thus, the two fourth signal line segments 1311 and the two fifth signal line segments 1321 can be connected through the third connection electrode 130, thereby realizing signal transmission of the two fourth signal line segments 1311 and the two fifth signal line segments 1321.

[0222] Optionally, the plurality of fourth signal segments 1311 and the plurality of fifth signal segments 1321 are all positive voltage drain drain (VDD) signal segments. That is, the plurality of fourth signal segments 1311 and the plurality of fifth signal segments 1321 can be connected via the plurality of third connection electrodes 130 to achieve transmission of positive power supply signals.

[0223] In the embodiment of the present application, the first display area 101a includes a positive power signal line, which can be connected to a positive power signal line segment of the second display area 101b close to the first display area 101a through the third connection electrode 127. In addition, the connection method can refer to the connection method between each positive power signal line segment in the second display area 101b, and the embodiment of the present application will not be repeated here.

[0224] As another possible situation, in the embodiment of the present application, refer to Fig.12 The display panel 10 may further include: a plurality of third connection electrodes 130 and a fourth conductive layer 131. The plurality of third connection electrodes 130 may be located in the same layer as the second source-drain electrode layer 121. The fourth conductive layer 131 may be located in the same layer as the first source-drain electrode layer 118, and the fourth conductive layer 131 may include a plurality of fourth signal line segments 1311. Each fourth signal line segment 1311 is connected to a pixel circuit 110, and at least some of the fourth signal line segments 1311 in the plurality of fourth signal line segments 1311 are electrically connected through at least some of the third connection electrodes 130.

[0225] refer to Fig.12 The passivation layer 119 may be a seventh via hole, and at least a portion of the third connection electrode 130 may be located in the seventh via hole and connected to the fourth signal line segment 1311 . Fig.12 , two fourth signal line segments 1311 are shown, and the passivation layer 119 has two seventh via holes. One end of the third connection electrode 130 is located in one seventh via hole and connected to one fourth signal line segment 1311. The other end of the third connection electrode 130 is located in another seventh via hole and connected to another fourth signal line segment 1311. Thus, the two fourth signal line segments 1311 are connected through the third connection electrode 130, thereby realizing signal transmission of the two fourth signal line segments 1311.

[0226] Optionally, the plurality of fourth signal line segments 1311 are all data signal line segments. That is, at least some of the fourth signal line segments 1131 in the plurality of fourth signal line segments 1311 are connected through at least some of the third connection electrodes 130 to achieve transmission of data signals. For example, the fourth signal line segments 1311 of each column of pixels are electrically connected through the third connection electrodes 130.

[0227] In the embodiment of the present application, the first display area 101a includes a data signal line, and the data signal line can be connected to the data signal line of the second display area 101b close to the first display area 101a through the third connection electrode 127. And, its connection method can refer to the connection method between the various data signal line segments in the second display area 101b, and the embodiment of the present application will not be repeated here.

[0228] As another possible situation, refer to Fig.13In the embodiment of the present application, the display panel 10 may further include: a plurality of third connection electrodes 130, a fourth conductive layer 131 and a second signal transmission layer 133. The plurality of third connection electrodes 130 may be located in the same layer as the second source and drain electrode layer 121. The fourth conductive layer 131 and the second gate layer 115 are located in the same layer, and the fourth conductive layer 131 includes a plurality of fourth signal line segments 1311. The second signal transmission layer 133 may be located in the same layer as the first source and drain electrode layer 118.

[0229] The second gate insulating layer 116 and the interlayer dielectric layer 117 may have an eighth via hole. The second signal transmission layer 133 may be located in the eighth via hole, and the second signal transmission layer 133 may be connected to the fourth signal line segment 1311. The passivation layer 119 has a ninth via hole, and at least a portion of the third connection electrode 130 may be located in the ninth via hole and connected to the second signal transmission layer 133.

[0230] Fig.13 , two fourth signal line segments 1311 and two second signal transmission patterns 1331 included in the second signal transmission layer 133 are shown. The second gate insulation layer 116 and the interlayer dielectric layer 117 may have two eighth vias. The two second signal transmission patterns 1331 are respectively located in one eighth via and connected to one fourth signal line segment 1311. The passivation layer 119 has two ninth vias. One end of the third connection electrode 130 is located in one ninth via and connected to one second signal transmission pattern 1331. The other end of the third connection electrode 130 is located in another ninth via and connected to another second signal transmission pattern 1331. Thus, the two fourth signal line segments 1311 are connected through the third connection electrode 130, thereby realizing signal transmission of the two fourth signal line segments 1311.

[0231] Optionally, the plurality of fourth signal line segments 1311 may all be initialization (vinit) signal line segments, that is, the plurality of fourth signal line segments 1311 are connected via the plurality of third connection electrodes 130 to implement transmission of the initialization signal.

[0232] In the embodiment of the present application, the first display area 101a includes an initialization signal line, and the initialization signal line can be connected to the initialization signal line of the second display area 101b close to the first display area 101a through the third connection electrode 127. And, its connection method can refer to the connection method between each initialization signal line segment in the second display area 101b, and the embodiment of the present application will not be repeated here.

[0233] Combination Figures 9 to 13At least part of the multiple connection electrodes (multiple first connection electrodes, multiple second connection electrodes, and multiple third connection electrodes) in the display panel can be used to electrically connect at least one of the first gate layer, the second gate layer, and the first source-drain electrode layer in the first TV area 101a, and at least one of the first gate layer, the second gate layer, and the first source-drain electrode layer in the second display area 101b. And / or, at least part of the multiple connection electrodes in the display panel are used to electrically connect at least two auxiliary electrode patterns 1061 located in the second display area 101b. And / or, at least part of the multiple connection electrodes in the display panel are used to connect at least one layer of opaque pattern in at least two pixel circuits in the second display area 101b.

[0234] Combination Figures 9 to 13 , the multiple connection electrodes may have multiple connection points. The connection points include connection vias or overlapping structures corresponding to the patterns connected to the multiple electrodes. For example, the connection points include: the overlapping part of the orthographic projection of the connection electrode on the base substrate 101 and the orthographic projection of the conductive layer on the base substrate 101. The orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 may have an overlapping area with the orthographic projection of at least one connection point on the base substrate 101.

[0235] Optionally, the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 may cover the orthographic projection of at least one connection point on the base substrate 101. Fig. 9 Two connections are shown, and the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 covers the orthographic projection of the two connections on the base substrate 101 .

[0236] Since the area where multiple layers of conductive film layers are superimposed (i.e., the area where the connection is located) has a greater diffraction effect on the camera, while the area where a single layer of conductive film layers is located has a smaller diffraction effect on the camera, the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 covers the orthographic projection of the connection on the base substrate 101, which can greatly reduce the diffraction and improve the display effect of the display panel.

[0237] Combination Figure 3 ,as well as Figures 9 to 13 The display panel 10 may further include: a pixel defining layer 134 located on a side of the second anode layer 107 away from the base substrate 101. Figure 3 The pixel defining layer 134 may have a plurality of tenth via holes, and at least a portion of the plurality of light-emitting layer patterns 1081 included in the second light-emitting layer 108 may be located in the tenth via holes. The second cathode layer 109 at least partially covers the tenth via holes, and at least one hollow region of the second cathode layer 109 does not overlap with the tenth via holes.

[0238] Combination Figure 3 ,as well as Figures 9 to 13 The display panel 10 may further include: a support layer 135 located on a side of the pixel defining layer 134 away from the base substrate 101. Figure 3 The support layer 135 may have a plurality of support patterns. The orthographic projections of the plurality of support patterns on the base substrate 101 and the orthographic projections of the light-emitting layer pattern 1081 on the base substrate 101 at least partially do not overlap. The portion of the second cathode layer 109 other than the hollowed-out region may be connected to the light-emitting layer pattern 1081 to ensure that the first sub-pixel located in the second display region 101b can emit light normally.

[0239] In the examples of this application, refer to Figure 1 and Figure 3 The first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 can be located in the same layer, the first light-emitting layer 104 and the second light-emitting layer 108 can be located in the same layer, and the first cathode layer 105 and the second cathode layer 109 can be located in the same layer. For example, the first cathode layer 105 and the second cathode layer 109 can be an integrated structure.

[0240] That is, the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 can be prepared by the same patterning process. The first light-emitting layer 104 and the second light-emitting layer 108 can be prepared by the same patterning process. The first cathode layer 105 and the second cathode layer 109 can be prepared by the same patterning process.

[0241] Fig.14 is a top view of another substrate provided in an embodiment of the present application. Fig.14 It can be seen that the base substrate 101 also has a peripheral region 101c surrounding the first display region 101a and the second display region 101b. The first auxiliary electrode layer 102 and the first cathode layer 105 may also be located in the peripheral region 101c. Fig.15 , a portion of the first auxiliary electrode layer 102 located in the peripheral region 101 c may be connected to a portion of the first cathode layer 105 located in the peripheral region 101 c .

[0242] Since the portion of the first auxiliary electrode layer 102 located in the peripheral region 101c is connected to the portion of the first cathode layer 105 located in the peripheral region 101c, it is not necessary to connect the portion of the first auxiliary electrode layer 102 located in the first display region 101a to the portion of the first cathode layer 105 located in the first display region 101a. Therefore, it is possible to avoid affecting the display effect of the first display region 101a due to the connection between the first auxiliary electrode layer 102 and the first cathode layer 105.

[0243] Optionally, the portion of the first auxiliary electrode layer 102 located in the peripheral area 101c and the portion of the first cathode layer 105 located in the peripheral area 101c can be overlapped with at least one layer of conductive pattern between the first auxiliary electrode layer 102 and the first cathode layer 105, respectively, to achieve electrical connection between the portion of the first auxiliary electrode layer 102 located in the peripheral area 101c and the portion of the first cathode layer 105 located in the peripheral area 101c.

[0244] refer to Fig.15 , the buffer layer 111, the first gate insulating layer 114, the second gate insulating layer 116, the interlayer dielectric layer 117, the passivation layer 119, the first planar layer 120 and the second planar layer 122 all have an eleventh via hole. The orthographic projection of the eleventh via hole on the base substrate 101 is located in the peripheral area 101c, and the eleventh via hole exposes the portion of the first auxiliary electrode layer 102 located in the peripheral area 101c.

[0245] The display panel 10 further includes: a third signal transmission layer 136, a fourth signal transmission layer 137, a fifth signal transmission layer 138, and a sixth signal transmission layer 139 located in the eleventh via hole. The third signal transmission layer 136 is located in the same layer as the second gate layer 115 and is connected to the first auxiliary electrode layer 102. The fourth signal transmission layer 137 is located in the same layer as the first source and drain electrode layer 118, the fifth signal transmission layer 138 is located in the same layer as the second source and drain electrode layer 121, and the sixth signal transmission layer 139 is located in the same layer as the second anode layer 107.

[0246] The pixel defining layer 134 has a twelfth via hole, the orthographic projection of the twelfth via hole on the base substrate 101 is located in the peripheral area 101c, and the sixth signal transmission layer 139 is exposed. The orthographic projection of the portion of the first cathode layer 105 located in the peripheral area 101a on the base substrate 101 at least partially overlaps with the orthographic projection of the sixth signal transmission layer 139 on the base substrate 101, and is connected to the sixth signal transmission layer 139. Thus, the first auxiliary electrode layer 102 and the first cathode layer 105 are connected through the third signal transmission layer 136, the fourth signal transmission layer 137, the fifth signal transmission layer 138 and the sixth signal transmission layer 139, so as to realize the transmission of signals between the first auxiliary electrode layer 102 and the first cathode layer 105.

[0247] refer to Fig.14 The peripheral area 101c may include: a first area 101c1 and a second area 101c2 arranged oppositely and in parallel, and a third area 101c3 and a fourth area 101c4 arranged oppositely and in parallel. The extension direction of the first area 101c1 may be perpendicular to the extension direction of the third area 101c3, and the distance between the second display area 101b and the first area 101c1 may be smaller than the distance between the second display area 101b and the second area 101c2.

[0248] refer to Fig.14 , the first area 101c1 may be located on the upper side of the first display area 101a, the second area 101c2 may be located on the lower side of the first display area 101a, the third area 101c3 may be located on the left side of the first display area 101a, and the fourth area 101c4 may be located on the right side of the first display area 101a. The distance between the second display area 101b and the third area 101c3 may be equal to the distance between the second display area 101b and the fourth display area, that is, the second display area 101b may be located in the middle of the side of the first display area 101a close to the first area 101c1.

[0249] In the embodiment of the present application, the orthographic projection of the first auxiliary electrode layer 102 on the base substrate 101 can cover the first display area 101a, that is, the first auxiliary electrode layer 102 can be prepared as a whole layer. Alternatively, the first auxiliary electrode layer 102 can only cover part of the first display area 101a. The embodiment of the present application does not limit the shape of the first auxiliary electrode layer 102, and it is only necessary to ensure that the first auxiliary electrode layer 102 can be connected to the first cathode layer 105 and the second auxiliary electrode layer 106.

[0250] On the premise that the orthographic projection of the first auxiliary electrode layer 102 on the base substrate 101 covers the first display area 101a, the first auxiliary electrode layer 102 can be located in the first area 101c1, the second area 101c2, the third area 101c3, and the fourth area 101c4 of the peripheral area 101c. In addition, the portion of the first auxiliary electrode layer 102 located in the first area 101c1 is connected to the portion of the first cathode layer 105 located in the first area 101c1. The portion of the first auxiliary electrode layer 102 located in the third area 101c3 is connected to the portion of the first cathode layer 105 located in the third area 101c3. The portion of the first auxiliary electrode layer 102 located in the fourth area 101c4 is connected to the portion of the first cathode layer 105 located in the fourth area 101c4. In addition, the portion of the first auxiliary electrode layer 102 located in the second area 101c2 is not connected to the portion of the first cathode layer 105 located in the second area 101c2.

[0251] Since other wirings are usually required to be arranged in the second area 101c2, the portion of the first auxiliary electrode layer 102 located in the second area 101c2 is not connected to the portion of the first cathode layer 105 located in the second area 101c2, thereby avoiding affecting the arrangement of other wirings.

[0252] Optionally, the first connection electrode 124, the second connection electrode 127, and the third connection electrode 130 can all be made of a transparent conductive material. This can ensure the transmittance of the second display area 101b and improve the imaging effect of the camera. For example, the first connection electrode 124, the second connection electrode 127, and the third connection electrode 130 can all be made of indium tin oxide (ITO).

[0253] As an optional implementation, refer to Fig.16 The second cathode layer 109 may include: a plurality of cathode patterns 1091. The plurality of cathode patterns 1091 may overlap each other, and the plurality of cathode patterns 1091 may surround at least one hollow region c after overlapping.

[0254] The orthographic projection of each cathode pattern 1091 on the substrate 101 may cover the orthographic projection of at least one light-emitting layer pattern 1081 on the substrate 101. For example, the orthographic projection of each cathode pattern 1091 on the substrate 101 may cover the orthographic projection of three light-emitting layer patterns 1081 on the substrate 101. The three light-emitting layer patterns are light-emitting layer patterns of three first sub-pixels, respectively. The three first sub-pixels are red (red, R) sub-pixels, green (green, G) sub-pixels, and blue (blue, B) sub-pixels.

[0255] refer to Fig.16 It can also be seen that the orthographic projection of each auxiliary electrode pattern 1061 on the base substrate 101 can cover the orthographic projection of at least one layer of opaque pattern in one pixel circuit 110 on the base substrate 101. In addition, since the distance between the three pixel circuits 110 covered by each cathode pattern 1091 is relatively close, the three auxiliary electrode patterns 1061 covering the three pixel circuits 110 can be directly overlapped without being connected through the first connection electrode 124.

[0256] As another optional implementation, refer to Figure 4 Each hollow area in the second cathode layer 109 is formed by digging a hole in the second cathode layer 109 .

[0257] Optionally, the boundary of at least one hollow area includes at least an arc. For example, the shape of the hollow area can be circular or elliptical. Of course, the shape of at least one hollow area can also be square or rectangular, etc., and the embodiment of the present application does not limit the shape of the hollow area. The area of ​​the hollow area ranges from 350 square microns to 630 square microns.

[0258] In the above two methods, the orthographic projection of each hollow region on the base substrate 101 may have an overlapping area with the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 that is less than 10% of the area of ​​the hollow region.

[0259] Fig.17 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application. It should be noted that, in the embodiment of the present application, the equivalent circuit diagram of the pixel circuit of the first sub-pixel located in the second display area 101b may be substantially the same as the equivalent circuit diagram of the pixel circuit of the second sub-pixel located in the first display area 101a. That is, Fig.17 The equivalent circuit diagram shown in may be an equivalent circuit diagram of a pixel circuit of a sub-pixel in the first display area 101b or the first display area 101a. However, the embodiment of the present application is not limited thereto. In the embodiment of the present application, the equivalent circuit diagram of the pixel circuit of the sub-pixel located in the first display area 101b may be different from the equivalent circuit diagram of the pixel circuit of the sub-pixel located in the first display area 101a.

[0260] Fig.18 1 is a plan view of a sub-pixel in a first display area provided in an embodiment of the present application, which schematically shows a plan view of a repeating unit in the first display area. Fig.19 yes Fig.18 A plan view of an active layer of a sub-pixel included in one repeating unit. Fig. 20 yes Fig.18 A plan view of a combination of an active layer of a sub-pixel and a first gate layer included in one repeating unit. Fig.21 yes Fig.18 A plan view of a combination of an active layer, a first gate layer, and a second gate layer of a sub-pixel included in one repeating unit. Fig. 22 yes Fig.18 A plan view of a combination of a sub-pixel active layer, a first gate layer, a second gate layer and a first source and drain layer included in one repeating unit. Fig.23 yes Fig.18 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a sub-pixel included in one repeating unit. Fig.24 yes Fig.18 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, and a second source-drain electrode layer of a sub-pixel included in one repeating unit. Fig.25 yes Fig.18 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a second source-drain electrode layer and a first anode layer of a sub-pixel included in one repeating unit.

[0261] In the embodiment of the present application, the pixel circuit located in the first display area 101a and the pixel circuit located in the second display area 101b in the display panel 10 may include: a plurality of thin film transistors and a storage capacitor. The pixel circuit is used to drive the light-emitting unit. The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. Each transistor includes a gate, a source and a drain.

[0262] Furthermore, the display panel 10 may further include a plurality of signal lines, for example, the plurality of signal lines include: a scanning signal line (also called a gate signal line) A1 for transmitting a scanning signal, a reset control signal line A2 for transmitting a reset control signal (for example, the reset control signal may be a scanning signal of a previous row), a light emitting control line A3 for transmitting a light emitting control signal, a data signal line A4 for transmitting a data signal, a positive power line A5 for transmitting a positive power signal, an initialization voltage line A6 for transmitting an initialization voltage Vint, and a negative power line A7 for transmitting a negative power signal.

[0263] The storage capacitor Cst may include two capacitor plates Cst1 and Cst2. In this article, the capacitor plate Cst1 may be referred to as one end, the first end or the first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 may be referred to as the other end, the second end or the second storage capacitor electrode of the storage capacitor Cst.

[0264] The pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7 which can be arranged along the following lines: Fig.19 The active layer may have a curved or bent shape, and may include a first active pattern 112a corresponding to the first transistor T1, a second active pattern 112b corresponding to the second transistor T2, a third active pattern 112c corresponding to the third transistor T3, a fourth active pattern 112d corresponding to the fourth transistor T4, a fifth active pattern 112e corresponding to the fifth transistor T5, a sixth active pattern 112f corresponding to the sixth transistor T6, and a seventh active pattern 112g corresponding to the seventh transistor T7.

[0265] The active layer 112 may include, for example, polysilicon, and, for example, includes a channel region, a source region, and a drain region. The channel region may not be doped or the doping type may be different from that of the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the thin film transistor is an N-type or a P-type transistor.

[0266] The first transistor T1 includes a first active pattern 112a and a first gate G1. The first active pattern 112a includes a first channel region 1121a, a first source region 1123a, and a first drain region 1125a. The gate G1 of the first transistor T1 is electrically connected to the reset control signal line A2, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line A6. And the drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3. The first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset control signal line A2 to transmit the initialization voltage Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, the first transistor T1 is also called an initialization transistor.

[0267] The second transistor T2 includes a second active pattern 112b and a second gate G2. The second active pattern 112b includes a second channel region 1121b, a second source region 1123b, and a second drain region 1125b. The gate G2 of the second transistor T2 is electrically connected to the scan signal line A1, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal transmitted through the scan signal line A1 to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing a diode connection of the third transistor T3.

[0268] The third transistor T3 includes a third active pattern 112c and a third gate G3. The third active pattern 112c includes a third source region 1123c, a third drain region 1125c, and a third channel region 1121c connecting the third source region 1123c and the third drain region 1125c. The third source region 1123c and the third drain region 1125c extend in two opposite directions relative to the third channel region 1121c. The third source region 1123c of the third transistor T3 is connected to the fourth drain region 1125d and the fifth drain region 1125e. The third drain region 1125c is connected to the second source region 1123b and the sixth source region 1123f. The gate G3 of the third transistor T3 is electrically connected to the first connection portion A8 through vias VAH1 and VAH2. The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the light emitting unit. That is, the third transistor T3 is also called a driving transistor.

[0269] The fourth transistor T4 includes a fourth active layer 112d and a fourth gate G4. The fourth active layer 112d includes a fourth channel region 1121d, a fourth source region 1123c, and a fourth drain region 1125d. The fourth transistor T4 is used as a switching device for selecting a light-emitting target sub-pixel. The fourth gate G4 is connected to the scan signal line A1, the fourth source region 1123c is connected to the data signal line A4 through the via VAH4, and the fourth drain region 1125d is connected to the first transistor T1 and the fifth transistor T5, that is, electrically connected to the node N2. The fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line A1 to perform a switching operation to transmit the data signal Dm to the source S3 of the third transistor T3.

[0270] The fifth transistor T5 includes a fifth active layer 112e and a fifth gate G5. The fifth active layer 112e includes a fifth channel region 1121e, a fifth source region 1123e, and a fifth drain region 1125e. The fifth source region 1123e may be connected to the positive power line A5 through a via VAH6. The gate G5 of the fifth transistor T5 is electrically connected to the light emitting control line A3, and the source S5 of the fifth transistor T5 is electrically connected to the positive power line A5. And the drain D5 of the fifth transistor T5 is electrically connected to the node N2.

[0271] The sixth transistor T6 includes a sixth active layer 112f and a sixth gate G6, and the sixth active layer 112f includes a sixth channel region 1121f, a sixth source region 1123f and a sixth drain region 1125f. The sixth drain region 1125f can be connected to the anode pattern through a via VAH7. The gate G6 of the sixth transistor T6 is electrically connected to the light emitting control line A3, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the anode pattern of the light emitting unit. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the light emitting control signal En transmitted through the light emitting control line A3 to transmit the driving voltage VDD to the light emitting unit, thereby allowing the driving current Id to flow into the light emitting unit.

[0272] The seventh transistor T7 includes a seventh active layer 112g and a seventh gate G7. The seventh active layer 112g includes a seventh source region 1123g, a seventh drain region 1125g and a seventh channel region 1121g. The seventh drain region 1125g is connected to the first source region 1123a of the first transistor T1. The seventh drain region 1125g can be electrically connected to the initialization voltage line A6 through the via VAH8, the second connection portion A9 and the via VAH5. The gate G7 of the seventh transistor T7 is electrically connected to the reset control signal line A2, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line A6.

[0273] One end (hereinafter referred to as a first storage capacitor electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1, and the other end (hereinafter referred to as a second storage capacitor electrode) Cst2 is electrically connected to the positive power line A5.

[0274] It should be noted that each thin film transistor T1, T2, T3, T4, T5, T6 and T7 is a p-channel field effect transistor, but the embodiments of the present application are not limited to this, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 may be an n-channel field effect transistor.

[0275] The display panel 10 includes a scanning signal line A1, a reset control signal line A2, a light emitting control line A3, and an initialization voltage line A6 arranged along a row direction to apply a scanning signal Sn, a reset control signal RESET, a light emitting control signal En, and an initialization voltage Vint to each sub-pixel, respectively. The display panel may further include a data signal line A4 and a positive power supply line A5 crossing the scanning signal line A1, the reset control signal line A2, the light emitting control line A3, and the initialization voltage line A6 to apply a data signal Dm and a driving voltage VDD to each sub-pixel, respectively.

[0276] like Fig. 20 As shown, the scanning signal line A1, the reset control signal line A2 and the light emitting control line A3 are all located in the first gate layer 113. The gates G1 to G7 of the above-mentioned transistors are also located in the first gate layer 113. For example, the portion where the reset control signal line A2 overlaps with the active layer 112 forms the gate G1 of the first transistor T1 and the gate G7 of the seventh transistor T7, respectively, the portion where the scanning signal line A1 overlaps with the active layer 112 forms the gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4, respectively, and the portion where the light emitting control line A3 overlaps with the active layer 112 forms the gate G6 of the sixth transistor T6 and the gate G5 of the fifth transistor T5, respectively.

[0277] Continue to refer to Fig. 20 , the display panel 10 may further include a plurality of first storage capacitor electrodes Cst1. The plurality of first storage capacitor electrodes Cst1 are also located in the first gate layer 113. The portion where the first storage capacitor electrode Cst1 overlaps with the active layer 1120 forms the third gate G3 of the third transistor T3. The first storage capacitor electrode Cst1 also forms one terminal of the storage capacitor Cst. That is, the first storage capacitor electrode Cst1 serves as both the gate G3 of the third transistor T3 and one electrode of the storage capacitor Cst.

[0278] For example, the orthographic projection of the first storage capacitor electrode Cst1 on the base substrate 101 may be substantially rectangular. Here, “substantially rectangular” may include a rectangle, a rectangle with at least one rounded corner, a rectangle with at least one chamfered corner, and the like.

[0279] like Fig.21 As shown, the initialization voltage line A6 is located in the second gate layer 115. The display panel may also include a plurality of second storage capacitor electrodes Cst2. The plurality of second storage capacitor electrodes Cst2 are also located in the second gate layer 115. The plurality of second storage capacitor electrodes Cst2 are respectively arranged corresponding to the plurality of first storage capacitor electrodes Cst1. That is, the orthographic projections of the plurality of second storage capacitor electrodes Cst2 on the base substrate 101 overlap at least partially with the orthographic projections of the corresponding first storage capacitor electrodes Cst1 on the base substrate 101. The second storage capacitor electrode Cst2 forms another terminal of the storage capacitor Cst. That is, the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 are arranged opposite to each other, and the orthographic projections of the two on the base substrate 101 overlap at least partially with each other, and a second gate insulating layer GI2 is arranged between them. For example, the first storage capacitor electrode Cst1 can be electrically connected to the first connection portion A8 through vias VAH1 and VAH2, and the second storage capacitor electrode Cst2 can be electrically connected to the positive power line A5 through vias VAH9. Thus, a portion where the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 overlap each other may form the storage capacitor Cst.

[0280] Combination Fig.21 and Fig.23 , the second storage capacitor electrode Cst2 may include a through hole TH2 to facilitate electrical connection between the first storage capacitor electrode Cst1 located below the second storage capacitor electrode Cst2 and a component located in the third conductive layer 23. For example, a portion of the first connection portion A8 is formed in the via hole VAH1 to form a conductive plug. The conductive plug extends through the through hole TH2 and is electrically connected to the first storage capacitor electrode Cst1. In this way, one end of the first connection portion A8 is electrically connected to one end Cst1 of the storage capacitor.

[0281] For example, the orthographic projection of the through hole TH2 on the substrate 1 may be substantially rectangular. Here, “substantially rectangular” may include a rectangle or a square, a rectangle or a square with at least one rounded corner, a rectangle or a square with at least one chamfered corner, and the like.

[0282] refer to Fig. 22 The data signal line A4 and the positive power line A5 are located in the first source-drain electrode layer 118. In addition, the first connection portion A8 and the second connection portion A9 are also located in the first source-drain electrode layer 118.

[0283] refer to Fig.23 , Fig.24 and Fig.25 , the third connection portion B1 is located in the second source-drain electrode layer 121. One end of the third connection portion B1 is electrically connected to the sixth transistor T6, and the other end is electrically connected to the anode pattern.

[0284] refer to Fig.25 A passivation layer PVX is provided between the second source-drain electrode layer 121 and the first anode layer 103. A via hole VAH10 may penetrate the passivation layer PVX. A portion of the anode pattern of the first anode layer is formed in the via hole VAH10, and the portion extends downward to be electrically connected to a portion of the third connection portion B1.

[0285] Thus, one end of the third connection portion B1 is electrically connected to the sixth transistor T6 through the via hole VAH7, and the other end of the third connection portion B1 is electrically connected to the anode pattern of the first anode layer through the via hole VAH10. In order to meet the preset pixel density requirements, the sub-pixels on the display panel need to be arranged in a prescribed manner, so that the extension lengths of the third connection portions B1 in the sub-pixels may be equal or unequal.

[0286] For example, refer to Fig.18 , Fig.23 and Fig.24 ,in, Fig.23 A plan view showing a pixel circuit of a red sub-pixel or a blue sub-pixel, Fig.24 A plan view of a pixel circuit of a green sub-pixel is shown. An extension length of the third connection portion B1 in the sixth sub-pixel 23 may be smaller than an extension length of the third connection portion B1 in the fourth sub-pixel 21 or the fifth sub-pixel 22 .

[0287] It should be noted that the following description mainly describes the differences between the structure of the first sub-pixel located in the second display area 101b and the structure of the second sub-pixel located in the first display area 101a. For the similarities between the two, refer to the above description.

[0288] It should also be noted that, in order to make the description of this article more concise, in the following, elements with the same or similar functions and / or structures in the first display area and the second display area may be represented by the same reference numerals, for example, each transistor, storage capacitor, and signal line located in the second display area may be represented by reference numerals corresponding to each transistor, storage capacitor, and signal line located in the first display area. It should be understood that in the following description, these elements are located in the second display area 101b.

[0289] Fig.26 It is an equivalent circuit diagram of another pixel circuit provided in an embodiment of the present application. Fig. 271 is a plan view of a sub-pixel in a second display area provided in an embodiment of the present application, which schematically shows a plan view of a repeating unit in the second display area. Fig.28 yes Fig. 27 A plan view of an active layer of a sub-pixel included in one repeating unit. Fig.29 yes Fig. 27 A plan view of a combination of an active layer of a sub-pixel and a first gate layer included in one repeating unit. Fig.30 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, and a second gate layer of a sub-pixel included in one repeating unit. Fig.31 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer and a first source and drain electrode layer of a sub-pixel included in one repeating unit. Fig.32 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source and drain electrode layer, and a connecting electrode film layer of a sub-pixel included in one repeating unit. Fig.33 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source and drain electrode layer, and a connecting electrode film layer of three sub-pixels included in a repeating unit. Fig.34 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a connecting electrode film layer and a second source-drain electrode layer of a sub-pixel included in one repeating unit. Fig.35 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a connecting electrode film layer, a second source-drain electrode layer and a second anode layer of a sub-pixel included in a repeating unit. Fig.36 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a connecting electrode film layer, a second source-drain electrode layer and a second anode layer of another sub-pixel included in one repeating unit. Fig.37 yes Fig. 27 A plan view of a combination of an active layer, a first gate layer, a second gate layer, a first source-drain electrode layer, a connecting electrode film layer, a second source-drain electrode layer and a second anode layer of another sub-pixel included in a repeating unit.

[0290] Combination Figures 26 to 37In the first display area 101b, the pixel circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel circuit is used to drive the light emitting unit. The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7. Each transistor includes a gate, a source and a drain.

[0291] The multiple signal lines include: a scanning signal line A1 for transmitting a scanning signal Sn, a reset control signal line A2 for transmitting a reset control signal RESET (for example, the reset control signal RESET can be a scanning signal of a previous row), a light control line A3 for transmitting a light control signal En, a data signal line A4 for transmitting a data signal Dm, a positive power line A5 for transmitting a driving voltage VDD, an initialization voltage line A6 for transmitting an initialization voltage Vint, and a negative power line A7 for transmitting a VSS voltage.

[0292] refer to Fig. 27 For a first sub-pixel, the active patterns of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are formed as a continuously extended part of the active layer 112. In the embodiment of the present application, "continuously extended" means that there is no disconnection in the middle.

[0293] refer to Fig. 27 The seventh active pattern 112g of the seventh transistor T7 is connected to the first active pattern 112a of the first transistor T1, the first active pattern 112a of the first transistor T1 is connected to the second active pattern 112b of the second transistor T2, the second active pattern 112b of the second transistor T2 is connected to the third active pattern 112c of the third transistor T3 and the sixth active pattern 112f of the sixth transistor T6, and the third active pattern 112c of the third transistor T3 is connected to the fourth active pattern 112d of the fourth transistor T4 and the fifth active pattern 112e of the fifth transistor T5.

[0294] refer to Fig. 27 and Fig.28 For a first sub-pixel located in the second display area 101b, the seventh active pattern 112g of the seventh transistor T7 extends from the first active pattern 112a of the first transistor T1 in a direction close to the scanning signal line A1 of the first sub-pixel. That is, the seventh active pattern 112g of the seventh transistor T7 is located at the lower right of the first active pattern 112a of the first transistor T1. With such a configuration, the outline of the occupied area of ​​the active layer of a first sub-pixel located in the second display area 101b is a square or approximately a square.

[0295] In the application embodiments, "occupied area" refers to the maximum area covered by the orthographic projection of a pattern or layer structure on the substrate substrate. Specifically, the orthographic projection of a pattern or layer structure on the substrate substrate has two sides that are farthest apart in the first direction X and two sides that are farthest apart in the second direction Y. The extension lines of these four sides will intersect to enclose an area, which is the occupied area of ​​the pattern or layer structure.

[0296] For a first sub-pixel located in the second display area 101b, the occupied area of ​​its active layer has a square or substantially square shape, such as Fig. 27 As shown, a dotted box is used to schematically illustrate an occupied area of ​​an active layer of a first sub-pixel located in the second display area 101b, and the occupied area has a dimension along the first direction X (i.e., width W1) and a dimension along the second direction Y (i.e., length L1), wherein the length L1 is substantially equal to the width W1.

[0297] In the embodiment of the present application, the occupied area of ​​the active layer of a first sub-pixel located in the second display area 101b is smaller than the occupied area of ​​the active layer of a second sub-pixel of the same color located in the first display area 101a. Thus, the occupied area of ​​the pixel circuit 10 of the first sub-pixel located in the second display area 101b can be smaller than the occupied area of ​​the pixel circuit of the second sub-pixel located in the first display area 101a.

[0298] like Fig.28 As shown, the scan signal line A1, the reset control signal line A2 and the light emitting control line A3 are all located in the first gate layer 113. The gates G1 to G7 of the above transistors are also located in the first gate layer 113. The first storage capacitor electrode Cst1 is also located in the first gate layer 113.

[0299] refer to Fig.28 , the portion where the scan signal line A1 overlaps with the active layer 112 forms the gate G2 of the second transistor T2 and the gate G4 of the fourth transistor T4 respectively. In addition, another portion where the scan signal line A1 overlaps with the active layer 112 also forms the gate G7 of the seventh transistor T7. That is, in the embodiment of the present application, in the second display area 101b, the gates of the seventh transistor T7, the second transistor T2 and the fourth transistor are all supplied with the scan signal Sn.

[0300] like Fig.29 As shown, the initialization voltage line A6 and the second storage capacitor electrode Cst2 are located in the second gate layer 115 .

[0301] Reference Fig.21For a second sub-pixel located in the first display area 101a, the second storage capacitor electrode Cst2 includes a through hole TH2, and the combination of the solid part of the second storage capacitor electrode Cst2 and the through hole TH2 is projected on the base substrate 101 in a rectangular or rounded rectangular shape.

[0302] Reference Fig.29 For a first sub-pixel located in the second display area 101b, the second storage capacitor electrode Cst2 has a notch NTH1 at one corner. That is, the orthographic projection of the second storage capacitor electrode Cst2 on the base substrate 101 is in an "L" shape. In other words, the orthographic projection of the combination of the solid part of the second storage capacitor electrode Cst2 and the notch NTH1 on the base substrate 101 is in the shape of a rectangle or a rounded rectangle.

[0303] The notch NTH1 exposes a portion of the first storage capacitor electrode Cst1 under the second storage capacitor electrode Cst2 so that the first storage capacitor electrode Cst1 is electrically connected to the other portion.

[0304] In the embodiment of the present application, the area of ​​the orthographic projection of the second storage capacitor electrode Cst2 of a first sub-pixel in the second display area 101b on the base substrate 101 is smaller than the area of ​​the orthographic projection of the second storage capacitor electrode Cst2 of a second sub-pixel in the first display area 101a on the base substrate 101. On this basis, the second storage capacitor electrode Cst2 of a first sub-pixel in the second display area 101b is designed to be "L"-shaped, and there is no need to form the through hole in the second storage capacitor electrode Cst2, which is conducive to ensuring that the overlapping area of ​​the first storage capacitor electrode Cst1 and the second storage capacitor electrode Cst2 of a first sub-pixel in the second display area 101b is large, that is, the capacitance value of the storage capacitor Cst is guaranteed.

[0305] like Fig.31 As shown, the connection portion 1A8 , the connection portion 1A9 , the connection portion 1B0 , and the connection portion 1B1 are located in the first source-drain electrode layer 118 .

[0306] A portion of the connection portion 1A8 is formed in the via hole VH6, and the portion extends downward to be electrically connected to a portion of the first storage capacitor electrode Cst1 exposed by the notch NTH1. Another portion of the connection portion 1A8 is formed in the via hole VH2, and the portion extends downward to be electrically connected to the drain electrode D2 of the second transistor T2 and the drain electrode D1 of the first transistor T1. Through the connection portion 1A8, the first storage capacitor electrode Cst1, the drain electrode D2 of the second transistor T2, and the drain electrode D1 of the first transistor T1 can be electrically connected.

[0307] A portion of the connection portion 1A9 is formed in the via hole VH12, and the portion extends downward to be electrically connected to the initialization voltage line A6. Another portion of the connection portion 1A9 is formed in the via hole VH4, and the portion extends downward to be electrically connected to the drain electrode D7 of the seventh transistor T7. Through the connection portion 1A9, the initialization voltage Vint transmitted by the initialization voltage line A6 can be supplied to the drain electrode D7 of the seventh transistor T7.

[0308] A portion of the connection portion 1B0 is formed in the via hole VH5, and the portion extends downward to be electrically connected to the source S7 of the seventh transistor T7. Another portion of the connection portion 1B0 is formed in the via hole VH10, and the portion extends downward to be electrically connected to the drain D6 of the sixth transistor T6. Through the connection portion 1B0, the source S7 of the seventh transistor T7 and the drain D6 of the sixth transistor T6 can be electrically connected.

[0309] A portion of the connection portion 1B1 is formed in the via hole VH7, and the portion extends downward to be electrically connected to the second storage capacitor electrode Cst2. Another portion of the connection portion 1B1 is formed in the via hole VH9, and the portion extends downward to be electrically connected to the source electrode S5 of the fifth transistor T5. Through the connection portion 1B1, the second storage capacitor electrode Cst2 can be electrically connected to the source electrode S5 of the fifth transistor T5.

[0310] Combination Figure 30 to Figure 35 In the second display area 101b, a connection electrode film layer f is provided. For example, the connection electrode film layer f may be made of a transparent conductive material such as indium tin oxide (i.e., ITO). The connection electrode film layer f may include a plurality of first connection electrodes, a plurality of second connection electrodes, and a plurality of third connection electrodes.

[0311] For ease of description, refer to Fig.32 In the second display area 101b, the plurality of first connection electrodes, the plurality of second connection electrodes and the plurality of third connection electrodes that may be included in the connection electrode film layer f are divided into a plurality of conductive leads. For example, the plurality of conductive leads may include a first conductive lead 1A1, a second conductive lead 2A1, a third conductive lead 1A2, a fourth conductive lead 2A2, a fifth conductive lead 1A3, a sixth conductive lead 2A3, a seventh conductive lead 1A6 and an eighth conductive lead 2A6. That is, these conductive leads are all made of a transparent conductive material such as indium tin oxide (i.e., ITO).

[0312] A portion of the data signal line segment 1A4 is formed in the via hole VH3 , and the portion extends downward to be electrically connected to the source electrode S4 of the fourth transistor T4 , thereby supplying the data signal Dm transmitted by the data signal line 1A4 to the fourth transistor T4 .

[0313] The positive power supply line segment 1A5 is disconnected at the pixel circuit of the first sub-pixel in the second display area 101b and is divided into two parts. For the convenience of description, the two parts are respectively represented as a first driving voltage sub-line 1A51 and a second driving voltage sub-line 1A52.

[0314] For example, the orthographic projection of the first driving voltage sub-line 1A51 on the base substrate 101 intersects with the orthographic projection of the initialization voltage line A6 on the base substrate 101. And the orthographic projection of the first driving voltage sub-line 1A51 on the base substrate 101 at least partially overlaps with the orthographic projection of the reset control signal line A2 on the base substrate 1.

[0315] For another example, the orthographic projection of the second driving voltage sub-line 1A52 on the base substrate 101 intersects with the orthographic projection of the light emitting control line A3 on the base substrate 1. And the orthographic projection of the second driving voltage sub-line 1A52 on the base substrate 101 at least partially overlaps with the orthographic projection of the second storage capacitor electrode Cst2 on the base substrate 1. A portion of the second driving voltage sub-line 1A52 is formed in the via hole VH7', and the portion extends downward to be electrically connected to a portion of the connecting portion 1B1, thereby being electrically connected to the second storage capacitor electrode Cst2. In this way, electrical connection between the positive power supply line, the second storage capacitor electrode Cst2 and the source S5 of the fifth transistor T5 can be achieved.

[0316] The first driving voltage sub-line 1A51 and the second driving voltage sub-line 1A52 are spaced apart from each other by a certain distance in the second direction Y. For example, the orthographic projection of one end of the first driving voltage sub-line 1A51 close to the second driving voltage sub-line 1A52 on the substrate substrate 101 partially overlaps with the orthographic projection of the reset control signal line A2 on the substrate substrate 101, and the orthographic projection of one end of the second driving voltage sub-line 1A52 close to the first driving voltage sub-line 1A51 on the substrate substrate 101 partially overlaps with the orthographic projection of the part of the second storage capacitor electrode Cst2 close to the light emitting control line A3 on the substrate substrate 101. The spaced apart first driving voltage sub-line 1A51 and second driving voltage sub-line 1A52 are electrically connected together through the connecting portion.

[0317] In the second display area 101b, the scanning signal line A1, the reset control signal line A2, the light emitting control line A3 and the initialization voltage line A6 in each sub-pixel extending along the first direction X are electrically connected through conductive leads located in the transparent conductive layer. In this way, in the light-transmitting area of ​​the second display area 101b, only transparent conductive leads are arranged, and conductive leads made of opaque materials such as metal are not arranged. In this way, the light transmittance of the second display area 101b can be ensured to be relatively high.

[0318] Specifically, a first conductive lead 1A1 and a second conductive lead 2A1 are respectively provided on both sides of a scanning signal line A1 of a first sub-pixel. A portion of the first conductive lead 1A1 is formed in a via hole VH15, and the portion extends downward to be electrically connected to one end of the scanning signal line A1. A portion of the second conductive lead 2A1 is formed in a via hole VH16, and the portion extends downward to be electrically connected to the other end of the scanning signal line A1. With the help of the first conductive lead 1A1 and the second conductive lead 2A1, the scanning signal lines A1 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the scanning signal Sn.

[0319] A third conductive lead 1A2 and a fourth conductive lead 2A2 are respectively provided on both sides of the reset control signal line A2 of a first sub-pixel. A portion of the third conductive lead 1A2 is formed in the via hole VH13, and the portion extends downward to be electrically connected to one end of the reset control signal line A2. A portion of the fourth conductive lead 2A2 is formed in the via hole VH14, and the portion extends downward to be electrically connected to the other end of the reset control signal line A2. With the help of the third conductive lead 1A2 and the fourth conductive lead 2A2, the reset control signal lines A2 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the reset signal Reset.

[0320] A fifth conductive lead 1A3 and a sixth conductive lead 2A3 are respectively provided on both sides of the light emitting control line A3 of a sub-pixel. A portion of the fifth conductive lead 1A3 is formed in the via hole VH17, and the portion extends downward to be electrically connected to one end of the light emitting control line A3. A portion of the sixth conductive lead 2A3 is formed in the via hole VH18, and the portion extends downward to be electrically connected to the other end of the light emitting control line A3. With the help of the fifth conductive lead 1A3 and the sixth conductive lead 2A3, the light emitting control lines A3 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the light emitting control signal Em.

[0321] On both sides of the initialization voltage line A6 of a first sub-pixel, a seventh conductive lead 1A6 and an eighth conductive lead 2A6 are respectively provided. A portion of the seventh conductive lead 1A6 is formed in the via hole VH11, and the portion extends downward to be electrically connected to one end of the initialization voltage line A6. A portion of the eighth conductive lead 2A6 is formed in the via hole VH12, and the portion extends downward to be electrically connected to the other end of the initialization voltage line A6. With the help of the seventh conductive lead 1A6 and the eighth conductive lead 2A6, the initialization voltage lines A6 of the sub-pixels in the same row can be electrically connected to facilitate the supply of the light-emitting initialization voltage signal Vinit.

[0322] In an embodiment of the present application, the line width of at least one of the scan signal line, reset signal line, light control signal line, initialization voltage line, data signal line and positive power line located in the second display area 101b may be less than or equal to the line width of the signal line for transmitting the same type of signal located in the first display area 101a.

[0323] For example, the line width of the data signal line segment 1A4 in the second display area 101b may be less than or substantially equal to the line width of the data signal line A1 in the first display area 101a. For example, the line width of the data signal line 164 in the second display area 101b may be between 1.5 μm (micrometers) and 3 μm, and the line width of the data signal line A4 in the first display area 101a may be between 2.5 μm and 4 μm.

[0324] For example, the line width of the positive power line segment 1A5 in the second display area 101b may be less than or substantially equal to the line width of the positive power line A5 in the first display area 101a. For example, the line width of the positive power line 1A5 in the second display area 101b may be between 2 μm and 5 μm, and the line width of the positive power line A5 in the first display area 101a may be between 4 μm and 7 μm.

[0325] For example, the line width of the scan signal line A1 in the second display area 101b may be less than or substantially equal to the line width of the scan signal line A1 in the first display area 101a. For example, the line width of the scan signal line A1 in the second display area 101b may be between 2 μm and 3 μm, and the line width of the scan signal line A1 in the first display area 101a may be between 3 μm and 4 μm.

[0326] For example, the line width of the initialization voltage line A6 in the second display area 101b may be less than or substantially equal to the line width of the initialization voltage line A6 in the first display area 101a. For example, the line width of the initialization voltage line A6 in the first display area 101a may be between 2 μm and 3 μm, and the line width of the initialization voltage line A6 in the first display area 101a may be between 3 μm and 6 μm.

[0327] In an embodiment of the present disclosure, the width-to-length ratio of each transistor T1 to T7 of the pixel circuit located in the second display area 101b may be substantially equal to the width-to-length ratio of the same type of transistors T1 to T7 of the pixel circuit located in the first display area 101a. The embodiment of the present application is not limited thereto, for example, the width-to-length ratio of each transistor T1 to T7 of the pixel circuit located in the second display area 101b may be smaller than the width-to-length ratio of the same type of transistors T1 to T7 of the pixel circuit located in the first display area 101a.

[0328] For example, the width-to-length ratio of the transistor T3 of the pixel circuit located in the second display area 101b may be substantially equal to the width-to-length ratio of the transistor T3 of the pixel circuit located in the first display area 101a. For example, the width-to-length ratio of the transistor T3 of the pixel circuit located in the second display area 101b and the width-to-length ratio of the transistor T3 of the pixel circuit located in the first display area 101a may be (2-4) / (20-26).

[0329] For example, the width-to-length ratio of the transistor T4 of the pixel circuit located in the second display area 101b may be substantially equal to the width-to-length ratio of the transistor T4 of the pixel circuit located in the first display area 101a. For example, the width-to-length ratio of the transistor T4 of the pixel circuit located in the second display area 101b and the width-to-length ratio of the transistor T4 of the pixel circuit located in the first display area 101a may be (2-3) / (2-4).

[0330] like Fig.32 As shown, the connecting portion 1B2 and the conductive connecting portion 1B3 are located in the second gate layer 115 .

[0331] A portion of the connection portion 1B2 is formed in the via hole VH1, and the portion extends downward to be electrically connected to the first drive voltage sub-line 1A51. Another portion of the connection portion 1B2 is formed in the via hole VH7", and the portion extends downward to be electrically connected to the second drive voltage sub-line 1A52. That is, through the connection portion 1B2, the first drive voltage sub-line 1A51 and the second drive voltage sub-line 1A52 can be electrically connected, so that the positive power lines of each sub-pixel located in the same column can be connected to facilitate the supply of the drive voltage signal VDD to each sub-pixel.

[0332] A portion of the conductive connection portion 1B3 is formed in the via hole VH10 ′, and the via hole VH10 ′ exposes a portion of the connection portion 1B0 , so that the conductive connection portion 1B3 can be electrically connected to the connection portion 1B0 .

[0333] like Figure 33 to Figure 35 As shown, the anode pattern of the first sub-pixel includes an anode body 10711 and an anode connection portion 10712 .

[0334] A portion of the anode connection portion 10712 may be formed in a via hole VH10" that exposes a portion of the conductive connection portion 1B3, so that the anode connection portion 10712 may be electrically connected to the conductive connection portion 1B3 and then to the connection portion 1B0. That is, the anode pattern 1071, the source S7 of the seventh transistor T7, and the drain D6 of the sixth transistor T6 may be electrically connected through the conductive connection portion 1B3 and the connection portion 1B0.

[0335] For example, Figure 33 to Figure 351 and 2 show plan views of the red sub-pixel F1, the blue sub-pixel F2 and the green sub-pixel F3 located in the second display area 101b. Figure 33 to Figure 35 As shown, in the second display area 101b, the pixel circuits of the red sub-pixel F1, the blue sub-pixel F2, and the green sub-pixel F3 can be substantially reduced to the size of the light-emitting unit and placed under the light-emitting unit. In this way, in the second display area 101b (i.e., the under-screen camera area), the pixel circuits of each sub-pixel can be built into the corresponding sub-pixel. Moreover, in the embodiment of the present application, the pixel circuits of each sub-pixel are built into the corresponding sub-pixel and hidden under the light-emitting unit of the corresponding sub-pixel, which can ensure that the transmittance of the second display area is relatively large, that is, it is conducive to achieving a high transmittance of the second display area.

[0336] In the embodiment of the present application, the occupied area of ​​the pixel circuit of each sub-pixel in the second display area 101b can be represented by the following area: Figure 33 to Figure 35 For the pixel circuit of each sub-pixel, in the first direction X, the fifth active pattern 112e of the fifth transistor T5 and the seventh active pattern 112g of the seventh transistor T7 are located at the leftmost and rightmost sides respectively, that is, the distance between the two in the first direction X is the largest; in the second direction Y, the initialization voltage line A6 and the light emitting control line A3 are located at the uppermost and lowermost sides respectively, that is, the distance between the two in the second direction Y is the largest. In this way, in the orthographic projection of the pixel circuit of a sub-pixel on the substrate, the fifth active pattern 112e of the fifth transistor T5 has a first side away from the seventh active pattern 112g of the seventh transistor T7, the seventh source pattern 112g of the seventh transistor T7 has a second side away from the fifth active pattern 112e of the fifth transistor T5, the initialization voltage line A6 has a third side away from the light emitting control line A3, and the light emitting control line A3 has a fourth side away from the initialization voltage line A6. The first side and the second side extend along the second direction Y, and the third side and the fourth side extend along the first direction X. The extension lines of the four sides intersect to enclose and form an area. The area is the occupied area of ​​the pixel circuit of a first sub-pixel located in the second display area 101b. In other words, the occupied area of ​​the pixel circuit of each sub-pixel in the second display area 101b can be represented by the following area: Fig.30 ,as well as Figure 33 to Figure 35 , eight vias VH11, VH12, VH13, VH14, VH15, VH16, VH17, and VH18 are respectively located at the outermost sides of the pixel circuit, and vias VH9 and VH10 are located at the outermost sides of the pixel circuit. The centers of every two adjacent vias in these 10 vias are connected in sequence to enclose a region, such as Figure 33 to Figure 35The area AR1 surrounded by a dotted line frame shown in FIG. 1 may be an occupied area of ​​a pixel circuit of a sub-pixel located in the second display area 101 b .

[0337] In the embodiment of the present application, the occupied area of ​​the light emitting unit of the sub-pixel in the second display area 101 b can be represented by the coverage area of ​​the orthographic projection of the anode pattern of the light emitting unit on the base substrate 101 .

[0338] In the embodiment of the present application, the pixel density in the second display area 101b is substantially equal to the pixel density in the first display area 101a. That is, within the same area, the number of first sub-pixels arranged in the second display area 101b is substantially equal to the number of second sub-pixels of the same color arranged in the first display area 101a. In this way, both the first display area and the second display area have a higher pixel density, can achieve a higher display quality, and have better display uniformity.

[0339] In the embodiments of the present application, unless otherwise specified, the expressions “substantially equal”, “substantially equal to”, etc. may indicate that the ratio of the two compared values ​​is approximately equal to 1. For example, the ratio of the two compared values ​​may be in the range of 0.8 to 1.2.

[0340] Reference Fig.28 For a first sub-pixel located in the second display area 101b, the seventh active pattern 112g of the seventh transistor T7 extends from the first active pattern 112a of the first transistor T1 in a direction close to the scanning signal line A1 of the first sub-pixel. That is, the seventh active pattern 112g of the seventh transistor T7 is located at the lower right of the first active pattern 112a of the first transistor T1. With such a setting, the outline of the occupied area of ​​the active layer of a first sub-pixel located in the second display area 101b is a square or approximately a square. In addition, the first pattern 10611 in the auxiliary electrode pattern 1061 is projected as a circle on the base substrate 101. With such a setting, it is beneficial to realize that the auxiliary electrode pattern 1061 covers the pixel circuit of the first sub-pixel.

[0341] For example, the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101 may cover the orthographic projection of the occupied area AR1 of at least one pixel circuit on the base substrate 101. That is, it covers the orthographic projection of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the storage capacitor Cst of the pixel circuit on the base substrate 101. Through such a setting, the diffraction effect of the pixel circuit of each sub-pixel on the camera of the second display area 101b can be reduced, and the display effect of the display panel 10 is guaranteed.

[0342] In summary, the embodiment of the present application provides a display panel, wherein the second cathode layer included in the display panel has a hollow area, so the second cathode layer does not cover the second display area in its entirety. Compared with a cathode layer that covers the second display area in its entirety, the influence on light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area is better.

[0343] Fig.38 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application. The method can be used to prepare Figure 1 The display panel 10 shown in FIG. Fig.38 , the method may include:

[0344] Step 201: Provide a substrate.

[0345] In the embodiment of the present application, when preparing the display panel 10, a base substrate 101 may be obtained. The base substrate 101 may be a glass substrate.

[0346] Step 202: forming a first auxiliary electrode layer, a first anode layer, a first light-emitting layer, and a first cathode layer stacked in sequence in the first display area.

[0347] In the examples of this application, refer to Figure 1 The first auxiliary electrode layer 102, the first anode layer 103, the first light emitting layer 104, and the first cathode layer 105 may all be located in the first display region 101a of the base substrate 101, and are sequentially stacked in a direction away from the base substrate 101. The first auxiliary electrode layer 102 may be connected to the first cathode layer 105.

[0348] Step 203: forming a second auxiliary electrode layer, a second anode layer, a second light-emitting layer, and a second cathode layer stacked in sequence in the second display area.

[0349] In the examples of this application, refer to Figure 1 The second auxiliary electrode 106 , the second anode layer 107 , the second light emitting layer 108 , and the second cathode layer 109 may all be located in the second display region 101 b of the base substrate 101 , and may be stacked in sequence in a direction away from the base substrate 101 .

[0350] The second auxiliary electrode layer 106 may be connected to the first auxiliary electrode layer 102 , the second cathode layer 109 may be connected to the first cathode layer 105 , and the second cathode layer 109 may have at least one hollow region.

[0351] Since the second cathode layer 109 included in the display panel 10 has at least one hollow area, the second cathode layer 109 does not cover the second display area 101b in its entirety. Compared with a cathode layer that covers the second display area 101b in its entirety, the influence on light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area 101b is better.

[0352] In the embodiment of the present application, the first auxiliary electrode layer 102 is connected to the first cathode layer 105, the second auxiliary electrode layer 106 is connected to the first auxiliary electrode layer 102, and the second cathode layer 109 is connected to the first cathode layer 105. That is, the first auxiliary electrode layer 102, the first cathode layer 105, the second auxiliary electrode layer 106, and the second cathode layer 109 are connected to each other, so that the voltage difference of the power signal received by the first cathode layer 105 and the second cathode layer 109 can be small, so as to ensure the brightness uniformity of the display panel 10, and the display effect of the display panel 10 is better.

[0353] Step 204: forming a plurality of pixel circuits in the second display area.

[0354] In the embodiment of the present application, each pixel circuit 110 may include at least one layer of opaque pattern b. The second auxiliary electrode layer 106 may include: a plurality of auxiliary electrode patterns 1061 arranged at intervals. At least 50% of the orthographic projection area of ​​at least one layer of opaque pattern b in at least one pixel circuit 110 on the base substrate 101 overlaps with the orthographic projection area of ​​an auxiliary electrode pattern 1061 on the base substrate 101. In this way, the diffraction effect of the pixel circuit 110 on the camera arranged in the second display area 101b can be small, and the display effect of the display panel 10 can be guaranteed.

[0355] In summary, the embodiment of the present application provides a method for preparing a display panel, wherein the display panel prepared by the method includes a second cathode layer having a hollow area, so the second cathode layer does not cover the second display area in its entirety. Compared with a cathode layer that covers the second display area in its entirety, the influence on light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area is better.

[0356] Fig.40 is a flow chart of another method for preparing a display panel provided in an embodiment of the present application. Fig.40 It can be seen that the method may include:

[0357] Step 301: Provide a substrate.

[0358] In the embodiment of the present application, when preparing the display panel 10, a base substrate 101 may be obtained. The base substrate 101 may be a glass substrate.

[0359] Step 302: forming a first auxiliary electrode layer in the first display region, and forming a second auxiliary electrode layer in the second display region.

[0360] In the examples of this application, refer to Fig.40 , a first auxiliary electrode layer 102 and a second auxiliary electrode layer 106 can be formed on one side of the base substrate 101 by a single patterning process. The first auxiliary electrode layer 102 can be located in the first display area 101a of the base substrate 101, and the second auxiliary electrode layer 106 can be located in the second display area 101b of the base substrate 101.

[0361] The materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may be the same. Optionally, the materials of the first auxiliary electrode layer 102 and the second auxiliary electrode layer 106 may both include metals, for example, both may be molybdenum or both may be aluminum alloys.

[0362] Optionally, the second auxiliary electrode layer 106 may include a plurality of auxiliary electrode patterns 1061 that are spaced apart from each other, and at least a portion of an edge of an orthographic projection of each auxiliary electrode pattern 1061 on the base substrate 101 may be arc-shaped.

[0363] Step 303: forming an active layer in the first display area and the second display area.

[0364] Fig.41 Schematic diagram of the structure of an active layer provided in an embodiment of the present application. Fig.41 , the width of the active layer 112 located in the first display area 101a is greater than the width of the active layer 112 located in the second display area 101b. This can improve the transmittance and pixel density of the second display area 101b, ensuring the imaging effect of the camera located in the second display area 101b.

[0365] Optionally, the width of the portion of the active layer 112 located in the first display area 101 a ranges from 2.0 μm to 2.5 μm, and the width of the portion of the active layer 112 located in the second display area 101 b ranges from 1.4 μm to 1.6 μm.

[0366] In the examples of this application, refer to Figures 42 to 44 , the active layer 112 may include a plurality of strip-shaped patterns. Moreover, the orthographic projection of the pattern in the first display area 101a of the active layer 112 on the base substrate 101 overlaps with the orthographic projection of the first auxiliary electrode layer 102 on the base substrate 101. The orthographic projection of the pattern in the second display area 101b of the active layer 112 on the base substrate 101 overlaps with the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101.

[0367] The material used to make the active layer 112 may include polycrystalline silicon (poly).

[0368] Step 304: forming a buffer layer on a side of the active layer away from the substrate.

[0369] In the embodiment of the present application, the material used to make the buffer layer 111 may include silicon nitride and silicon oxide.

[0370] Step 305 : forming a first gate layer on a side of the buffer layer away from the substrate.

[0371] Fig.45 is a schematic diagram of the structure of a first gate layer provided in an embodiment of the present application. Fig.45 The width of the first gate layer 113 located in the first display area 101a is greater than the width of the first gate layer 113 located in the second display area 101b. This can improve the transmittance and pixel density of the second display area 101b, ensuring the imaging effect of the camera located in the second display area 101b.

[0372] Optionally, the width of the portion of the first gate layer 113 located in the first display region 101 a ranges from 3.0 μm to 3.4 μm, and the width of the portion of the first gate layer 113 located in the second display region 101 b ranges from 1.8 μm to 2.0 μm.

[0373] In the examples of this application, refer to Figures 46 to 48 , a first gate layer 113 may be formed on a side of the second buffer layer 113 away from the base substrate 101. Figures 45 to 48 , the first gate layer 113 may include a plurality of strip-shaped patterns. Moreover, the orthographic projection of the pattern in the first display area 101a in the first gate layer 113 on the base substrate 101 overlaps with the orthographic projection of the first auxiliary electrode layer 102 on the base substrate 101. The orthographic projection of the pattern in the first gate layer 113 on the second display area 101b on the base substrate 101 overlaps with the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101.

[0374] Step 306: Form a first gate insulating layer on a side of the first gate layer away from the substrate.

[0375] refer to Figures 49 to 51 , in order to facilitate the illustration of the various via holes 115a in the first gate insulating layer 114, Figures 49 to 51 The via hole 115a is represented by a filling pattern. Other areas without a filling pattern are used to represent areas where the first gate insulating layer 114 has a solid material. Figures 49 to 51The first gate insulating layer 114 has a via hole 115 a in a portion located in the second display region 101 b , and has no via hole 115 a in a portion located in the first display region 101 a .

[0376] Step 307 : forming a second gate layer on a side of the first gate insulating layer away from the substrate.

[0377] Fig.52 is a schematic diagram of the structure of a second gate layer provided in an embodiment of the present application. Fig.52 , the width of the second gate layer 115 located in the first display area 101a is greater than the width of the second gate layer 115 located in the second display area 101b. This can improve the transmittance and pixel density of the second display area 101b, ensuring the imaging effect of the camera located in the second display area 101b.

[0378] Optionally, the width of the portion of the second gate layer 115 located in the first display region 101 a ranges from 3.0 μm to 3.4 μm, and the width of the portion of the second gate layer 115 located in the second display region 101 b ranges from 1.8 μm to 2.0 μm.

[0379] In the examples of this application, refer to Figures 53 to 55 , a second gate layer 115 may be formed on a side of the first gate insulating layer 114 away from the base substrate 101. Figure 52 to Figure 55 , the second gate layer 115 may include a plurality of patterns. Moreover, the orthographic projection of the pattern in the second gate layer 115 located in the first display area 101a on the base substrate 101 overlaps with the orthographic projection of the first auxiliary electrode layer 102 on the base substrate 101. The orthographic projection of the pattern in the second gate layer 115 located in the second display area 101b on the base substrate 101 overlaps with the orthographic projection of the auxiliary electrode pattern 1061 on the base substrate 101.

[0380] Step 308 : forming a second gate insulating layer and an interlayer dielectric layer on a side of the second gate layer away from the substrate.

[0381] Fig.56 It is a schematic diagram of the structure of an interlayer dielectric layer provided in an embodiment of the present application. Fig.57 It is a schematic diagram of forming an interlayer dielectric layer in a second display area provided by an embodiment of the present application. Fig.58 It is a schematic diagram of forming an interlayer dielectric layer in a first display area provided by an embodiment of the present application. Fig.59 It is a schematic diagram of forming an interlayer dielectric layer in a first display area and a second display area provided by an embodiment of the present application.

[0382] In order to facilitate the illustration of the various via holes 118a in the interlayer dielectric layer 117, Figure 56 to Figure 59 The via hole 118a is represented by a fill pattern. Other areas without fill patterns are used to represent areas where the interlayer dielectric layer 117 has solid material. Figure 56 to Figure 59 The interlayer dielectric layer 117 has a via hole 118a in both the portion located in the first display area 101a and the portion located in the second display area 101b.

[0383] It should be noted that each via hole 118a opened in the interlayer dielectric layer 117 is used to connect the subsequently formed film layer with the film layer on the side of the interlayer dielectric layer 117 close to the base substrate 101. That is, each via hole 118a is a via hole for connecting the film layer, so the larger the aperture of the via hole, the smaller the transmittance; the smaller the aperture of the via hole, the greater the transmittance.

[0384] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the via 118a of the interlayer dielectric layer 117 located in the second display area 101a can be made smaller than the aperture of the via 118a of the interlayer dielectric layer 117 located in the first display area 101a.

[0385] Optionally, the aperture of the via hole 118a of the interlayer dielectric layer 117 in the first display area 101a ranges from 2.3 μm to 2.5 μm, and the aperture of the via hole 118a of the interlayer dielectric layer 117 in the second display area 101b ranges from 1.8 μm to 2.0 μm.

[0386] In the embodiment of the present application, the film layer structure of the second gate insulating layer 116 and the film layer structure of the interlayer dielectric layer 117 may be the same, and the embodiment of the present application will not be described in detail herein.

[0387] Step 309 , forming a first source and drain layer on a side of the interlayer dielectric layer away from the substrate.

[0388] Fig.60 Schematic diagram of the structure of a first source and drain layer provided in an embodiment of the present application. Fig.60 The width of the first source-drain electrode layer 118 located in the first display area 101a is greater than the width of the first source-drain electrode layer 118 located in the second display area 101b. This can improve the transmittance and pixel density of the second display area 101b, ensuring the imaging effect of the camera located in the second display area 101b.

[0389] Optionally, the width of the portion of the first source and drain electrode layer 118 located in the first display region 101 a ranges from 3.0 μm to 3.2 μm, and the width of the portion of the first source and drain electrode layer 118 located in the second display region 101 b ranges from 1.4 μm to 1.6 μm.

[0390] In the examples of this application, refer to Figures 61 to 63 , a first source-drain electrode layer 118 may be formed on a side of the interlayer dielectric layer 117 away from the substrate 101. Figure 60 to Figure 63 , the first source-drain electrode layer 118 may include a plurality of patterns. Moreover, the orthographic projection of the pattern in the first source-drain electrode layer 118 located in the first display region 101a on the substrate substrate 101 overlaps with the orthographic projection of the first auxiliary electrode layer 102 on the substrate substrate 101. The orthographic projection of the pattern in the first source-drain electrode layer 118 located in the second display region 101b on the substrate substrate 101 overlaps with the orthographic projection of the auxiliary electrode pattern 1061 on the substrate substrate 101.

[0391] Step 310: forming a passivation layer on a side of the first source and drain layer away from the substrate.

[0392] Fig.64 It is a schematic diagram of the structure of a passivation layer provided in an embodiment of the present application. Fig.65 It is a schematic diagram of forming a passivation layer in a second display area provided by an embodiment of the present application. Fig.66 This is a schematic diagram of forming a passivation layer in a first display area provided by an embodiment of the present application. Fig.67 This is a schematic diagram of forming a passivation layer in a first display area and a second display area provided by an embodiment of the present application.

[0393] To facilitate illustration of the various via holes 120a in the passivation layer 119, Figure 64 to Figure 67 The via hole 120a is indicated by a fill pattern. Other areas without fill patterns are used to indicate areas where the passivation layer 119 has solid material. Figure 66 to Figure 67 The passivation layer 119 has a via hole 120a in both the portion located in the first display area 101a and the portion located in the second display area 101b.

[0394] It should be noted that each via hole 120a opened in the passivation layer 119 is used to connect the subsequently formed film layer with the film layer on the side of the passivation layer 119 close to the base substrate 101. In other words, each via hole 120a is a via hole for connecting the film layer. The larger the aperture of the via hole, the smaller the transmittance; the smaller the aperture of the via hole, the greater the transmittance.

[0395] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the via hole 120a of the passivation layer 119 located in the first display area 101a can be made larger than the aperture of the via hole 120a of the passivation layer 119 located in the second display area 101a.

[0396] Optionally, the aperture of the via hole 120a of the passivation layer 119 located in the first display area 101a ranges from 4.5 μm to 5 μm, and the aperture of the via hole 120a of the passivation layer 119 located in the second display area 101b ranges from 1.8 μm to 2.0 μm.

[0397] Step 311: forming a connecting electrode film layer on a side of the passivation layer away from the base substrate.

[0398] In the examples of this application, refer to Figures 68 to 71 , the connecting electrode film layer f may include a plurality of first connecting electrodes 124, a plurality of second connecting electrodes 127, and a plurality of third connecting electrodes 130. That is, the plurality of first connecting electrodes 124, the plurality of second connecting electrodes 127, and the plurality of third connecting electrodes 130 may be prepared by the same preparation process. Among them, each of the plurality of first connecting electrodes 124, the plurality of second connecting electrodes 127, and the plurality of third connecting electrodes 130 may be made of a transparent conductive material. In this way, the transmittance of the second display area 101b can be ensured, and the imaging effect of the camera is improved. For example, the first connecting electrode 124, the second connecting electrode 127, and the third connecting electrode 130 may all be made of ITO.

[0399] Step 312: forming a first planar layer on a side of the connecting electrode film layer away from the base substrate.

[0400] Fig.72 It is a schematic diagram of the structure of a first planar layer provided in an embodiment of the present application. Fig.73 It is a schematic diagram of forming a first flat layer in a second display area provided by an embodiment of the present application. Fig.74 It is a schematic diagram of forming a first flat layer in a first display area provided by an embodiment of the present application. Fig.75 This is a schematic diagram of forming a first flat layer in a first display area and a second display area provided by an embodiment of the present application.

[0401] In order to facilitate the illustration of the various via holes 121a in the first planar layer 120, Figure 72 to Figure 75 The via hole 121a is indicated by a fill pattern. Other areas without fill patterns are used to indicate areas where the first planar layer 120 has solid material. Figure 72 to Figure 75 The first planar layer 120 has a via hole 121 a in both the portion located in the first display area 101 a and the portion located in the second display area 101 b .

[0402] It should be noted that each via hole 121a opened in the first flat layer 120 is used to connect the subsequently formed film layer with the film layer on the side of the first flat layer 120 close to the base substrate 101. In other words, each via hole 121a is a via hole for connecting the film layer. The larger the aperture of the via hole, the smaller the transmittance; the smaller the aperture of the via hole, the greater the transmittance.

[0403] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the via hole 121a of the first flat layer 120 located in the first display area 101a can be made larger than the aperture of the via hole 121a of the first flat layer 120 located in the second display area 101a.

[0404] Optionally, the aperture of the via hole 121a of the first planar layer 120 located in the first display area 101a ranges from 2.3 μm to 2.5 μm, and the aperture of the via hole 120a of the first planar layer 120 located in the second display area 101b ranges from 1.8 μm to 2.0 μm.

[0405] Step 313: forming a second source-drain layer on a side of the first planar layer away from the substrate.

[0406] Fig.76 Schematic diagram of the structure of a second source and drain layer provided in an embodiment of the present application. Fig.76 The width of the second source-drain electrode layer 121 located in the first display area 101a is greater than the width of the second source-drain electrode layer 121 located in the second display area 101b. This can improve the transmittance and pixel density of the second display area 101b, ensuring the imaging effect of the camera located in the second display area 101b.

[0407] Optionally, the width of the portion of the second source-drain electrode layer 121 located in the first display region 101 a ranges from 4.5 μm to 5 μm, and the width of the portion of the second source-drain electrode layer 121 located in the second display region 101 b ranges from 1.4 μm to 1.6 μm.

[0408] In the examples of this application, refer to Figure 76 to Figure 79 , a second source-drain electrode layer 121 may be formed on a side of the first planar layer 120 away from the base substrate 101. Figure 76 to Figure 79, the second source-drain electrode layer 121 may include a plurality of patterns. Moreover, the orthographic projection of the pattern in the second source-drain electrode layer 121 located in the first display region 101a on the substrate substrate 101 overlaps with the orthographic projection of the first auxiliary electrode layer 102 on the substrate substrate 101. The orthographic projection of the pattern in the second source-drain electrode layer 121 located in the second display region 101b on the substrate substrate 101 overlaps with the orthographic projection of the auxiliary electrode pattern 1061 on the substrate substrate 101.

[0409] Step 314: forming a second planarization layer on a side of the second source and drain electrode layer away from the substrate.

[0410] Fig.80 It is a schematic diagram of the structure of a second planar layer provided in an embodiment of the present application. Fig.81 It is a schematic diagram of forming a second flat layer in a second display area provided by an embodiment of the present application. Fig.82 It is a schematic diagram of forming a second flat layer in a first display area provided by an embodiment of the present application. Fig.83 This is a schematic diagram of forming a second flat layer in a first display area and a second display area provided by an embodiment of the present application.

[0411] In order to facilitate the illustration of each via hole 123a in the second planar layer 122, Figure 80 to Figure 83 The via hole 123a is indicated by a fill pattern. Other areas without fill patterns are used to indicate areas where the second planar layer 122 has solid material. Figure 80 to Figure 83 The second planar layer 122 has a via hole 123a in both the portion located in the first display area 101a and the portion located in the second display area 101b.

[0412] It should be noted that each via hole 123a opened in the second flat layer 122 is used to connect the subsequently formed film layer with the film layer on the side of the second flat layer 122 close to the base substrate 101. In other words, each via hole 123a is a via hole for connecting the film layer. The larger the aperture of the via hole, the smaller the transmittance; the smaller the aperture of the via hole, the greater the transmittance.

[0413] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the via hole 123a of the second flat layer 122 located in the first display area 101a can be made larger than the aperture of the via hole 123a of the first flat layer 123 located in the second display area 101a.

[0414] Optionally, the aperture of the via hole 123a of the second planar layer 122 located in the first display area 101a ranges from 3.8 μm to 4.1 μm, and the aperture of the via hole 123a of the second planar layer 122 located in the second display area 101b ranges from 3.3 μm to 3.5 μm.

[0415] Step 315 , forming a first anode layer in the first display area, and forming a second anode layer in the second display area.

[0416] In the embodiment of the present application, the first anode layer 103 and the second anode layer 107 can be formed by the same patterning process. The first anode layer 103 can be located in the first display area 101a of the base substrate 101, and the second anode layer 107 can be located in the second display area 101b of the base substrate 101.

[0417] Fig.84 It is a schematic diagram of a first anode layer and a second anode layer provided in an embodiment of the present application. Fig.85 It is a schematic diagram of forming a second anode layer in a second display area provided by an embodiment of the present application. Fig.86 An embodiment of the present application provides a schematic diagram of forming a first anode layer in a first display area. Fig.87 It is a schematic diagram of forming a first anode layer in a first display area and forming a second anode layer in a second display area provided by an embodiment of the present application.

[0418] refer to Fig.84 , the second anode layer 107 may include: a plurality of anode patterns 1071 arranged at intervals. Fig.85 and Fig.87 The orthographic projection of each anode pattern 1071 of the plurality of anode patterns 1071 on the base substrate 101 may be located within the orthographic projection of one auxiliary electrode pattern 1061 on the base substrate 101. Fig.84 , the first anode layer 103 may include a plurality of anode patterns 1031 arranged at intervals. Fig.86 and Fig.87 The orthographic projections of the plurality of anode patterns 1031 on the base substrate 101 are all located within the orthographic projection of the first auxiliary electrode layer 102 on the base substrate 101 .

[0419] In the embodiment of the present application, each anode pattern 1071 included in the second anode layer 107 can be used to form a light-emitting unit of a first sub-pixel. Each anode pattern 1031 included in the first anode layer 103 can be used to form a light-emitting unit of a second sub-pixel. The display panel 10 may include a plurality of sub-pixels, and the sub-pixel located in the second display area 101b among the plurality of sub-pixels is the first sub-pixel. The sub-pixel located in the first display area 101a among the plurality of sub-pixels is the second sub-pixel.

[0420] The plurality of sub-pixels include: red sub-pixels, green sub-pixels and blue sub-pixels. In addition, the first display area 101a and the second display area 101b may have sub-pixels of various colors. That is, the plurality of first sub-pixels of the first display area 101a include red sub-pixels, green sub-pixels and blue sub-pixels. The plurality of second sub-pixels of the second display area 101b include red sub-pixels, green sub-pixels and blue sub-pixels.

[0421] In order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the size of the anode pattern 1071 of the first sub-pixel located in the second display area 101b can be made smaller than the size of the anode pattern 1031 of the second sub-pixel located in the first display area 101a.

[0422] Optionally, the size of the anode pattern 1071 of the red sub-pixel located in the second display area 101b is smaller than the size of the anode pattern 1031 of the red sub-pixel located in the first display area 101a. The size of the anode pattern 1071 of the green sub-pixel located in the second display area 101b is smaller than the size of the anode pattern 1031 of the green sub-pixel located in the first display area 101a. The size of the anode pattern 1071 of the blue sub-pixel located in the second display area 101b is smaller than the size of the anode pattern 1031 of the blue sub-pixel located in the first display area 101a.

[0423] For example, the diameter of the anode pattern 1031 of the red sub-pixel located in the first display area 101a ranges from 30 μm to 32 μm, and the diameter of the anode pattern 1071 of the red sub-pixel located in the second display area 101b ranges from 20 μm to 22 μm. The diameter of the anode pattern 1031 of the green sub-pixel located in the first display area 101a ranges from 25 μm to 27 μm, and the diameter of the anode pattern 1071 of the green sub-pixel located in the second display area 101b ranges from 16 μm to 18 μm. The diameter of the anode pattern 1031 of the blue sub-pixel located in the first display area 101a ranges from 35 μm to 37 μm, and the diameter of the anode pattern 1031 of the blue sub-pixel located in the second display area 101b ranges from 23 μm to 25 μm.

[0424] Step 316: forming a pixel defining layer on a side of the first anode layer and the second anode layer away from the substrate.

[0425] Fig.88 It is a structural schematic diagram of a pixel definition layer provided in an embodiment of the present application. Fig.89 It is a schematic diagram of forming a pixel defining layer in a second display area provided by an embodiment of the present application. Fig.90 This is a schematic diagram of forming a pixel defining layer in a first display area provided by an embodiment of the present application. Fig.91 This is a schematic diagram of forming a pixel defining layer in a first display area and a second display area provided by an embodiment of the present application.

[0426] refer to Figures 88 to 91 The pixel defining layer 134 may have a plurality of tenth via holes 134a, and each tenth via hole 134a may expose an anode pattern. For example, the tenth via hole 134a in the pixel defining layer 134 located in the first display region 101a may expose an anode pattern 1031 in the first anode layer 103, and the tenth via hole 134a in the pixel defining layer 134 located in the second display region 101b may expose an anode pattern 1071 in the second anode layer 107.

[0427] In order to facilitate the illustration of each of the tenth via holes 134a in the pixel defining layer 134, Figures 88 to 91 The first via hole 134a is represented by a filling pattern. Other areas without a filling pattern are used to represent areas where the pixel defining layer 134 has a solid material. Figures 88 to 91 The portion of the pixel defining layer 134 located in the first display area 101 a and the portion located in the second display area 101 b both have a tenth via hole 134 a .

[0428] It should be noted that each of the tenth via holes 134a opened in the pixel defining layer 134 is used to connect the subsequently formed film layer with the film layer on the side of the pixel defining layer 134 close to the base substrate 101. That is, each of the tenth via holes 134a is a via hole for connecting the film layer. The larger the aperture of the tenth via hole, the smaller the transmittance; the smaller the aperture of the tenth via hole, the greater the transmittance.

[0429] Therefore, in order to improve the transmittance and pixel density of the second display area 101b and ensure the imaging effect of the camera located in the second display area 101b, the aperture of the tenth via hole 134a of the pixel defining layer 134 located in the first display area 101a can be made larger than the aperture of the tenth via hole 134a of the pixel defining layer 134 located in the second display area 101a.

[0430] Optionally, the aperture of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1071 of the red sub-pixel located in the second display area 101b is smaller than the aperture of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1031 of the red sub-pixel located in the first display area 101a. The aperture of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1071 of the green sub-pixel located in the second display area 101b is smaller than the aperture of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1031 of the green sub-pixel located in the first display area 101a. The aperture of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1071 of the blue sub-pixel located in the second display area 101b is smaller than the aperture of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1031 of the blue sub-pixel located in the first display area 101a.

[0431] For example, the aperture range of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1031 of the red sub-pixel located in the first display area 101a is 24 μm to 26 μm. The aperture range of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1071 of the red sub-pixel located in the second display area 101b is 16 μm to 18 μm. The aperture range of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1031 of the green sub-pixel located in the first display area 101a is 18 μm to 20 μm. The aperture range of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1071 of the green sub-pixel located in the second display area 101b is 12 μm to 14 μm. The aperture of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1031 of the blue sub-pixel in the first display area 101a is in the range of 29 μm to 31 μm. The aperture of the tenth via hole 134a in the pixel defining layer 134 for exposing the anode pattern 1071 of the blue sub-pixel in the second display area 101b is in the range of 19 μm to 21 μm.

[0432] Step 317: forming a first light-emitting layer in the first display area, and forming a second light-emitting layer in the second display area.

[0433] In the embodiment of the present application, the first light emitting layer 104 and the second light emitting layer 108 can be formed by the same patterning process. The first light emitting layer 104 can be located in the first display area 101a of the base substrate 101, and the second light emitting layer 108 can be located in the second display area 101b of the base substrate 101.

[0434] Optionally, the first light-emitting layer 104 and the second light-emitting layer 108 can be prepared by using a fine metal mask (FMM).

[0435] refer to Fig.88 , the portion of the pixel defining layer 134 located in the first display area 101a and the portion located in the second display area 101b may both have a tenth via hole. The light-emitting layer pattern of the first light-emitting layer 104 may be located in the tenth via hole 134a of the portion of the pixel defining layer 134 in the first display area 101a, and connected to an anode pattern exposed by the tenth via hole 134a. The light-emitting layer pattern 1081 of the second light-emitting layer 108 may be located in the tenth via hole of the portion of the pixel defining layer 134 in the second display area 101b, and connected to an anode pattern exposed by the tenth via hole.

[0436] It should be noted that each light-emitting layer pattern included in the first light-emitting layer 104 can be used to constitute a light-emitting unit of a second sub-pixel, and each light-emitting layer pattern 1081 included in the second light-emitting layer 108 can be used to constitute a light-emitting unit of a first sub-pixel.

[0437] Step 318: forming a support layer on a side of the first light-emitting layer and the second light-emitting layer away from the base substrate.

[0438] In the embodiment of the present application, a support layer 135 may be formed on the side of the first light-emitting layer 104 and the second light-emitting layer 108 away from the base substrate 101. The support layer 135 may have a plurality of support patterns, and the orthographic projections of the plurality of support patterns on the base substrate 101 at least partially do not overlap with the orthographic projections of the light-emitting layer pattern on the base substrate 101. This allows the cathode layer (the first cathode layer 105 or the second cathode layer 109) formed subsequently to contact the light-emitting layer pattern, thereby ensuring that the display panel 10 can emit light normally.

[0439] Step 319: forming a first cathode layer in the first display area, and forming a second cathode layer in the second display area.

[0440] In the examples of this application, refer to Fig.92 The first cathode layer 105 and the second cathode layer 109 may be formed by the same patterning process. The first cathode layer 105 may be located in the first display region 101a of the base substrate 101, and the second cathode layer 109 may be located in the second display region 101b of the base substrate 101. The first cathode layer 105 may be connected to the second cathode layer 109.

[0441] refer to Figure 92 to Figure 95The first cathode layer 105 has no hollow region, and the first cathode layer 105 is connected to the light-emitting layer pattern of the first light-emitting layer 104. The second cathode layer 109 has at least one hollow region, so the portion of the second cathode layer 109 other than the at least one hollow region can be connected to the light-emitting layer pattern 1081 of the second light-emitting layer 108.

[0442] In the embodiment of the present application, the first cathode layer 105 and the first auxiliary electrode layer 102 formed in step 302 may also be located in the middle peripheral region 101c of the base substrate 101. The portion of the first cathode layer 105 located in the peripheral region 101c may be connected to the portion of the first auxiliary electrode layer 102 located in the peripheral region 101c.

[0443] Since other wirings are usually required to be arranged in the second area 101c2 of the peripheral area 101c, the portion of the first auxiliary electrode layer 102 located in the second area 101c2 is not connected to the portion of the first cathode layer 105 located in the second area 101c2 to avoid affecting the arrangement of other wirings.

[0444] Furthermore, the portion of the first auxiliary electrode layer 102 located in the first region 101c1 is connected to the portion of the first cathode layer 105 located in the first region 101c1. The portion of the first auxiliary electrode layer 102 located in the third region 101c3 is connected to the portion of the first cathode layer 105 located in the third region 101c3. The portion of the first auxiliary electrode layer 102 located in the fourth region 101c4 is connected to the portion of the first cathode layer 105 located in the fourth region 101c4.

[0445] In summary, the embodiment of the present application provides a method for preparing a display panel, wherein the display panel prepared by the method includes a second cathode layer having a hollow area, so the second cathode layer does not cover the second display area in its entirety. Compared with a cathode layer that covers the second display area in its entirety, the influence on light transmittance can be effectively reduced, and the imaging effect of the camera located in the second display area is better.

[0446] Fig.96 is a schematic diagram of the structure of a display device provided in an embodiment of the present application. Fig.96 It can be seen that the display device may include: an image sensor 40 and a display panel 10 as provided in the above embodiment. The image sensor 40 may be located on a side of the base substrate 101 of the display panel 10 away from the second auxiliary electrode layer 106, and located in the second display area 101b of the base substrate 101. The image sensor 30 may be a front camera of the display device, for capturing images.

[0447] Optionally, the display device may be an OLED display device, a liquid crystal display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, or any other product or component with a display function.

[0448] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: A base substrate, wherein the base substrate has a first display area and a second display area; A first auxiliary electrode layer, a first anode layer, a first light-emitting layer and a first cathode layer are located in the first display area and are sequentially stacked in a direction away from the base substrate; A second auxiliary electrode layer, a second anode layer, a second light emitting layer and a second cathode layer are located in the second display area and are sequentially stacked in a direction away from the base substrate; Wherein, the first auxiliary electrode layer is connected to the first cathode layer, the second auxiliary electrode layer is connected to the first auxiliary electrode layer, the second cathode layer is connected to the first cathode layer, and the second cathode layer has at least one hollow area; The display panel also includes a plurality of pixel circuits located in the second display area, each of the pixel circuits including at least one layer of opaque pattern; wherein the second auxiliary electrode layer includes: a plurality of electrically connected auxiliary electrode patterns, at least 50% of the orthographic projection area of ​​at least one layer of opaque pattern in at least one of the pixel circuits on the base substrate overlaps with the orthographic projection area of ​​the auxiliary electrode pattern on the base substrate.

2. The display panel according to claim 1, characterized in that: The orthographic projection of the auxiliary electrode pattern on the base substrate covers the orthographic projection of at least one layer of opaque pattern in at least one of the pixel circuits on the base substrate.

3. The display panel according to claim 1, characterized in that: At least a portion of the edge of the orthographic projection of the auxiliary electrode pattern on the base substrate is arc-shaped.

4. The display panel according to claim 1, characterized in that: The auxiliary electrode pattern includes: a first pattern and a second pattern; The orthographic projection of the first pattern on the base substrate overlaps with more than 50% of the orthographic projection area of ​​at least one layer of opaque pattern in at least one pixel circuit on the base substrate; The second pattern is used to be electrically connected to the adjacent auxiliary electrode pattern.

5. The display panel according to claim 4, characterized in that: The orthographic projection of the first pattern on the base substrate is in a circular shape.

6. The display panel according to claim 1, characterized in that: The base substrate also has a peripheral area surrounding the first display area and the second display area; The first auxiliary electrode layer and the first cathode layer are also located in the peripheral region, and a portion of the first auxiliary electrode layer located in the peripheral region is electrically connected to a portion of the first cathode layer located in the peripheral region.

7. The display panel according to claim 6, characterized in that: The orthographic projection of the first auxiliary electrode layer on the base substrate covers the first display area; The peripheral area includes: a first area and a second area arranged opposite to and in parallel, and a third area and a fourth area arranged opposite to and in parallel, the extension direction of the first area is perpendicular to the extension direction of the third area, and the distance between the second display area and the first area is smaller than the distance between the second display area and the second area; The portion of the first auxiliary electrode layer located in the first region is connected to the portion of the first cathode layer located in the first region, the portion of the first auxiliary electrode layer located in the third region is connected to the portion of the first cathode layer located in the third region, and the portion of the first auxiliary electrode layer located in the fourth region is connected to the portion of the first cathode layer located in the fourth region; A portion of the first auxiliary electrode layer located in the second region is not connected to a portion of the first cathode layer located in the second region.

8. The display panel according to any one of claims 1 to 7, characterized in that: The plurality of auxiliary electrode patterns overlap each other.

9. The display panel according to any one of claims 1 to 7, characterized in that: The display panel further includes: a plurality of first connection electrodes located in the second display area, and the plurality of auxiliary electrode patterns are electrically connected through the plurality of first connection electrodes.

10. The display panel according to any one of claims 1 to 7, characterized in that: The display panel further includes: an active layer, a buffer layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, and a first source and drain layer, which are located in the first display area and the second display area and are sequentially stacked in a direction away from the base substrate; The first source-drain electrode layer includes a plurality of first source-drain electrode layer patterns corresponding to the respective pixel circuits; the active layer includes a plurality of active patterns corresponding to the respective pixel circuits; the first gate layer includes a plurality of first gate layer patterns corresponding to the respective pixel circuits; and the second gate layer includes a plurality of second gate layer patterns corresponding to the respective pixel circuits; The at least one layer of opaque patterns of the pixel circuit includes: a group of the first source and drain layer patterns located in the first source and drain layer, a group of the active patterns located in the active layer, a group of the first gate patterns located in the first gate layer, and a group of the second gate patterns located in the second gate layer.

11. The display panel according to claim 10, characterized in that: The display panel further includes: a first conductive layer located at the same layer as the first source and drain electrode layer, and a second conductive layer located at the same layer as the second gate layer; a buffer layer, a first gate insulating layer, a second gate insulating layer, and the interlayer dielectric layer all have first via holes; the second conductive layer and the first conductive layer are electrically connected to the auxiliary electrode pattern through the first via holes; The display panel further comprises a passivation layer and a first planarization layer located on a side of the first source and drain electrode layer away from the base substrate, and a plurality of first connection electrodes located between the passivation layer and the first planarization layer; The passivation layer has a second via hole, at least a portion of the first connecting electrode is located in the second via hole and connected to the first conductive layer; the plurality of first connecting electrodes are used to connect the plurality of auxiliary electrode patterns.

12. The display panel according to claim 10, characterized in that: The display panel further includes: a passivation layer and a first planarization layer located on a side of the first source and drain electrode layer away from the base substrate, a plurality of second connection electrodes located between the passivation layer and the first planarization layer, a first signal transmission layer located on the same layer as the first source and drain electrode layer, and a third conductive layer located on the same layer as the first gate layer; The first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer all have a third via hole; the first signal transmission layer is electrically connected to the third conductive layer through the third via hole; The passivation layer has a fourth via hole, and at least a portion of the second connection electrode is located in the fourth via hole and connected to the first signal transmission layer.

13. The display panel according to claim 12, characterized in that: The third conductive layer includes: a plurality of first signal line segments, a plurality of second signal line segments, and a plurality of third signal line segments; Wherein, each of the plurality of first signal line segments, the plurality of second signal line segments, and the plurality of third signal line segments is connected to one pixel circuit; The plurality of second connecting electrodes include: a plurality of first-type second connecting electrodes connected to the plurality of first signal line segments, a plurality of second-type second connecting electrodes connected to the plurality of second signal line segments, and a plurality of third-type second connecting electrodes connected to the plurality of third signal line segments.

14. The display panel according to claim 13, characterized in that: The multiple first signal line segments are gate signal line segments for transmitting gate signals, the multiple second signal line segments are reset control signal line segments for transmitting reset control signals, and the multiple third signal line segments are light-emitting control signal line segments for transmitting light-emitting control signals.

15. The display panel according to claim 10, characterized in that: The display panel further includes: a plurality of third connection electrodes, and a fourth conductive layer; the fourth conductive layer includes a plurality of fourth signal line segments; Each of the fourth signal line segments is connected to at least one of the pixel circuits, and at least some of the fourth signal line segments among the plurality of fourth signal line segments are electrically connected via at least some of the third connection electrodes.

16. The display panel according to claim 15, characterized in that: The display panel further includes a passivation layer and a first planarization layer located on a side of the first source-drain electrode layer away from the base substrate, and a second source-drain electrode layer located on the first planarization layer away from the first source-drain electrode layer; The fourth conductive layer and the first source-drain electrode layer are located in the same layer, and the plurality of third connection electrodes are located between the passivation layer and the first planar layer; The display panel further comprises: a fifth conductive layer located in the same layer as the second source-drain electrode layer, the fifth conductive layer comprising a plurality of fifth signal line segments; the passivation layer has a fifth via hole; At least a portion of the third connection electrode is located in the fifth via hole and connected to the fourth signal line segment. The first planar layer has a sixth via hole. At least a portion of the fifth signal line segment is located in the sixth via hole and connected to the third connection electrode.

17. The display panel according to claim 16, characterized in that: The plurality of fourth signal line segments and the plurality of fifth signal line segments are all positive power signal line segments, and are used to transmit positive power signals.

18. The display panel according to claim 15, characterized in that: The display panel further comprises a passivation layer and a first planarization layer located on a side of the first source and drain electrode layer away from the base substrate; The fourth conductive layer and the first source-drain electrode layer are located in the same layer, and the plurality of third connection electrodes are located between the passivation layer and the first planarization layer; The passivation layer has a seventh via hole; At least a portion of the third connection electrode is located in the seventh via hole and connected to the fourth signal line segment.

19. The display panel according to claim 18, characterized in that: The plurality of fourth signal line segments are data signal line segments, which are used to transmit data signals.

20. The display panel according to claim 15, characterized in that: The display panel further comprises a passivation layer and a first planarization layer located on a side of the first source and drain electrode layer away from the base substrate; The fourth conductive layer and the second gate layer are located in the same layer, and the plurality of third connecting electrodes are located between the passivation layer and the first planar layer; The display panel further includes: a second signal transmission layer located in the same layer as the first source and drain electrode layer; an eighth via hole is provided in the second gate insulating layer and the interlayer dielectric layer; the second signal transmission layer is located in the eighth via hole, and the second signal transmission layer is connected to the fourth signal line segment; The passivation layer has a ninth via hole, and at least a portion of the third connection electrode is located in the ninth via hole and connected to the second signal transmission layer.

21. The display panel according to claim 15, characterized in that: The plurality of fourth signal line segments are initialization signal line segments, and are used to transmit initialization signals.

22. The display panel according to claim 1, characterized in that: The display panel further comprises: an active layer, a buffer layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, an interlayer dielectric layer, a first source-drain electrode layer, a passivation layer and a first planar layer, which are located in the first display area and the second display area and are stacked in sequence in a direction away from the base substrate; the display panel further comprises a plurality of connecting electrodes located between the passivation layer and the first planar layer; at least part of the plurality of connecting electrodes are used to electrically connect at least one of the first gate layer, the second gate layer and the first source-drain electrode layer in the first display area and at least one of the first gate layer, the second gate layer and the first source-drain electrode layer in the second display area, and / or at least part of the plurality of connecting electrodes are used to electrically connect at least two of the auxiliary electrode patterns located in the second display area, and / or at least part of the plurality of connecting electrodes are used to connect at least one layer of an opaque pattern in at least two of the pixel circuits in the second display area; Among them, the multiple connecting electrodes have multiple connecting points, and the connecting points include connecting vias or overlapping structures corresponding to the respective patterns connected to the multiple connecting electrodes, and the orthographic projection of the auxiliary electrode pattern on the base substrate has an overlapping area with the orthographic projection of at least one of the connecting points on the base substrate.

23. The display panel according to claim 22, characterized in that: The orthographic projection of the auxiliary electrode pattern on the base substrate covers the orthographic projection of at least one of the connection points on the base substrate.

24. The display panel according to any one of claims 1 to 7, characterized in that: The second anode layer includes a plurality of anode patterns arranged at intervals; The display panel further comprises: a pixel defining layer located on a side of the second anode layer away from the base substrate; The pixel defining layer has a plurality of tenth via holes, and the tenth via holes expose the corresponding anode pattern; the second light-emitting layer includes: a plurality of light-emitting layer patterns, and the light-emitting layer patterns are at least partially located in the tenth via holes; The second cathode layer at least partially covers the tenth via hole, and the at least one hollow region of the second cathode layer does not overlap with the tenth via hole.

25. The display panel according to any one of claims 1 to 7, characterized in that: The boundary of the at least one hollow area at least partially comprises an arc shape.

26. The display panel according to any one of claims 1 to 7, characterized in that: The first cathode layer and the second cathode layer are an integrated structure.

27. The display panel according to any one of claims 1 to 7, characterized in that: An area of ​​an overlapping portion of an orthographic projection of the hollow region on the base substrate and an orthographic projection of the auxiliary electrode pattern on the base substrate is less than 10% of an area of ​​the hollow region.

28. A method for preparing a display panel, characterized in that: The method comprises: Providing a base substrate, the base substrate having a first display area and a second display area; Forming a first auxiliary electrode layer, a first anode layer, a first light emitting layer, and a first cathode layer stacked in sequence in the first display area; Forming a second auxiliary electrode layer, a second anode layer, a second light emitting layer, and a second cathode layer stacked in sequence in the second display area; forming a plurality of pixel circuits in the second display area; Among them, the first auxiliary electrode layer is connected to the first cathode layer, the second auxiliary electrode layer is connected to the first auxiliary electrode layer, the second cathode layer is connected to the first cathode layer, and the second cathode layer has at least one hollow area; the second auxiliary electrode layer includes: a plurality of electrically connected auxiliary electrode patterns; at least 50% of the orthographic projection area of ​​at least one layer of opaque pattern in at least one of the pixel circuits on the base substrate overlaps with the orthographic projection area of ​​one of the auxiliary electrode patterns on the base substrate.

29. A display device, characterized in that: The display device comprises: an image sensor and a display panel according to any one of claims 1 to 27; The image sensor is located on a side of the base substrate in the display panel away from the second anode layer, and overlaps with the second display area of ​​the base substrate.

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