A Montgomery modular multiplication method and device based on 2

Abstract

The present invention discloses a base-2 Montgomery modular multiplication method and device. By simplifying operations such as subtraction, intermediate coefficients, and multiplication, the standard base-2 Montgomery modular multiplication algorithm is structurally adjusted and optimized. The device includes a top-level control unit, a data distribution unit, and a core computing unit. The top-level control unit's input is connected to input data X, Y, and N, a calculation completion signal, and an intermediate calculation result, while its output outputs Montgomery calculation numbers A and B, modulus N, a final result, and a final result valid signal. The data distribution unit is connected to the top-level control unit and outputs a certain bit of Montgomery calculation number A, calculation number B, modulus N, and a data distribution completion signal. The core computing unit is connected to the data distribution unit and outputs an intermediate calculation result and a calculation completion signal. The present invention is applied to large-number modular multiplication operations and can significantly reduce the time and resources required for actual operation.

Description

Technical Field

[0001] The present invention relates to a Montgomery modular multiplication method and device based on 2, belonging to the field of digital signal processing and information encryption of ultra-large-scale integrated circuits. Background Art

[0002] The RSA algorithm is one of the most widely used asymmetric cryptographic systems. Its principle is based on the principle that, according to number theory, finding two large prime numbers of several hundred or even thousands of bits is relatively simple, while factoring their product to obtain these two large prime numbers is extremely difficult. This principle allows the corresponding public and private key pairs to be generated. The RSA algorithm uses this public and private key pair as a power exponent to perform modular exponentiation operations to encrypt and decrypt original text.

[0003] The performance of the RSA algorithm depends primarily on the efficiency of modular multiplication and exponentiation operations after modular exponentiation. Because the operations involved in the RSA algorithm involve large numbers exceeding thousands of digits, modular multiplication becomes the algorithm's speed bottleneck. The primary factor affecting modular multiplication speed is modular operations, which are essentially division operations. Compared to addition, subtraction, and multiplication, division operations incur greater time and space overhead, significantly reducing the speed of RSA encryption and decryption. To address this issue, in 1985, Montgomery transformed the multiplier and multiplicand into a residue class representation of the modulus N (Montgomery field). He then discovered an algorithm that performs modular multiplication using only addition, multiplication, and shift operations. Because the division operations are replaced by multiplication and shift operations, the Montgomery modular multiplication algorithm achieves more efficient modular multiplication.

[0004] Currently, when implementing Montgomery modular multiplication operations of arbitrary length, each loop calculation involves bit-by-bit comparisons of large numbers, subtraction operations, and a large number of multiplication operations, which consume a lot of hardware resources and time resources. This results in low computational efficiency when implementing the algorithm on hardware. Therefore, a method more suitable for hardware implementation is needed to replace the use of the above operations. Summary of the Invention

[0005] In order to optimize the area and power consumption of hardware and improve the performance and energy efficiency of the system, the present invention provides an optimized 2-based Montgomery modular multiplication method and device.

[0006] The technical solution adopted in the method of the present invention is as follows:

[0007] A Montgomery modular multiplication method based on base 2, the specific steps of the method comprising:

[0008] S1. Calculate RRN based on the bit length k of the multipliers X and Y, where RRN = 2^2(k+3) mod N, where N is the modulus. Assign the multipliers X and RRN to the calculation numbers A and B, respectively, and perform a Montgomery modular multiplication on the calculation numbers A, B, and the modulus N as follows:

[0009] S11, expand the bit length of the calculation number A to k+3 and set the two highest bits A[k+2] and A[k+1] of A to 0, expand the bit length of the calculation number B to k+2, shift it left by one bit and set the lowest bit B[0] of B to 0, then assign the lowest bit S[0] of the Montgomery modular multiplication calculation result S obtained in the previous loop to the intermediate coefficient q, and then use a judgment statement to realize the summation of the product of the lowest bit A[0] of the calculation number A and the calculation number B and the product of the intermediate coefficient q and the modulus N, and sum the above summation result with the Montgomery modular multiplication calculation result S and shift it right by one bit to obtain the updated value of S; wherein, the initial value of the calculation result S participating in the operation in the first loop is 0;

[0010] S12, repeat step S11 k+3 times, each time replacing the lowest bit A[0] with the i-th bit A[i] of the calculated number A, and incrementing the value of i by 1 after the calculation. The loop ends when the value of i equals k+2. The calculation result S is updated to the intermediate calculation result mid_S and used as X', where X' is the value of the multiplier X in the Montgomery field.

[0011] S2, assign the multiplier Y and RRN to the calculation numbers A and B respectively and repeat step S1 to obtain Y', where Y' is the value of the multiplier Y in the Montgomery domain;

[0012] S3, assign X' and Y' to the calculation numbers A and B respectively and repeat step S1 to obtain Z', where Z' is the value of the final result Z of the modular multiplication of the multipliers X and Y with N as the modulus in the Montgomery field;

[0013] S4, assign Z' and 1 to the calculated numbers A and B respectively and repeat step S1 to obtain the final result Z.

[0014] Furthermore, in step S11, since the i-th digit A[i] of the calculated number A and the intermediate coefficient q are both 1-bit numbers, the two are first spliced ​​into a 2-bit number and then judged. If the spliced ​​number is 00, S is updated to S; if it is 01, S is updated to S+N; if it is 10, S is updated to S+B; if it is 11, S is updated to S+B+N.

[0015] The present invention also provides a device for implementing Montgomery modular multiplication based on a base of 2, comprising:

[0016] The top-level control unit is configured to receive input data and data from the core computing unit, and select a calculation number and a modulus to be subjected to Montgomery modular multiplication according to a current state of a state machine of the top-level control unit and a signal input from the core computing unit;

[0017] The data distribution unit is used to receive the calculation number and modulus transmitted by the top-level control unit, and transmit the calculation number A bit by bit from low to high to the core calculation unit, and transmit the calculation number B and modulus N to the core calculation unit at the same time;

[0018] The core computing unit is used to receive data transmitted by the data distribution unit, with its input end connected to the output end of the data distribution unit, and is used to calculate new intermediate calculation results and transmit them to the top-level control unit.

[0019] Furthermore, the top-level control unit includes a state machine structure with four states, wherein the four states are: converting the multiplier X into the Montgomery domain, converting the multiplier Y into the Montgomery domain, performing calculations in the Montgomery domain, and converting Z' from the Montgomery domain into the final result Z, where Z' is the value of the final result Z in the Montgomery domain; the input end of the top-level control unit inputs the multipliers X, Y and modulus N, a calculation completion signal and an intermediate calculation result mid_S, and the output end outputs the Montgomery calculation numbers A, B and modulus N to the data distribution unit, and outputs the final result Z and the final result valid signal Z_done to the outside; when the top-level control unit traverses the above four states, the modular multiplication operation of the input data X, Y, N is completed to obtain the final result Z.

[0020] Furthermore, the data distribution unit is used to transmit the calculation number A bit by bit from low to high to the core computing unit, and at the same time transmit the calculation number B and the modulus N to the core computing unit; when the highest bit of the calculation number A is transmitted, the data distribution unit transmits a data distribution completion signal to the core computing unit; the input end of the data distribution unit inputs the Montgomery calculation number A, B and modulus N output by the top-level control unit, and its output end outputs a certain bit of the Montgomery calculation number A, the calculation number B, the modulus N and the data distribution completion signal dis_done.

[0021] Furthermore, the core computing unit includes a multiplexer, two adders and a shift register; the output end of the core computing unit outputs the intermediate computing result mid_S and the computing completion signal Z_done to the top-level control unit.

[0022] The present invention simplifies subtraction, intermediate coefficient, and multiplication operations based on the standard algorithm, and structurally adjusts and optimizes the Montgomery modular multiplication algorithm based on base 2. Specifically, the simplified subtraction operation optimizes the bit-by-bit comparison and subtraction operations for large numbers with thousands of bits; the simplified intermediate coefficient calculation reduces one addition and one high-bit multiplication operation in the loop; and the optimized multiplication operation simplifies the three multipliers and three adders in the original loop into one multiplexer and two adders. In the actual implementation process of the hardware architecture of the present invention, time delay, hardware area, and power consumption are greatly reduced, thereby improving overall performance and energy efficiency, and having great advantages over the existing standard Montgomery modular multiplication algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a flow chart of modular multiplication operations using Montgomery modular multiplication, (a) a complete modular multiplication operation flow chart (including four Montgomery modular multiplications), where X, Y, and N represent input data, Z represents output data, and X'Y'Z' represents the value of the corresponding data in the Montgomery domain; (b) a standard Montgomery modular multiplication operation flow chart, where A, B, and N represent input data, and S represents the Montgomery modular multiplication calculation result.

[0024] Figure 2 The present invention adopts the Montgomery modular multiplication pseudo code after simplifying the subtraction operation, intermediate coefficient and multiplication operation.

[0025] Figure 3 Schematic diagram of the overall hardware architecture of the present invention using Montgomery modular multiplication to perform modular multiplication operations.

[0026] Figure 4 It is a structural diagram of the top-level control unit of the present invention.

[0027] Figure 5 It is a structural diagram of the data distribution unit of the present invention.

[0028] Figure 6 This is a structural diagram of the core computing unit when the present invention only uses simplified subtraction operations.

[0029] Figure 7 This is a structural diagram of the core computing unit when the present invention adopts simplified subtraction operations and intermediate coefficient calculations.

[0030] Figure 8 This is a structural diagram of the core computing unit when the present invention adopts simplified subtraction operations, intermediate coefficient calculations, and multiplication operations. DETAILED DESCRIPTION

[0031] The embodiment of the present invention provides an optimized Montgomery modular multiplication method based on base 2, the specific steps of which include:

[0032] S1. When receiving the multipliers X, Y, and modulus N, calculate RRN based on the bit length k of the multipliers X and Y, where RRN = 2^2(k+3) mod N, where N is the modulus. Assign the multipliers X and RRN to the calculation numbers A and B, respectively, and perform a Montgomery modular multiplication on the calculation numbers A, B, and modulus N as follows:

[0033] S11, expand the bit length of the calculation number A to k+3 and set the two highest bits A[k+2] and A[k+1] of A to 0, expand the bit length of the calculation number B to k+2, shift it left by one bit and set the lowest bit B[0] of B to 0, then assign the lowest bit S[0] of the Montgomery modular multiplication calculation result S obtained in the previous loop to the intermediate coefficient q, and then use a judgment statement to realize the summation of the product of the lowest bit A[0] of the calculation number A and the calculation number B and the product of the intermediate coefficient q and the modulus N, and sum the above summation result with the Montgomery modular multiplication calculation result S and shift it right by one bit to obtain the updated value of S; wherein, the initial value of the calculation result S participating in the operation in the first loop is 0;

[0034] S12, repeat step S11 k+3 times, each time replacing the lowest bit A[0] with the i-th bit A[i] of the calculated number A, and incrementing the value of i by 1 after the calculation. The loop ends when the value of i equals k+2. The calculation result S is updated to the intermediate calculation result mid_S and used as X', where X' is the value of the multiplier X in the Montgomery field.

[0035] S2, assign the multiplier Y and RRN to the calculation numbers A and B respectively and repeat step S1 to obtain Y', where Y' is the value of the multiplier Y in the Montgomery domain;

[0036] S3, assign X' and Y' to the calculation numbers A and B respectively and repeat step S1 to obtain Z', where Z' is the value of the final result Z of the modular multiplication of the multipliers X and Y with N as the modulus in the Montgomery field;

[0037] S4, assign Z' and 1 to the calculated numbers A and B respectively and repeat step S1 to obtain the final result Z.

[0038] The Montgomery modular multiplication method based on 2 that is optimized by the present invention is as follows: Figure 2 As shown in the figure, compared with the existing standard Montgomery modular multiplication algorithm, structural adjustments and optimizations have been made, including:

[0039] 1. Simplify subtraction operations: As shown in Figure 1(b), during the standard Montgomery modular multiplication operation, the range of S is S < 2N. Therefore, after the loop ends, at most one comparison and subtraction operation are still required. If the input calculation numbers A and B are also converged within 2N, the comparison of S and N and the subtraction calculation of S - N can be omitted during the continuous modular multiplication operation, and only one subtraction operation needs to be performed after the last modular multiplication to obtain the final result. To make A < 2N and B < 2N, the present invention makes k → k + 2, so that 2N < 2(k + 2) - 1; after ensuring A < 2N and B < 2N, to make S < 2N still hold after increasing the loop count, the bit lengths of A and B are respectively extended to k + 2 and k + 1 here, and the highest bit A[k + 1] of A is set to 0.

[0040] One Montgomery modular multiplication operation does not perform a complete modular multiplication operation. As shown in Figure 1(a), a complete modular multiplication operation also requires a Montgomery modular multiplication operation MMM(Z’, 1). Therefore, the final result is ZR = Z’ + QN (where Q is the number obtained by arranging the q in each loop bit by bit, and R is 2^(k + 2)). The following derivation proves that the present invention will ensure that the final result Z of the modular multiplication of the multiplier X and Y with N as the modulus satisfies Z < N:

[0041] ZR = Z’ + QN

[0042] Z = (Z’ + QN) / R

[0043] Z ≤ (Z’ + (R - 1)N) / R (1)

[0044] Z < (R + 1)N / R

[0045] Z < (R + 1)N / R

[0046] Z < N + N / R

[0047] Since N / R < 1 and both Z and N are positive integers, so Z ≤ N. And if Z = N, then Z’ ≡ 0 mod N, and further it can be deduced that A ≡ 0 mod N. However, by definition, A < N, so S ≠ N, and at the same time it can be obtained that S < N. Therefore, the subtraction operation performed after the last modular multiplication can also be omitted.

[0048] 2. Simplify the calculation of intermediate coefficients: On the basis of eliminating the subtraction operation, the calculation of the intermediate coefficient q can be further simplified. The existing calculation formula for the intermediate coefficient q is as follows.

[0049] q = S[0] + A[i]B[0] (2)

[0050] Since both S[0] and A[i] participate in the loop, optimization can only be performed at B[0]. Shift B left by one position, that is, let B→2B. The advantage of this is that b[0]=0, and then the present invention simplifies the calculation formula of q to q=S[0]. However, since the value of B has become twice as much as before, it is necessary to add a loop (i.e. k+2→k+3), expand the bit length of the calculation number A to k+3 and set the highest two digits of A A[k+2] and A[k+1] to 0, and expand the bit length of the calculation number B to k+2 to obtain the correct modular multiplication result. The above data processing method that reduces one addition and one high-bit multiplication operation will significantly improve the running speed of the modular multiplication operation.

[0051] 3. Simplify the multiplication operation: Since A[i] and the intermediate coefficient q in the multiplication A[i]B and qN are both 1-bit numbers, the multiplication operation can be implemented using a judgment statement. That is, first concatenate A[i] and q into a 2-bit number and then make a judgment. If the concatenated number is 00, update S to S; if it is 01, update S to S+N; if it is 10, update S to S+B; if it is 11, update S to S+B+N. In this way, two multiplication operations can be omitted, and only two addition operations are required to complete the current loop.

[0052] This embodiment also provides a device for implementing the above method, including a top-level control unit, a data distribution unit, and a core computing unit, such as Figure 3 As shown in Figure 1(a), the top-level control unit receives input data X, Y, N and the intermediate calculation result mid_S, outputs the final result Z, and controls the remaining units in the form of a state machine to perform four Montgomery modular multiplications as shown in Figure 1(a). The data distribution unit distributes the calculation number A obtained from the top-level control unit bit by bit to the core calculation unit, and also distributes the calculation number B and the modulus N to the core calculation unit. The core calculation unit calculates the distributed data to obtain the intermediate calculation result and transmits it to the top-level control unit for storage. During this process, after the distribution of each bit of the calculation number A is completed and the core calculation unit completes the calculation, a state of the top-level control unit is completed. When the fourth state is completed, the final result Z is output.

[0053] The specific implementation process of the above device includes:

[0054] (1) The top-level control unit receives input data and data from the core computing unit, and selects the number of calculations and moduli required for Montgomery modular multiplication based on the current state of the state machine and the input signals from the data distribution unit and the core computing unit. In particular, due to the optimization of simplified subtraction operations and intermediate coefficient calculations, the number of calculations RRN will be different from the standard algorithm, such as Figure 4As shown, the top-level control unit is a state machine structure with four states: converting the multiplier X to the Montgomery domain, converting the multiplier Y to the Montgomery domain, performing calculations in the Montgomery domain, and converting Z' from the Montgomery domain to the final result Z, where Z' is the value of the final result Z in the Montgomery domain. The top-level control unit's inputs receive the multipliers X and Y, the modulus N, a calculation completion signal, and the intermediate calculation result mid_S. Its output outputs the Montgomery calculation numbers A and B and the modulus N to the data distribution unit, and outputs the final result Z and the final result valid signal Z_done to the external device. After traversing these four states, the top-level control unit completes the modular multiplication operation on the input data X, Y, and N, obtaining the final result Z.

[0055] (2) After receiving the calculation number and modulus of the Montgomery modular multiplication transmitted by the top-level control unit, the data distribution unit transmits the calculation number A from low to high bit by bit, as well as the calculation number B, modulus N and other large numbers to the core computing unit. When the highest bit of the calculation number A is transmitted, the data distribution unit transmits a data distribution completion signal to the core computing unit. The data interface of the data distribution unit is as follows: Figure 5 As shown, its input end inputs the Montgomery calculation number A, B and modulus N output by the top-level control unit, and its output end outputs a bit of the Montgomery calculation number A, the calculation number B, the modulus N and the data distribution completion signal dis_done.

[0056] (3) The input end of the core computing unit is connected to the output end of the data distribution unit. After receiving the calculation numbers transmitted by the data distribution unit, it calculates the new intermediate calculation result mid_S and transmits it to the top-level control unit.

[0057] Example 1

[0058] This embodiment uses Figure 3 The overall hardware architecture shown and Figure 6 The core computing unit shown utilizes an optimized method for simplified subtraction operations. When the input data X and Y are k-bit large numbers, the simplified subtraction optimization yields RRN as 2^2(k+2) mod N. The device's inputs are connected to each unit's system clock signal clk, system reset signal rst_n, and the input data X, Y, and N from the top-level control unit. The output is connected to the top-level control unit's final result Z and the final result valid signal Z_done.

[0059] When input data signals X, Y, and N arrive and the system clock signal rises, the state machine in the top-level control unit is in 00. It calculates the value of RRN and assigns X and RRN to calculation numbers A and B, respectively. These calculation numbers A and B are then output to the data distribution unit. The data distribution unit receives calculation number A and expands its highest bit to make A[k+1] = 0. It extracts each bit as A[i] and distributes A[i], B, and N to the core computing unit for loop calculations. The first loop distributes A[0], the second loop distributes A[1], and so on. Simultaneously, a counter begins counting. After distributing the highest bit A[k+1] of A, the counter resets to zero and transmits the distribution completion signal, dis_done, to the core computing unit.

[0060] After receiving A[i], B and N, the core computing unit starts to calculate with S obtained in the previous cycle, and updates the value of S when the rising edge of the system clock signal arrives. When the distribution completion signal dis_done is received and the calculation is completed, S is assigned to the intermediate calculation result mid_S, and the intermediate calculation result mid_S and the calculation completion signal cal_done are transmitted to the top-level control unit.

[0061] When the calculation completion signal cal_done is valid, the top-level control unit receives the intermediate calculation result mid_S and assigns it to X', and the state machine transfers to the next state 01.

[0062] When the state machine is in state 01, each unit repeats the operation of the previous state. Unlike state 00, the top-level control unit assigns Y and RRN to the calculation numbers A and B respectively. At the same time, when cal_done is valid, the current intermediate calculation result mid_S is assigned to Y', and the state machine transfers to the next state 10.

[0063] When the state machine is in states 10 and 11, its operation is the same as the above states, and calculations of Z'=MMM(X',Y') and Z=MMM(Z',1) are performed respectively. When state 11 ends, the device outputs the final result Z and the final result valid signal through the top-level control unit, and the state machine transfers to state 00 to wait for the arrival of the next set of input data.

[0064] Example 2

[0065] This embodiment uses Figure 3 The overall hardware architecture shown and Figure 7The core computing unit shown is used to adopt an optimized method for simplifying subtraction operations and intermediate coefficient calculations. The interfaces of each unit are the same as those in Example 1. The difference is that in this embodiment, RRN is 2^2(k+3) mod N, and in the data distribution unit, the highest bit of the calculation number A is expanded so that A[k+2]=A[k+1]=0, and the calculation number B is shifted to the left so that B[0]=0. The core computing unit of this embodiment has one fewer multiplier and one fewer adder than in Example 1, reducing the area and power consumption of the device.

[0066] Example 3

[0067] This embodiment uses Figure 3 The overall hardware architecture shown and Figure 8 The core computing unit shown is used to adopt an optimized method of simplifying subtraction operations, intermediate coefficient calculations, and multiplication operations. Figure 8 As shown, the core computing unit includes a multiplexer, two adders, and a shift register. The multiplexer takes the calculation number B, modulus N, B+N, and 0 as input signals, S[0] and A[i] as judgment signals, and A[i]B+qN as output signal; one adder implements the addition operation of B and N; the other adder implements the addition operation of S and A[i]B+qN; the shift register implements the shift operation of the output signal of the latter adder, and takes the updated S as the output signal. The input end of the core computing unit is connected to one bit of the calculation number A, the calculation number B, and the modulus N. After calculation, its output end is connected to the top-level control unit to transmit the new intermediate calculation result mid_S and the calculation completion signal cal_done to it. This embodiment optimizes only the core computing unit based on Example 2, and the remaining calculation numbers and number of loops are the same as Example 2. Compared with Example 2, the core computing unit of this embodiment uses a multiplexer instead of two multipliers, which can greatly reduce the time and resources required in actual operation and improve performance and energy efficiency.

Claims

1. A Montgomery modular multiplication method based on base 2, characterized in that: The specific steps of this method include: S1. Calculate RRN based on the bit length k of the multipliers X and Y, where RRN = 2^2(k+3) mod N, where N is the modulus. Assign the multipliers X and RRN to the calculation numbers A and B, respectively, and perform a Montgomery modular multiplication on the calculation numbers A, B, and the modulus N as follows: S11, expand the bit length of the calculation number A to k+3 and set the two highest bits A[k+2] and A[k+1] of A to 0, expand the bit length of the calculation number B to k+2, shift it left by one bit and set the lowest bit B[0] of B to 0, then assign the lowest bit S[0] of the Montgomery modular multiplication calculation result S obtained in the previous loop to the intermediate coefficient q, and then use a judgment statement to realize the summation of the product of the lowest bit A[0] of the calculation number A and the calculation number B and the product of the intermediate coefficient q and the modulus N, and sum the above summation result with the Montgomery modular multiplication calculation result S and shift it right by one bit to obtain the updated value of S; wherein, the initial value of the calculation result S participating in the operation in the first loop is 0; S12, repeat step S11 k+3 times, each time replacing the lowest bit A[0] with the i-th bit A[i] of the calculated number A, and incrementing the value of i by 1 after the calculation. The loop ends when the value of i equals k+2. The calculation result S is updated to the intermediate calculation result mid_S and used as X', where X' is the value of the multiplier X in the Montgomery field. S2, assign the multiplier Y and RRN to the calculation numbers A and B respectively and repeat step S1 to obtain Y', where Y' is the value of the multiplier Y in the Montgomery domain; S3, assign X' and Y' to the calculation numbers A and B respectively and repeat step S1 to obtain Z', where Z' is the value of the final result Z of the modular multiplication of the multipliers X and Y with N as the modulus in the Montgomery field; S4, assign Z' and 1 to the calculated numbers A and B respectively and repeat step S1 to obtain the final result Z.

2. The Montgomery modular multiplication method based on base 2 according to claim 1, wherein: In step S11, since the i-th bit A[i] of the calculated number A and the intermediate coefficient q are both 1-bit numbers, the two are first spliced ​​into a 2-bit number and then judged. If the spliced ​​number is 00, S is updated to S; if it is 01, S is updated to S+N; if it is 10, S is updated to S+B; if it is 11, S is updated to S+B+N.

3. A device for implementing Montgomery modular multiplication based on base 2, for implementing the method according to claim 1 or 2, characterized in that: include: The top-level control unit is configured to receive input data and data from the core computing unit, and select a calculation number and a modulus to be subjected to Montgomery modular multiplication according to a current state of a state machine of the top-level control unit and a signal input from the core computing unit; The data distribution unit is used to receive the calculation number and modulus transmitted by the top-level control unit, and transmit the calculation number A bit by bit from low to high to the core calculation unit, and transmit the calculation number B and modulus N to the core calculation unit at the same time; The core computing unit is used to receive data transmitted by the data distribution unit, with its input end connected to the output end of the data distribution unit, and is used to calculate new intermediate calculation results and transmit them to the top-level control unit.

4. The device for implementing Montgomery modular multiplication based on base 2 according to claim 3, wherein: The top-level control unit includes a state machine structure with four states, wherein the four states are: converting the multiplier X into the Montgomery domain, converting the multiplier Y into the Montgomery domain, performing calculations in the Montgomery domain, and converting Z' from the Montgomery domain into the final result Z, where Z' is the value of the final result Z in the Montgomery domain; the input end of the top-level control unit inputs the multipliers X, Y and modulus N, a calculation completion signal and an intermediate calculation result mid_S, and the output end outputs the Montgomery calculation numbers A, B and modulus N to the data distribution unit, and outputs the final result Z and the final result valid signal Z_done to the outside; when the top-level control unit traverses the above four states, the modular multiplication operation on the input data X, Y, and N is completed to obtain the final result Z.

5. The device for implementing Montgomery modular multiplication based on base 2 according to claim 3, wherein: The data distribution unit is used to transmit the calculation number A bit by bit from low to high to the core computing unit, and at the same time transmit the calculation number B and modulus N to the core computing unit; when the highest bit of the calculation number A is transmitted, the data distribution unit transmits a data distribution completion signal to the core computing unit; the input end of the data distribution unit inputs the Montgomery calculation number A, B and modulus N output by the top-level control unit, and its output end outputs a certain bit of the Montgomery calculation number A, the calculation number B, the modulus N and the data distribution completion signal dis_done.

6. The device for implementing Montgomery modular multiplication based on base 2 according to claim 3, characterized in that: The core computing unit includes a multiplexer, two adders and a shift register; the output end of the core computing unit outputs the intermediate computing result mid_S and the computing completion signal Z_done to the top-level control unit.

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