Array substrate and display panel
By setting an auxiliary electrode layer on the array substrate and opening holes at key locations, the short circuit problem of the electrode layer was solved, improving the yield and transmittance of the display panel and ensuring the accuracy of the repair.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU CHINA STAR OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2022-07-21
- Publication Date
- 2026-05-22
AI Technical Summary
In the prior art, short circuits are prone to occur between the pixel electrodes and source/drain electrodes, transparent ITO electrodes and gate of the display panel, resulting in yield loss. Furthermore, it is difficult to determine the position defects during laser repair, which can easily cause misalignment.
An auxiliary electrode layer is set on the array substrate, and openings are set at the positions of the corresponding pixel electrode, source/drain electrode and gate to avoid short circuits between electrode layers. At the same time, alignment marks are used to assist in repair and ensure repair accuracy.
This effectively avoids short circuits between electrode layers, improves the yield of display panels, and enhances display performance by increasing transmittance through auxiliary electrode layers.
Smart Images
Figure CN115274698B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology
[0002] Currently, display panel resolutions are increasing while pixel units are becoming smaller. Due to limitations in exposure equipment capabilities, linewidth and channel size cannot be further reduced, leading to decreased light transmittance. Typically, a transparent ITO electrode is introduced between the color resist and the organic film to replace the traditional metal common electrode. However, during laser repair of defective points / lines in the pixel electrode and subsequent processes, short circuits frequently occur between the pixel electrode and the source / drain electrodes, the transparent ITO electrode, and the gate electrode, resulting in yield loss. Furthermore, the laser repair points are difficult to determine, causing problems such as misalignment during repair.
[0003] Therefore, improvements are urgently needed to address the shortcomings of existing technologies. Summary of the Invention
[0004] The purpose of this application is to provide a display panel and display device that can solve the problem in the prior art where short circuits occur between the pixel electrode and the source / drain electrode, the transparent ITO electrode and the gate, respectively, resulting in yield loss.
[0005] This application provides an array substrate having multiple pixel units, including: a substrate; an auxiliary electrode layer disposed on one side of the substrate; and a pixel electrode disposed on the side of the auxiliary electrode layer away from the substrate and electrically connected to the auxiliary electrode layer; wherein the auxiliary electrode layer has a first opening at the position corresponding to the pixel electrode.
[0006] Optionally, in some embodiments of this application, the array substrate further includes: a source / drain electrode disposed on the side of the auxiliary electrode layer near the substrate and electrically connected to the pixel electrode; wherein the auxiliary electrode layer has a second opening at the position corresponding to the source / drain electrode.
[0007] Optionally, in some embodiments of this application, the array substrate further includes: a gate, disposed on the substrate and located on the side of the source / drain electrode close to the substrate; wherein the auxiliary electrode layer has a third opening at the position corresponding to the gate.
[0008] Optionally, in some embodiments of this application, the array substrate further includes: a common electrode disposed on the same layer as the gate electrode; a gate insulating layer disposed on the side of the gate electrode facing away from the substrate and covering the gate electrode; an active layer disposed between the gate insulating layer and the source / drain electrode and electrically connected to the source / drain electrode; an interlayer insulating layer disposed on the side of the source / drain electrode facing away from the active layer; a color resist layer disposed between the interlayer insulating layer and the auxiliary electrode layer; and a planarization layer disposed on the side of the auxiliary electrode layer facing away from the color resist layer; wherein the common electrode is electrically connected to the pixel electrode.
[0009] Optionally, in some embodiments of this application, the pixel electrode is electrically connected to the source / drain electrode through a first via, the pixel electrode is electrically connected to the auxiliary electrode layer through a second via, and the pixel electrode is electrically connected to the common electrode through a third via; wherein the first via sequentially penetrates the planarization layer, the color resist layer, and the interlayer insulating layer; the second via penetrates the planarization layer; and the third via sequentially penetrates the planarization layer, the color resist layer, the interlayer insulating layer, and the gate insulating layer.
[0010] Optionally, in some embodiments of this application, the array substrate further includes: an alignment mark, which is disposed on the same layer as the pixel electrode and corresponds to the first opening.
[0011] Optionally, in some embodiments of this application, the alignment mark is the same as the pixel electrode material.
[0012] Optionally, in some embodiments of this application, any pixel unit includes at least one sub-pixel unit, and the alignment mark is disposed between two adjacent sub-pixel units.
[0013] Optionally, in some embodiments of this application, the auxiliary electrode is a transparent electrode.
[0014] Accordingly, this application also provides a display panel, including an opposing substrate and an array substrate disposed opposite to the opposing substrate; wherein the array substrate is the array substrate described in any of the above embodiments.
[0015] Compared to existing technologies, the array substrate described in this application has multiple pixel units, including: a substrate, a gate disposed on one side of the substrate, a source / drain electrode disposed on the side of the gate facing away from the substrate, an auxiliary electrode layer disposed on the side of the source / drain electrode facing away from the gate, and a pixel electrode disposed on the side of the auxiliary electrode layer facing away from the source / drain electrode. The pixel electrode is electrically connected to the source / drain electrode and the auxiliary electrode layer, respectively. The auxiliary electrode layer has a first opening corresponding to the pixel electrode. When the array substrate has a faulty dot and needs repair, since the auxiliary electrode layer is not present at the pixel electrode position, a short circuit between the pixel electrode and the auxiliary electrode layer is avoided. Preferably, the auxiliary electrode layer has a second opening corresponding to the source / drain electrode position and a third opening corresponding to the gate position. When a faulty point on the array substrate requires repair, since the source / drain electrodes do not have the corresponding auxiliary electrode layer, a short circuit between the source / drain electrodes and the auxiliary electrode layer is avoided. Similarly, when a faulty point on the array substrate requires repair, since the gate electrode does not have the corresponding auxiliary electrode layer, a short circuit between the gate electrode and the auxiliary electrode layer is avoided.
[0016] Furthermore, the array substrate also includes alignment marks, which are disposed on the same layer as the pixel electrode and correspond to the first opening. The alignment marks allow the position of the first opening to be directly determined from one side of the pixel electrode, thereby enabling repair at the location of the first opening and reducing repair point errors during repair. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic cross-sectional view of the array substrate described in the embodiments of this application;
[0019] Figure 2 This is a planar schematic diagram of a portion of the structure of the array substrate described in the embodiments of this application. Figure 1 ;
[0020] Figure 3 This is a planar schematic diagram of a portion of the structure of the array substrate described in the embodiments of this application. Figure 2 ;
[0021] Figure 4 This is a planar schematic diagram of a portion of the structure of the array substrate described in the embodiments of this application. Figure 3 ;
[0022] Figure 5 This is a planar schematic diagram of a portion of the structure of the array substrate described in the embodiments of this application. Figure 4 ;
[0023] Figure 6 This is a planar schematic diagram of a portion of the structure of the array substrate described in the embodiments of this application. Figure 5 ;
[0024] Figure 7 This is a cross-sectional structural diagram of the display panel described in the embodiment of this application. Detailed Implementation
[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0026] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0027] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; or they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0029] Specifically, please refer to Figures 1 to 3 This application provides an array substrate 10, including a substrate 101, a gate 102, a common electrode 103, a gate insulating layer 104, an active layer 105, source / drain electrodes 106, an interlayer insulating layer 107, a color resist layer 108, an auxiliary electrode layer 109, a planarization layer 1010, and a pixel electrode 1011. The gate 102 is disposed on one side of the substrate 101. The common electrode 103 is disposed on one side of the substrate 101 and is disposed in the same layer as the gate 102. The gate insulating layer 104 is disposed on the side of the gate 102 away from the substrate 101 and covers the gate 102. The active layer 105 is disposed on the side of the gate insulating layer 104 away from the gate 102. The source / drain electrodes 106 are disposed on the side of the gate 102 away from the gate insulating layer. One side of 104 is electrically connected to the active layer 105. The interlayer insulating layer 107 is disposed on the side of the source / drain electrode 106 away from the active layer 105. The color resist layer 108 is disposed on the side of the interlayer insulating layer 107 away from the source / drain electrode 106. The auxiliary electrode layer 109 is disposed on the side of the color resist layer 108 away from the interlayer insulating layer 107. The planarization layer 1010 is disposed on the side of the auxiliary electrode layer 109 away from the color resist layer 108. The pixel electrode 1011 is disposed on the side of the auxiliary electrode layer 109 away from the planarization layer 1010 and is electrically connected to the common electrode 103, the source / drain electrode 106, and the auxiliary electrode layer 109, respectively. The auxiliary electrode layer 109 has a first opening 1091 at the position corresponding to the pixel electrode 1011. When the array substrate 10 has a faulty point that needs to be repaired, laser repair is usually used. During the laser repair process, two adjacent electrode layers may be connected together due to metal melting, resulting in a short circuit. The auxiliary electrode layer 109 of this application has a first opening 1091 at the position corresponding to the pixel electrode 1011. When the array substrate 10 has a faulty point that needs to be repaired, since there is no auxiliary electrode layer 109 at the position corresponding to the pixel electrode 1011, a short circuit between the pixel electrode 1011 and the auxiliary electrode layer 109 is avoided.
[0030] like Figure 3 As shown, it can be understood that the auxiliary electrode layer 109 is provided with a first opening 1091 at the position corresponding to the pixel electrode 1011. That is, the first opening 1091 is located in the orthogonal projection area of the auxiliary electrode layer 109 on the pixel electrode 1011.
[0031] In this application, the pixel electrode 1011 is electrically connected to the source / drain electrode 106 through a first via 1012, the pixel electrode 1011 is electrically connected to the auxiliary electrode layer 109 through a second via 1013, and the pixel electrode 1011 is electrically connected to the common electrode 103 through a third via 1014. The first via 1012 sequentially penetrates the planarization layer 1010, the color resist layer 108, and the interlayer insulating layer 107; the second via penetrates the planarization layer 1010; and the third via 1014 sequentially penetrates the planarization layer 1010, the color resist layer 108, the interlayer insulating layer 107, and the gate insulating layer 104. The auxiliary electrode layer 109 is a transparent electrode layer. The auxiliary electrode layer 109 can replace part of the function of the common electrode 103, thereby reducing the area of the metal electrodes in the array substrate 10, increasing the transmittance of the array substrate 10, increasing the pixel aperture ratio, and improving the display effect.
[0032] like Figure 4 As shown, in one embodiment, the auxiliary electrode layer 109 has a second opening 1092 corresponding to the position of the source / drain electrode 106. That is, the second opening 1092 is located within the orthogonal projection area of the auxiliary electrode layer 109 on the source / drain electrode 106. When the array substrate 10 has a faulty point that needs to be repaired, since the auxiliary electrode layer 109 is not present at the position corresponding to the source / drain electrode 106, a short circuit between the source / drain electrode 106 and the auxiliary electrode layer 109 is avoided.
[0033] like Figure 5 As shown, in one embodiment, the auxiliary electrode layer 109 has a third opening 1093 at the position corresponding to the gate 102. That is, the third opening 1093 is located within the orthogonal projection area of the auxiliary electrode layer 109 on the gate 102. When the array substrate 10 has a faulty point that needs to be repaired, since the auxiliary electrode layer 109 is not present at the position corresponding to the gate 102, a short circuit between the gate 102 and the auxiliary electrode layer 109 is avoided. It can be understood that the third opening 1093 can partially overlap with the second opening 1092, that is, the third opening 1093 and the second opening 1092 can together form an irregularly shaped hole.
[0034] It is understood that the auxiliary electrode layer 109 covers the surface of the color resist layer 108, but a first opening 1091 is provided at the position corresponding to the pixel electrode 1011, a second opening 1092 is provided at the position corresponding to the source / drain electrode 106, and a third opening 1093 is provided at the position corresponding to the gate 102.
[0035] like Figure 6 As shown, in one embodiment, the array substrate 10 further includes an alignment mark 1015, which is disposed on the same layer as the pixel electrode 1011 and corresponds to the first opening 1091. The alignment mark 1015 is made of the same material as the pixel electrode 1011. The alignment mark 1015 and the pixel electrode 1011 are disposed on the same film layer, thereby enabling the simultaneous fabrication of the alignment mark 1015 and the pixel electrode 1011, and allowing control over the distance between the alignment mark 1015 and adjacent pixel electrodes 1011 during the fabrication of the pixel electrode 1011 film layer. It is understood that the alignment mark 1015 is actually fabricated simultaneously with the pixel electrode 1011. Since the first opening 1091 on the auxiliary electrode layer 109 is covered by the pixel electrode 1011 after the pixel electrode 1011 is fabricated, the position of the first opening 1091 cannot be quickly determined when the array substrate 10 has a faulty dot pattern that needs to be repaired. The alignment mark 1015 allows the position of the first opening 1091 to be directly determined on one side of the pixel electrode 1011, thereby enabling repair at the position of the first opening 1091. Furthermore, the alignment mark 1015 can also be set corresponding to the second opening 1092 and / or the third opening 1093 to facilitate determining the positions of the second opening 1092 and / or the third opening 1093.
[0036] In one embodiment, any pixel unit includes at least one sub-pixel unit, and the alignment mark 1015 is disposed between two adjacent sub-pixel units. That is, the alignment mark 1015 is located outside the aperture area of the sub-pixel unit and does not affect the size of the aperture area of the sub-pixel unit. Preferably, the length L of the alignment mark 1015 is the same as the width D of the first aperture.
[0037] In this application, the material of the gate insulating layer 104 or the interlayer insulating layer 107 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride. The materials of the other films in this application can be conventional materials in the art, and will not be described further here.
[0038] like Figure 7 As shown, this application also provides a display panel 1, including a counter substrate 20 and an array substrate 10 disposed opposite to the counter substrate 20. The specific structure of the array substrate 10 is described in the previous embodiment.
[0039] The display panel 1 described in this application can be applied to any display device, including, but not limited to, wearable smart bracelets, smartwatches, VR devices, mobile phones, e-books, e-newspapers, televisions, personal portable computers, etc.
[0040] In summary, the array substrate 10 described in this application has multiple pixel units, including: a substrate 101, a gate 102 disposed on one side of the substrate 101, a source / drain electrode 106 disposed on the side of the gate 102 away from the substrate 101, an auxiliary electrode layer 109 disposed on the side of the source / drain electrode 106 away from the gate 102, and a pixel electrode 1011 disposed on the side of the auxiliary electrode layer 109 away from the source / drain electrode 106. The pixel electrode 1011 is electrically connected to the source / drain electrode 106 and the auxiliary electrode layer 109, respectively. The auxiliary electrode layer 109 has a first opening 1091 at the position corresponding to the pixel electrode 1011. When the array substrate 10 has a faulty pixel that needs repair, since the auxiliary electrode layer 109 is not present at the position corresponding to the pixel electrode 1011, a short circuit between the pixel electrode 1011 and the auxiliary electrode layer 109 is avoided. Preferably, the auxiliary electrode layer has a second opening 1092 corresponding to the position of the source / drain electrode 106, and a third opening 1093 corresponding to the position of the gate electrode 102. When the array substrate 10 has a faulty connection and needs repair, since the auxiliary electrode layer 109 is not present at the position corresponding to the source / drain electrode 106, a short circuit between the source / drain electrode 106 and the auxiliary electrode layer 109 is avoided. When the array substrate 10 has a faulty connection and needs repair, since the auxiliary electrode layer 109 is not present at the position corresponding to the gate electrode 102, a short circuit between the gate electrode 102 and the auxiliary electrode layer 109 is avoided.
[0041] Furthermore, the array substrate 10 also includes an alignment mark 1015, which is disposed on the same layer as the pixel electrode 1011 and corresponds to the first opening 1091. The alignment mark 1015 allows the position of the first opening 1091 to be directly determined on one side of the pixel electrode 1011, thereby enabling repair at the position of the first opening 1091 and reducing repair point errors during repair.
[0042] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0043] The above provides a detailed description of an array substrate 10 and a display panel 1 provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. An array substrate having multiple pixel units, characterized in that, include: Substrate; An auxiliary electrode layer is disposed on one side of the substrate. as well as Pixel electrodes and alignment marks are arranged at intervals in the same layer and are made of the same material. The pixel electrodes are disposed on the side of the auxiliary electrode layer away from the substrate. The portion of the pixel electrode above the auxiliary electrode layer is separated to form a first part of the pixel electrode and a second part of the pixel electrode. The first part of the pixel electrode is electrically connected to the auxiliary electrode layer. The source / drain electrode is disposed on the side of the auxiliary electrode layer near the substrate and is electrically connected to the second part of the pixel electrode; A common electrode is electrically connected to the first portion of the pixel electrode; wherein... The auxiliary electrode layer has a first opening at the position corresponding to the pixel electrode, the alignment mark corresponds to the first opening, and the length of the alignment mark is the same as the width of the first opening; Each of the pixel units includes at least one sub-pixel unit, and the alignment mark is disposed between two adjacent sub-pixel units.
2. The array substrate as described in claim 1, characterized in that, The auxiliary electrode layer has a second opening at the position corresponding to the source / drain electrode.
3. The array substrate as described in claim 2, characterized in that, The array substrate further includes: A gate electrode is disposed on the substrate and located on the side of the source / drain electrode closest to the substrate; wherein... The auxiliary electrode layer has a third opening at the position corresponding to the gate.
4. The array substrate as described in claim 3, characterized in that, The array substrate further includes: The common electrode is disposed in the same layer as the gate electrode; A gate insulating layer is disposed on the side of the gate away from the substrate and covers the gate; An active layer is disposed between the gate insulating layer and the source / drain electrodes, and is electrically connected to the source / drain electrodes; An interlayer insulating layer is disposed on the side of the source / drain electrode opposite to the active layer; A color resist layer is disposed between the interlayer insulating layer and the auxiliary electrode layer; and A planarization layer is disposed on the side of the auxiliary electrode layer opposite to the color resist layer.
5. The array substrate as described in claim 4, characterized in that, The second part of the pixel electrode is electrically connected to the source / drain electrode through the first via, the first part of the pixel electrode is electrically connected to the auxiliary electrode layer through the second via, and the first part of the pixel electrode is electrically connected to the common electrode through the third via. in The first via sequentially penetrates the planarization layer, the color resist layer, and the interlayer insulating layer; the second via penetrates the planarization layer; and the third via sequentially penetrates the planarization layer, the color resist layer, the interlayer insulating layer, and the gate insulating layer.
6. The array substrate as claimed in claim 1, characterized in that, The auxiliary electrode is a transparent electrode.
7. A display panel, characterized in that, It includes a counter substrate and an array substrate disposed opposite to the counter substrate; wherein The array substrate is the array substrate according to any one of claims 1 to 6.