Interference Mitigation in High-Speed ​​Ethernet Communication Networks

Abstract

Data symbols in an input signal are detected by a slicer of a DFE of a transceiver device. An output of a feedback filter of the DFE is generated during a particular clock cycle based on a first group of one or more data symbols detected during a first one or more previous clock cycles and a second group of one or more data symbols detected during a second one or more previous clock cycles. The second group is separated from the first group by a third group of one or more data symbols detected during a third one or more clock cycles that occurs after the first one or more clock cycles and before the second one or more clock cycles, wherein the output is generated without using the third group of symbols. The output is subtracted from the input signal to generate an equalized input to the slicer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 959,666, filed on January 10, 2020, and entitled “Digital Signal Processor (DSP) Electromagnetic Interference (EMI) Mitigation on High Speed ​​Automotive PHYs,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to Ethernet communication systems, and more particularly to mitigating interference in high-speed Ethernet communication systems. Background Art

[0004] Modern vehicles such as advanced in-vehicles often use Ethernet technology to connect components through a wired physical network within the vehicle. In-vehicle Ethernet networks have been evolving to increase the transmission speeds supported by the network. For example, the "100Base-T1" Ethernet specified by the Institute of Electrical and Electronics Engineers (IEEE) 802.3bw standard supports a transmission speed of 100 megabits per second (Mbps), and the "1000Base-T1" Ethernet specified by the IEEE 802.3bp standard supports a transmission speed of 1 gigabit per second (1Gbps). The updated IEEE802.3ch Base-T1 standard supports 2.5Gbps, 5Gbps, and 10G Gbps transmission speeds. In addition, other alliances such as the Mobile Industry Processor Interface (MIPI) Alliance and the Automotive SerDes Alliance are currently developing in-vehicle Ethernet solutions that will support transmission speeds of up to 16Gbps.

[0005] Automotive Ethernet applications face stringent requirements to ensure safe operation in the multiple environments commonly found in automotive applications. One important requirement in automotive applications is electromagnetic compatibility (EMC), or the ability of devices and systems to operate in their electromagnetic environment without compromising their functionality and without malfunctioning. For example, Ethernet networks in vehicles need to operate properly in the presence of strong electromagnetic interference (EMI), such as in the presence of cellular phone signals, lightning, and electromagnetic discharge (ESD) events. However, as the transmission speeds supported by in-vehicle networks continue to increase, meeting such stringent requirements has become difficult. For example, although decision feedback equalizers (DFEs) can be used to mitigate electromagnetic interference in receiver devices, current DFE designs cannot support the increasing transmission speeds of in-vehicle networks. Summary of the invention

[0006] In one embodiment, a transceiver device for use in an in-vehicle Ethernet network. The transceiver device includes: an equalizer configured to mitigate interference in an input signal received by the transceiver device, the equalizer including a decision feedback equalizer (DFE), the decision feedback equalizer including a limiter and a feedback filter, the limiter configured to detect data symbols in the input signal, the feedback filter configured to generate a filter output during a specific clock cycle based on i) a first group of one or more data symbols detected by the limiter during a first one or more previous clock cycles and ii) a second group of one or more data symbols detected by the limiter during a second one or more second previous clock cycles, wherein the second group of one or more data symbols is separated from the first group of one or more data symbols by a third group of one or more data symbols detected by the limiter during a third one or more clock cycles, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, and the feedback filter output is generated in the specific clock cycle without using the third group of one or more data symbols; and a summing junction configured to subtract the filter output from the input signal to generate an equalized input to the limiter.

[0007] In another embodiment, a method for mitigating interference in a signal received by a transceiver device in an in-vehicle Ethernet network. The method includes: receiving an input signal at an equalizer of the transceiver device, the equalizer including a decision feedback equalizer (DFE); detecting data symbols in the input signal using a limiter of the DFE; generating a filter output at a feedback filter of the DFE, the filter output being generated during a particular clock cycle based on i) a first set of one or more data symbols detected by the limiter during a first one or more previous clock cycles and ii) a second set of one or more data symbols detected by the limiter during a second one or more previous clock cycles, wherein the second set of one or more data symbols is separated from the first set of one or more data symbols by a third set of one or more data symbols detected by the limiter during a third one or more clock cycles, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, the feedback filter output being generated in the particular clock cycle without using the third set of one or more data symbols; and subtracting the filter output from the input signal to generate an equalized input to the limiter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an example communication system in which communication devices implement the high-speed interference mitigation techniques of the present disclosure, according to one embodiment.

[0009] Figure 2According to one embodiment Figure 1 A block diagram of an example transceiver device for use with a communication device in a communication system.

[0010] Figure 3 According to one embodiment Figure 2 A block diagram of an example equalizer utilized in conjunction with a transceiver device.

[0011] Figure 4 According to one embodiment Figure 3 Block diagram of an example decision feedback equalizer (DFE) utilized together with an equalizer.

[0012] Figure 5 According to one embodiment Figure 4 A block diagram of an example finite impulse response (FIR) filter utilized together with a DFE.

[0013] Figure 6A-6B According to the embodiment Figure 4 A diagram of example DFE coefficients utilized together with the DFE.

[0014] Figure 7 is a flow chart of an example method for mitigating interference in signals received by a transceiver device in an in-vehicle Ethernet network, according to one embodiment. DETAILED DESCRIPTION

[0015] In the embodiments described below, a decision feedback equalizer (DFE) supports operations (e.g., filtering and channel equalization) in high-speed networks, such as, for example, multi-gigabit Ethernet in-vehicle networks. In one embodiment, the DFE is used in conjunction with a feed-forward equalizer (FFE) to mitigate interference from a received signal propagating through a communication channel. As explained in more detail below, in one embodiment, the FFE / DFE combination detects the presence of narrowband interference in the received signal. In response to detecting interference, the FFE adapts its filter coefficients to generate a notch filter to remove the detected interference from the signal. In addition, the DFE adapts its coefficients to offset the effects of the notch filter generated by the FFE so that the equalizer can accurately detect the transmitted symbols based on the received signal.

[0016] Typically, a DFE includes a limiter and a feedback filter. The limiter is configured to identify a transmit symbol based on a sample of a received signal. The feedback filter calculates a filter output using a previous decision made by the limiter (e.g., during a previous clock cycle) to be applied to an input signal presented to the DFE during a current clock cycle. The feedback filter includes a plurality of filter taps, each corresponding to a specific previously detected symbol, and the feedback filter is used to calculate a weighted contribution based on a specific previously detected symbol. Current DFEs are generally not able to operate at high speeds (e.g., speeds greater than 1 GHz) because current high-speed DFE designs cannot sufficiently close the timing within a single clock cycle to feed back the symbol detected in the previous clock cycle to the feedback filter and perform the calculations required for the feedback filter to generate the filter output for the current clock cycle. With current DFEs, digital logic / data paths of up to approximately 1 GHz are possible. Some such current DFEs utilize parallel DFE paths combined with "lookahead / unrolling" of one or more filter taps to achieve operation at higher (e.g., 1 GHz) speeds. However, such current DFEs are unable to handle multi-GHz symbol baud rates of transceiver devices, such as the 5.625 GHz used in 10GBASE-T1 Ethernet. Furthermore, with current DFEs, the hardware complexity of the "look-ahead / unrolling" implementation grows exponentially with higher modulation orders (e.g., PAM4 modulation used in 10GBASE-T1 Ethernet), especially in systems utilizing multiple parallel DFE paths, making such implementation impossible or cost-prohibitive (e.g., in terms of silicon area, power consumption, chip cost, etc.).

[0017] In order to enable the DFE to operate at a sufficiently high speed, in the embodiments described below, a set of one or more filter taps of the feedback filter of the DFE are not implemented as conventional filter taps. For example, one or more filter taps are effectively forced to be "zero" filter taps so that the set of one or more filter taps are not used to generate a filter output during the current clock cycle. Thus, in one embodiment, during a particular clock cycle, the feedback filter generates a filter output based on i) a first set of one or more data symbols detected by a limiter during a first one or more previous clock cycles and ii) a second set of one or more data symbols detected by the limiter during a second one or more previous clock cycles. In one embodiment, the second set of one or more data symbols is separated from the first set of one or more data symbols by a third set of one or more data symbols detected by the limiter during a third one or more clock cycles, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, and the feedback filter output is generated in the particular clock cycle without using the third set of one or more data symbols. As explained in more detail below, this “zeroing” of the filter taps relaxes the timing constraints on subsequent filter taps used in generating the filter output during the current clock cycle, thereby allowing the DFE to support operation at higher speeds than is possible in a traditional DFE where all filter taps are implemented and used to generate the filter output during the current clock cycle.

[0018] Figure 1is a block diagram of an example system 100 according to one embodiment, wherein a transceiver device utilizes a DFE in which a set of filter taps are effectively set to zero to enable the DFE to operate at high speeds, such as greater than 1 GHz speeds. The system 100 includes a first network interface device 102 coupled to a second network interface device 104 via a network link 106. In one embodiment, the first network interface device 102 and the second network interface device 104 are associated with electronic devices of an in-vehicle network system. By way of example only, in one embodiment, the first network interface device 102 is associated with an accessory device such as a camera or a telematics radio device in a car, and the second network interface device 104 is associated with a central processing unit in the car. In other embodiments, the first network interface device 102 and / or the second network interface device 104 are associated with other suitable electronic devices in the car, such as infotainment devices, sensor devices, control devices, etc. in the car. In one embodiment, the network link 106 between the network interface device 102 and the network interface device 104 comprises a single twisted pair copper link. In another embodiment, the network link 106 is a suitable link other than a single twisted pair copper link. For example, in various embodiments, the network link 106 is a plurality of pairs of copper links, optical links, fiber links, radio frequency plastic waveguide links, etc. In some embodiments, the first network interface device 102 and the second network interface device 104 are utilized in a network other than an in-vehicle network. For example, in some embodiments, the first network interface device 102 and the second network interface device 104 are utilized in an industrial or process industry network.

[0019] The network interface device 102 includes one or more physical layer (PHY) processors 130 (sometimes referred to herein as “PHY processors 130” for brevity). The PHY processor 130 includes a transceiver 180 configured to transmit and receive signals over the link 106. In one embodiment, the network interface device 102 also includes one or more media access control (MAC) processors 132 (sometimes referred to herein as “MAC processors 132” for brevity) coupled to the PHY processor 130. In another embodiment, the network interface device 102 omits the MAC processor 132. For example, in one embodiment, the MAC processor 132 is external to the network interface device 102.

[0020] The network interface device 102 is implemented using one or more integrated circuits (ICs) configured to operate as described below. For example, the PHY processor 130 may be implemented at least in part on a first IC, and the MAC processor 132 may be implemented at least in part on a second IC. As another example, at least a portion of the PHY processor 130 and at least a portion of the MAC processor 132 may be implemented on a single IC. For example, the network interface device 102 may be implemented using a system on chip (SoC), wherein the SoC includes at least a portion of the PHY processor 130 and at least a portion of the MAC processor 132.

[0021] In one embodiment, the transceiver 180 of the PHY processor 130 includes an equalizer 182. The equalizer 182 includes a decision feedback equalizer (DFE) 184. In one embodiment, the equalizer 180 additionally includes a feed forward equalizer (FFE) 186.

[0022] Continue to refer Figure 1 , the network interface device 104 includes one or more physical layer (PHY) processors 150 (sometimes referred to herein as “PHY processors 150” for brevity). The PHY processor 150 includes a transceiver 190 configured to transmit and receive signals over the link 106. In one embodiment, the network interface device 104 also includes one or more media access control (MAC) processors 152 (sometimes referred to herein as “MAC processors 152” for brevity) coupled to the PHY processor 150. In another embodiment, the network interface device 104 omits the MAC processor 152. For example, in one embodiment, the MAC processor 152 is external to the network interface device 104.

[0023] The network interface device 104 is implemented using one or more integrated circuits (ICs) configured to operate as described below. For example, the PHY processor 150 may be implemented at least in part on a first IC, and the MAC processor 152 may be implemented at least in part on a second IC. As another example, at least a portion of the PHY processor 150 and at least a portion of the MAC processor 152 may be implemented on a single IC. For example, the network interface device 104 may be implemented using a system on chip (SoC), wherein the SoC includes at least a portion of the PHY processor 150 and at least a portion of the MAC processor 152.

[0024] In one embodiment, transceiver 190 of PHY processor 150 includes equalizer 192. In one embodiment, equalizer 192 of transceiver 190 is the same as or similar to equalizer 182 of transceiver 180. In one embodiment, equalizer 182 includes a DFE (not shown) that is the same as or similar to DFE 184. In one embodiment, equalizer 182 also includes an FFE that is the same as or similar to FFE 186.

[0025] Still reference Figure 1 In one embodiment, the DFE 184 of the equalizer 182 includes a multi-tap feedback filter (e.g., a finite impulse response (FIR) filter, an infinite impulse response (IIR) filter, or other suitable type of multi-tap filter), wherein respective filter taps of the feedback filter correspond to symbols detected during a plurality of previous clock cycles. In order to enable the DFE 184 to operate at a sufficiently high speed, a set of one or more filter taps of the multi-tap filter corresponding to symbols detected during a more recent clock cycle are intentionally not implemented as “filter taps”, or are in fact forced to be “zero” filter taps, such that ultimately the set of one or more filter taps are not used to generate a filter output during a current clock cycle. Thus, in one embodiment, during a particular clock cycle, the feedback filter generates a filter output based on i) a first set of one or more data symbols detected by a slicer during a first one or more previous clock cycles and ii) a second set of one or more data symbols detected by the slicer during a second one or more previous clock cycles, wherein the second set of one or more data symbols are separated from the first set of one or more data symbols by a third set of one or more data symbols detected by the slicer during a third one or more clock cycles, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, the feedback filter output being generated in the particular clock cycle without using the third set of one or more data symbols. This effective zeroing of the filter taps relaxes timing constraints on subsequent filter taps used in generating the filter output in the current clock cycle, thereby allowing the DFE to support higher speeds than is possible in a conventional DFE in which all filter taps are used to generate the filter output during the current clock cycle.

[0026] Figure 2 is a block diagram of an example transceiver device 200 according to one embodiment. According to one embodiment, the transceiver 200 and Figure 1 The first network interface device 102 and / or the second network interface device 104 of the system 100 are utilized together. For example, in one embodiment, the transceiver device 200 is used together with the first network interface device 102 and / or the second network interface device 104 of the system 100. Figure 1For ease of explanation, reference is made to each of the transceivers 180 and / or 190. Figure 1 The transceiver device 200 is described with reference to the network interface devices 102, 104 of the system 100. In other embodiments, the transceiver device 200 is used in conjunction with a network interface device 102, 104 different from the network interface device 102 of the system 100. Figure 1 The network interface devices 102, 104 of the system 100 are used and / or utilized in conjunction with Figure 1 of systems 100 different systems.

[0027] The transceiver 200 includes a transmitter 202, a receiver 204, and an echo canceller 206. The transmitter 202 includes a forward error correction (FEC) physical coding sublayer (PSC) encoder 210, a scrambler 212, a symbol mapper 214, a power spectral density (PSD) filter 216, and a digital-to-analog converter (DAC) 218. For example, the FEC / PSC encoder encodes the data to be transmitted using one or more codes (such as Reed-Solomon codes). The scrambler 212 scrambles the encoded data to generate a scrambled encoded data stream. The symbol mapper 214 maps the bits of the scrambled encoded data stream to modulation symbols using a modulation technique such as two-level power amplitude modulation (PAM2) or four-level power amplitude modulation (PAM4), for example, to generate a modulated signal. The PSD filter filters the modulated signal to appropriately shape the modulated signal for transmission, for example, to ensure that the transmitted signal meets power density and transmission control requirements. DAC 218 converts the signal to an analog signal for transmission via network link 106 .

[0028] The echo canceller 206 receives the output of the symbol mapper 214 and generates an echo cancellation signal. In one embodiment, the receiver 204 utilizes the echo cancellation signal to cancel the echo that may be present in the receiver 204 via the Figure 1 The echo in the signal received by network link 106 is caused by the signal simultaneously transmitted by transmitter 202 via network link 106.

[0029] Receiver 204 includes a hybrid and high pass filter (HPF) 230, a low pass filter (LPF) 232, an analog-to-digital converter (ADC) 234, a combiner 236, an equalizer 237 including an FFE 238 and a DFE 240, and an FEC / PCS decoder 242. Hybrid / HPF 230 applies high pass filtering and hybrid frequency compensation to the received signal. LPF 232 applies low pass filtering to the received signal to attenuate or remove the out-of-band high frequency components of the received signal. ADC 234 converts the filtered received signal into a digital signal. Combiner 236 combines the digital signal with the output of echo canceller 206 and provides the echo-canceled signal to equalizer 237. Equalizer 237 equalizes the signal to reverse the channel effect and remove interference from the signal, and detects the transmitted symbols in the signal. In one embodiment, equalizer 237 is configured to generate a notch filter to mitigate narrowband EMI. For example, when EMI is detected in the signal, the coefficients of FFE 238 are applied to generate a notch at the narrowband interference frequency in the signal. In one embodiment, the coefficients of DFE 240 are then applied to equalize the channel using the notch filter and offset the effect of the notch filter. FEC / PCS decoder 242 demodulates and decodes the signal using one or more codes, such as Reed-Solomon codes.

[0030] The receiver 204 also includes a digital signal processing (DSP) physical medium attachment (PMA) controller 250, an adaptation controller 252, and a digital timing recovery processor 254. The DSP / PMA controller 250 and the adaptation controller 250 control various operational aspects of the receiver 104. The adaptation controller 252 is configured to control the components of the equalizer 237 to quickly adapt the communication channel and remove interference caused by the communication channel. In one embodiment, when EMI is detected in the signal, the adaptation controller 252 controls the equalizer 237 to quickly adapt its coefficients to mitigate narrowband EMI interference. For example, the adaptation controller 252 detects the presence of EMI in the signal based on an error signal received by the adaptation controller from the DFE 240. In one embodiment, the adaptation controller 252 controls the adaptation rate of the coefficients of the FFE 238 and the DFE 240 based on the magnitude of the error. For example, in one embodiment, when the error size increases, this indicates that there is EMI interference in the channel, and the adaptation controller 252 controls the FFE 238 and the DFE 240 to increase the adaptation rate of the coefficients of the FFE 238 and the DFE 240 so that the equalizer 237 adapts quickly to reduce EMI.

[0031] Figure 3 is a block diagram of an example equalizer 300 according to one embodiment. According to one embodiment, the equalizer 300 is Figure 1The first network interface device 102 and / or the second network interface device 104 and / or Figure 2 For example, in one embodiment, the equalizer 300 corresponds to Figure 1 The equalizer 182 and / or Figure 2 In other embodiments, the equalizer 300 is different from the equalizer 237. Figure 1 The network interface devices 102, 104 and / or Figure 2 The transceiver device 200 is utilized together with the device.

[0032] The equalizer 300 includes an FFE 302 and a DFE 304. In one embodiment, the FFE 302 includes a finite impulse response (FIR) filter having a plurality of filter taps 310. In one embodiment, each filter tap 310 is implemented as a delay element 312 and a multiplier 314. Each filter tap 310 utilizes a corresponding coefficient w i In operation, the FFE 302 adjusts the coefficient w i In one embodiment, the FFE is configured to adjust the coefficient w i to generate a notch at the EMI frequency present in the communication channel and mitigate the EMI of the signal received from the communication channel.

[0033] The DFE 304 includes a limiter 324, a feedback filter 328, and a summing junction 330. The limiter 324 is configured to make a symbol decision based on the equalized input signal from the FFE 302. In one embodiment, during each clock cycle of the DFE 304, the limiter 324 makes a symbol decision based on the signal provided to the input of the limiter 324. In one embodiment, the symbol decision made by the limiter 324 is fed back to the feedback filter 328. The feedback filter 328 is configured to generate a filter output based on the symbol fed back from the limiter 324. In one embodiment, the feedback filter 328 includes a plurality of filter taps 329. In one embodiment, the filter taps 329 include a delay element 332 and a multiplier 334. Generally, the delay element 332 stores the decision made by the limiter 324 during a particular previous clock cycle, and the multiplier 334 multiplies the decision stored in the delay element 332 by a corresponding coefficient c. i. In one embodiment, each filter tap 329 operates on a specific previous decision made by the limiter 324. Thus, for example, in one embodiment, the first filter tap 329 operates on a decision made by the limiter 324 during the clock cycle immediately prior to the current clock cycle, the second filter tap 329 having an input coupled to the output of the first filter tap 329 operates on a decision made by the limiter 324 two clock cycles prior to the current clock cycle, the third filter tap 329 having an input coupled to the output of the second filter tap 329 operates on a decision made by the limiter 324 three clock cycles prior to the current clock cycle, and so on. In one embodiment, the feedback filter 328 includes 24 filter taps, the 24 filter taps corresponding to the decisions made by the limiter 324 during 24 consecutive clock cycles prior to the current clock cycle. In another embodiment, the feedback filter 328 includes an appropriate number of filter taps other than 24 filter taps.

[0034] Typically, at high speeds in a conventional DFE, it is difficult to turn off timing on a filter tap corresponding to a decision made by a limiter during one or more of the most recent clock cycles immediately prior to a current clock cycle. For example, at high speeds, a multiplier for a filter tap that operates on a decision made by a limiter during one or more of the most recent clock cycles immediately prior to a current clock cycle may not be stable during the current clock cycle. In other words, it is difficult or impossible to "turn off the timing of the filter tap" at high speeds. In one embodiment, in order to relax the requirements for turning off the timing of the filter tap 329, one or more filter taps 329 of the DFE 304 are "unimplemented" as conventional filter taps. For example, each of such one or more filter taps 329 is implemented to include only a delay element 329, and the multiplier 334 is omitted. Thus, each of such one or more filter taps 329 is effectively and intentionally forced to have a "zero" coefficient c i. As an example, in one embodiment, filter taps 4 through 7 of feedback filter 328 are not implemented as conventional filter taps. Thus, in this embodiment, the values ​​of coefficients c4 through c7 are effectively intentionally set to zero. In another embodiment, another suitable set of filter taps 329 of feedback filter 328 are not implemented as conventional filter taps and no coefficient multiplication is performed. In at least some embodiments, because a set of one or more filter taps 329 are not implemented as conventional filter taps and no coefficient multiplication is performed, the requirements for the timing of closing subsequent filter taps 329 (e.g., filter taps 8 through 24) in DFE 304 are relaxed, allowing DFE 304 to operate efficiently at higher speeds than would be possible in a system that implements all filter taps. These and other techniques for enabling efficient operation of DFE 304 at high speeds are described in more detail below, according to some embodiments.

[0035] Figure 4 is a block diagram of an example DFE 400 according to one embodiment. Figure 1 The first network interface device 102 and / or the second network interface device 104 and / or Figure 2 The transceiver device 200 and / or Figure 3 For example, in one embodiment, the DFE 400 corresponds to Figure 1 DFE 184 and / or Figure 2 DFE 240 and / or Figure 3 In other embodiments, the DFE 400 is different from Figure 1 The network interface devices 102, 104 and / or Figure 2 The transceiver device 200 and / or Figure 3 The equalizer 300 device is utilized together.

[0036] In another embodiment, DFE 400 includes a suitable number of paths other than four parallel paths. In one embodiment, DFE 400 is configured to operate at PAM 4 modulation at 5.625G symbols per second. In other embodiments, DFE 400 is configured to operate at a suitable modulation other than PAM4 modulation and / or at a speed other than 5.625G symbols per second.

[0037] In one embodiment, the DFE 400 includes four parallel paths 410. Thus, in this embodiment, the DFE 400 operates at a clock rate of 1 / 4 the symbol rate. By way of example only, in an embodiment where the symbol rate is 5.625G symbols per second, the DFE 400 operates at 1.40625 GHz. In other embodiments, the DFE 400 includes N parallel paths 410 different from the four parallel paths, and the DFE operates at a clock rate of 1 / N the symbol rate. In the illustrated embodiment, the parallel paths 410 include a first path 410a configured to process a sample x0 of an input signal, a second path 410b configured to process a sample x1, a third path 410c configured to process a sample x3 of an input signal, and a fourth path 410d configured to process a sample x4 of an input signal. In one embodiment, each path 410 includes a corresponding feedback filter 411, a corresponding set of limiters 416, and a corresponding multiplexer 418. Typically, each path 410 is configured to generate a plurality of feedback signals based on the input sample x1. i Generate the i-th symbol decision s i , the input sample x i The previously detected symbol s is either directly equalized (e.g. in the case of a multiplexer selection signal) or mapped to the corresponding data symbol According to one embodiment, path 410a is described in more detail below. In one embodiment, paths 410b through 410d are generally the same as path 410a, and for the sake of brevity, paths 410b through 410d are generally not described below.

[0038] In one embodiment, parallel path 410a includes feedback filter 411, which in turn includes FIR portion 412 and expanded filter tap portion 414. FIR portion 412 implements a set of filter taps associated with corresponding filter coefficients c. For example, in one embodiment, FIR portion 412 implements a set of filter taps associated with corresponding filter coefficients c8 to c 24 17 filter taps are associated with the FIR portion 412, where filter taps c4 through c7 are effectively forced to zero. During each clock cycle, the FIR portion 412 receives four data symbols and generates a FIR filter output based on the four received data symbols and additional previously received data symbols. In the illustrated embodiment, during a particular clock cycle 0, in one embodiment, the FIR portion 412 receives data symbol and where the subscript represents the number of previous clock cycles between the current clock cycle 0 and the clock cycle during which the corresponding symbol decision was made. Thus, for example, the data symbol corresponds to a decision made eight clock cycles prior to the current clock cycle. Thus, because coefficients c4 through c7 are effectively forced to zero, in this embodiment, the "most recent" decision for the calculation performed by FIR portion 412 during the current clock cycle was made eight clock cycles prior to the current clock cycle. Thus, in one embodiment, effectively forcing coefficients c4 through c7 to zero relaxes the constraints imposed by the remaining filter taps c8 through c9. 24 The calculations performed are close to the timing requirements.

[0039] In one embodiment, the expanded filter tap portion 414 includes a first filter tap portion 415 and a third filter tap portion 416 associated with coefficients c1 and c3 of the feedback filter 411, respectively. In one embodiment, the filter tap portion associated with the second coefficient c2 of the feedback filter 411 is not implemented in the feedback filter 411. In other words, in this embodiment, the value of the coefficient c2 is effectively forced to zero. In one embodiment, effectively setting the coefficient c2 to zero allows the expanded filter tap portion 414 to be implemented more efficiently and using less hardware (e.g., less silicon area) than a system in which any expanded filter tap coefficients are intentionally set to zero.

[0040] In one embodiment, the data symbol corresponding to the filter tap c1 is used and the data symbol corresponding to filter tap c3 The expanded filter tap section 414 pre-calculates the equalized output of the feedback filter 411 in parallel branch 417 for all possible combinations of values ​​of and data symbols The value of each of is selected from a set of multiple possible values ​​depending on the particular modulation of the signal being equalized. As an example, in an embodiment utilizing PAM4 modulation, for example, the data symbol and data symbols The value of each of is selected to be two values ​​from a set of four values ​​corresponding to four possible modulation levels, such as {3, -1, 1, 3}. In one embodiment, data symbols are selected for different branches in parallel branches 417. , By i) a) the input signal x at the input of the DFE i The samples and b) the output y of the FIR part i and ii) performed in the corresponding branch 417 of the expanded filter tap portion 414 The results of the feedback filter 411 are added to generate the corresponding equalized output in the parallel branch 417. In one embodiment, the corresponding equalized output of the feedback filter 411 is provided to the corresponding limiter 430. Therefore, in one embodiment, the limiter 430 is based on the limiter input The corresponding slicer 430 outputs the corresponding data symbol decision, which is provided as an input to the multiplexer 418. Then, in one embodiment, when the detected symbol s -1 and -3 Corresponding data symbols and When actual decisions are available, they are used as control signals to multiplexer 418 to select the appropriate output of feedback filter 411.

[0041] Continue to refer Figure 4 , in a particular clock cycle, the DFE 400 generates a corresponding symbol decision d in the corresponding parallel path 410. Therefore, in the illustrated embodiment, the DFE 400 generates four symbol decisions d in a particular clock cycle. In an embodiment utilizing PAM4 modulation, the i-th symbol decision with possible values ​​{3, -1, 1, 3} is mapped according to and is mapped to the non-negative symbol s i Therefore, in this embodiment, the symbol s i has a non-negative value in the value set {0,1,2,3}. In other embodiments, other suitable mappings are used to convert Mapping to non-negative s i In one embodiment, the limiter 416 is based on the following, based on the limiter input To generate symbolic decisions:

[0042]

[0043] In other embodiments, the decision is generated in other suitable manners.

[0044] Still reference Figure 4 In one embodiment, the DFE 400 is configured (or an adaptation controller, such as the adaptation controller 252 is configured) to adapt the filter tap coefficients c based on the limiter errors generated by the limiters 430. In one embodiment, for a decision generated by the jth limiter 430 during a particular clock cycle, the jth limiter 430 generates the limiter error according to:

[0045]

[0046] Where slicerIn(0,j) is the signal at the input of the jth slicer 430 during a particular clock cycle, and slicerOut(0,j) is the signal at the output of the jth slicer 430 during a particular clock cycle. In one embodiment, the filter coefficients are adapted once per clock cycle. In one embodiment, the coefficient values ​​for clock cycle m+1 are calculated using a least mean square (LMS) calculation based on the coefficient values ​​and errors used in clock cycle m as follows:

[0047]

[0048] where n is the filter coefficient index (or equivalently, the filter tap index), μ(n) is the LMS step size, and e l is generated by the slicer 430 and is related to the decision made during a particular clock cycle The error corresponding to the output signal selected by multiplexer 418 in path 410 of . In other embodiments, the filter coefficients are updated based on the error generated by limiter 430 in other suitable ways. For example, in some embodiments, calculations other than LMS calculations are used to update the filter coefficients.

[0049] Figure 5 is a block diagram of an example FIR section 500 according to one embodiment. In one embodiment, the FIR section 500 corresponds to Figure 4 In other embodiments, the FIR portion 500 may be different from the FIR portion 412 of the DFE 400. Figure 4 In the illustrated embodiment, the FIR section 500 is configured to receive four parallel inputs during each clock cycle. o to in4 and generate a single output out0. In operation, the parallel inputs in o to in4 are multiplied by the corresponding coefficient c, and the sum is stored in the corresponding delay element 502. Each delay element D502 typically stores the sum of four previous data symbols multiplied by the corresponding filter tap coefficient. Therefore, in one embodiment, each delay element D2502 provides a delay of four clock cycles.

[0050] FIG. 6A to FIG. 6B 6 is a graph of example coefficients 600, 650 of a feedback filter of a DFE according to an embodiment. In the graphs 600, 650, the x-axis illustrates the filter taps of the feedback filter and the y-axis illustrates the value of the coefficient c of the feedback filter. In one embodiment, the DFE coefficients 600, 650 are plotted against Figure 4 In other embodiments, the coefficients 600, 650 are used with a DFE 400 different from Figure 4The DFE 400 is utilized together with the feedback filter of the DFE. In one embodiment, the coefficients 600, 650 are applied to equalize the input signal from the FFE coupled to the input of the DFE.

[0051] See first Fig. 6A , curve 600 illustrates example coefficients of a feedback filter of a DFE in the absence of EMI interference in a communication channel. In one embodiment, coefficient values ​​c2 and c4 to c7 are zeros for the feedback filter. For example, in one embodiment, filter taps corresponding to coefficients c2 and c4-c7 are not implemented, effectively forcing the values ​​of coefficients c2 and c4-c7 to zero, as discussed above. Now referring to Figure 6B , curve 650 illustrates example coefficients of the feedback filter of the DFE when EMI interference is present in the communication channel. In one embodiment, the coefficient values ​​c2 and c4 to c7 of the feedback filter are kept at zero. According to one embodiment, curve 650 illustrates the coefficients c8 to c9 of the feedback filter. 24 , which is suitable for counteracting the notch filter generated by FFE.

[0052] Figure 7 is a flow chart of an example method 700 for mitigating interference in a signal received by a transceiver device in an in-vehicle Ethernet network according to an embodiment. In one embodiment, the method 700 is Figure 1 In other embodiments, the method 700 is implemented by the PHY processor 150 of the network interface device 102 of the system. Figure 1 Another suitable communication device (e.g., network interface device 104) of system 100, or implemented in a different Figure 1 The system 100 is a suitable system.

[0053] At block 702, an input signal is received. In one embodiment, the input signal at block 702 is received at an input of an equalizer of a transceiver device. For example, in one embodiment, Figure 1 The input signal is received at an input of the equalizer 182 of the network interface device 102. In another embodiment, at an equalizer different from the equalizer 182 and / or at a different Figure 1 The input signal is received at an equalizer of a suitable communication device of the network interface device 102. In one embodiment, the equalizer includes at least a DFE. In one embodiment, the equalizer also includes a FFE.

[0054] At block 704, data symbols are detected based on the input signal received at block 702. In one embodiment, the data symbols are detected by a slicer of the DFE. In another embodiment, the data symbols are detected in a suitable manner other than the slicer of the DFE.

[0055] At block 706, a filter output of a feedback filter of the DFE is generated based on the data symbols detected at block 704. In an embodiment, during a particular clock cycle, the filter output at block 706 is generated based on the data symbols detected at block 704 during a plurality of previous clock cycles prior to the particular clock cycle. In an embodiment, during a particular clock cycle, the filter output is generated based on i) a first set of one or more data symbols detected by a slicer during a first one or more previous clock cycles and ii) a second set of one or more data symbols detected by the slicer in a second one or more previous clock cycles. The second set of one or more data symbols is separated from the first set of one or more data symbols by a third set of one or more data symbols detected by the slicer during a third one or more clock cycles, in an embodiment, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, the feedback filter output being generated in the particular clock cycle without using the third set of one or more data symbols.

[0056] At block 708, the filter output generated at block 796 is subtracted from the input signal to generate an equalized input to the limiter.

[0057] In one embodiment, a transceiver device for use in an in-vehicle Ethernet network. The transceiver device includes: an equalizer configured to mitigate interference in an input signal received by the transceiver device, the equalizer including a decision feedback equalizer (DFE), the decision feedback equalizer (DFE) including a limiter and a feedback filter, the limiter configured to detect data symbols in the input signal, the feedback filter configured to generate a filter output during a specific clock cycle based on i) a first group of one or more data symbols detected by the limiter during a first one or more previous clock cycles and ii) a second group of one or more data symbols detected by the limiter during a second one or more second previous clock cycles, wherein the second group of one or more data symbols is separated from the first group of one or more data symbols by a third group of one or more data symbols detected by the limiter during a third one or more clock cycles, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, and the feedback filter output is generated in the specific clock cycle without using the third group of one or more data symbols; and a summing junction configured to subtract the filter output from the input signal to generate an equalized input to the limiter.

[0058] In other embodiments, the transceiver device further includes any suitable combination of one or two or more of the following features.

[0059] The feedback filter includes a plurality of filter taps including at least a first group of filter taps, wherein the first group of filter taps includes at least a first filter tap, a second filter tap, and a third filter tap.

[0060] The first filter tap and the third filter tap are implemented as expanded filter taps, and the expanded filter taps are configured to perform multiple pre-calculations to determine multiple filter outputs corresponding to multiple possible data symbol values ​​for the first filter tap and the second filter tap, wherein a particular filter output among the multiple filter outputs is selected based on an actual data symbol detected by the limiter during a first previous clock cycle and a second previous clock cycle, and wherein the second filter tap stores a value corresponding to a data symbol detected by the limiter during a third clock cycle occurring after the first clock cycle and before the second clock cycle, wherein the second data symbol is not used by the feedback filter to generate the filter output during the particular clock cycle.

[0061] The first previous clock cycle immediately precedes the particular clock cycle,

[0062] The second previous clock cycle occurs two clock cycles before the particular clock cycle.

[0063] The feedback filter also includes a second set of filter taps, the second set of filter taps including one or more filter taps, which are configured to store one or more data symbols that are not used by the feedback filter to generate a filter output during a particular clock cycle.

[0064] The second set of filter taps also includes one or more additional filter taps configured to process corresponding data symbols of the second set of one or more data symbols detected by the slicer during a second one or more previous clock cycles.

[0065] The DFE includes a plurality of parallel paths configured to process corresponding ones of consecutive samples of an input signal.

[0066] The slicer is configured to detect the particular data symbol by determining that the particular data symbol corresponds to a particular value from a set of a plurality of possible values ​​for the data symbol.

[0067] The equalizer also includes a feed forward equalizer (FFE) having an output coupled to an input of the DFE.

[0068] The FFE is configured to generate a notch filter to mitigate electromagnetic interference.

[0069] The DFE is configured to equalize the effect of the notch filter on the input signal.

[0070] The transceiver of claim 1 further comprises an adaptation controller configured to adapt coefficients of a feedback filter of the DFE during a particular clock cycle based on a limiter error detected by the limiter during a previous clock cycle immediately before the particular clock cycle.

[0071] In another embodiment, a method for mitigating interference in a signal received by a transceiver device in an in-vehicle Ethernet network. The method includes: receiving an input signal at an equalizer of the transceiver device, the equalizer including a decision feedback equalizer (DFE); detecting data symbols in the input signal using a limiter of the DFE; generating a filter output at a feedback filter of the DFE, the filter output being generated during a particular clock cycle based on i) a first set of one or more data symbols detected by the limiter during a first one or more previous clock cycles and ii) a second set of one or more data symbols detected by the limiter during a second one or more previous clock cycles, wherein the second set of one or more data symbols is separated from the first set of one or more data symbols by a third set of one or more data symbols detected by the limiter during a third one or more clock cycles, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, the feedback filter output being generated in the particular clock cycle without using the third set of one or more data symbols; and subtracting the filter output from the input signal to generate an equalized input to the limiter.

[0072] In other embodiments, the method further includes any suitable combination of one or two or more of the following features.

[0073] Generating the filter output includes generating the filter output using a plurality of filter taps, the plurality of filter taps including at least a first set of filter taps and a second set of filter taps.

[0074] The first group of filter taps includes at least a first filter tap, a second filter tap, and a third filter tap, and wherein generating a filter output includes: generating the filter output using the first filter tap and the third filter tap implemented as expanded filter taps, the expanded filter taps being configured to perform multiple pre-calculations to determine multiple filter outputs corresponding to multiple possible data symbol values ​​for the first filter tap and the second filter tap, wherein a specific filter output among the multiple filter outputs is selected based on an actual data symbol detected by the limiter during a first previous clock cycle and a second previous clock cycle, and wherein the method further includes: storing in the second filter tap a value corresponding to a data symbol detected by the limiter during a third clock cycle occurring after the first clock cycle and before the second clock cycle, wherein the second data symbol is not used by the feedback filter to generate the filter output during the specific clock cycle.

[0075] Generating a filter output includes selecting a filter output among a plurality of filter outputs using actual data symbols detected by a limiter during: i) a first previous clock cycle, wherein the first previous clock cycle immediately precedes a particular clock cycle, and ii) a second previous clock cycle, wherein the second previous clock cycle occurs two clock cycles prior to the particular clock cycle.

[0076] The method also includes storing one or more data symbols in one or more filter taps of the second set of filter taps, the one or more data symbols not used by the feedback filter to generate a filter output during a particular clock cycle.

[0077] Generating the filter output includes processing corresponding data symbols of the second set of one or more data symbols detected by the slicer during a second one or more previous clocks using one or more additional filter taps from the second set of filter taps.

[0078] Generating the filter output includes generating the filter output using a corresponding feedback filter portion in a corresponding path in a plurality of parallel paths of the DFE, the corresponding path in the parallel paths being configured to process a corresponding sample in consecutive samples of the input signal.

[0079] Detecting a data symbol in the input signal includes detecting the particular data symbol by determining that the particular data symbol corresponds to a particular value in a set of a plurality of possible values ​​for the data symbol.

[0080] The equalizer also includes a feedforward equalizer (FFE) having an output coupled to an input of the DFE, wherein the method includes generating a notch filter at the FFE to mitigate electromagnetic interference, and equalizing an effect of the notch filter on the input signal at the DFE.

[0081] The method further includes updating, during the particular clock cycle, coefficients of a feedback filter of the DFE based on a limiter error detected by the limiter during a previous clock cycle immediately preceding the particular clock cycle.

[0082] At least some of the various blocks, operations, and techniques described above may be implemented using hardware, a processor executing firmware instructions, a processor executing software instructions, or any combination thereof. When implemented using a processor executing software or firmware instructions, the software or firmware instructions may be stored in any suitable computer-readable memory, such as a random access memory (RAM), a read-only memory (ROM), flash memory, etc. The software or firmware instructions may include machine-readable instructions that, when executed by one or more processors, cause the one or more processors to perform various actions.

[0083] When implemented in hardware, the hardware may include one or more of discrete components, integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), and the like.

[0084] Although the invention has been described with reference to specific examples, these examples are intended to be illustrative only and not limiting of the invention, and changes, additions and / or deletions may be made to the disclosed embodiments without departing from the scope of the invention.

Claims

1. A transceiver device for use in a vehicle Ethernet network, the transceiver device comprising: an equalizer configured to mitigate interference in an input signal received by the transceiver device, the equalizer comprising a decision feedback equalizer (DFE), the decision feedback equalizer comprising: a slicer configured to detect data symbols in the input signal, a feedback filter configured to: generate a filter output during a particular clock cycle based on i) a first group of one or more data symbols detected by the slicer during a first one or more previous clock cycles and ii) a second group of one or more data symbols detected by the slicer during a second one or more second previous clock cycles, wherein the second group of one or more data symbols are separated from the first group of one or more data symbols by a third group of one or more data symbols detected by the slicer during a third one or more clock cycles, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, the feedback filter output being generated in the particular clock cycle without using the third group of one or more data symbols to ease timing constraints for turning off timing on the second group of one or more data symbols, the second group of one or more data symbols being used to generate the feedback filter output in the particular clock cycle, and A summing junction is configured to subtract the filter output from the input signal to generate an equalized input to the limiter.

2. The transceiver device according to claim 1, wherein the feedback filter comprises a plurality of filter taps, the plurality of filter taps comprising at least a first group of filter taps, wherein the first group of filter taps comprises at least a first filter tap, a second filter tap, and a third filter tap.

3. A transceiver device according to claim 2, wherein the first filter tap and the third filter tap are implemented as expanded filter taps, and the expanded filter taps are configured to perform multiple pre-calculations to determine multiple filter outputs corresponding to multiple possible data symbol values ​​for the first filter tap and the second filter tap, wherein a specific filter output among the multiple filter outputs is selected based on an actual data symbol detected by the limiter during a first previous clock cycle and a second previous clock cycle, and wherein the second filter tap stores a value corresponding to a data symbol detected by the limiter during a third clock cycle occurring after the first previous clock cycle and before the second previous clock cycle, wherein the data symbol corresponding to the value stored at the second filter tap is not used by the feedback filter to generate the filter output during the specific clock cycle. 4 . The transceiver device of claim 3 , wherein i) the first previous clock cycle immediately precedes the specific clock cycle and ii) the second previous clock cycle occurs two clock cycles before the specific clock cycle.

5. The transceiver device of claim 2 , wherein the feedback filter further comprises a second set of filter taps, the second set of filter taps comprising one or more filter taps, the one or more filter taps being configured to store one or more data symbols, the one or more data symbols not being used by the feedback filter to generate the filter output during the particular clock cycle.

6. A transceiver device according to claim 5, wherein the second group of filter taps also includes one or more additional filter taps, and the one or more additional filter taps are configured to process corresponding data symbols of the second group of one or more data symbols detected by the limiter during the second one or more previous clock cycles. 7 . The transceiver device of claim 1 , wherein the DFE comprises a plurality of parallel paths configured to process respective ones of consecutive samples of the input signal.

8. The transceiver device of claim 1, wherein the slicer is configured to detect the particular data symbol by determining that the particular data symbol corresponds to a particular value from a set of a plurality of possible values ​​for the data symbol.

9. The transceiver device of claim 1 , wherein the equalizer further comprises a feed-forward equalizer (FFE) having an output coupled to an input of the DFE, wherein: The FFE is configured to generate a notch filter to mitigate electromagnetic interference, and The DFE is configured to equalize an effect of the notch filter on the input signal.

10. The transceiver device of claim 1 , further comprising an adaptation controller configured to adapt coefficients of the feedback filter of the DFE during the particular clock cycle based on a limiter error detected by the limiter during a previous clock cycle immediately before the particular clock cycle.

11. A method for mitigating interference in a signal received by a transceiver device in an in-vehicle Ethernet network, the method comprising: receiving an input signal at an equalizer of the transceiver device, the equalizer comprising a decision feedback equalizer (DFE); Detecting data symbols in the input signal using a limiter of the DFE; generating a filter output at a feedback filter of the DFE, the filter output being generated during a particular clock cycle based on i) a first set of one or more data symbols detected by the slicer during a first one or more previous clock cycles and ii) a second set of one or more data symbols detected by the slicer during a second one or more previous clock cycles, wherein the second set of one or more data symbols are separated from the first set of one or more data symbols by a third set of one or more data symbols detected by the slicer during a third one or more clock cycles, the third one or more clock cycles occurring after the first one or more clock cycles and before the second one or more clock cycles, the feedback filter output being generated in the particular clock cycle without using the third set of one or more data symbols to ease a timing constraint for turning off timing on the second set of one or more data symbols used to generate the feedback filter output in the particular clock cycle; as well as The filter output is subtracted from the input signal to generate an equalized input to the limiter.

12. The method of claim 11, wherein generating the filter output comprises: The filter output is generated using a plurality of filter taps, the plurality of filter taps comprising at least a first set of filter taps and a second set of filter taps.

13. The method of claim 12, wherein the first set of filter taps includes at least a first filter tap, a second filter tap, and a third filter tap, and wherein generating the filter output comprises: The filter output is generated using the first filter tap and the third filter tap implemented as expanded filter taps, the expanded filter taps being configured to perform multiple pre-calculations to determine multiple filter outputs corresponding to multiple possible data symbol values ​​for the first filter tap and the second filter tap, wherein a particular filter output among the multiple filter outputs is selected based on an actual data symbol detected by the limiter during a first previous clock cycle and a second previous clock cycle, and wherein the method further comprises: storing in the second filter tap a value corresponding to a data symbol detected by the limiter during a third clock cycle occurring after the first previous clock cycle and before the second previous clock cycle, wherein the data symbol corresponding to the value stored at the second filter tap is not used by the feedback filter to generate the filter output during the particular clock cycle.

14. The method of claim 13, wherein generating the filter output comprises: The filter output is selected among the multiple filter outputs using actual data symbols detected by the limiter during the following clock cycles: i) the first previous clock cycle, wherein the first previous clock cycle immediately precedes the particular clock cycle, and ii) the second previous clock cycle, wherein the second previous clock cycle occurs two clock cycles before the particular clock cycle.

15. The method according to claim 12, further comprising: One or more data symbols are stored in one or more filter taps of the second set of filter taps, the one or more data symbols not used by the feedback filter to generate the filter output during the particular clock cycle.

16. The method of claim 15, wherein generating the filter output comprises: Corresponding data symbols of the second set of one or more data symbols detected by the slicer during the second one or more previous clock cycles are processed using one or more additional filter taps of the second set of filter taps.

17. The method of claim 11, wherein generating the filter output comprises: The filter output is generated using a respective feedback filter portion in a respective one of a plurality of parallel paths of the DFE, the respective one of the parallel paths being configured to process a respective one of consecutive samples of the input signal.

18. The method of claim 11, wherein detecting the data symbol in the input signal comprises: The particular data symbol is detected by determining that the particular data symbol corresponds to a particular value from a set of a plurality of possible values ​​for the data symbol.

19. The method of claim 11, wherein the equalizer further comprises a feed-forward equalizer (FFE), the FFE having an output coupled to an input of the DFE, wherein the method comprises: generating a notch filter at the FFE to mitigate electromagnetic interference, and The effect of the notch filter on the input signal is equalized at the DFE.

20. The method according to claim 11, further comprising: During the particular clock cycle, coefficients of the feedback filter of the DFE are updated based on a slicer error detected by the slicer during a previous clock cycle immediately preceding the particular clock cycle.

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