Communication System for Anti-Fooling in Chip Testing

Abstract

A communication system for anti-fooling in chip testing is disclosed. In the system, the PC side generates log data based on the test cycle in response to the RS232 signal; the test board starts the test of the chip under test based on the SOT signal to generate the RS232 signal and the TTL step signal. After the test is completed, the test board is communicatively connected to the PC side and sends the RS232 signal to the PC side. The field programmable gate array (FPGA) is communicatively connected to the test board to send the SOT signal to the test board and receive the TTL step signal generated by the test board. The field programmable gate array (FPGA) is communicatively connected to the PC side to receive the log data and compare the log data with the TTL step signal to generate an error-free signal. The chip sorting device is communicatively connected to the field programmable gate array (FPGA). In response to the error-free signal, the chip sorting device receives the TTL step signal and sorts the chips based on the TTL step signal.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip testing, and in particular, relates to a communication system for anti-fooling in chip testing. Background Art

[0002] Currently, the implementation of chip testing is all completed based on ATE (Automatic Test Equipment); the testing is completed through the structure of PC - ATE - IC. In actual production, the following situations may occur: ① Small-cost testing, but the price of ATE is expensive, driving up production costs. ② For the testing scheme of chips with encryption algorithm requirements, generally, a non-ATE platform scheme is adopted. And each chip design company makes its own test board and dedicated interface, which results in that independent third-party testing factories cannot control and manage it uniformly like the ATE scheme. Most of the test boards provided by chip design companies only have the function of two-way communication with the Handler (chip sorting equipment under test), and the communication between the test board and the PC host computer is usually one-way. The system does not realize the interconnection and interoperability among the Handler, the test board, and the PC host computer responsible for saving logs. Therefore, when the PC host computer fails to successfully save the correct log, the Handler and the test board will continue to complete the subsequent test tasks and cannot give timely feedback, resulting in an abnormality where the log does not match the actual sorting result of the chip under test. Such abnormalities will force the production line to conduct secondary testing on the chips of the abnormal batch, affecting the overall operation efficiency of the production line. For a type of chips with non-repeatable testing requirements, it will cause greater losses.

[0003] The above information disclosed in the background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art in this country. Summary of the Invention

[0004] Aiming at the problems existing in the prior art, the present invention proposes a communication system for anti-fooling in chip testing, which realizes the interconnection and interoperability among the test board, the chip sorting equipment Handler, and the PC side based on the FPGA board. Furthermore, in the case of log loss or log error during the execution of the test task, the current test task is suspended, and feedback is given to the machine for alarm, notifying the staff to go to the site for inspection and handling, effectively avoiding the situation where the production line needs to conduct secondary testing on the tested chips due to the inconsistency between the log and the actual sorting result of the chip under test, and improving the efficiency of the production line.

[0005] The object of the present invention is achieved through the following technical solutions. A communication system for anti-fooling in chip testing includes:

[0006] A PC side, which generates log data based on the test cycle in response to the RS232 signal;

[0007] A test board that starts testing a chip under test based on an SOT signal to generate an RS232 signal and a TTL step signal. After the test is completed, the test board is communicatively connected to the PC end and sends the RS232 signal to the PC end.

[0008] A field-programmable gate array (FPGA) that is communicatively connected to the test board to send an SOT signal to the test board and receive the TTL step signal generated by the test board. The FPGA is communicatively connected to the PC end to receive the log data and compare the log data with the TTL step signal to generate an error-free signal; otherwise, no TTL step signal is sent.

[0009] A chip sorting device that is communicatively connected to the FPGA. In response to the error-free signal, the chip sorting device receives the TTL step signal and sorts the chips based on the TTL step signal.

[0010] In the communication system for anti-fooling chip testing, the chip sorting device includes an alarm unit that alarms when the chip sorting device waits for the TTL step signal to time out.

[0011] In the communication system for anti-fooling chip testing, the alarm unit includes a buzzer or an LED light.

[0012] In the communication system for anti-fooling chip testing, the FPGA is installed in the PCIE slot of the PC end.

[0013] In the communication system for anti-fooling chip testing, the FPGA communicatively connects to the test board and the chip sorting device through an adapter board.

[0014] In the communication system for anti-fooling chip testing, the test board and the chip sorting device are respectively connected to the adapter board via DB25 connecting wires.

[0015] In the communication system for anti-fooling chip testing, the adapter board is a PCB board.

[0016] In the communication system for anti-fooling chip testing, the power supply of the FPGA uses 3.3V power supply from the PCIE port of the PC end.

[0017] In the communication system for anti-fooling chip testing described above, the field programmable gate array (FPGA) includes a TTL interface for communicating with the chip sorting device and a PCIE interface for communicating with the PC side. The PC side sends log data to the FPGA via the PCIE interface, and the log data includes the test binning results of the host computer.

[0018] In the communication system for anti-fooling chip testing described above, when the chips in the chip sorting device are placed ready, an SOT signal is sent to the field programmable gate array (FPGA).

[0019] Compared with the prior art, the present invention has the following advantages: The present invention can effectively avoid the anomaly that the log saved by the host computer in the original board-level test scheme does not match the actual sorting result of the chip under test, realizes the interconnection and interoperability among the Handler, the test board, and the PC host computer responsible for saving the log, so that the machine will give an alarm in time when the data log is lost or transmitted incorrectly, and feedback to the staff, thereby effectively improving the efficiency and quality of the production line. At the same time, based on this system, by burning different logic firmware into the FPGA for different models of ICs with board-level test requirements, universality can be achieved. Compared with the current scheme, the present invention improves the deficiencies of the original scheme, has a low invention cost, strong compatibility, can be used in this invention in a variety of board-level test systems, and expands the functions of the test board. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] By reading the following detailed description of the preferred specific embodiments, various other advantages and benefits of the present invention will become clear to those of ordinary skill in the art. The drawings in the specification are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the present invention. Obviously, the following described drawings are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. Moreover, throughout the drawings, the same reference numerals are used to represent the same components.

[0021] In the drawings:

[0022] Figure 1 is a schematic structural diagram of a communication system for anti-fooling chip testing according to an embodiment of the present invention;

[0023] Figure 2 is a schematic working flow diagram of a communication system for anti-fooling chip testing according to an embodiment of the present invention.

[0024] The present invention will be further explained below with reference to the drawings and embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0025] The following will refer to the attachedFigures 1 to 2 Specific embodiments of the present invention will be described in more detail. Although specific embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be fully conveyed to those skilled in the art.

[0026] It should be noted that certain terms are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. The specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of components as the criterion for distinction. As mentioned throughout the specification and claims, "comprising" or "including" is an open-ended term and should be interpreted as "including but not limited to". The subsequent description in the specification is the preferred embodiment for implementing the present invention, but the description is for the purpose of the general principles of the specification and is not intended to limit the scope of the present invention. The protection scope of the present invention shall be subject to what is defined by the appended claims.

[0027] For the convenience of understanding the embodiments of the present invention, the following will further explain with specific embodiments in conjunction with the drawings, and each drawing does not constitute a limitation on the embodiments of the present invention.

[0028] For better understanding, as Figures 1 to 2 shown, in a communication system for anti-fooling in chip testing,

[0029] A PC terminal that generates log data based on a test cycle in response to an RS232 signal;

[0030] A test board that starts testing the chip to be tested based on an SOT signal to generate an RS232 signal and a TTL walking signal. After the test is completed, the test board is communicatively connected to the PC terminal and sends the RS232 signal to the PC terminal.

[0031] A field-programmable gate array (FPGA) that is communicatively connected to the test board to send an SOT signal to the test board and receive the TTL walking signal generated by the test board. The field-programmable gate array (FPGA) is communicatively connected to the PC terminal to receive the log data and compare the log data and the TTL walking signal to generate an error-free signal, otherwise no TTL walking signal is sent.

[0032] A chip sorting device that is communicatively connected to the field-programmable gate array (FPGA). In response to the error-free signal, the chip sorting device receives the TTL walking signal and sorts the chips based on the TTL walking signal.

[0033] In a preferred embodiment of the communication system for anti-fooling in chip testing, the chip sorting device includes an alarm unit, and when the chip sorting device receives a waiting timeout for the TTL step signal, the alarm unit gives an alarm.

[0034] In a preferred embodiment of the communication system for anti-fooling in chip testing, the alarm unit includes a buzzer or an LED light.

[0035] In a preferred embodiment of the communication system for anti-fooling in chip testing, the field programmable gate array (FPGA) is installed in the PCIE slot of the PC.

[0036] In a preferred embodiment of the communication system for anti-fooling in chip testing, the field programmable gate array (FPGA) communicates with the test board and the chip sorting device through an adapter board.

[0037] In a preferred embodiment of the communication system for anti-fooling in chip testing, the test board and the chip sorting device are respectively connected to the adapter board via DB25 connecting wires.

[0038] In a preferred embodiment of the communication system for anti-fooling in chip testing, the adapter board is a PCB board.

[0039] In a preferred embodiment of the communication system for anti-fooling in chip testing, the power supply of the field programmable gate array (FPGA) is powered by 3.3V from the PCIE port of the PC.

[0040] In a preferred embodiment of the communication system for anti-fooling in chip testing, the field programmable gate array (FPGA) includes a TTL interface for communicating with the chip sorting device and a PCIE interface for communicating with the PC. The PC sends log data including the test binning results of the host computer to the field programmable gate array (FPGA) via the PCIE interface.

[0041] In a preferred embodiment of the communication system for anti-fooling in chip testing, when the chips in the chip sorting device are placed ready, an SOT signal is sent to the field programmable gate array (FPGA).

[0042] In one embodiment, during use, first install the corresponding driver program of the CH368 driver chip on the PC side to configure the PCIE communication environment. Install the FPGA board into the PCIE slot of the PC, and use a SCSI-68Pin connection cable to connect the FPGA and the adapter board. The FPGA is connected to the test board and the Handler sorter through the adapter board and uses a DB25 connection cable. Open the host computer on the PC side and operate the Handler to send the SOT signal. The FPGA conveys this signal to the test board. After the test board finishes the test, the FPGA compares the log information on the PC side with the step signal of the test board. If there is no error, it sends the step signal to the Handler, and the Handler sorts the chips to be tested. If there is an error in the data, the FPGA will notify the Handler to send an alarm message.

[0043] In one embodiment, the communication system for anti-fooling in chip testing receives the log data on the PC side and the TTL step signal sent by the test board to the Handler within a test cycle, and then sends these signals to the FPGA. The FPGA integrates and compares the signals at both ends. If the log signal and the TTL step signal are consistent, the FPGA sends the received binning information to the Handler through the TTL protocol.

[0044] In one embodiment, the communication system for anti-fooling in chip testing includes an Altera Cyclone II FPGA, a level conversion chip 74LVC164245, a PCIE driver chip CH368, a SCSI-68pin connection cable, a DB25 connection cable, and a PCB board (adapter board / Load Board). With the FPGA as the main body, data processing and transmission are completed, and the power supply is powered by 3.3V from the PCIE port of the PC side. The FPGA board is installed in the PCIE x1 interface of the PC motherboard and is connected to the adapter board through a SCSI-68pin connection cable. The adapter board has a total of three ports. The two ends are DB25 female head ports, which are respectively connected to the Handler and the test board. Among them, the port connected to the Handler needs to pass through the 74LVC164245 level conversion chip. The function of this chip is to convert the 0V / 3.3V standard output by the FPGA into the 0V / 5V level standard recognizable by the Handler. The other end is a SCSI-68pin port connected to the FPGA.

[0045] In one embodiment, the FPGA constructs a data transmission module, including a TTL interface and a PCIE interface. The PCIE interface uses the driver chip CH368. Through the PCIE interface, the FPGA can communicate with the host computer software running on the PC. The PC will send the test binning result received by the host computer to the FPGA. The TTL interface is mainly responsible for the communication between the FPGA and the Handler. The FPGA sends the correct binning signal to the Handler through the TTL interface.

[0046] Further, after the Handler sends the SOT (start to test) signal to the FPGA, it indicates that the chip to be tested has been placed. The FPGA will send a start instruction to the test board. After the test program is executed, the test board will first send the test result to the PC through the serial port. After a delay, the test board will send the EOT (end of test) and the step signal of binning to the FPGA.

[0047] Furthermore, the PC will send the test result received by the host computer to the FPGA through the PCIE. The FPGA will compare the binning information at both ends. If the number and content of the information sent at both ends are the same, the FPGA will send the step signal containing this information to the Handler for sorting. If the number or content of the information sent at both ends is inconsistent, the FPGA will not send the TTL signal to the Handler. At that time, the Handler will give an overtime alarm to notify the production line staff to handle it.

[0048] Further, according to different test platforms, different logic firmware can be burned into the FPGA to adapt to a variety of Handlers, test boards and their protocols.

[0049] Although the embodiments of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above specific embodiments and application fields. The above specific embodiments are merely illustrative and guiding, rather than restrictive. Those of ordinary skill in the art can also make many forms under the inspiration of this specification and without departing from the scope protected by the claims of the present invention. These all belong to the scope of protection of the present invention.

Claims

1. A communication system for anti-fooling in chip testing, comprising: A PC terminal, which generates log data based on a test cycle in response to an RS232 signal; A test board, which starts the test of the chip under test based on an SOT signal to generate an RS232 signal and a TTL walking signal. After the test is completed, the test board is communicatively connected to the PC terminal and sends the RS232 signal to the PC terminal; A field programmable gate array (FPGA), which is communicatively connected to the test board to send an SOT signal to the test board and receive the TTL walking signal generated by the test board. The field programmable gate array (FPGA) is communicatively connected to the PC terminal to receive the log data and compare the log data with the TTL walking signal to generate an error-free signal, otherwise it does not send the TTL walking signal; A chip sorting device, which is communicatively connected to the field programmable gate array (FPGA). In response to the error-free signal, the chip sorting device receives the TTL walking signal and sorts the chips based on the TTL walking signal. The field programmable gate array (FPGA) includes a TTL interface for communicating with the chip sorting device and a PCIE interface for communicating with the PC terminal. The PC terminal sends the log data to the field programmable gate array (FPGA) via the PCIE interface. The log data includes the test binning result of the host computer. The TTL interface is responsible for the communication between the field programmable gate array (FPGA) and the chip sorting device. The field programmable gate array (FPGA) sends the correct binning signal to the chip sorting device through the TTL interface. When the chip sorting device sends an SOT signal to the field programmable gate array (FPGA), it indicates that the chip under test has been placed. The field programmable gate array (FPGA) sends a start command to the test board. After the test program is completed, the test board first sends the test result to the PC terminal through the serial port. After a delay period, the test board will send an EOT and the walking signal of binning to the field programmable gate array (FPGA).

2. The communication system for chip test anti-fooling according to claim 1, wherein, The chip sorting device includes an alarm unit, which alarms when the chip sorting device receives the TTL walking signal and waits for a timeout.

3. The communication system for chip test anti-fooling according to claim 2, wherein, The alarm unit includes a buzzer or an LED light.

4. The communication system for anti-fooling in chip testing according to claim 1, wherein, The field programmable gate array (FPGA) is installed in the PCIE slot of the PC terminal.

5. The communication system for chip test anti-fooling according to claim 4, wherein, The field programmable gate array (FPGA) is communicatively connected to the test board and the chip sorting device through an adapter board.

6. The communication system for chip test anti-fooling according to claim 5, wherein, The test board and the chip sorting device are respectively connected to the adapter board via a DB25 connection line.

7. The communication system for chip test anti-fooling according to claim 5, wherein, The adapter board is a PCB board.

8. The communication system for chip test anti-fooling according to claim 4, wherein, The power supply of the field programmable gate array (FPGA) is powered by 3.3V of the PCIE port of the PC terminal.

9. The communication system for chip test anti-fooling according to claim 1, wherein, When the chips in the chip sorting device are placed ready, an SOT signal is sent to the field programmable gate array (FPGA).

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