Display panel and display device

Abstract

The present application provides a display panel and a display device, wherein the frame area of ​​the display panel includes a first frame area and a second frame area located on opposite sides of the display area, and the display panel includes: a substrate; a driving circuit layer, including: a plurality of pixel driving circuits arranged in the display area and a plurality of multiplexing circuits arranged in the first frame area, one end of a multiplexing circuit being electrically connected to the plurality of pixel driving circuits; a signal terminal, located in the second frame area; a first metal layer, including a plurality of adapter wires, one end of the adapter wire being electrically connected to the corresponding signal terminal, and the other end of the adapter wire being electrically connected to the other end of the corresponding multiplexing circuit. The present application arranges the multiplexing circuit in the first frame area, and electrically connects the signal terminal arranged in the second frame area to the multiplexer arranged in the first frame area through the adapter wire, thereby greatly reducing the frame width and routing density of the second frame area, and improving the screen-to-body ratio and production yield of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In existing display panels, the data driver chip is directly electrically connected to the data line through the signal terminal arranged at the lower frame to output the pixel voltage to the light-emitting pixel, which results in a large number of signal terminals. In order to reduce the number of signal terminals, a multiplexing circuit (Demux) is arranged between the data driver chip and the data line in the related art to decompose a signal channel of the data driver chip into multiple signal channels, and then electrically connected to each data line accordingly.

[0003] As current display technology is developing towards a high screen-to-body ratio, the bottom frame of the display panel needs to be smaller and smaller. The multiplexer set on the bottom frame of the display panel occupies more space on the bottom frame, hindering the realization of a high screen-to-body ratio of the display panel. Summary of the invention

[0004] The present application provides a display panel and a display device, which can effectively solve the technical problems of a large lower frame width and dense wiring layout caused by a multiplexing circuit occupying the lower frame space in the existing display panel.

[0005] In one aspect, the present application provides a display panel, the display panel comprising a display area and a frame area, the frame area comprising a first frame area and a second frame area located on two opposite sides of the display area,

[0006] The display panel comprises:

[0007] substrate;

[0008] A driving circuit layer is arranged on one side of the substrate, the driving circuit layer comprising: a plurality of pixel driving circuits arranged in the display area and a plurality of multiplexing circuits arranged in the first frame area, one end of one of the multiplexing circuits is electrically connected to the plurality of pixel driving circuits;

[0009] A signal terminal is arranged on one side of the substrate and located in the second frame area;

[0010] The first metal layer is arranged on a side of the driving circuit layer away from the substrate, and the first metal layer includes a plurality of adapter wires, one end of the adapter wire is electrically connected to the corresponding signal terminal, and the other end of the adapter wire is electrically connected to the other end of the corresponding multiplexing circuit.

[0011] Optionally, the driving circuit layer further includes: a plurality of virtual pixel driving circuits arranged in the first border area,

[0012] The display panel further includes:

[0013] a light-emitting layer, arranged on a side of the first metal layer away from the substrate, the light-emitting layer comprising: a plurality of light-emitting pixels arranged in the display area, the pixel driving circuit being electrically connected to the corresponding light-emitting pixels, and the dummy pixel driving circuit being not electrically connected to the light-emitting pixels in the display area;

[0014] Wherein, the virtual pixel driving circuit and the multiplexing circuit are both arranged adjacent to the pixel driving circuit of the display area.

[0015] Optionally, the multiplexing circuit is arranged in a gap area between two adjacent virtual pixel driving circuits.

[0016] Optionally, the driving circuit layer does not include a virtual pixel driving circuit, and the multiplexing circuit is arranged adjacent to the pixel driving circuit of the display area.

[0017] Optionally, the driving circuit layer further includes:

[0018] A semiconductor layer is arranged on one side of the substrate, and the semiconductor layer includes: a first semiconductor located in the display area and arranged corresponding to the pixel driving circuit, and a second semiconductor located in the first frame area and arranged corresponding to the multiplexing circuit;

[0019] A second metal layer is disposed on a side of the semiconductor layer away from the substrate, the second metal layer comprising: a first gate located in the display area and corresponding to the pixel driving circuit, and a second gate located in the first frame area and corresponding to the multiplexing circuit;

[0020] A third metal layer is arranged on a side of the second metal layer away from the substrate, the third metal layer comprising: a first source and a first drain located in the display area and corresponding to the pixel driving circuit, and a second source and a second drain located in the first frame area and corresponding to the multiplexing circuit;

[0021] The first metal layer is arranged on a side of the third metal layer away from the substrate, and the adapter wire and the pixel driving circuit are at least partially overlapped.

[0022] Optionally, the driving circuit layer also includes a fourth metal layer, which is arranged on a side of the third metal layer away from the substrate, and the fourth metal layer includes: a plurality of data lines in the display area, and one end of the multiplexing circuit is electrically connected to the pixel driving circuit through the data lines.

[0023] Optionally, each of the multiplexing circuits includes a data bus, a plurality of data branch lines and a plurality of switch units, the data bus is arranged on the second metal layer, the data branch lines are arranged on the third metal layer, and the switch unit includes the second semiconductor, the second gate, the second source and the second drain;

[0024] Among them, one end of the data bus is electrically connected to the other end of the adapter line, the other end of the data bus is electrically connected to one end of multiple data branch lines, the other end of the data branch line is electrically connected to the second source, and the second drain is electrically connected to the data line.

[0025] Optionally, the driving circuit layer further includes a fifth metal layer, the fifth metal layer is arranged on a side of the second metal layer away from the substrate, and the third metal layer is arranged on a side of the fifth metal layer away from the substrate;

[0026] Each of the multiplexing circuits further includes a plurality of electrostatic protection circuits, and the second drain is electrically connected to the data line through the electrostatic protection circuit;

[0027] Among them, the electrostatic protection circuit includes a first part. Among two adjacent electrostatic protection circuits in the multiplexing circuit, the first part of one of the electrostatic protection circuits is located in the second metal layer, and the first part of the other electrostatic protection circuit is located in the fifth metal layer.

[0028] Optionally, each of the multiplexing circuits includes a data bus, four data lines and four switch units, wherein:

[0029] The light-emitting pixels include: a first light-emitting pixel having a first light-emitting color, a second light-emitting pixel having a second light-emitting color, and a third light-emitting pixel having a third light-emitting color.

[0030] Among them, the four data branch lines in each of the multiplexing circuits are electrically connected to a column of the first light-emitting pixels, a column of the second light-emitting pixels, a column of the third light-emitting pixels, and another column of the second light-emitting pixels through different data lines.

[0031] On the other hand, the present application provides a display device, comprising a housing and any one of the display panels described above, wherein the housing has a containing space, and the display panel is disposed in the containing space.

[0032] The present application provides a display panel and a display device. The present application sets a multiplexing circuit in a first frame area, and electrically connects a signal terminal set in a second frame area with a multiplexer set in the first frame area through a switching line, thereby greatly reducing the frame width and wiring density of the second frame area, and improving the screen-to-body ratio and production yield of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 A schematic plan view of a pixel driving circuit and a multiplexing circuit in a display panel provided in Embodiment 1 of the present application being electrically connected via a data line;

[0035] Figure 2 A plan view schematically shows that a signal terminal and a multiplexing circuit in a display panel are electrically connected via a switching line for the first embodiment of the present application;

[0036] Figure 3 A schematic diagram of the film layer structure of a display panel provided in Example 1 of the present application;

[0037] Figure 4 A schematic plan view of a multiplexing circuit provided in Embodiment 1 of the present application;

[0038] Figure 5 This is a plan view of a multiplexing circuit provided in Embodiment 2 of the present application. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0040] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and / or settings discussed in itself. In addition, the present application provides various specific examples of processes and materials, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials. The following is described in detail respectively, and it should be noted that the description order of the following embodiments is not used as a limitation to the preferred order of the embodiments.

[0041] Embodiment 1

[0042] Figure 1 A schematic plan view of a pixel driving circuit and a multiplexing circuit in a display panel provided in Embodiment 1 of the present application being electrically connected via a data line; Figure 2 A plan view schematically shows that a signal terminal and a multiplexing circuit in a display panel are electrically connected via a switching line for the first embodiment of the present application; Figure 3 This is a schematic diagram of the film structure of the display panel provided in the embodiment of the present application. Figure 1 , Figure 2 and Figure 3 As shown, embodiment 1 of the present application provides a display panel, the display panel having a display area 01 and a frame area 02, the frame area 02 including a first frame area 021 and a second frame area 022 located on opposite sides of the display area 01, the display panel including: a substrate 10; a driving circuit layer 20, arranged on one side of the substrate 10, the driving circuit layer 20 including: a plurality of pixel driving circuits 21 arranged in the display area 01 and a plurality of multiplexing circuits 22 arranged in the first frame area 021, one end of one of the multiplexing circuits 22 being electrically connected to the plurality of pixel driving circuits 21; a signal terminal A, arranged on one side of the substrate 10 and located in the second frame area 022; a first metal layer 30, arranged on a side of the driving circuit layer 20 away from the substrate 10, the first metal layer 30 including a plurality of adapter wires 31, one end of the adapter wire 31 being electrically connected to the corresponding signal terminal A, and the other end of the adapter wire 31 being electrically connected to the other end of the corresponding multiplexing circuit 22.

[0043] In the prior art, the signal terminal A is used to receive the data signal output by the data driver chip (source IC), and the signal terminal A and the multiplexing circuit are both arranged in the second frame area, so that the frame width and wiring density of the second frame area are larger.

[0044] In the display panel provided in the present application, the adapter line 31 spans the second border area 022, the display area 01 and the first border area 021, and is electrically connected to the signal terminal A of the second border area 022 and the multiplexing circuit 22 of the first border area 021, respectively, so that the multiplexing circuit 22 can be set in the first border area 021 of the display panel, and receive the data signal output by the signal terminal A through the adapter line 31, thereby greatly reducing the border width and wiring density of the second border area 022 while ensuring the normal transmission of the data signal, thereby improving the screen-to-body ratio and production yield of the display panel.

[0045] Specifically, the first border area 021 is located on the upper side of the display area 01, and the second border area 022 is located on the lower side of the display area 01. The second border area 022 is provided with the signal terminal A, gate drive circuit winding, VDD routing, test circuit and other circuits. Therefore, the circuit layout of the second border area 022 is relatively dense. The present application transfers the multiplexing circuit 22 to the first border area 021 with a relatively loose circuit layout, thereby avoiding the problem of the second border area 022 having a larger width and an overly dense circuit layout caused by setting the multiplexing circuit 22 in the second border area 022.

[0046] Further, the third frame area 023 is located on the left side of the display area 01, and the fourth frame area 024 is located on the right side of the display area 01. A gate driving circuit is disposed on at least one of the third frame area 023 and the fourth frame area 024, and the gate driving circuit winding is electrically connected to the gate driving circuit.

[0047] In some embodiments of the present application, the driving circuit layer 20 also includes: a plurality of virtual pixel driving circuits (not shown in the figure) arranged in the first border area 021, and the display panel also includes: a light-emitting layer 404, which is arranged on the side of the first metal layer 30 away from the substrate 10, and the light-emitting layer 404 includes: a plurality of light-emitting pixels arranged in the display area 01, the pixel driving circuit 21 is electrically connected to the corresponding light-emitting pixels, and the virtual pixel driving circuit is not electrically connected to the light-emitting pixels in the display area 01; wherein the virtual pixel driving circuit and the multiplexing circuit 22 are both arranged adjacent to the pixel driving circuit 21 of the display area 01.

[0048] In the display panel provided by the present application, the virtual pixel driving circuit is arranged adjacent to the pixel driving circuit 21 of the display area 01, and its function is to prevent external static electricity from directly damaging the pixel driving circuit 21 of the display area 01, and to make the patterned structure of the pixel driving circuit 21 of the display area 01 more uniformly etched during the preparation of the display panel, thereby ensuring the film quality. The present application arranges the virtual pixel driving circuit and the multiplexing circuit 22 adjacent to the pixel driving circuit 21 of the display area 01, so that the multiplexing circuit 22 can also prevent external static electricity from directly damaging the pixel driving circuit 21 of the display area 01 and make the patterned structure of the pixel driving circuit 21 of the display area 01 more uniformly etched.

[0049] Furthermore, the multiplexing circuit 22 is arranged in a gap region between two adjacent virtual pixel driving circuits.

[0050] In the display panel provided by the present application, since the virtual pixel driving circuit will occupy part of the space of the first border area 021, the present application sets the multiplexing circuit 22 in the gap area between two adjacent virtual pixel driving circuits, thereby being able to fully utilize the gap area between two adjacent virtual pixel driving circuits without increasing the width of the first border area 021 to complete the setting of the multiplexing circuit 22.

[0051] Of course, the present application does not require that the virtual pixel driving circuit must be provided in the first border area 021. In other embodiments of the present application, the driving circuit layer 20 does not include a virtual pixel driving circuit, and the multiplexing circuit 22 is provided adjacent to the pixel driving circuit 21 of the display area 01. Since the multiplexing circuit 22 adjacent to the pixel driving circuit 21 can also prevent external static electricity from directly damaging the pixel driving circuit 21 of the display area 01 and make the patterned structure of the pixel driving circuit 21 of the display area 01 etched more uniformly, the virtual pixel driving circuit of the first border area 021 can be omitted.

[0052] Figure 4 This is a schematic plan view of a multiplexing circuit in the first border area provided in the first embodiment of the present application. Figure 3 and Figure 4As shown, in some embodiments of the present application, the driving circuit layer 20 further includes: a first via hole 24, and the adapter line 31 is electrically connected to the multiplexing circuit 22 through the first via hole 24. In order to arrange the multiplexing circuit 22 adjacent to the pixel driving circuit 21 of the display area 01, the first via hole 24 is arranged on a side of the multiplexing circuit 22 away from the display area 01.

[0053] In some embodiments of the present application, the driving circuit layer 20 further includes: a semiconductor layer 203, which is arranged on one side of the substrate 10, and the semiconductor layer 203 includes: a first semiconductor located in the display area 01 and corresponding to the pixel driving circuit 21, and a second semiconductor located in the first frame area 021 and corresponding to the multiplexing circuit 22; a second metal layer 205, which is arranged on a side of the semiconductor layer 203 away from the substrate 10, and the second metal layer 205 includes: a first gate located in the display area 01 and corresponding to the pixel driving circuit 21, and a second gate located in the first frame area 021. 021 and a second gate arranged corresponding to the multiplexing circuit 22; a third metal layer 213 is arranged on a side of the second metal layer 205 away from the substrate 10, and the third metal layer 213 includes: a first source and a first drain located in the display area 01 and corresponding to the pixel driving circuit 21, and a second source and a second drain located in the first border area 021 and corresponding to the multiplexing circuit 22; wherein, the first metal layer 30 is arranged on a side of the third metal layer 213 away from the substrate 10, and the adapter 31 is arranged to at least partially overlap with the pixel driving circuit 21.

[0054] In some embodiments of the present application, the driving circuit layer 20 also includes a fourth metal layer 215, which is arranged on a side of the third metal layer 213 away from the substrate 10, and the fourth metal layer 215 includes: a plurality of data lines 23 in the display area 01, and one end of the multiplexing circuit 22 is electrically connected to the pixel driving circuit 21 through the data line 23.

[0055] Continue to refer to Figure 3 and Figure 4In some embodiments of the present application, each of the multiplexing circuits 22 includes a data bus 221, multiple data branch lines 222 and multiple switch units 223, the data bus 221 is arranged on the second metal layer 205, the data branch line 222 is arranged on the third metal layer 213, and the switch unit 223 includes the second semiconductor, the second gate, the second source and the second drain; wherein, one end of the data bus 221 is electrically connected to the other end of the adapter line 31, the other end of the data bus 221 is electrically connected to one end of the multiple data branch lines 222, the other end of the data branch line 222 is electrically connected to the second source, and the second drain is electrically connected to the data line 23.

[0056] Furthermore, one end of the data bus 221 is electrically connected to the other end of the adapter line 31 through the first via 24 .

[0057] In some embodiments of the present application, each of the multiplexing circuits 22 includes a data bus 221 , four data branch lines 222 and four switch units 223 .

[0058] Among them, in conventional technology, each multiplexing circuit only includes three data branch lines and three switch units, that is, the multiplexing circuit 22 provided in the present application has more wiring and a more complex structure. The present application sets the multiplexing circuit 22 with more wiring and more complex structure in the first border area 021, and sets the multiplexing circuit 22 adjacent to the pixel driving circuit 21 of the display area 01, thereby greatly reducing the border width and wiring density of the second border area 022, improving the screen-to-body ratio and production yield of the display panel, and at the same time preventing external static electricity from directly damaging the pixel driving circuit 21 of the display area 01 and making the patterned structure of the pixel driving circuit 21 of the display area 01 etched more uniformly.

[0059] In some embodiments of the present application, the luminous pixels include: a first luminous pixel with a first luminous color, a second luminous pixel with a second luminous color, and a third luminous pixel with a third luminous color, wherein the four data branch lines 222 in each of the multiplexing circuits 22 are electrically connected to a column of the first luminous pixels, a column of the second luminous pixels, a column of the third luminous pixels, and another column of the second luminous pixels through different data lines 23.

[0060] Further, the light emitting color of the first light emitting pixel is red, the light emitting color of the second light emitting pixel is green, and the light emitting color of the third light emitting pixel is blue.

[0061] Furthermore, the type of the display panel is, for example, an organic light-emitting diode (OLED) display panel. Of course, the present application does not limit the type of the display panel. In other embodiments of the present application, the type of the display panel may also be a liquid crystal display panel or an inorganic light-emitting diode display panel.

[0062] The following is a further introduction to the film structure of the display area 01 of the display panel. Figure 3 In some embodiments of the present application, the substrate 10 includes a first base substrate 101, a first buffer layer 102 and a second base substrate 103 which are stacked in sequence, and the driving circuit layer 20 includes a light-shielding metal layer 201, a second buffer layer 202, a semiconductor layer 203, a first gate insulating layer 204, a second metal layer 205, a second gate insulating layer 206, a fifth metal layer 207, an interlayer dielectric layer 208, an active layer 209, a third gate insulating layer 210, a sixth metal layer 211, a passivation layer 212, the third metal layer 213, a first The flat layer 214, the fourth metal layer 215 and the second flat layer 216; the first metal layer 30 is arranged on the surface of the second flat layer 216 away from the substrate 10; the surface of the first metal layer 30 away from the substrate 10 is covered with a third flat layer 301; the surface of the third flat layer 301 away from the substrate 10 is formed with a light-emitting functional layer 40, and the light-emitting functional layer 40 includes a first electrode layer 401, a pixel definition layer 402, a spacer layer 403, the light-emitting layer 404 and a cathode layer 405 which are sequentially stacked in the direction of the second substrate 103 away from the first substrate 101. Of course, in other embodiments of the present application, the pixel definition layer 402 and the spacer layer 403 can be formed by a single film forming process.

[0063] Furthermore, the first via hole 24 penetrates the second planar layer 216, the first planar layer 214, the passivation layer 212, the third gate insulating layer 210, the interlayer dielectric layer 208 and the second gate insulating layer 206, so that the transfer line 31 located in the first metal layer 30 is electrically connected to the data bus 221 located in the second metal layer through the first via hole 24. It should be noted that the first via hole 24 is formed by at least one etching process.

[0064] On the other hand, the present application further provides a display device, comprising a housing and any one of the display panels described above, wherein the housing has a containing space, and the display panel is disposed in the containing space.

[0065] Embodiment 2

[0066] Figure 5 This is a schematic plan view of a multiplexing circuit in the first border area provided in the second embodiment of the present application. Figure 1-3 and Figure 5 As shown, embodiment 2 of the present application provides a display panel, the display panel having a display area 01 and a frame area 02, the frame area 02 including a first frame area 021 and a second frame area 022 located on opposite sides of the display area 01, the display panel including: a substrate 10; a driving circuit layer 20, arranged on one side of the substrate 10, the driving circuit layer 20 including: a plurality of pixel driving circuits 21 arranged in the display area 01 and a plurality of multiplexing circuits 22 arranged in the first frame area 021, one end of one of the multiplexing circuits 22 being electrically connected to the plurality of pixel driving circuits 21; a signal terminal A, arranged on one side of the substrate 10 and located in the second frame area 022; a first metal layer 30, arranged on a side of the driving circuit layer 20 away from the substrate 10, the first metal layer 30 including a plurality of adapter wires 31, one end of the adapter wire 31 being electrically connected to the corresponding signal terminal A, and the other end of the adapter wire 31 being electrically connected to the other end of the corresponding multiplexing circuit 22.

[0067] The display panel provided in the second embodiment of the present application has a structure similar to that of the display panel in the first embodiment, and the present application will not repeat the same parts. The difference is that the driving circuit layer 20 also includes a fifth metal layer 207, and the fifth metal layer 207 is arranged on the side of the second metal layer 205 away from the substrate 10, and the third metal layer 213 is arranged on the side of the fifth metal layer 207 away from the substrate 10; each of the multiplexing circuits 22 also includes a plurality of electrostatic protection circuits 224, and the second drain is electrically connected to the data line 23 through the electrostatic protection circuit 224; wherein the electrostatic protection circuit 224 includes a first part 2241, and in two adjacent electrostatic protection circuits 224 in the multiplexing circuit 22, the first part 2241 of one of the electrostatic protection circuits 224 is located in the second metal layer 205, and the first part 2241 of the other electrostatic protection circuit 224 is located in the fifth metal layer 207.

[0068] In the display panel provided by the present application, since each of the multiplexing circuits 22 further includes a plurality of electrostatic protection circuits 224, the provision of the electrostatic protection circuits 224 can further enhance the electrostatic protection capability of the multiplexing circuit 22. Moreover, in two adjacent electrostatic protection circuits 224 of the multiplexing circuit 22, the first portion 2241 of one of the electrostatic protection circuits 224 is located in the second metal layer 205, and the first portion 2241 of the other electrostatic protection circuit 224 is located in the fifth metal layer 207, thereby further improving the electrostatic protection capability of the electrostatic protection circuit 224 and reducing interference between the two adjacent electrostatic protection circuits 224 of the multiplexing circuit 22.

[0069] In summary, the present application provides a display panel and a display device, wherein the display panel has a display area and a frame area, wherein the frame area includes a first frame area and a second frame area located on opposite sides of the display area, and the display panel includes: a substrate; a driving circuit layer, arranged on one side of the substrate, wherein the driving circuit layer includes: a plurality of pixel driving circuits arranged in the display area and a plurality of multiplexing circuits arranged in the first frame area, wherein one end of one of the multiplexing circuits is electrically connected to the plurality of pixel driving circuits; a signal terminal, arranged on one side of the substrate and located in the second frame area; a first metal layer, arranged on a side of the driving circuit layer away from the substrate, wherein the first metal layer includes a plurality of adapter wires, wherein one end of the adapter wire is electrically connected to the corresponding signal terminal, and the other end of the adapter wire is electrically connected to the other end of the corresponding multiplexing circuit. The present application arranges the multiplexing circuit in the first frame area, and electrically connects the signal terminal arranged in the second frame area to the multiplexer arranged in the first frame area through the adapter wire, thereby greatly reducing the frame width and routing density of the second frame area, and improving the screen-to-body ratio and production yield of the display panel.

[0070] The above is a detailed introduction to a display panel and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area and a frame area, wherein the frame area includes a first frame area and a second frame area located on two opposite sides of the display area. The display panel comprises: substrate; The driving circuit layer is arranged on one side of the substrate and includes: A plurality of pixel driving circuits are arranged in the display area; a fourth metal layer, comprising a plurality of data lines located in the display area; A plurality of multiplexing circuits are arranged in the first frame area, one end of one of the multiplexing circuits is electrically connected to the plurality of the pixel driving circuits through the data line; and, A plurality of virtual pixel driving circuits are arranged in the first border area; the plurality of virtual pixel driving circuits and the plurality of multiplexing circuits are arranged adjacent to the pixel driving circuit in the display area, and the multiplexing circuit is arranged in a gap area between two adjacent virtual pixel driving circuits; The display panel further includes: A signal terminal is arranged on one side of the substrate and located in the second frame area; a first metal layer, disposed on a side of the driving circuit layer away from the substrate, the first metal layer comprising a plurality of adapter wires, one end of each adapter wire being electrically connected to the corresponding signal terminal, and the other end of each adapter wire being electrically connected to the other end of the corresponding multiplexing circuit; and The light-emitting layer is arranged on a side of the first metal layer away from the substrate, and includes a plurality of light-emitting pixels arranged in the display area. The pixel driving circuit is electrically connected to the corresponding light-emitting pixels, and the virtual pixel driving circuit is not electrically connected to the light-emitting pixels in the display area.

2. The display panel according to claim 1, characterized in that: The transfer line at least partially overlaps with the pixel driving circuit.

3. The display panel according to claim 1, characterized in that: The driving circuit layer further includes a first via hole, and the other end of the adapter line is electrically connected to the other end of the corresponding multiplexing circuit through the first via hole.

4. The display panel according to claim 3, characterized in that: The first via hole is disposed on a side of the multiplexing circuit away from the display area.

5. The display panel according to claim 1, characterized in that: The driving circuit layer also includes: A semiconductor layer is arranged on one side of the substrate, and the semiconductor layer includes: a first semiconductor located in the display area and arranged corresponding to the pixel driving circuit, and a second semiconductor located in the first frame area and arranged corresponding to the multiplexing circuit; A second metal layer is disposed on a side of the semiconductor layer away from the substrate, the second metal layer comprising: a first gate located in the display area and corresponding to the pixel driving circuit, and a second gate located in the first frame area and corresponding to the multiplexing circuit; A third metal layer is arranged on a side of the second metal layer away from the substrate, and the third metal layer includes: a first source and a first drain located in the display area and corresponding to the pixel driving circuit, and a second source and a second drain located in the first border area and corresponding to the multiplexing circuit; wherein the first metal layer is arranged on a side of the third metal layer away from the substrate.

6. The display panel according to claim 5, characterized in that: The fourth metal layer is disposed on a side of the third metal layer away from the substrate.

7. The display panel according to claim 5, characterized in that: Each of the multiplexing circuits comprises a data bus, a plurality of data branch lines and a plurality of switch units, wherein the data bus is arranged on the second metal layer, the data branch lines are arranged on the third metal layer, and the switch unit comprises the second semiconductor, the second gate, the second source and the second drain; Among them, one end of the data bus is electrically connected to the other end of the adapter line, the other end of the data bus is electrically connected to one end of multiple data branch lines, the other end of the data branch line is electrically connected to the second source, and the second drain is electrically connected to the data line.

8. The display panel according to claim 5, characterized in that: The driving circuit layer further includes a fifth metal layer, the fifth metal layer is arranged on a side of the second metal layer away from the substrate, and the third metal layer is arranged on a side of the fifth metal layer away from the substrate; Each of the multiplexing circuits further includes a plurality of electrostatic protection circuits, and the second drain is electrically connected to the data line through the electrostatic protection circuit; The electrostatic protection circuit includes a first part. Among the two adjacent electrostatic protection circuits in the multiplexing circuit, the first part of one of the electrostatic protection circuits is located in the second metal layer, and the first part of the other electrostatic protection circuit is located in the fifth metal layer.

9. The display panel according to any one of claims 1 to 8, characterized in that: Each of the multiplexing circuits comprises a data bus, four data branch lines and four switch units, wherein: The light-emitting pixels include: a first light-emitting pixel having a first light-emitting color, a second light-emitting pixel having a second light-emitting color, and a third light-emitting pixel having a third light-emitting color. Among them, the four data branch lines in each of the multiplexing circuits are electrically connected to a column of the first light-emitting pixels, a column of the second light-emitting pixels, a column of the third light-emitting pixels and another column of the second light-emitting pixels through different data lines.

10. A display device, characterized in that: The display device comprises a housing and a display panel as claimed in any one of claims 1 to 9, wherein the housing has an accommodating space, and the display panel is arranged in the accommodating space.

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