Semiconductor device manufacturing method and plasma processing method

Abstract

A semiconductor device manufacturing method for manufacturing a semiconductor device having a Gate All Around type field effect transistor, includes a step of removing an organic film of an n-type channel, a step of removing a work function control metal film of a bottom surface between channels, a step of forming a protective film on an organic film of a p-type channel, and a step of removing a work function control metal film of the n-type channel.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices and a plasma processing method. Background Technology

[0002] In the continuous improvement of the functionality and performance of integrated circuit chips, transistor miniaturization is indispensable. According to the 2020 edition of the IRDS (International Roadmap for Devices and Systems), the indicator of pattern miniaturization, known as a technology node, is currently the 5nm node, projected to reach the 3nm node in 2024, and further to the 1nm node in 2033. The size combining the actual transistor wiring width and wiring spacing is called the pitch, and half of this is called the half pitch (HP). Generally, it is set at HP15nm for the 5nm node, HP12nm for the 3nm node, and HP8nm for the 1nm node. Furthermore, various discussions are underway regarding the construction and materials of components used to achieve transistor miniaturization and performance improvement.

[0003] Examples include the introduction of deformation into the source / drain regions of a metal oxide semiconductor field-effect transistor (MOSFET), the introduction of highly dielectric gate insulating films and metal, and the introduction of novel structures such as planar to fin-type transistors. Fin-type FETs improve gate controllability by covering the periphery of the three-dimensional fin-type channel with the gate, and suppress the short-channel effect (i.e., increased leakage current) caused by the reduction in gate length accompanying transistor miniaturization.

[0004] Furthermore, recent advancements in miniaturization have led to the development of Gate All Around (GAA) FETs, where the channel is fabricated as a linear or sheet-like stack and surrounded by a gate. GAA FETs completely surround the linear or sheet-like channel (nanowire channel / nanosheet channel) with a gate, thus further improving gate controllability and suppressing short-channel effects compared to Fin FETs. In both Fin and GAA FETs, a gate insulating film, a work function control metal film (WFM), and a high-k gate metal film (HK) are stacked on the FET channel.

[0005] The WFM film determines the threshold voltage required to activate the FET, thus necessitating the use of appropriate metal materials depending on the FET type and application. Consequently, the FET manufacturing process requires replacing the WFM film for each FET type, complicating the process and hindering transistor miniaturization. For example, to fabricate very narrow-pitch n-channel and p-channel FETs separately, it's necessary to remove the WFM film from only one type and then deposit an appropriate metal film on the removed portion. Achieving this process increases the number of steps, presenting various challenges and making it difficult to implement.

[0006] Patent document 1 discloses a method related to the manufacturing process of n-channel FETs and p-channel FETs in the manufacturing process of GAA-type FETs.

[0007] Prior art literature

[0008] Patent documents

[0009] Patent Document 1: U.S. Patent Application Publication No. 2018 / 0308768 Summary of the Invention

[0010] -The technical problem that the invention aims to solve-

[0011] As wiring becomes increasingly miniaturized, narrow-pitch structures with very narrow gate dimensions are gradually emerging. To fabricate narrow-pitch GAA-type FET structures for both n-channel and p-channel FETs, it is necessary to remove the WFM film from only one side and then deposit an appropriate metal film on the removed portion. To achieve this process, multiple repeated film deposition, etching, and mask patterning steps are required, resulting in a large number of steps. Even within these steps, the mask patterning process presents challenges, requiring multiple mask patterning operations on unetched areas. With the recent trend towards narrower pitches, the alignment accuracy of the mask pattern formation is sought at the nanometer level, and this alignment accuracy is gradually reaching its limit.

[0012] According to the technology in Patent Document 1, a method is disclosed whereby, in order to form a WFM film for each type of channel FET in the manufacturing process of a GAA-type FET—in other words, to manufacture an n-channel FET and a p-channel FET—the WFM film in the channel region of one FET is removed, but only the WFM film in the channel region of the other FET is removed. This demonstrates that a suitable WFM film can be formed in the portion of the removed WFM film in the channel region of one FET, simplifying the manufacturing process and thus reducing the increase in the number of steps. In particular, according to the method in Patent Document 1, repeated mask pattern formation is unnecessary, and the alignment of mask patterns, which is extremely difficult to achieve in narrow-pitch formation, is eliminated.Figure 1 The first method described in Patent Document 1. Figure 1 In this context, Rn represents the n-channel FET formation region, and Rp represents the p-channel FET formation region. Figure 1 (A) indicates the etching process of the hard mask 102. Figure 1 (B) indicates the etching process of the organic embedded film 103. Figure 1 (C) indicates the under-etching process of the WFM film 104 in the n-channel FET formation region Rn. Figure 1 (D1) and (D2) represent the reflux process of the organic embedded membrane 103.

[0013] As Figure 1 The cross-sectional structure of the semiconductor device of the sample described in (A) is briefly described. The cross-sectional structure of the semiconductor device is that of the gate portion of a Gate All Around (GAA) type FET, that is, multiple chip-shaped channel layers 106 are stacked together, and the entire periphery of the channel layers 106 is covered by the gate electrode 105 through a gate insulating film (not shown). In this figure, the source and drain regions of the GAA type FET are not shown.

[0014] An n-channel FET formation region Rn for forming an n-channel FET and a p-channel FET formation region Rp for forming a p-channel FET are formed on the surface side of a silicon semiconductor substrate (Si substrate) 107. A WFM film (work function control metal film) 104 is formed on top of an insulating film such as a silicon oxide film formed on the surface side of the semiconductor substrate 107. The semiconductor substrate 107 can also be considered a semiconductor wafer.

[0015] In the n-channel FET formation region Rn, three silicon films (Si films) 106 constituting the channel layer (channel region) of the n-channel FET are disposed along the longitudinal direction, and the entire periphery of each of the three silicon films 106 is covered by an HK film (low-resistance gate metal film) 105. Furthermore, the HK films 105 covering the entire periphery of the three silicon films 106 are each covered by a WFM film 104. A gate insulating film (not shown) is disposed between the silicon films (Si films) 106 and the HK films 105.

[0016] In the p-channel FET formation region Rp, similarly to the n-channel FET formation region Rn, three silicon films 106 constituting the channel layer (channel region) of the p-channel FET are disposed along the longitudinal direction, and the entire periphery of each of the three silicon films 106 is covered by an HK film 105. Furthermore, the entire periphery of each of the HK films 105 covering the periphery of the three silicon films 106 is covered by a WFM film 104. A gate insulating film (not shown) is disposed between the silicon films (Si films) 106 and the HK films 105.

[0017] In the n-channel FET formation region Rn and the p-channel FET formation region Rp, an organic embedded film 103 is formed to cover the upper surface and side surfaces of the WFM film 104. A hard mask film 102 is selectively configured to cover the upper surface of the organic embedded film 103 in the p-channel FET formation region Rp, and a resist mask film 101 is selectively configured to cover the upper side of the hard mask film 102.

[0018] According to the first method of patent document 1 (processing in) Figure 1 (Following the arrows shown in the image, proceed in the direction of (A)->(B)->(C)). First, as... Figure 1 As shown in (A), a hard mask film 102 of SiO2, etc., is etched along the resist mask film 101. Then, as... Figure 1 As shown in (B), a hard mask film 102 is used as an etching mask to etch an organic embedded film 103 containing organic matter, such as an organic planarizing layer (OPL) or a polymethyl methacrylate (PMMA) film, in the n-channel FET formation region Rn. Then, as... Figure 1 As shown in (C), a certain amount of etching (under-etching) is performed on the exposed n-channel FET formation region Rn of the WFM film 104, and the WFM film 104 at the bottom of the n-channel FET formation region Rn and the p-channel FET formation region Rp is removed. As a result, the WFM film 104 is separated at the boundary between the p-channel FET formation region Rp and the n-channel FET formation region Rn, and at the same time, a concave space 111 is formed at the bottom of the organic embedded film 103 of the p-channel FET formation region Rp.

[0019] Although not illustrated, Figure 1 Next, in step (C), a heat treatment (reflow treatment) slightly lower than its glass transition temperature is applied to the organic embedded film 103 of the p-channel FET formation region Rp, thereby slightly melting the organic embedded film 103 of the p-channel FET formation region Rp to fill the concave space 111 formed at the bottom of the organic embedded film 103 in the region Rp. Thus, the WFM film 104 and HK film 105 of the p-channel FET formation region Rp are completely protected by the organic embedded film 103. Next, it is explained that by etching away only the WFM film 104 of the n-channel FET formation region Rn, and forming an appropriate WFM film 104 in the removed portion, both an n-channel FET and a p-channel FET can be formed.

[0020] However, according to the first method in Patent Document 1, temperature control for slightly melting the organic embedded film 103 used to form the p-channel FET region Rp is very difficult. While maintaining the organic embedded film 103 in the p-channel FET region Rp at a temperature slightly lower than its glass transition temperature, and only filling the concave space 111 formed at the bottom of the organic embedded film 103 in that region Rp, it is very difficult to uniformly control the temperature of the entire wafer surface at a temperature slightly lower than the glass transition temperature. For example, in the reflow process of the organic embedded film 103, if heat treatment is performed at a lower temperature than the glass transition temperature, such as... Figure 1 As shown in (D1), the organic embedded film 103 will not melt and cannot fill the concave space 111 formed at the bottom of the organic embedded film 103 in the p-channel FET formation region Rp. During the reflow process of the organic embedded film 103, as... Figure 1 As shown in (D2), conversely, when heat treatment is performed at a temperature equal to or higher than the glass transition temperature, the melting of the embedded organic film 103 is promoted, causing fluid movement of the embedded organic film 103. The melted embedded organic film 103 may cover areas it shouldn't cover, namely the n-channel FET formation region Rn. Furthermore, the promoted melting causes fluid movement of the embedded organic film 103 in the p-channel FET formation region Rp, resulting in embedded organic film defects 112, thus preventing it from achieving its intended function. Therefore, according to the first method of Patent Document 1, the following problem exists: the permissible temperature range is very narrow, and even a very small temperature difference cannot achieve the desired effect.

[0021] Figure 2 This refers to the second method described in Patent Document 1. Figure 2 In this context, Rn represents the n-channel FET formation region, and Rp represents the p-channel FET formation region. Figure 2 (A) indicates the etching process of the hard mask 102. Figure 2 (B) indicates the etching process of the organic embedded film 103. Figure 2 (C) indicates the under-etching process of the WFM film 104 in the n-channel FET formation region Rn. Figure 2 (E) indicates the deposition process of membrane 212. Figure 2 (F) indicates the etching process of film 212.

[0022] According to the second method in Patent Document 1 (processing in) Figure 2 The arrows shown in the image are arranged in the order of (A)->(B)->(C)->(E)->(F). First, as shown in the image... Figure 2 As shown in (A), a hard mask film 102 of SiO2, etc., is etched along the resist mask film 101. Then, as... Figure 2 As shown in (B), the organic buried film 103 containing organic matter in the n-channel FET formation region Rn is etched. Then, as... Figure 2 As shown in (C), a certain amount of etching (under-etching) is performed on the WFM film 104 of the exposed n-channel FET formation region Rn, and the WFM film 104 at the bottom of the n-channel FET formation region Rn and the p-channel FET formation region Rp is removed. As a result, the WFM film 104 is separated at the boundary between the p-channel FET formation region Rp and the n-channel FET formation region Rn, and at the same time, a concave space 111 is formed at the bottom of the organic embedded film 103 of the p-channel FET formation region Rp (same as the first method up to this point).

[0023] Next, as Figure 2 As shown in (E), an atomic layer deposition (ALD) method is used to deposit a SiO2 film, or an oxide film other than SiO2 (hereinafter referred to as SiO2 film) 212, onto the entire surface of the p-channel FET formation region Rp and the n-channel FET formation region Rn with a fixed film thickness. In this case, in principle, regarding its deposition range, the organic embedded film 103 in the p-channel FET formation region Rp, the concave space 111 formed at the bottom of the organic embedded film 103 in the p-channel FET formation region Rp, and the WFM film 104 and HK film 105 in the n-channel FET formation region Rn are deposited one atomic layer at a time, and the deposited film thickness is all the same.

[0024] Next, as Figure 2 As shown in (F), the SiO2 film 212 deposited by ALD is removed by etching. At this point, it is difficult to either selectively leave the SiO2 film 212 formed in the concave space 111 formed at the bottom of the organic embedded film 103 in the p-channel FET formation region Rp unetched, or to slow down the etching rate so that the SiO2 film 212 remains unremoved. Therefore, the WFM film 104 and HK film 105 in the p-channel FET formation region Rp are completely protected by the organic embedded film 103 and the SiO2 film 212 deposited by ALD. Next, it is explained that by etching away only the WFM film 104 in the n-channel FET formation region Rn, and forming an appropriate WFM film 104 in the removed portion, it is possible to form the n-channel FET formation region Rn and the p-channel FET formation region Rp.

[0025] However, according to the second method in Patent Document 1, it is very difficult to achieve the following operation: selectively not etching the SiO2 film 212 formed only in the concave space 111 formed at the bottom of the organic buried film 103 in the p-channel FET formation region Rp, or to slow down the etching rate. Assuming that the size of the concave space 111 formed at the bottom of the organic buried film 103 in the p-channel FET formation region Rp is very small compared to other parts, the etching rate may also be slower than other parts due to the obstruction of etchant penetration, the so-called micro-loading effect. According to the formation process of the concave space 111 formed at the bottom of the organic buried film 103 in the p-channel FET formation region Rp, at least a concave space of the same size must also be formed at the bottom of the n-channel FET formation region Rn. In other words, the concave space 111 formed at the bottom of the organic buried film 103 in the p-channel FET formation region Rp and the concave space formed at the bottom of the n-channel FET formation region Rn are the same size, resulting in the deposition of a film in two spaces of the same size using ALD.

[0026] In other words, it is difficult to selectively omit the SiO2 film 212 deposited in the concave space 111 formed at the bottom of the organic embedded film 103 in the p-channel FET formation region Rp, or to slow down the etching rate so that the SiO2 film 212 is not removed and remains. The reason for this is that if the deposited film 212 deposited in the concave space 111 formed at the bottom of the organic embedded film 103 in the p-channel FET formation region Rp is selectively omitted, or the etching rate is slowed down so that the SiO2 film 212 is not removed and remains, then the SiO2 film in the concave space formed at the bottom of the n-channel FET formation region Rn will also not be removed and will remain.

[0027] According to the second method in Patent Document 1, there is a problem that when a deposited film (212) is formed by ALD, the ALD-based SiO2 film 212 is not left in the concave space 111 formed at the bottom of the organic embedded film 103 in the p-channel FET formation region Rp during subsequent etching.

[0028] The present invention addresses the aforementioned problems by providing a plasma processing method that enables the selective deposition of a protective film (organic film) on the surface of an insulating film (organic embedded film) among a metal film (WFM film and HK film) and an insulating film (organic embedded film) disposed on a substrate.

[0029] -Methods for solving technical problems-

[0030] If we simply describe the outline of a representative solution in this invention, it will be as follows.

[0031] That is, a representative aspect of the present invention relates to a semiconductor device manufacturing method for manufacturing a semiconductor device having a gate-all-around (GAA) field-effect transistor. The semiconductor device manufacturing method includes: a step of removing an organic film from an n-type channel; a step of removing a work function control metal film on the bottom surface between channels; a step of forming a protective film on an organic film in a p-type channel; and a step of removing a work function control metal film from an n-type channel.

[0032] -Invention Effects-

[0033] According to the semiconductor device manufacturing method of the present invention, a protective film can be selectively deposited only on the organic film of the p-type channel. Therefore, the work function control metal film of the p-type channel FET formation region can be completely protected with the protective film. Then, the work function control metal film of the n-type channel FET can be removed only by etching.

[0034] The following description of the implementation methods will make the issues, structures, and effects beyond those described above clearer. Attached Figure Description

[0035] Figure 1 This is a diagram illustrating the first method of Patent Document 1.

[0036] Figure 2 This is a diagram illustrating the second method of Patent Document 1.

[0037] Figure 3 This is a diagram illustrating the structure of the microwave plasma etching apparatus that can be used in this invention.

[0038] Figure 4 This is a flowchart illustrating the etching process of Example 1.

[0039] Figure 5 This is a diagram illustrating surface modification treatment.

[0040] Figure 6 This is a diagram illustrating the organic film deposition process.

[0041] Figure 7 This is a graph representing the analysis results obtained using X-ray photoelectron spectroscopy.

[0042] Figure 8 This is a flowchart of the etching process in Example 2.

[0043] Figure 9 This is a graph representing the thickness of organic membranes. Detailed Implementation

[0044] The embodiments of the present invention will be described below with reference to the accompanying drawings.

[0045] In this embodiment, as a technique for completely protecting the WFM and HK films in the p-channel FET formation region with organic films without relying on heat treatment or ALD, the thickness of the organic films formed on the surfaces of the metal films (WFM and HK films) in the n-channel FET formation region and the organic embedded films in the p-channel FET formation region is controlled based on the difference in incubation time of the surface modification treatment. The incubation time refers to the time from the start of film formation until the generated film-forming species expands to the size of a critical nucleus and appears as a film. Furthermore, this time varies depending on the surface modification treatment conditions.

[0046] In other words, by controlling the incubation time through surface modification treatment, organic films can be selectively formed in the organic embedded membrane. As a processing step, an organic film deposition process is performed after the surface modification treatment, thereby controlling the film thickness of the organic film formed on each surface.

[0047] In this embodiment, in the plasma processing method for selectively forming organic films on WFM and HK films and organic embedded films, the surface modification treatment is performed by controlling the parameters of plasma etching so that the incubation time of WFM and HK films is longer than that of organic embedded films.

[0048] Furthermore, in the plasma processing method for selectively forming organic films on WFM and HK films, it is preferable to control the parameters for plasma etching to perform surface modification and organic film deposition, so that the incubation time of WFM and HK films is longer than that of organic films, and an organic film is formed on the organic film.

[0049] (Example of the overall structure of a plasma processing device)

[0050] A schematic cross-sectional view of a microwave plasma etching apparatus (hereinafter also referred to as a "plasma processing apparatus") 300 that can utilize the ECR (Electron Cyclotron Resonance) method according to one embodiment of the present invention is shown below. Figure 3 In this microwave plasma etching apparatus 300, a cluster plate 302 (e.g., made of quartz) and a dielectric window 303 (e.g., made of quartz) for supplying etching gas into the vacuum container 301 are arranged at the upper part of the vacuum container 301, which is open at the top. By sealing the vacuum container 301, a processing chamber 304, which serves as a plasma processing chamber, is formed. A gas supply device 305 for allowing the etching gas to circulate is connected to the cluster plate 302.

[0051] Furthermore, a vacuum exhaust device 306 is connected to the vacuum container 301 via an exhaust on / off valve 317 and an exhaust speed variable valve 318. Opening the exhaust on / off valve 317 activates the vacuum exhaust device 306, thereby depressurizing the pressure within the processing chamber 304 to a vacuum state depressurized from atmospheric pressure. The pressure within the processing chamber 304 is adjusted to the desired pressure via the exhaust speed variable valve 318.

[0052] Etching gas is supplied from gas supply device 305 into processing chamber 304 via cluster plate 302 and is exhausted by vacuum exhaust device 306 via exhaust speed variable valve 318.

[0053] Furthermore, a sample mounting electrode 311, serving as a sample stage, is disposed at the lower part of the vacuum container 301 opposite to the shower plate 302. Since high-frequency power for plasma generation is supplied to the processing chamber 304, a waveguide 307 for transmitting electromagnetic waves is disposed above the dielectric window 303. Electromagnetic waves transmitted to the waveguide 307 are oscillated from an electromagnetic wave generating power supply 309, which serves as a microwave power source, via a matching converter 319. A pulse generating unit 321 is installed in the electromagnetic wave generating power supply 309, thereby enabling pulse modulation of microwaves at a repetition frequency that can be arbitrarily set. The frequency of the electromagnetic waves is not particularly limited, but in this embodiment, 2.45 GHz microwaves are used.

[0054] A magnetic field generating coil 310 is installed outside the processing chamber 304 to generate a magnetic field. The electromagnetic waves oscillated by the electromagnetic wave generating power supply 309 interact with the magnetic field generated by the magnetic field generating coil 310 to generate high-density plasma in the processing chamber 304, thereby performing etching processing on the wafer 312, which is a sample, arranged on the sample mounting electrode 311, which serves as a sample stage.

[0055] The cluster plate 302, sample mounting electrode 311, magnetic field generating coil 310, exhaust valve 317, exhaust speed variable valve 318, and wafer 312 are coaxially arranged relative to the central axis of the processing chamber 304. Therefore, the flow of etching gas, plasma-generated atomic clusters and ions, and further reaction products generated by etching are coaxially supplied and exhausted relative to the wafer 312. This coaxial arrangement has the effect of making the in-plane uniformity of the etching rate and etched shape of the wafer approach axial symmetry, thus improving the uniformity of the wafer processing. The electrode surface of the sample mounting electrode 311 is covered with a thermally sprayed film (not shown), and a DC power supply 316 is connected to the sample mounting electrode 311 via a high-frequency filter 315. Furthermore, a high-frequency bias power supply 314 is connected to the sample mounting electrode 311 via a matching circuit 313. The high-frequency bias power supply 314 is connected to a pulse generation unit 321, which can selectively supply time-modulated high-frequency power to the sample mounting electrode 311. The frequency of the high-frequency bias is not specifically limited, but in this embodiment a high-frequency bias of 400 kHz is used, and sometimes 800 kHz is used depending on the method.

[0056] The control unit 320, which controls the ECR microwave plasma etching apparatus 300 described above, controls the following parameters through an input unit (not shown): including the repetition frequency and duty cycle of the electromagnetic wave generating power supply 309, the high-frequency bias power supply 314, and the pulse on / off timing of the pulse generating unit 121; and etching parameters such as the gas flow rate, processing pressure, microwave power, high-frequency bias power, coil current, pulse on-time, and off-time.

[0057] Duty cycle refers to the ratio of the on-time to one cycle of the pulse. In this embodiment, the pulse repetition frequency can be varied from 5Hz to 10kHz, and the duty cycle can be varied from 1% to 90%. Furthermore, the time modulation can also be set using the on-time and off-time. Next, an embodiment using the microwave plasma etching apparatus 300 described above will be described.

[0058] [Example 1]

[0059] Figure 4 This illustrates the etching process in Example 1. Figure 4 In this context, Rn represents the n-channel FET formation region, and Rp represents the p-channel FET formation region. Figure 4 (A) represents the etching process that removes the hard mask 102 of the n-channel FET formation region Rn. Figure 4 (B) indicates the etching process that removes the organic embedded film 103 of the n-channel FET formation region Rn. Figure 4(C) represents the under-etching process of the WFM film 104 in the n-channel FET formation region Rn. Through this process, the WFM film 104 on the bottom surface between the channels of the n-channel FET formation region Rn and the p-channel FET formation region Rp is removed. Therefore, Figure 4 (C) can also be referred to as the process of removing the WFM film 104 on the bottom surface between the channels of the n-channel FET formation region Rn and the p-channel FET formation region Rp. Figure 4 (G) indicates the surface modification process. Figure 4 (H) represents the organic film deposition process. Through the surface modification process and the organic film deposition process, a protective film 431 is selectively formed on the organic embedded film 103 in the p-type channel formation region Rp. Therefore, the surface modification process and the organic film deposition process can also be referred to as the process of forming a protective film 431 on the organic film 103 in the p-type channel formation region Rp. The surface modification process can be referred to as the first process, and the organic film deposition process can be referred to as the second process performed after the first process. Figure 4 (I) indicates the process of removing the WFM membrane 104 from the n-type channel forming region Rn. Figure 4 Etching process along Figure 4 The arrows shown in the figure are directed in the order of (A)->(B)->(C)->(G)->(H)->(I).

[0060] about Figure 4 The cross-sectional structure of the semiconductor device described in (A) as a sample will be briefly described. The cross-sectional structure of the semiconductor device is the structure of the gate portion of a Gate All Around (GAA) type FET, that is, multiple chip-shaped channel layers 106 are stacked together, and the entire periphery of the channel layers 106 is covered by the gate electrode 105 through a gate insulating film (not shown). In this figure, the source and drain regions of the GAA type FET are not shown.

[0061] An n-channel FET formation region Rn for forming an n-channel FET and a p-channel FET formation region Rp for forming a p-channel FET are formed on the surface side of a silicon semiconductor substrate (Si substrate) 107. A WFM film (work function control metal film) 104 is formed on top of an insulating film such as silicon oxide film formed on the surface side of the semiconductor substrate 107. The semiconductor substrate 107 can also be considered as a semiconductor wafer.

[0062] In the n-channel FET formation region Rn, three silicon films (Si films) 106 constituting the channel layer (channel region) of the n-channel FET are disposed along the longitudinal direction, and the entire periphery of each of the three silicon films 106 is covered by an HK film (low-resistance gate metal film) 105. Furthermore, the HK films 105 covering the entire periphery of the three silicon films 106 are each covered by a WFM film 104. A gate insulating film (not shown) is disposed between the silicon films (Si films) 106 and the HK films 105.

[0063] In the p-channel FET formation region Rp, similarly to the n-channel FET formation region Rn, three silicon films 106 constituting the channel layer (channel region) of the p-channel FET are disposed along the longitudinal direction, and the entire periphery of each of the three silicon films 106 is covered by an HK film 105. Furthermore, the entire periphery of each of the HK films 105 covering the periphery of the three silicon films 106 is covered by a WFM film 104. A gate insulating film (not shown) is disposed between the silicon films (Si films) 106 and the HK films 105.

[0064] In the n-channel FET formation region Rn and the p-channel FET formation region Rp, the organic embedded film 103 is formed to cover the upper surface and side surfaces of the WFM film 104. The hard mask film 102 is selectively configured to cover the upper surface of the organic embedded film 103 in the p-channel FET formation region Rp, and the resist mask film 101 is selectively configured to cover the upper side of the hard mask film 102. In the sample of this embodiment, a SiO2 film was used as the hard mask film 102, but hard mask films such as SiN can also be used. Furthermore, although an example of an organic film using a BARC (Bottom Anti-Reflective Coat) film is described for the organic embedded film 103, organic films such as OPL (Organic Planarizing Layer) film and PMMA (Polymethyl methacrylate) film can also be used. Furthermore, while examples of using a TiN film for the WFM film (work function control metal film) 104 and an HfO film for the HK film (low resistance gate metal film) 105 are given, appropriate metal materials may be used depending on the type and application of the FET.

[0065] According to Example 1, firstly, as Figure 4 As shown in (A), the SiO2 film 102, which serves as a hard mask, is etched along the resist mask 101. Then, as... Figure 4 As shown in (B), the organic buried film, namely the BARC film 103, in the n-channel FET formation region Rn is etched. Then, as... Figure 4As shown in (C), a certain amount of etching (under-etching) is performed on the exposed WFM film, i.e., the TiN film 104, of the n-channel FET formation region Rn, and the TiN film 104 on the bottom surface (bottom) between the channels of the n-channel FET formation region Rn and the p-channel FET formation region Rp is removed. As a result, the TiN film 104 is separated at the boundary between the p-channel FET formation region Rp and the n-channel FET formation region Rn, and at the same time, a concave space 111 is formed at the bottom of the organic embedded film 103 of the p-channel FET formation region Rp.

[0066] Next, as Figure 4 As shown in (G), surface modification plasma 421 is generated in the processing chamber 304 of the microwave plasma etching apparatus 300 to perform surface modification treatment on the side surface of the BARC film 103 in the p-channel FET formation region Rp (hereinafter, the surface modification treatment is referred to as (G)). Here, in Figure 3 Microwave plasma etching apparatus 300 setting Figure 5 Surface modification treatment (G) was performed under the following surface modification conditions 51: flow rate (100 sccm) and gas pressure (1.0 Pa) of sulfur hexafluoride (SF6) gas, microwave power (600 W) and high-frequency bias power (0 W), and processing time (5 sec). Sulfur hexafluoride (SF6) gas can be referred to as a fluorine-containing gas, a first gas, or a first process gas. In other words, Figure 4 The surface modification process (first process) shown in (G) can be described as a process of exposing plasma generated using fluorine-containing gas to the n-channel FET formation region Rn and the p-channel FET formation region Rp.

[0067] In this embodiment, an example of using SF6 gas as the first gas is described, but other fluorine-containing gases such as nitrogen trifluoride (NF3), trifluoromethane (CHF3), fluoromethane (CH3F), difluoromethane (CH2F2), and perfluorocyclobutane (C4F8), which are commonly used as process gases, may also be used as the first gas.

[0068] Next, as Figure 4 As shown in (H), an organic film deposition process is performed (hereinafter, the organic film deposition process is referred to as (H)). In the organic film deposition process (H), an organic film deposition plasma 422 is generated in the processing chamber 304 to form an organic film (protective film) 431 on the side surface of the BARC film 103 and the space 111 in the p-channel FET formation region Rp. Here, in Figure 3 In the microwave plasma etching apparatus, set Figure 6Organic film deposition was performed under the following conditions (H): a mixed gas containing nitrogen (N2) gas (flow rate: 60 sccm), argon (Ar) gas (flow rate: 288 sccm), and methane (CH4) gas (flow rate: 12 sccm), with a gas pressure of 3.5 Pa, microwave power (1000 W), high-frequency bias power (0 W), and processing time (10 sec). Alternatively, ethane (C2H6), propane (C3H8), or butane (C4H6) gas can be used instead of methane (CH4) gas. 10 Gases containing carbon and hydrogen, such as chloromethane (CH3Cl), dichloromethane (CH2Cl2), and methanol (CH3OH), are included. Methane (CH4) gas can be referred to as a second gas or a second process gas. In other words, Figure 4 The organic film deposition process (second process) shown in (H) can be described as a process that, after the surface modification process (first process), exposes the n-channel FET formation region Rn and the p-channel FET formation region Rp with plasma generated using a gas containing carbon and hydrogen. Furthermore, the processing time (5 seconds) of the surface modification process (first process) is shorter than the processing time (10 seconds) of the organic film deposition process (second process).

[0069] Next, as Figure 4 As shown in (I), the process of removing the WFM film 104 from the n-type channel forming region Rn is carried out.

[0070] Through this organic film deposition process (H), an organic film 431 is formed inside the concave space 111 on the side and bottom of the BARC film 103 in the p-channel FET formation region Rp. At this time, no organic film 431 is formed on the surface of the TiN film 104 and the HfO film 105 in the n-channel FET formation region Rn. Thus, by performing the organic film deposition process (H) after the surface modification process (G), an organic film 431 is selectively formed in the BARC film 103 in the p-channel FET formation region Rp, while no organic film 431 is formed in the WFM film 104 and the HK film 105 in the n-channel FET formation region Rn. Furthermore, by splitting the sample and observing and measuring the cross-section of the organic film 431 using a SEM (Scanning Electron Microscope), it can be determined that the thickness of the organic film 431 is approximately 5 nm.

[0071] Next, in order to investigate the mechanism by which the organic film 431 can be selectively formed on the BARC film 103 in this embodiment, the surfaces of the BARC film 103, TiN film 104, and HfO film 105 were analyzed using X-ray photoelectron spectrophotometry (XPS) before and after the surface modification treatment (G) in this embodiment. The elemental ratio analysis results of each surface of the BARC film 103, TiN film 104, and HfO film 105 are shown below. Figure 7 .exist Figure 7 In the figure, 71 represents the elemental ratio (%) on the surface of BARC film 103, 72 represents the elemental ratio (%) on the surface of HfO film 105, and 73 represents the elemental ratio (%) on the surface of TiN film 104.

[0072] like Figure 7 As shown, a characteristic of the surface modification treatment (G) is that the proportion of fluorine (F) on each film surface increases. In other words, before and after the surface modification treatment (G), the proportion of fluorine (F) changes from 0.9% to 30.7% on the BARC film 103 surface, from 2.4% to 22.0% on the HfO film 105 surface, and from 0.6% to 7.9% on the TiN film 104 surface.

[0073] It is speculated that CF is used on the surface of BARC film 103. x The fluorinated state exists, specifically as TiFx on the surface of TiN film 104 and as HfFx or other fluorinated states on the surface of HfO film 105. As a mechanism considered based on this result, each film surface is fluorinated through surface modification treatment (G), followed by organic film deposition treatment (H) to supply C (carbon) or CH (methyl). It is believed that since the main component of BARC film 103 is C (carbon), the binding between F (fluorine) based on surface modification treatment (G) and C (carbon) based on organic film deposition treatment (H) is stronger, thus it is deposited or adsorbed on the surface of BARC film 103 as CF (carbon fluoride). On the other hand, it is believed that on the surfaces of TiN film 104 and HfO film 105, the fluorinated forms become TiFx (titanium fluoride) and HfFx (hafnium fluoride), which may detach or volatilize.

[0074] Regarding this mechanism, it can also be said that if the processing time of the organic film deposition treatment (H) is 5 seconds, the deposition of organic film 431 cannot be confirmed on the surface of TiN film 104 or HfO film. However, if the processing time of the organic film deposition treatment (H) is set to 10 seconds, the deposition of organic film 431 can be confirmed. It is believed that if the F (fluorine) on the surface of TiN film 104 or HfO film 105 detaches or volatilizes and disappears during the processing time of organic film deposition treatment (H) of 5 to 10 seconds, then organic film 431 is deposited suddenly. It is believed that the aforementioned incubation time control mechanism is also the same.

[0075] In this embodiment, as a technique for completely protecting the p-channel FET formation region Rp with organic film 431 without relying on heat treatment or ALD, the thickness of the organic film 431 formed on the surfaces of BARC film 103, WFM film 104, and HK film 105 is controlled based on the difference in incubation time of the surface modification treatment (G). Here, incubation time refers to the time from the start of film formation until the generated film-forming species expands to the size of the critical nucleus and appears as a film. In addition, this time varies depending on the surface modification treatment conditions (see 51).

[0076] In other words, by using surface modification treatment (G) to control the incubation time, an organic film 431 can be selectively formed on the surface of the organic embedded film 103. As a processing step, an organic film deposition treatment (H) is performed after the surface modification treatment (G), thereby controlling the film thickness of the organic film 431 formed on the respective surfaces of the BARC film 103, WFM film 104, and HK film 105.

[0077] In this embodiment, in the plasma processing method for selectively forming organic film 431 on organic embedded film 103 for WFM film 104 and HK film 105, the surface modification treatment (G) is performed by controlling the plasma etching parameters (51) so that the incubation time of organic film 431 relative to WFM film 104 and HK film 105 is longer than the incubation time of organic film 431 relative to organic embedded film 103.

[0078] Furthermore, in the plasma processing method for selectively forming organic film 431 on organic embedded film 103 for WFM film 104 and HK film 105, it is preferable to control the plasma etching parameters (51, 61) to perform surface modification treatment (G) and organic film deposition treatment (H), so that the incubation time of organic film 431 relative to WFM film 104 and HK film 105 is longer than the incubation time of organic film 431 relative to organic embedded film 103, and organic film 431 is formed on organic embedded film 103.

[0079] [Example 2]

[0080] exist Figure 8 A flowchart illustrating the etching process of Example 2. Figure 9 It indicates that it has been implemented. Figure 8 The thickness of the organic film during the process was determined. In Example 1, the sample after surface modification treatment (G) and organic film deposition treatment (H) was split open, and the cross-section of the formed organic film 431 was observed and measured by SEM. The results showed that the thickness of the organic film 431 was approximately 5 nm. Next, in Example 2, a method for increasing the thickness of the organic film 431 to be formed will be described.

[0081] As in Example 1 Figure 4 In order to further increase the thickness of the organic film 431 only on the surface of the BARC film 103, the organic film 431 is prevented from depositing on the surfaces of the TiN film 104 and the HfO film 105 by increasing the incubation time, thus preventing the depletion of F (fluorine). On the surface of the BARC film 103, the thickness of the organic film 431 is increased by increasing the processing time of the organic film deposition treatment (H).

[0082] right Figure 8 The etching process of Example 2 will be described.

[0083] (Step S1: SiO2 film etching process)

[0084] like Figure 4 As shown in (A), the SiO2 film 102, which serves as a hard mask, is etched along the resist mask film 101.

[0085] (Step S2: Organic Embedded Film Etching Process)

[0086] like Figure 4 As shown in (B), the organic buried film, namely the BARC film 103, of the n-channel FET formation region Rn is etched.

[0087] (Step S3: WFM film under-etching process)

[0088] like Figure 4 As shown in (C), a certain amount of etching (under-etching) is performed on the WFM film, i.e. the TiN film 104, of the exposed n-channel FET formation region Rn, and the TiN film 104 at the bottom of the n-channel FET formation region Rn and the p-channel FET formation region Rp is removed.

[0089] (Step S4: Surface modification treatment process)

[0090] like Figure 4As shown in (G), surface modification plasma 421 is generated in the processing chamber 304 of the microwave plasma etching apparatus 300 to perform surface modification treatment on the side surface of the BARC film 103 in the p-channel FET formation region Rp. The surface modification treatment utilizes... Figure 5 The surface modification treatment conditions shown are 51.

[0091] (Step S5: Organic film deposition process)

[0092] like Figure 4 As shown in (H), an organic film deposition process is performed. In the organic film deposition process, an organic film deposition plasma 422 is generated within the processing chamber 304, forming an organic film 431 on the side surface of the BARC film 103 in the p-channel FET formation region Rp and in the space 111. The organic film deposition process utilizes... Figure 6 Organic film deposition treatment conditions 61 as shown.

[0093] (Repeated multiple times)

[0094] Then, steps S4 and S5 are repeated multiple times. The number of repetitions is set to n. Here, the value of n is set so that the thickness of the organic membrane 431 becomes the desired thickness value.

[0095] (Step S6: Organic membrane thickness measurement process)

[0096] Then, the thickness of organic membrane 431 was measured.

[0097] It should be noted that, although in Figure 8 Not illustrated, but after confirming in step S6 that the thickness of the organic film 431 has reached the desired thickness value, as shown... Figure 4 As shown in (I), the process of removing the WFM film 104 from the n-type channel forming region Rn is carried out.

[0098] like Figure 9 As shown, when the number of repetitions n is 1, the thickness of the organic film 431 is, for example, 5 nm. When the number of repetitions n is 2, the thickness of the organic film 431 is, for example, 9 nm. When the number of repetitions n is 3, the thickness of the organic film 431 is, for example, 14 nm.

[0099] like Figure 9 As shown, by repeatedly performing step S4 (surface modification process) to step S5 (organic film deposition process) multiple times (n times), the thickness of the organic film 431 can be prevented from increasing on the surface of TiN film 104 and HfO film 105, while the thickness of the organic film 431 can be increased on the surface of BARC film 103.

[0100] In this embodiment, an application example of a microwave plasma etching apparatus using the ECR (Electron Cyclotron Resonance) method with microwaves has been described, but it is not limited to this. Plasma etching apparatuses using capacitively coupled or inductively coupled plasma generation units can also be used.

[0101] As described above, in the plasma processing method for selectively forming organic films on WFM and HK films according to this embodiment, the plasma etching parameters are controlled so that the incubation time of the WFM and HK films is longer than that of the organic embedded film. Surface modification and organic film deposition processes are then performed, thereby enabling the selective formation of organic films only on the organic embedded film. Furthermore, through repeated surface modification and organic film deposition processes, the thickness of the organic film formed on the organic embedded film is increased.

[0102] The invention described above is based on specific embodiments, but the invention is not limited to the above embodiments. Various modifications can be made without departing from its spirit. For example, the above embodiments have been described in detail for ease of understanding, but it is not necessarily limited to having all the described structures. Furthermore, regarding a part of the structure of each embodiment, other structures can be added to, deleted from, or replaced.

[0103] -Explanation of Figure Markers-

[0104] 101···Resist Mask

[0105] 102··· Rigid mask

[0106] 103···Organic Embedded Membrane (Organic Membrane)

[0107] 104···WFM membrane (work function controlled metal membrane)

[0108] 105···HK film (low resistance gate metal film)

[0109] 106···Si film (channel layer)

[0110] 107···Si substrate

[0111] 111··· Concave space

[0112] 421··· Plasma for Surface Modification

[0113] 422··· Plasma for Organic Film Deposition

[0114] 431··· Organic membrane (protective membrane).

Claims

1. A method for manufacturing a semiconductor device, comprising manufacturing a semiconductor device having a full-ring gate field-effect transistor, The semiconductor device manufacturing method is characterized by having: The process of removing the organic membrane from the n-type channel; The process of removing the metal film by controlling the work function of the bottom surface between the channels; The process of forming a protective film on an organic membrane in a p-type channel; and The process of removing metal film by controlling the work function of an n-type channel. The process of forming the protective film includes: a first step of exposing plasma generated using fluorine-containing gas to the n-type channel and the p-type channel.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The process of forming the protective film further includes a second step, after the first step, exposing the n-type channel and the p-type channel to plasma generated using a gas containing carbon and hydrogen.

3. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The processing time of the first process is shorter than that of the second process.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The fluorine-containing gas is SF6 gas, NF3 gas, CHF3 gas, CH3F gas, CH2F2 gas, or C4F8 gas.

5. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The gas containing carbon and hydrogen is methane gas.

6. The method for manufacturing a semiconductor device according to claim 2, characterized in that, The plasma in the second process is generated using a mixture of methane, nitrogen, and argon.

7. A plasma processing method for forming a full-ring gate field-effect transistor. The plasma treatment method is characterized by having: The process of removing the organic membrane from the n-type channel; The process of removing the metal film by controlling the work function of the bottom surface between the channels; The process of forming a protective film on an organic membrane in a p-type channel; and The process of removing metal film by controlling the work function of an n-type channel. The process of forming the protective film includes: a first step of exposing plasma generated using fluorine-containing gas to the n-type channel and the p-type channel.

8. The plasma treatment method according to claim 7, characterized in that, The process of forming the protective film further includes a second step, after the first step, exposing the n-type channel and the p-type channel to plasma generated using a gas containing carbon and hydrogen.

9. The plasma treatment method according to claim 8, characterized in that, The processing time of the first process is shorter than that of the second process.

10. The plasma treatment method according to claim 7, characterized in that, The fluorine-containing gas is SF6 gas, NF3 gas, CHF3 gas, CH3F gas, CH2F2 gas, or C4F8 gas.

11. The plasma treatment method according to claim 8, characterized in that, The gas containing carbon and hydrogen is methane gas.

12. The plasma treatment method according to claim 8, characterized in that, The plasma in the second process is generated using a mixture of methane, nitrogen, and argon.

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