A circuit and method for improving the test accuracy of chip testing equipment

Abstract

A circuit and method for improving the test accuracy of chip testing equipment, characterized in that: the circuit includes a DUT signal generating unit, a synchronous clock signal generating unit, a first switch unit, a second switch unit and a subtractor; wherein the DUT signal generating unit transmits the DUT signal to the first switch unit; the synchronous clock signal generating unit is used to collect the DUT signal to update the clock signal, and send the updated clock signal to the subtractor based on the control of the second control signal; the first switch unit is used to control the DUT signal input into the second switch unit, and control the on or off state of the synchronous clock signal generating unit; the second switch unit is used to control the synchronous clock signal input into the subtractor; the subtractor is used to generate a high-precision signal to be tested. The circuit in the present invention can protect the test equipment, improve the signal to be tested, and has a simple structure, low cost, good effect, and wide application.

Description

Technical Field

[0001] The present invention relates to the field of chip testing, and more specifically, to a circuit and method for improving the testing accuracy of chip testing equipment. Background Art

[0002] In the prior art, dedicated chip testing equipment is usually used to perform FT (Final Test) on the chips before they leave the factory. In the final test, various parameters of the output signal of the chip under test are tested, for example, the frequency, duty cycle, time quantity, multiple transition times and other information of the output signal of the chip under test are collected. It can be seen that the above information that needs to be collected has high requirements for the time collection accuracy of the chip testing equipment.

[0003] However, the mainstream chip testing equipment on the market has limited testing accuracy. With the development of the integrated circuit industry, the requirements for chip testing parameter accuracy are becoming increasingly higher. The time acquisition accuracy of chip testing seriously restricts the development of chip products and their competitiveness in the market.

[0004] In addition, since the mainstream chip testing equipment on the market has a high accuracy, most chip testing equipment is within the scope of testing the small signal output by the chip. When the chip inputs an excessively large signal into the chip testing equipment, it may easily affect the safety of the chip testing equipment. There is no method in the prior art that can simultaneously improve the accuracy of the signal to be tested and protect the chip testing equipment.

[0005] Therefore, there is an urgent need for a circuit and method that can improve the test accuracy of chip testing equipment. Summary of the invention

[0006] In order to solve the deficiencies in the prior art, the purpose of the present invention is to provide a circuit and method for improving the test accuracy of chip testing equipment, by adding an improvement circuit between the chip to be tested and the chip testing equipment, so that the test signal output in the improvement circuit has better level jump performance and a more stable waveform.

[0007] The present invention adopts the following technical solutions. In the first aspect, the present invention relates to a circuit for improving the test accuracy of a chip test device, characterized in that: the circuit includes a DUT signal generating unit, a synchronous clock signal generating unit, a first switch unit, a second switch unit and a subtractor; wherein the DUT signal generating unit is connected to the synchronous clock signal generating unit and the first switch unit, and is used to transmit the DUT signal to the synchronous clock signal generating unit and the first switch unit; the synchronous clock signal generating unit is connected to the DUT signal generating unit, the first switch unit and the second switch unit, and is used to realize turning on or off based on the first control signal of the first switch unit, and collect the DUT signal to update the clock signal, and send the updated clock signal to the subtractor based on the control of the second control signal of the second switch unit; the first switch unit, The control unit is connected to the DUT signal generating unit, the synchronous clock signal generating unit, the second switch unit and the subtractor respectively, and is used to generate a first control signal and control the DUT signal generating unit to input the generated DUT signal into the second switch unit, and is used to control the on or off state of the synchronous clock signal generating unit; the second switch unit is connected to the first switch unit, the synchronous clock signal generating unit and the subtractor, and is used to receive the first control signal from the first switch unit, and generate a second control signal based on the first control signal to control the synchronous clock signal to be input into the subtractor; the subtractor is connected to the first control unit and the second control unit, and is used to collect and calculate the DUT signal from the first control unit and the synchronous clock signal from the second control unit to generate a high-precision test signal.

[0008] Preferably, the first switch unit includes a first comparator and a first PMOS tube T1; wherein the positive phase input terminal of the first comparator is connected to the DUT signal generating unit, and the negative phase input terminal is connected to the reference signal Vref1; the output terminals are respectively connected to the gate of the first PMOS tube T1 and the synchronous clock signal generating unit; the drain of the first PMOS tube T1 is connected to the DUT signal generating unit, and the source is respectively connected to the second switch unit and the subtractor.

[0009] Preferably, the second switch unit comprises an OR gate, a second comparator and a second PMOS tube T2; wherein one input end of the OR gate is connected to the source of the first PMOS tube T1 in the first switch unit, the other input end is grounded, and the output end is connected to the positive phase input end of the second comparator; the negative phase input end of the second comparator is grounded, and the output end is connected to the gate of the second PMOS tube T2; the drain of the second PMOS tube T2 is connected to the synchronous clock signal generating unit, and the source is connected to the subtractor.

[0010] Preferably, both the first comparator and the second comparator are ultra-high-speed comparators.

[0011] Preferably, the synchronous clock signal generating unit comprises an AND gate and a synchronous clock signal generator; wherein one input end of the AND gate is connected to the DUT signal generating unit to receive the DUT signal, the other input end is connected to the synchronous clock signal generator, and the output end is connected to the synchronous clock signal generator to feed back the output end signal of the AND gate to the synchronous clock signal generator; the output end of the synchronous clock signal generator is connected to the drain of the second PMOS tube T2.

[0012] Preferably, the positive input terminal of the subtractor is connected to the source of the first PMOS tube T1 in the first switch unit, the negative input terminal is connected to the source of the second PMOS tube T2 in the second switch unit, and the output terminal is output to the chip testing equipment as a high-precision test signal Vo.

[0013] Preferably, the operational amplifier in the subtractor is an ultra-high-speed operational amplifier.

[0014] Preferably, in the subtractor, the resistor R1 connected to the negative phase input terminal, the feedback resistor R2 between the negative phase input terminal and the output terminal, the resistor R3 connected to the positive phase input terminal, and the resistor R4 grounded at the positive phase input terminal are all high-precision resistors with the same resistance value.

[0015] Preferably, in the subtractor, the resistance values ​​of the resistor R1 connected to the negative phase input terminal, the feedback resistor R2 between the negative phase input terminal and the output terminal, the resistor R3 connected to the positive phase input terminal, and the resistor R4 grounded at the positive phase input terminal are determined based on the amplitude of the DUT signal.

[0016] A second aspect of the present invention relates to a method for improving the test accuracy of a chip test device. The method is implemented using a circuit for improving the test accuracy of a chip test device as described in the first aspect of the present invention.

[0017] The beneficial effect of the present invention lies in that, compared with the prior art, a circuit and method for improving the test accuracy of a chip testing device in the present invention can add an improvement circuit between the chip to be tested and the chip testing device, so that the test signal output in the improvement circuit has better level jump performance and a more stable waveform.

[0018] The beneficial effects of the present invention also include:

[0019] 1. Since the output signal to be tested has higher accuracy, the test accuracy of the chip test equipment is effectively improved;

[0020] 2. The improved circuit structure of the present invention is simple, low-cost, and effective, and can be effectively compatible with various chip testing equipment;

[0021] 3. The improved circuit in the present invention utilizes the protection level of the chip test equipment as a reference voltage, thereby ensuring that the high-precision test signal output by the circuit will not damage the performance of the chip test equipment, thereby ensuring the safety of the chip test equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of circuit connections when a chip testing device in the prior art of the present invention performs chip testing;

[0023] Figure 2 A schematic diagram of the circuit structure of a circuit for improving the test accuracy of a chip test device in the present invention;

[0024] Figure 3 A schematic diagram of a waveform structure of a test signal obtained when a chip testing device in the prior art of the present invention performs chip testing;

[0025] Figure 4 The present invention is a schematic diagram of a waveform structure of a test signal obtained when a circuit for improving the test accuracy of a chip test device performs chip testing. DETAILED DESCRIPTION

[0026] The present application is further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and cannot be used to limit the protection scope of the present application.

[0027] Figure 1 FIG. 1 is a schematic diagram of circuit connection when a chip testing device in the prior art of the present invention performs chip testing. Figure 1 As shown, a chip testing device is connected to a DUT (Device Under Test) to detect the output signal of the DUT. In one embodiment of the present invention, the DUT may be a batch of chips under test, and the DUT signal refers to the device under test signal, which may be a signal from the chip under test in the present invention.

[0028] At present, the prior art has chip testing equipment of various manufacturers, functions, principles, etc. In the present invention, in order to realize the collection of time information such as frequency, duty cycle, time quantity, multiple transition moments, etc. of the chip signal to be tested, a device that can accurately measure the time parameters of the signal is selected. In one embodiment of the present invention, the chip testing equipment is a QTMU device produced by AccoTEST. Each module in the device can support multiple time measurement channels, and can configure channels according to the user's choice, thereby saving a lot of test time. In addition, the QTMU device can support the measurement of multiple time parameters such as edges, pulses, delays, frequencies and duty cycles. The highest resolution of the time quantity reaches 65ps, and the maximum frequency measurement range reaches about 10MHz.

[0029] However, the signal to be tested output by the chip may have various problems such as slow switching speed, burrs, delay, etc. during the high and low level switching process, resulting in signal errors, making it impossible for the QTMU device to accurately parse the signal to be tested, thereby seriously restricting the test accuracy of the QTMU device. With the development of the integrated circuit industry, the requirements for the accuracy of chip test parameters are getting higher and higher. In order to improve the test accuracy of QTMU equipment and various chip test equipment, the present invention provides a circuit and method for improving the test accuracy of chip test equipment.

[0030] Figure 2 FIG. 1 is a schematic diagram of a circuit structure of a circuit for improving the test accuracy of a chip test device in the present invention. Figure 2 As shown, the first aspect of the present invention relates to a circuit for improving the test accuracy of a chip test device, the circuit comprising a DUT signal generating unit, a synchronous clock signal generating unit, a first switch unit, a second switch unit and a subtractor; wherein the DUT signal generating unit is connected to the synchronous clock signal generating unit and the first switch unit, and is used to transmit the DUT signal to the synchronous clock signal generating unit and the first switch unit; the synchronous clock signal generating unit is connected to the DUT signal generating unit, the first switch unit and the second switch unit, and is used to realize turning on or off based on a first control signal of the first switch unit, and to collect the DUT signal to update the clock signal, and to send the updated clock signal to the subtractor based on the control of the second control signal of the second switch unit; the first switch unit, The control unit is connected to the DUT signal generating unit, the synchronous clock signal generating unit, the second switch unit and the subtractor respectively, and is used to generate a first control signal and control the DUT signal generating unit to input the generated DUT signal into the second switch unit, and is used to control the on or off state of the synchronous clock signal generating unit; the second switch unit is connected to the first switch unit, the synchronous clock signal generating unit and the subtractor, and is used to receive the first control signal from the first switch unit, and generate a second control signal based on the first control signal to control the synchronous clock signal to be input into the subtractor; the subtractor is connected to the first control unit and the second control unit, and is used to collect and calculate the DUT signal from the first control unit and the synchronous clock signal from the second control unit to generate a high-precision test signal.

[0031] Preferably, the first switch unit includes a first comparator and a first PMOS tube T1; wherein the positive phase input terminal of the first comparator is connected to the DUT signal generating unit, and the negative phase input terminal is connected to the reference signal Vref1; the output terminals are respectively connected to the gate of the first PMOS tube T1 and the synchronous clock signal generating unit; the drain of the first PMOS tube T1 is connected to the DUT signal generating unit, and the source is respectively connected to the second switch unit and the subtractor.

[0032] Specifically, when the DUT signal is in an abnormal state, the amplitude of the DUT signal is large and will be greater than the reference voltage Vref1. The reference voltage Vref1 can be a protection level of the chip test equipment. When the first switch unit detects that the DUT signal is in an abnormal state, it can control the circuit at its back end to be in a closed state, so that the chip test equipment, such as the QTMU device, can be protected.

[0033] It can be understood that the control principle is to input the DUT signal and the reference voltage to the positive input terminal and the negative input terminal of the first comparator respectively, and select the output high level or low level according to the comparison result of the DUT signal and the reference voltage. When the DUT signal is greater than the reference voltage, a high level is output, so that the first PMOS tube T1 is turned off. At the same time, the high level controls the AND gate and the synchronous clock signal in the synchronous clock unit to be in the off state. When the DUT signal is less than the reference voltage, the DUT signal is in a normal state. At this time, the first comparator outputs a low level, so that the first PMOS tube T1 is turned on, and the AND gate and the clock signal generator enter the working state at the same time.

[0034] When the first PMOS tube T1 is turned on, the DUT signal will enter the second switch unit and the subtractor through the source-drain conduction current of the first PMOS tube.

[0035] Preferably, the second switch unit comprises an OR gate, a second comparator and a second PMOS tube T2; wherein one input end of the OR gate is connected to the source of the first PMOS tube T1 in the first switch unit, the other input end is grounded, and the output end is connected to the positive phase input end of the second comparator; the negative phase input end of the second comparator is grounded, and the output end is connected to the gate of the second PMOS tube T2; the drain of the second PMOS tube T2 is connected to the synchronous clock signal generating unit, and the source is connected to the subtractor.

[0036] When the DUT signal is in a normal working state, the second switch unit detects the DUT signal output from the first switch unit and starts the working state. Specifically, after receiving the DUT signal, one input end of the OR gate performs an OR operation with the ground potential and inputs it into the second comparator. After the second comparator compares the DUT signal with the ground potential, it outputs it to the gate of the second PMOS tube T2 to control the conduction or cutoff of the second PMOS tube T2 according to the high and low potentials of the DUT signal. Specifically, when the output of the DUT signal is a high potential, the second PMOS tube T2 is cut off; when the output of the DUT signal is a low potential, the second PMOS tube T2 is turned on. When the second PMOS tube is turned on, the clock signal from the synchronous clock signal production unit can be output to the subtractor.

[0037] Since the DUT signal used for testing is a bipolar signal with both positive and negative pulses, an OR gate is used in the present invention to convert the bipolar signal into a unipolar signal to adapt to the subtractor in the circuit. The second switch unit in the present invention, after the operation of the OR gate and the second comparator, can also synchronize the DUT signal output by the synchronous clock signal generating unit with the synchronous clock signal.

[0038] Preferably, the first comparator and the second comparator are both ultra-high-speed comparators. In order to ensure that the output signal has high precision, various devices in the circuit of the present invention should have a high and relatively accurate response rate.

[0039] Specifically, ultra-high-speed comparators with small propagation delays on the market can be used, such as comparators with propagation delays between 1ns and 2ns. With the development of products, ps-level comparators can also be used in the future, thereby improving the response rate of the overall circuit and minimizing output noise.

[0040] Preferably, the synchronous clock signal generating unit comprises an AND gate and a synchronous clock signal generator; wherein one input end of the AND gate is connected to the DUT signal generating unit to receive the DUT signal, the other input end is connected to the synchronous clock signal generator, and the output end is connected to the synchronous clock signal generator to feed back the output end signal of the AND gate to the synchronous clock signal generator; the output end of the synchronous clock signal generator is connected to the drain of the second PMOS tube T2.

[0041] Specifically, the AND gate compares the fixed state from the synchronous clock signal, and after performing AND operation on the DUT signal, the feedback generated at the output end is input into the synchronous clock signal. The synchronous clock signal generator can generate a synchronous clock signal based on the feedback, which is completely synchronized with the high and low level switching frequency of the DUT signal.

[0042] After the synchronous clock signal generating unit generates the synchronous clock signal, the synchronous clock signal is input into the subtractor based on the switching state of the second PMOS tube in the second switching unit.

[0043] Preferably, the positive input terminal of the subtractor is connected to the source of the first PMOS tube T1 in the first switch unit, the negative input terminal is connected to the source of the second PMOS tube T2 in the second switch unit, and the output terminal is output to the chip testing equipment as a high-precision test signal Vo.

[0044] It can be understood that when the second PMOS tube is turned on, the clock signal from the synchronous clock signal production unit can be output to the subtractor. That is, when the DUT signal outputs a high level, the subtractor will perform a subtraction operation on the DUT signal and the clock signal. When the DUT signal output is a low level, the subtractor directly outputs the DUT signal. Therefore, by using the circuit in the present invention, the part of the DUT signal that exceeds the clock signal can be cut off, thereby reducing the switching time when at least half of the DUT signal is switched between high and low levels, reducing a large number of glitches generated by the DUT signal during the level switching process, and making the output signal to be tested more accurate.

[0045] Preferably, the operational amplifier in the subtractor is an ultra-high-speed operational amplifier.

[0046] Specifically, in order to make the subtractor have good and accurate response performance and the output waveform have higher precision, the operational amplifier therein can be set to an ultra-high-speed operational amplifier, and the high-speed operational amplifier can have a larger SR (Slew Rate) and stronger driving capability.

[0047] In the present invention, an ultra-high-speed operational amplifier with a large bandwidth and a high SR on the market can be used according to the DUT signal to be tested. For example, an ultra-high-speed operational amplifier AD8000 is selected, which has an output current of 100mA, a bandwidth of 1.5GHz, and a slew rate of 4100V / μs.

[0048] Preferably, in the subtractor, the resistor R1 connected to the negative phase input terminal, the feedback resistor R2 between the negative phase input terminal and the output terminal, the resistor R3 connected to the positive phase input terminal, and the resistor R4 grounded at the positive phase input terminal are all high-precision resistors with the same resistance value.

[0049] Preferably, in the subtractor, the resistance values ​​of the resistor R1 connected to the negative phase input terminal, the feedback resistor R2 between the negative phase input terminal and the output terminal, the resistor R3 connected to the positive phase input terminal, and the resistor R4 grounded at the positive phase input terminal are determined based on the amplitude of the DUT signal. For example, 50ohm≤R≤100ohm, where R is the resistance value of resistors R1 to R4. In order to ensure the good output performance of the subtractor, resistors with high precision should be selected. In order to avoid the influence of too large resistance on the output unit, in the present invention, a 100ohm resistor is selected as the above four resistors. Because the resistance values ​​of the four resistors are equal, the output of the subtractor is V O =V1-V2.

[0050] Specifically, the output of the subtractor in the present invention is modulated by the DUT signal V from the first switch unit. DUT , the synchronous clock signal V modulated by the second switch unit CLK Related.

[0051] According to the principle of the subtractor, the non-inverting input terminal of the subtractor is:

[0052] V DUT =(R3 / R4+1)·V1=2V1

[0053] The negative input of the subtractor is:

[0054] V CLK =(R1 / R2+1)·V2-V O / R2=2V2-V O / R

[0055] Solving the formula, we can get:

[0056] V1=R4·V DUT / (R3+R4)=V DUT / 2

[0057] V2=(V CLK ·R t +V O ) / (R1+R2)=R2 / 2+V o / (R1+R2)

[0058] It can be seen that the output of the subtractor is:

[0059] V O =V1-V2=R4·V DUT / (R3+R4)-(V CLK R2+V O ) / (R1+R2)

[0060] Then there is,

[0061] When R1=R2=R3=R4=R,

[0062] V O =(V DUT -V CLK )R / (2R-1)≈(V DUT -V CLK ) / 2.

[0063] Figure 3 FIG. 1 is a schematic diagram of a waveform structure of a test signal obtained when a chip test device in the prior art of the present invention performs chip testing. Figure 3As shown in the figure, due to the performance limitation of the chip to be tested, or the signal connected from the PCB path for the purpose of testing is interfered by the PCB path, the chip output signal directly output to the chip test equipment, or output to the chip test equipment after simple shaping by the comparator, has poor effect. Specifically, there are many glitches in the process of high and low level switching of the signal, resulting in uncertain switching time, long switching time, and easy to cause bit errors.

[0064] Figure 4 The waveform structure diagram of the test signal obtained when the circuit for improving the test accuracy of the chip test equipment in the present invention performs chip testing. Figure 4 As shown, the circuit in the present invention not only ensures that the output voltage of the DUT signal will not be too high, but also shapes the DUT signal based on the clock signal, thereby reducing signal glitches, determining the switching time, reducing bit errors, and ensuring the test accuracy of chip testing equipment, such as QTMU equipment.

[0065] The second aspect of the present invention relates to a method for improving the test accuracy of a chip test device, wherein the method is implemented by a circuit for improving the test accuracy of a chip test device as described in the first aspect of the present invention.

[0066] The beneficial effect of the present invention lies in that, compared with the prior art, a circuit and method for improving the test accuracy of a chip testing device in the present invention can add an improvement circuit between the chip to be tested and the chip testing device, so that the test signal output in the improvement circuit has better level jump performance and a more stable waveform.

[0067] The beneficial effects of the present invention also include:

[0068] 1. Since the output signal to be tested has higher accuracy, the test accuracy of the chip test equipment is effectively improved;

[0069] 2. The improved circuit structure of the present invention is simple, low-cost, and effective, and can be effectively compatible with various chip testing equipment;

[0070] 3. The improved circuit in the present invention utilizes the protection level of the chip test equipment as a reference voltage, thereby ensuring that the high-precision test signal output by the circuit will not damage the performance of the chip test equipment, thereby ensuring the safety of the chip test equipment.

[0071] The applicant of the present invention has made a detailed explanation and description of the implementation examples of the present invention in conjunction with the drawings in the specification. However, those skilled in the art should understand that the above implementation examples are only preferred implementation schemes of the present invention, and the detailed description is only to help readers better understand the spirit of the present invention, but not to limit the scope of protection of the present invention. On the contrary, any improvements or modifications based on the inventive spirit of the present invention should fall within the scope of protection of the present invention.

Claims

1. A circuit for improving the test accuracy of a chip test device, characterized in that: The circuit includes a DUT signal generating unit, a synchronous clock signal generating unit, a first switch unit, a second switch unit and a subtractor; wherein, The DUT signal generating unit is connected to the synchronous clock signal generating unit and the first switch unit, and is used to transmit the DUT signal to the synchronous clock signal generating unit and the first switch unit; The synchronous clock signal generating unit is connected to the DUT signal generating unit, the first switch unit, and the second switch unit, and is used to realize turning on or off based on the first control signal of the first switch unit, and collect the DUT signal to update the clock signal, and send the updated clock signal to the subtractor based on the control of the second control signal of the second switch unit; The first switch unit is connected to the DUT signal generating unit, the synchronous clock signal generating unit, the second switch unit and the subtractor respectively, and is used to generate a first control signal and control the DUT signal generating unit to input the generated DUT signal into the second switch unit, and is used to control the on or off state of the synchronous clock signal generating unit; The second switch unit is connected to the first switch unit, the synchronous clock signal generating unit, and the subtractor, and is used to receive the first control signal from the first switch unit, and generate a second control signal based on the first control signal to control the synchronous clock signal to be input into the subtractor; The subtractor is connected to the first control unit and the second control unit, and is used to collect and calculate the DUT signal from the first control unit and the synchronous clock signal from the second control unit to generate a high-precision test signal.

2. A circuit for improving the test accuracy of chip testing equipment according to claim 1, characterized in that: The first switch unit includes a first comparator and a first PMOS tube T1; wherein, The positive phase input terminal of the first comparator is connected to the DUT signal generating unit, and the negative phase input terminal is connected to the reference signal Vref1; the output terminal is respectively connected to the gate of the first PMOS tube T1 and the synchronous clock signal generating unit; The drain of the first PMOS tube T1 is connected to the DUT signal generating unit, and the source is connected to the second switch unit and the subtractor respectively.

3. A circuit for improving the test accuracy of chip testing equipment according to claim 2, characterized in that: The second switch unit includes an OR gate, a second comparator and a second PMOS tube T2; wherein, One input end of the OR gate is connected to the source of the first PMOS transistor T1 in the first switch unit, the other input end is grounded, and the output end is connected to the non-inverting input end of the second comparator; The negative phase input terminal of the second comparator is grounded, and the output terminal is connected to the gate of the second PMOS transistor T2; The drain of the second PMOS tube T2 is connected to the synchronous clock signal generating unit, and the source is connected to the subtractor.

4. A circuit for improving the test accuracy of chip testing equipment according to claim 3, characterized in that: The first comparator and the second comparator are both ultra-high-speed comparators.

5. A circuit for improving the test accuracy of chip testing equipment according to claim 3, characterized in that: The synchronous clock signal generating unit comprises an AND gate and a synchronous clock signal generator; wherein, One input end of the AND gate is connected to the DUT signal generating unit to receive the DUT signal, the other input end is connected to the synchronous clock signal generator, and the output end is connected to the synchronous clock signal generator to feed back the output end signal of the AND gate to the synchronous clock signal generator; The output end of the synchronous clock signal generator is connected to the drain of the second PMOS tube T2.

6. A circuit for improving the test accuracy of chip testing equipment according to claim 5, characterized in that: The positive input terminal of the subtractor is connected to the source of the first PMOS tube T1 in the first switch unit, the negative input terminal is connected to the source of the second PMOS tube T2 in the second switch unit, and the output terminal is output to the chip testing equipment as a high-precision test signal Vo.

7. A circuit for improving the test accuracy of chip testing equipment according to claim 6, characterized in that: The operational amplifier in the subtractor is an ultra-high-speed operational amplifier.

8. A circuit for improving the test accuracy of chip testing equipment according to claim 7, characterized in that: In the subtractor, the resistor R1 connected to the negative phase input terminal, the feedback resistor R2 between the negative phase input terminal and the output terminal, the resistor R3 connected to the positive phase input terminal, and the resistor R4 grounded at the positive phase input terminal are all high-precision resistors with the same resistance value.

9. A circuit for improving the test accuracy of chip testing equipment according to claim 8, characterized in that: In the subtractor, the resistance values ​​of the resistor R1 connected to the negative phase input terminal, the feedback resistor R2 between the negative phase input terminal and the output terminal, the resistor R3 connected to the positive phase input terminal, and the resistor R4 connected to the positive phase input terminal are determined based on the amplitude of the DUT signal.

10. A method for improving the test accuracy of a chip test device, characterized in that: The method is implemented by using a circuit for improving the testing accuracy of chip testing equipment as described in claims 1-9.

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