Gate drive circuit, display driver and display panel

Abstract

The present invention discloses a gate drive circuit, a display driver, and a display panel. The gate drive circuit includes N cascaded shift register modules, each of which includes: a trigger write unit, a first control unit, and an output adjustment unit; the first control unit and the output adjustment unit are connected to a first node; the trigger write unit and the output adjustment unit are connected to a second node; the output adjustment unit is configured to adjust the potential of the output end of the shift register module according to the potentials of the first node and the second node; the output end of the k-th shift register module is electrically connected to the trigger signal input end of the trigger write unit in the k+1-th shift register module, and the first node of the k-th shift register module is electrically connected to the node control signal input end of the first control unit in the k+1-th shift register module. The present invention can solve the problems of complex gate drive circuit structure and the large number of components used.

Description

Technical Field

[0001] The present invention relates to the technical field of shift registers, and in particular to a gate drive circuit, a display driver and a display panel. Background Art

[0002] The gate drive circuit is used to drive the pixel circuit in the display panel, thereby controlling the pixel circuit to perform light-emitting display, and has important applications in the field of modern display technology.

[0003] However, the existing gate driving circuit has problems such as a complex circuit structure and a large number of components, which further causes the gate driving circuit to occupy a larger frame of the display panel, thereby limiting further applications of the display panel. Summary of the Invention

[0004] The present invention provides a gate drive circuit, a display driver and a display panel to solve the problem that the gate drive circuit has a complex structure and uses a large number of components.

[0005] According to one aspect of the present invention, a gate drive circuit is provided, comprising N cascaded shift register modules, each of which comprises:

[0006] trigger writing unit, first control unit and output regulating unit;

[0007] The first control unit and the output adjustment unit are connected to a first node; the trigger writing unit and the output adjustment unit are connected to a second node;

[0008] The output adjustment unit is configured to adjust the potential of the output end of the shift register module according to the potentials of the first node and the second node; the output end of the k-th stage shift register module is electrically connected to the trigger signal input end of the trigger write unit in the k+1-th stage shift register module, and the first node of the k-th stage shift register module is electrically connected to the node control signal input end of the first control unit in the k+1-th stage shift register module;

[0009] In the 2k-1th stage shift register module, the trigger write unit is configured to write a signal at its trigger signal input terminal into the second node according to the first clock signal, and the first control unit is configured to write a signal at its node control signal input terminal into the first node according to the second clock signal;

[0010] In the 2k-level shift register module, the trigger write unit is configured to write the signal at its trigger signal input end into the second node according to the second clock signal, and the first control unit is configured to write the signal at its node control signal input end into the first node according to the first clock signal; wherein, N≥2, N / 2≥k≥1.

[0011] Optionally, the output adjustment unit includes a pull-up subunit and a pull-down subunit;

[0012] The first end of the pull-up subunit is connected to the first power signal, the control end of the pull-up subunit is electrically connected to the corresponding first node, and the second end of the pull-up subunit is electrically connected to the first end of the pull-down subunit and serves as the output end of the corresponding shift register module;

[0013] The control end of the pull-down subunit is electrically connected to the corresponding second node, and the second end of the pull-down subunit is connected to the second power signal.

[0014] Optionally, the output adjustment unit further includes:

[0015] a first capacitor, wherein a first end of the first capacitor is electrically connected to the first end of the pull-up sub-unit, and a second end of the first capacitor is electrically connected to the control end of the pull-up sub-unit;

[0016] The capacitance value of the first capacitor in the k-th shift register module is greater than the capacitance value of the first capacitor in the (k+1)-th shift register module.

[0017] Optionally, the shift register module further includes:

[0018] a second control unit and a coupling unit, wherein a first end of the coupling unit is electrically connected to a first end of the second control unit, and a second end of the coupling unit is electrically connected to a corresponding second node;

[0019] In the 2k-1th stage shift register module, the second control unit is configured to write the second clock signal into the first end of the coupling unit according to the signal of the corresponding second node;

[0020] In the 2k-th stage shift register module, the second control unit is configured to write the first clock signal into the first end of the coupling unit according to the signal of the corresponding second node.

[0021] Optionally, the first-stage shift register module further includes a power supply introduction unit and a third control unit;

[0022] The power supply introduction unit is configured to write the second power supply signal into the control terminal of the third control unit according to the first clock signal;

[0023] The third control unit is configured to write the second clock signal into the node control signal input terminal of the corresponding trigger write unit according to the signal of its control terminal.

[0024] Optionally, the first-stage shift register module further includes: a first feedback adjustment unit configured to write the first clock signal into the control terminal of the third control unit according to the signal of the corresponding second node.

[0025] Optionally, the first-stage gate driving module further includes: a second feedback regulating unit configured to write the first power supply signal into the first terminal of the coupling unit according to the signal of the control terminal of the third control unit.

[0026] Optionally, the first-stage gate driving module further includes: a third feedback adjustment unit configured to write a first power supply signal into the first node according to a signal of the second node.

[0027] According to another aspect of the present invention, a display driver is provided, comprising a plurality of the above-mentioned gate driving circuits connected in cascade.

[0028] According to another aspect of the present invention, a display panel is provided, comprising the above-mentioned display driver.

[0029] The technical solution of an embodiment of the present invention adopts a gate drive circuit including N cascaded shift register modules, each of which includes: a trigger write unit, a first control unit, and an output adjustment unit; the first control unit and the output adjustment unit are connected to a first node; the trigger write unit and the output adjustment unit are connected to a second node; the output adjustment unit is configured to adjust the potential of the output end of the shift register module according to the potentials of the first node and the second node; the output end of the k-th shift register module is electrically connected to the trigger signal input end of the trigger write unit in the k+1-th shift register module, and the first node of the k-th shift register module is electrically connected to the node control signal input end of the first control unit in the k+1-th shift register module. The node control signal input ends corresponding to the subsequent shift register modules are all connected to the first node of the previous shift register module, eliminating the need for additional modules, thereby greatly reducing the complexity of the gate drive circuit, reducing the number of required components, and further reducing the frame of the gate drive circuit.

[0030] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0032] Figure 1 A schematic diagram of the circuit structure of a gate drive circuit provided by an embodiment of the present invention;

[0033] Figure 2 A schematic diagram of the circuit structure of another gate drive circuit provided by an embodiment of the present invention;

[0034] Figure 3 A schematic diagram of the circuit structure of another gate drive circuit provided by an embodiment of the present invention;

[0035] Figure 4 A schematic diagram of the circuit structure of another gate drive circuit provided by an embodiment of the present invention;

[0036] Figure 5 A timing diagram of a gate drive circuit provided by an embodiment of the present invention;

[0037] Figure 6 A schematic diagram of a circuit structure of a display driver provided by an embodiment of the present invention;

[0038] Figure 7 A schematic structural diagram of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0041] Figure 1 A schematic diagram of a gate drive circuit according to an embodiment of the present invention is provided. Figure 1The gate drive circuit includes N cascaded shift register modules 10, each of which includes: a trigger write unit 101, a first control unit 102, and an output adjustment unit 103; the first control unit 102 and the output adjustment unit 103 are connected to a first node N1; the trigger write unit 101 and the output adjustment unit 103 are connected to a second node N2; the output adjustment unit 103 is configured to adjust the potential of the output end of the shift register module according to the potentials of the first node N1 and the second node N2; the output end of the k-th shift register module is electrically connected to the trigger signal input end of the trigger write unit 101 in the k+1-th shift register module, and the first node N1 of the k-th shift register module is electrically connected to the k+1-th shift register module. The node control signal input terminal of the first control unit 102 in the memory module 10 is electrically connected; in the 2k-1-th level shift register module 10, the trigger write unit 101 is configured to write the signal of its trigger signal input terminal into the second node N2 according to the first clock signal ECK1, and the first control unit 102 is configured to write the signal of its node control signal input terminal into the first node according to the second clock signal ECK2; in the 2k-th level shift register, the trigger write unit 101 is configured to write the signal of its trigger signal input terminal into the second node according to the second clock signal, and the first control unit 102 is configured to write the signal of its node control signal input terminal into the first node according to the first clock signal; wherein, N≥2, N / 2≥k≥1.

[0042] Specifically, the shift register module 10 can shift the signal at its input end and output it from its output end. In each shift register module 10, the trigger signal input end of the trigger writing unit 101 serves as the input end of the shift register module 10, and the output end of the output adjustment unit 103 serves as the output end of the shift register module 10. The trigger signal EIN input to the input end of the first-stage shift register module 10 outputs a first shift signal EM1 after passing through the first-stage shift register module 10. The first shift signal EM1 serves as the trigger signal of the second-stage shift register module 10, and outputs a second shift signal EM2 after passing through the second-stage shift register module 10. The first shift signal EM1 and the second shift signal EM2 provide light-emitting control signals for two rows of pixel circuits in the display panel. Of course, this embodiment is described by taking a gate drive circuit including two-stage shift register modules as an example. In other embodiments, the gate drive circuit may also include more shift register modules. The output adjustment unit 103 can output a first power supply voltage VGH or a second power supply voltage VGL under the regulation of the first node N1 and the second node N2. For example, when the level of the first node N1 is at an active level, the output adjustment unit 103 outputs the first power supply voltage VGH, and when the level of the second node N2 is at an active level, the output adjustment unit 103 outputs the second power supply voltage VGL. Under the control of the first control unit 102 and the trigger writing unit 101, the shift register module can shift the trigger signal and output it, wherein the first power supply voltage VGH is at a high level and the second power supply voltage VGL is at a low level. The gate drive circuit of this embodiment ultimately outputs a signal as a light-emitting control signal for the pixel circuit, and its active level is a high level, that is, within a frame time, the high level duration is short and the low level duration is long. Therefore, the duration of the effective level on the first node N1 is shorter than the time of one frame. The first-stage shift register needs to input the low-level signal to the node control signal input terminal of the first control module 102 during part of the clock cycle within one frame time, and then input it to the first node N1 through the first control module 102.The node control signal input end of the first control module 102 in the first-stage shift register module 10 requires an additional module (such as a third control unit 103 and a power supply introduction unit, which will be described later) to achieve a low level in part of the clock cycle and a high level in the remaining cycles; when the existing shift register is cascaded, each stage of the shift register requires the above-mentioned third control module and trigger write module; while in this embodiment, the node control signal input end corresponding to the k+1-stage shift register module 10 is directly connected to the first node of the k-stage shift register module. Since the signal of the first node meets the conditions required by the node control signal input end corresponding to the next-stage shift register module (that is, the low-level duration is shorter than the high-level duration), the solution of this embodiment requires fewer components to output N shift signals than the components required by the existing gate drive circuit that outputs N shift signals. Therefore, this embodiment can greatly reduce the complexity of the gate drive circuit, reduce the number of required components, and thereby reduce the frame of the gate drive circuit.

[0043] The technical solution of this embodiment includes N cascaded shift register modules, each of which includes: a trigger write unit, a first control unit, and an output adjustment unit; the first control unit and the output adjustment unit are connected to a first node; the trigger write unit and the output adjustment unit are connected to a second node; the output adjustment unit is configured to adjust the potential of the output end of the shift register module according to the potentials of the first node and the second node; the output end of the k-th shift register module is electrically connected to the trigger signal input end of the trigger write unit in the k+1-th shift register module, and the first node of the k-th shift register module is electrically connected to the node control signal input end of the first control unit in the k+1-th shift register module. The node control signal input ends corresponding to the subsequent shift register modules are all connected to the first node of the previous shift register module, eliminating the need for additional modules, thereby greatly reducing the complexity of the gate drive circuit, reducing the number of required components, and further reducing the frame of the gate drive circuit.

[0044] Optionally, Figure 2 A circuit structure diagram of another gate drive circuit provided by an embodiment of the present invention, referring to Figure 2 The output regulation unit 10 includes a pull-up subunit and a pull-down subunit; the first end of the pull-up subunit is connected to the first power supply signal VGH, the control end of the pull-up subunit is electrically connected to the corresponding first node, and the second end of the pull-up subunit is electrically connected to the first end of the pull-down subunit and serves as the output end of the corresponding shift register module 10; the control end of the pull-down subunit is electrically connected to the corresponding second node, and the second end of the pull-down subunit is connected to the second power supply signal VGL.

[0045] Specifically, both the pull-up subunit and the pull-down subunit can be composed of transistors, typically P-type transistors; of course, in some other embodiments, they can also be N-type transistors. Figure 2 As shown, taking the gate drive circuit including a two-stage shift register module as an example, in the first-stage shift register module, the pull-up subunit includes a first transistor M1, and the pull-down subunit includes a second transistor M2. The first electrode of the first transistor M1 is connected to the first power signal VGH, and the second electrode of the first transistor M1 is electrically connected to the first electrode of the second transistor M2 to serve as the output terminal of the first-stage shift register module. The control electrode of the first transistor M1 is electrically connected to the corresponding first node N1; the second electrode of the second transistor M2 is connected to the second power signal VGL, and the control electrode of the second transistor M2 is electrically connected to the corresponding second node N2. In the second-stage shift register module, the pull-up subunit includes a third transistor M3, and the pull-down subunit includes a fourth transistor M4. The first electrode of the third transistor M3 is connected to the first power signal VGH, and the second electrode of the third transistor M3 is electrically connected to the first electrode of the fourth transistor M4 to serve as the output terminal of the second-stage shift register module. The control electrode of the third transistor M3 is electrically connected to the corresponding first node; the second electrode of the fourth transistor M4 is connected to the second power voltage VGL, and the control electrode of the fourth transistor M4 is electrically connected to the second node N2. In each shift register module, when the first node N1 is at a low level, the pull-up subunit is turned on to output the first power signal VGH; when the second node N2 is at a low level, the pull-down subunit is turned on to output the second power signal VGL.

[0046] Preferably, if Figure 2 As shown, the output regulating unit further includes a first capacitor C1, a first end of the first capacitor C1 is electrically connected to the first end of the pull-up subunit, and a second end of the first capacitor C1 is electrically connected to the control end of the pull-up subunit; the capacitance value of the first capacitor C1 in the k-th level shift register module is greater than the capacitance value of the first capacitor C1 in the k+1-th level shift register module.

[0047] Specifically, the first capacitor C1 is used to maintain the potential of the first node N1, so that the potential of the first node N1 can be maintained for a long time, thereby ensuring that the pull-up submodule remains in the off state or the on state. In this embodiment, the first node N1 of the k-th stage shift register module needs to charge the first capacitor C1 of the k+1-th stage shift register module. Therefore, the capacitance value of the first capacitor C1 in the k-th stage shift register module is set to be greater than the capacitance value of the first capacitor C1 in the k+1-th stage shift register module. This can ensure that the first capacitor C1 in each stage of the shift register module can be charged to a sufficient voltage to ensure that the corresponding pull-up submodule is turned on or off, thereby allowing more shift register modules to be cascaded.

[0048] For example, continue to refer to Figure 2 In the first-stage shift register module, the trigger write unit 101 includes a fifth transistor M5, a first electrode of the fifth transistor M5 serving as a trigger signal input terminal for receiving the corresponding trigger signal EIN, a second electrode of the fifth transistor M5 being electrically connected to the second node N2, and a control electrode of the fifth transistor M5 being connected to the first clock signal ECK1; the first control unit 102 includes a sixth transistor M6, a first electrode of the sixth transistor M6 serving as a node control signal input terminal for inputting the node control signal, a second electrode of the sixth transistor M6 being electrically connected to the first node N1, and a control electrode of the sixth transistor M6 being connected to the second clock signal ECK2.

[0049] In the second-stage shift register module, the trigger write unit 101 includes a seventh transistor M7, the first electrode of the seventh transistor M7 serves as a trigger signal input terminal for receiving the corresponding trigger signal, the second electrode of the seventh transistor M7 is electrically connected to the second node N2, and the control electrode of the seventh transistor M7 is connected to the second clock signal ECK2; the first control unit 102 includes an eighth transistor M8, the first electrode of the eighth transistor M8 serves as a node control signal input terminal, and is electrically connected to the first node of the first-stage shift register module, the second electrode of the eighth transistor M8 is electrically connected to the first node N1, and the control electrode of the eighth transistor M8 is connected to the first clock signal ECK1. Figure 1 and Figure 2 The first-level shift register module also includes a power introduction unit 104 and a third control unit 103; the power introduction unit 104 is configured to write the second power signal VGL into the control end of the third control unit 103 according to the first clock signal ECK1, and the third control unit 103 is configured to write the second clock signal ECK2 into the node control signal input end of the corresponding trigger write unit according to the signal of its control end.

[0050] Specifically, the power introduction unit 104 and the third control unit 103 are used to control the potential of the node control signal input terminal; exemplarily, the power introduction unit 104 may include a ninth transistor M9, the first electrode of the ninth transistor M9 serves as the first end of the power introduction unit 104, the second electrode of the ninth transistor M9 serves as the second end of the power introduction unit 104, and the control electrode of the ninth transistor M9 serves as the control end of the power introduction unit 104; the third control unit 103 includes a tenth transistor M10 and a second capacitor C2, the first electrode of the tenth transistor M10 serves as the first end of the third control unit 103, the second electrode of the tenth transistor M10 serves as the second end of the third control unit 103, and the control electrode of the tenth transistor M10 serves as the control end of the third control unit 103; the first end of the second capacitor C2 is electrically connected to the control electrode of the tenth transistor M10, and the second end of the second capacitor C2 is electrically connected to the second electrode of the tenth transistor M10.

[0051] Preferably, if Figure 2 As shown, the gate drive circuit may further include an eleventh transistor M11, a twelfth transistor M12, and a thirteenth transistor M13. The second electrode of the ninth transistor M9 is electrically connected to the control electrode of the tenth transistor M10 via the thirteenth transistor M13. The second electrode of the fifth transistor M5 is electrically connected to the control electrode of the second transistor M2 via the eleventh transistor M11. The second electrode of the seventh transistor M7 is electrically connected to the control electrode of the fourth transistor M4 via the twelfth transistor M12. The eleventh transistor M11, the twelfth transistor M12, and the thirteenth transistor M13 are all normally-on transistors, that is, their control electrodes are connected to the second power supply signal VGL, and are all used to reduce leakage current.

[0052] Optionally, Figure 3 A circuit structure diagram of another gate drive circuit provided by an embodiment of the present invention, referring to Figure 3 The shift register module also includes: a second control unit 105 and a coupling unit 106; a first end of the coupling unit 106 is electrically connected to the first end of the second control unit 105, and a second end of the coupling unit 106 is electrically connected to the corresponding second node N2; in the 2k-1 level shift register module, the second control unit 105 is configured to write the second clock signal ECK2 into the first end of the coupling unit 106 according to the signal of the corresponding second node N2; in the 2k level shift register module, the second control unit 105 is configured to write the first clock signal ECK1 into the first end of the coupling unit 106 according to the signal of the corresponding second node N2.

[0053] Specifically, when the level of the second node N2 is low, the second control unit 105 is turned on, causing the clock signal to be periodically coupled to the second node N2 via the coupling unit 106. When the clock signal is low, the clock signal further lowers the level of the second node N2. When the clock signal is high, due to the relatively low level of the second node N2, the high-level portion of the clock signal is insufficient to pull the second node N2 to a high level. In other words, by providing the second control unit 105 and the coupling unit 106, the level of the second node N2 can be periodically lowered, ensuring that the pull-down sub-unit is opened to a deeper level.

[0054] For example, Figure 3As shown, in the first-stage shift register module, the second control unit 105 includes a fourteenth transistor M14, the first electrode of the fourteenth transistor M14 serves as the first end of the second control unit 105, the second electrode of the fourteenth transistor M14 serves as the second end of the second control unit 105, and the control electrode of the fourteenth transistor M14 serves as the control end of the second control unit 105; the coupling unit 106 includes a third capacitor C3, the first end of the third capacitor C3 serves as the first end of the coupling unit 106, and the second end of the third capacitor C3 serves as the second end of the coupling unit 106.

[0055] In the second-stage shift register module, the second control unit includes a fifteenth transistor M15, the first electrode of the fifteenth transistor M15 serves as the first end of the second control unit 105, the second electrode of the fifteenth transistor M15 serves as the second end of the second control unit 105, and the control electrode of the fifteenth transistor M15 serves as the control end of the second control unit 105; the coupling unit includes a fourth capacitor C4, the first end of the fourth capacitor C4 serves as the first end of the coupling unit, and the second end of the fourth capacitor C4 serves as the second end of the coupling unit.

[0056] Optionally, Figure 4 A circuit structure diagram of another gate drive circuit provided by an embodiment of the present invention, referring to Figure 4 The first-stage shift register module further includes: a first feedback adjustment unit 107, configured to write the first clock signal ECK1 to the control terminal of the third control unit based on the signal of the second node N2. The first feedback adjustment unit 107 can be used to periodically transmit a high-level signal to the control terminal of the third control unit when the second node N2 is at a low level, thereby ensuring that the third control unit is in an off state, thereby causing the node control signal input terminal of the first control unit to be a high-level signal. Exemplarily, the first feedback adjustment unit 107 includes a sixteenth transistor M16, a first electrode of the sixteenth transistor M16 is electrically connected to the control electrode of the tenth transistor M10, a second electrode of the sixteenth transistor M16 is connected to the first clock signal ECK1, and the control electrode of the sixteenth transistor M16 is electrically connected to the second node N2.

[0057] Optionally, continue to refer to Figure 4The first-stage gate drive circuit further includes: a second feedback regulation unit 108, configured to write the first power supply signal VGH to the first terminal of the coupling unit based on a signal from the control terminal of the third control unit. Specifically, the second feedback regulation unit 108 can write a high level to the coupling unit when the control terminal of the third control unit is at a low level, thereby maintaining the second node N2 at a high level to prevent the pull-down sub-unit from being mis-turned on. Exemplarily, the second feedback sub-module 108 includes a seventeenth transistor M17, the control terminal of the seventeenth transistor M17 is electrically connected to the control terminal of the tenth transistor M10, the second terminal of the seventeenth transistor M17 is electrically connected to the first terminal of the third capacitor C3, and the first terminal of the seventeenth transistor M17 is connected to the first power supply signal VGH.

[0058] Optionally, continue to refer to Figure 4 The first-stage shift register module also includes a third feedback adjustment unit 109, configured to write the first power supply signal to the first node N1 based on the signal at the second node N2. When the second node N2 is at a low level, the third feedback adjustment unit 109 writes the first power supply signal VGH to the first node N1, causing the pull-up submodule to turn off. In other words, by providing the third feedback adjustment unit, the pull-up submodule can be turned off when the pull-down submodule is turned on, avoiding output errors caused by the pull-up and pull-down submodules being turned on at the same time. Exemplarily, the third feedback adjustment unit includes an eighteenth transistor M18, a first electrode of the eighteenth transistor M18 being connected to the first power supply signal VGH, a second electrode of the eighteenth transistor M18 being electrically connected to the first node N1, and a second electrode of the eighteenth transistor M18 being electrically connected to the second node N2.

[0059] It should be noted that, among the first electrode and the second electrode of the transistor mentioned in this embodiment, one is the source electrode of the transistor, the other is the drain electrode of the transistor, and the control electrode of the transistor is the gate electrode of the transistor.

[0060] For example, Figure 5 A timing diagram of a gate drive circuit provided by an embodiment of the present invention, Figure 5 and Figure 4 Corresponding, combining Figure 5 and Figure 4 , the overall timing of the gate drive circuit provided by the embodiment of the present invention is described. In order to facilitate distinction, the first node N1 and the second node N2 in the first stage shift register module are respectively Figure 5 N1 and N2 in the second stage shift register module, the first node N1 and the second node N2 are respectively Figure 5 It is defined that the control electrode of the tenth transistor M10 corresponds to N3, the first electrode of the sixth transistor M6 corresponds to N4, the second electrode of the fifth transistor M5 corresponds to N5, and the second electrode of the ninth transistor M9 corresponds to N6.

[0061] In the first stage T1, the trigger signal EIN is at a low level, the first clock signal ECK1 is at a low level, and the second clock signal ECK2 is at a high level; the fifth transistor M5 is turned on, the potential of N2 is VGL-vth, and N9 maintains the level of the previous stage and remains at a low level; the eighteenth transistor M18 is turned on, N1 and N8 are both at a high level, the first transistor M1 and the third transistor M3 are turned off; EM1 and EM2 are both at a low level.

[0062] In the second stage T2, the trigger signal EIN is at a low level, the first clock signal ECK1 is at a high level, and the second clock signal ECK2 is at a low level. Since the fourteenth transistor M14 is turned on, N2 is still at a low level, and N9 is also at a low level, the eighteenth transistor M18 is turned on, N1 and N8 are both at a high level, the first transistor M1 and the third transistor M3 are turned off; EM1 and EM2 are both at a low level.

[0063] In the third stage T3, the trigger signal EIN is high, the first clock signal ECK1 is low, and the second clock signal ECK2 is high; N2 is pulled high by the trigger signal EIN, and since N6 is low, N3 is also low, so that M10 is turned on, and N4 remains high. That is, at this time, the second transistor M2 and the first transistor M1 are turned off, and EM1 maintains the low-level output of the previous stage; N8 is still high, the third transistor M3 is turned off, and N9 is low, so that the fourth transistor M4 is turned on, and EM2 remains low.

[0064] In the fourth stage T4, the trigger signal EIN is at a high level, the first clock signal ECK1 is at a high level, and the second clock signal ECK2 is at a low level. N1 is written to a low level, and N2 remains at a high level. N4 is written to a low level, so that N1 is also written to a low level. However, since the eighth transistor M8 is turned off, N8 maintains the level of the previous stage, that is, N8 is at a high level, and EM1 is pulled high by the first transistor M1. At this time, N9 is pulled high by EM1, the third transistor M3 and the fourth transistor M4 are both turned off, and EM2 maintains a low level.

[0065] In the fifth stage T5, the trigger signal EIN is high, the first clock signal ECK1 is low, and the second clock signal ECK2 is high. N2 and N9 are both pulled high, causing the second transistor M2 and the fourth transistor M4 to turn off. Since the sixth transistor M6 is turned off and the eighth transistor M8 is turned on, N1 maintains the potential of the previous stage, that is, remains low, and N8 is written to a low level. During this stage, the first transistor M1 and the third transistor M3 are turned on, causing EM1 and EM2 to be high. Furthermore, by configuring the capacitance of the first capacitor C1 in different shift register modules, the potentials of N1 and N8 can be made negative, ensuring that the corresponding transistors are turned on more deeply.

[0066] In the sixth stage T6, the trigger signal EIN is high, the first clock signal ECK1 is high, and the second clock signal ECK2 is low; N2 and N9 are both written to high; the eighth transistor M8 is turned off, and N8 remains low, so that the third transistor M3 is turned on, and EM2 remains high; the N4 times tenth transistor M10 is written to low, so that N1 is written to low by N4, and then the first transistor M1 is also turned on, and EM1 remains high.

[0067] In the seventh stage T7, the trigger signal EIN is at a low level, the first clock signal ECK1 is at a low level, and the second clock signal ECK2 is at a high level; N2 is written to a low level, causing the second transistor M2 to be turned on and EM1 to output a low level; and the eighteenth transistor M18 is turned on, N1 is pulled high, thereby causing N8 to be pulled high, and the first transistor M1 and the third transistor M3 to be turned off; because the seventh transistor M7 is turned off, N9 still maintains the level of the previous stage, that is, remains at a high level, and ultimately causes EM2 to still maintain the output of the previous stage, that is, EM2 remains at a high level.

[0068] In the eighth stage T8, the trigger signal EIN is at a low level, the first clock signal ECK1 is at a high level, and the second clock signal ECK2 is at a low level; N2 still remains at a low level, so that N5 remains at a high level; and N8 has no low level written and remains at a high level; at this time, the seventh transistor M7 is turned on, and N9 is pulled low; ultimately, the second transistor M2 and the fourth transistor M4 are turned on, the first transistor M1 and the third transistor M3 are turned off, and EM1 and EM3 are both at a low level.

[0069] In the ninth stage T9, the trigger signal EIN is at a low level, the first clock signal ECK1 is at a low level, and the second clock signal ECK2 is at a high level; N2 and N9 are written at a low level, the eighteenth transistor M18 is turned on, and N1 and N8 are both written at a high level; at this time, the second transistor M2 and the fourth transistor M4 are turned on, the first transistor M1 and the third transistor M3 are turned off, and EM1 and EM3 are both at a low level.

[0070] In the tenth stage T10, the trigger signal EIN is at a low level, the first clock signal ECK1 is at a high level, and the second clock signal ECK2 is at a low level; the fourteenth transistor M14 is turned on, N2 is still at a low level, then N9 is also at a low level, the eighteenth transistor M18 is turned on, N1 and N8 are both at a high level, the first transistor M1 and the third transistor M3 are turned off; EM1 and EM2 are both at a low level.

[0071] The subsequent stages are a cycle of the ninth stage T9 and the tenth stage T10, which will not be described in detail here.

[0072] comprehensive Figure 4 and Figure 5 It can be seen that the gate driving circuit of this embodiment can output two-level light-emitting control signals and drive two rows of pixel circuits. In addition, it uses fewer components, thereby simplifying the circuit structure and reducing the circuit area.

[0073] In addition, it should be noted that if the pulse width of the output signal of the shift register module needs to be adjusted, it can be achieved by adjusting the pulse width of the trigger signal EIN.

[0074] The embodiment of the present invention further provides a display driver, such as Figure 6 As shown, Figure 6 A circuit structure diagram of a display driver provided in an embodiment of the present invention, wherein the display driver 201 includes multiple cascaded gate drive circuits 2011, and the gate drive circuit 2011 is the gate drive circuit provided by any embodiment of the present invention; wherein the trigger signal EIN of the n-th stage gate drive circuit is provided by the output signal of the last stage shift register module of the n-1-th stage gate drive circuit, where n is greater than or equal to 2.

[0075] Specifically, the display driver 201 can be applied to a display panel to provide a light-emitting control signal for a pixel circuit in the display panel. Since it includes the gate drive circuit provided by any embodiment of the present invention, it also has the same beneficial effects, which will not be described in detail here. The display driver 201 can be set at the frame position of the display panel. Preferably, the display panel can be provided with two display drivers 201, respectively located on both sides of the display panel, thereby reducing the voltage drop on the signal line in the display area of ​​the display panel and improving the display uniformity. In this embodiment, taking the example that each gate drive circuit includes an odd number of shift register modules, the first clock signal ECK1 of the odd-level gate drive circuit is provided by the first clock signal line CK1, and the second clock signal ECK2 of the odd-level gate drive circuit is provided by the second clock signal line CK2; the first clock signal ECK1 of the even-level gate drive circuit is provided by the second clock signal line CK2, and the second clock signal ECK2 of the even-level gate drive circuit is provided by the first clock signal line CK1. If the gate driving circuit includes an even number of shift register modules, the first clock signal ECK1 in each stage of the shift register module is provided by the first clock signal line CK1 , and the second clock signal ECK2 is provided by the second clock signal line CK2 .

[0076] The embodiment of the present invention further provides a display panel, such as Figure 7 As shown, Figure 7 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, referring to Figure 7The display panel includes the display driver 201 provided by any embodiment of the present invention and n rows of pixel circuits PX; the pixel circuit includes a driving module, a light-emitting module, a data writing module, a first light-emitting control module, a second light-emitting control module and a storage module; the driving module is used to generate a driving current, and the light-emitting module is used to respond to the driving current; the storage module is used to maintain the level of the control end of the driving module; the data writing module is used to write the data signal to the control end of the driving module in the data writing phase, and the first light-emitting control module and the second light-emitting control module are used to provide a path for the driving current in the light-emitting phase; the display driver is used to provide the light-emitting control signal required by the pixel circuit.

[0077] The display panel can be a mobile phone, tablet computer, smart watch, MP3, MP4, smart helmet or other wearable device. Since it includes the display driver provided by any embodiment of the present invention, it also has the same beneficial effects and will not be repeated here.

[0078] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0079] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A gate drive circuit, characterized in that: The invention comprises N-stage shift register modules connected in cascade, each of which comprises: trigger writing unit, first control unit and output regulating unit; The first control unit and the output adjustment unit are connected to a first node; the trigger writing unit and the output adjustment unit are connected to a second node; The output adjustment unit is configured to adjust the potential of the output end of the shift register module according to the potentials of the first node and the second node; the output end of the k-th stage shift register module is electrically connected to the trigger signal input end of the trigger write unit in the k+1-th stage shift register module, and the first node of the k-th stage shift register module is electrically connected to the node control signal input end of the first control unit in the k+1-th stage shift register module; In the 2k-1th stage shift register module, the trigger write unit is configured to write a signal at its trigger signal input terminal into the second node according to the first clock signal, and the first control unit is configured to write a signal at its node control signal input terminal into the first node according to the second clock signal; In the 2k-level shift register module, the trigger write unit is configured to write the signal at its trigger signal input end into the second node according to the second clock signal, and the first control unit is configured to write the signal at its node control signal input end into the first node according to the first clock signal; wherein, N≥2, N / 2≥k≥1.

2. The gate drive circuit according to claim 1, wherein: The output regulating unit includes a pull-up subunit and a pull-down subunit; The first end of the pull-up subunit is connected to the first power signal, the control end of the pull-up subunit is electrically connected to the corresponding first node, and the second end of the pull-up subunit is electrically connected to the first end of the pull-down subunit and serves as the output end of the corresponding shift register module; The control end of the pull-down subunit is electrically connected to the corresponding second node, and the second end of the pull-down subunit is connected to the second power signal.

3. The gate drive circuit according to claim 2, wherein: The output adjustment unit further includes: a first capacitor, wherein a first end of the first capacitor is electrically connected to the first end of the pull-up sub-unit, and a second end of the first capacitor is electrically connected to the control end of the pull-up sub-unit; The capacitance value of the first capacitor in the k-th shift register module is greater than the capacitance value of the first capacitor in the (k+1)-th shift register module.

4. The gate drive circuit according to claim 2, wherein: The shift register module further includes: a second control unit and a coupling unit, wherein a first end of the coupling unit is electrically connected to a first end of the second control unit, and a second end of the coupling unit is electrically connected to a corresponding second node; In the 2k-1th stage shift register module, the second control unit is configured to write the second clock signal into the first end of the coupling unit according to the signal of the corresponding second node; In the 2k-th stage shift register module, the second control unit is configured to write the first clock signal into the first end of the coupling unit according to the signal of the corresponding second node.

5. The gate driving circuit according to claim 4, wherein: The first-level shift register module further includes a power supply introduction unit and a third control unit; The power supply introduction unit is configured to write the second power supply signal into the control terminal of the third control unit according to the first clock signal; The third control unit is configured to write the second clock signal into the node control signal input terminal of the corresponding first control unit according to the signal at its control terminal.

6. The gate driving circuit according to claim 5, wherein: The first-stage shift register module further includes: a first feedback adjustment unit configured to write the first clock signal into the control terminal of the third control unit according to the signal of the corresponding second node.

7. The gate driving circuit according to claim 5, wherein: The first-stage gate driving module further includes: a second feedback regulating unit configured to write the first power supply signal into the first terminal of the coupling unit according to the signal of the control terminal of the third control unit.

8. The gate driving circuit according to claim 1, wherein: The first-stage gate driving module further includes: a third feedback regulating unit configured to write a first power supply signal into the first node according to a signal of the second node.

9. A display driver, characterized in that: The display driver includes a plurality of gate driving circuits according to any one of claims 1 to 8 connected in cascade.

10. A display panel, characterized in that: The display panel includes the display driver according to claim 9.

Images