Shift register and driving method therefor, and display substrate

Abstract

Provided are a shift register and a driving method therefor, and a display substrate. The shift register comprises a plurality of cascaded first shift register units configured to provide scanning control signals, and a plurality of cascaded second shift register units configured to provide light-emission control signals, wherein each first shift register unit comprises a first scanning signal output module and a second scanning signal output module; the second scanning signal output modules of adjacent stages are connected to pixels in different rows, and two second scanning signal output modules corresponding to two adjacent rows of pixels are symmetrically distributed, with respect to a display area, in a first area and a second area of a non-display area on opposite sides relative to the display area; each second shift register unit comprises a first light-emitting signal output module and a second light-emitting signal output module; and at least the first light-emitting signal output modules or the second light-emitting signal output modules are distributed at intervals in a second direction with the second scanning signal output modules and are aligned in a first direction.

Description

Shift register, driving method thereof and display substrate TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular to a shift register, a driving method thereof and a display substrate. BACKGROUND

[0002] The shift register generally comprises a plurality of cascaded shift register units, also known as gate drive on array (GOA) units, for short. The plurality of cascaded GOA units are respectively coupled with a plurality of rows of pixels in a display panel. The plurality of cascaded GOA units drive the plurality of rows of pixels in the display panel row by row to make the display panel display. In order to realize local refresh, the types of scanning signals required by the pixel circuit of some display devices increase, which leads to more complex shift register wiring and larger space occupation, and is not conducive to the narrow frame of the display substrate.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those skilled in the art.

[0004] SUMMARY

[0005] In one aspect of the present disclosure, a shift register is provided, comprising: a plurality of cascaded first shift register units configured to provide a scanning control signal; a plurality of cascaded second shift register units configured to provide a light emitting control signal; the first shift register unit comprises a control sub-circuit, a first output sub-circuit and a second output sub-circuit, wherein a first signal output end of the first output sub-circuit inputs a cascade signal to a control sub-circuit of a next stage first shift register unit; the second output sub-circuit is configured to provide a first voltage signal or a shielding signal of a shielding signal end to a second signal output end; the first shift register unit comprises a first scanning signal output module and a second scanning signal output module; the second scanning signal output modules of adjacent stages are connected to different rows of pixels, and the two second scanning signal output modules corresponding to two adjacent rows of pixels are symmetrically distributed about the display area on the two sides of the opposite display area of the non-display area in the first and second regions; the second shift register unit comprises a first light emitting signal output module and a second light emitting signal output module, wherein at least one of the first light emitting signal output module and the second light emitting signal output module is spaced apart from the second scanning signal output module in the second direction and aligned in the first direction.

[0006] In another aspect of the present disclosure, a display substrate is provided, comprising: a plurality of rows of pixels and a shift register as previously described; the display substrate comprises a display area and a non-display area surrounding the display area, the non-display area comprises a first area and a second area located on opposite sides of the display area, wherein the second scan signal output modules of adjacent stages are connected to different rows of pixels, and the two second scan signal output modules corresponding to two adjacent rows of pixels are symmetrically distributed in the first area and the second area with respect to the display area; at least one of the first light-emitting signal output module and the second light-emitting signal output module is spaced apart from the second scan signal output module in the second direction and aligned in the first direction.

[0007] In yet another aspect of the present disclosure, a driving method of the shift register as previously described is provided, the method comprising: in a first refresh time period, the shielding signal is a periodic active level signal, and the corresponding pixels are controlled to perform data refresh; in a second refresh time period, the shielding signal is changed from the active level signal to an inactive level signal, and the corresponding pixels are controlled to stop data refresh; in a third refresh time period, the shielding signal remains as the inactive level signal, and the corresponding pixels are controlled to keep data unrefreshed. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0009] FIG. 1 is a plan view of a display substrate according to an embodiment of the present disclosure;

[0010] FIG. 2 is an equivalent circuit diagram of a pixel circuit of a single light-emitting element in a display substrate according to an embodiment of the present disclosure;

[0011] FIG. 3 is an equivalent circuit diagram of a pixel circuit of a single light-emitting element in a display substrate according to an embodiment of the present disclosure;

[0012] FIG. 4 is a structural block diagram of a display substrate according to an embodiment of the present disclosure;

[0013] FIG. 5A is an equivalent circuit diagram of a pixel circuit of a single light-emitting element in a display substrate according to an embodiment of the present disclosure; FIG. 5B is a timing diagram of the pixel circuit according to the embodiment of FIG. 5A;

[0014] FIG. 6 is a structural block diagram of a display substrate according to an embodiment of the present disclosure;

[0015] FIG. 7 is a structural block diagram of a first scan signal output module according to an embodiment of the present disclosure;

[0016] FIG. 8 is an equivalent circuit diagram of a first scan signal output module according to an embodiment of the present disclosure;

[0017] FIG. 9A is one of timing diagrams of a shift register according to an embodiment of the present disclosure; FIG. 9B is a flowchart of a driving method of a shift register according to an embodiment of the present disclosure;

[0018] FIG. 10 is a partial plan view of a shift register according to an embodiment of the present disclosure;

[0019] FIG. 11 is a plan view of a first scan signal output module according to an embodiment of the present disclosure;

[0020] FIG. 12 is a plan view of a second scan signal output module according to an embodiment of the present disclosure;

[0021] FIG. 13 is a cross-sectional view taken along line AA' of FIG. 11;

[0022] FIG. 14 is an equivalent circuit diagram of a second shift register unit according to an embodiment of the present disclosure;

[0023] FIG. 15 is a plan view of a second shift register unit according to an embodiment of the present disclosure;

[0024] FIG. 16 is a structural block diagram of a shift register according to further embodiments of the present disclosure;

[0025] FIG. 17 is another of timing diagrams of a shift register according to an embodiment of the present disclosure;

[0026] FIG. 18 is a partial plan view of a shift register according to further embodiments of the present disclosure;

[0027] FIG. 19 is a partial plan view of a shift register according to an embodiment of the present disclosure, in which one second scan signal output module and one second shift register unit are shown;

[0028] FIG. 20 is a partial plan view of a shift register according to an embodiment of the present disclosure, in which two second scan signal output modules and two second shift register units are shown in an alternate arrangement;

[0029] FIG. 21A shows a plan view of a first semiconductor layer in the shift register of FIG. 19; FIG. 21B shows a plan view of a first conductive layer in the shift register of FIG. 19; FIG. 21C shows a plan view of a second conductive layer in the shift register of FIG. 19; FIG. 21D shows a plan view of a third conductive layer in the shift register of FIG. 19; and FIG. 21E shows a plan view of a fourth conductive layer in the shift register of FIG. 19.

[0030] It should be noted that, for the sake of clarity, the size of a layer, structure, or region in the drawings can be exaggerated or reduced, i.e., the drawings are not necessarily drawn to scale relative to each other. DETAILED DESCRIPTION

[0031] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0032] It should be noted that in the drawings, the size and relative size of the elements can be exaggerated for clarity and / or descriptive purposes. Thus, the size and relative size of the elements in the drawings should not be construed as being to scale. In the description and drawings, identical or similar reference numerals indicate identical or similar components.

[0033] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by one of ordinary skill in the art. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects.

[0034] In this document, unless otherwise specified, directional terms such as "upper", "lower", "left", "right", "inner", "outer" and the like are used to indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure, and do not indicate or imply that the devices, elements or components referred to must have a particular orientation, be constructed or operated in a particular orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationship they represent may also change accordingly. Therefore, these directional terms should not be understood as limiting the present disclosure.

[0035] In this document, directional expressions "first direction" and "second direction" are used to describe different directions of the display substrate, for example, the row direction and the column direction of the display substrate. It should be understood that such expressions are only exemplary descriptions, and are not limitations on the present disclosure.

[0036] In this specification, unless otherwise specified, the expression "electrically connected" can mean that two components or elements are directly electrically connected, for example, a component or an element A is in direct contact with a component or an element B and an electrical signal can be transmitted between the two components or elements; can mean that two components or elements are electrically connected through a conductive medium such as a conductive wire, for example, a component or an element A is electrically connected to a component or an element B through a conductive wire to transmit an electrical signal between the two components or elements; and can mean that two components or elements are electrically connected through at least one electronic component, for example, a component or an element A is electrically connected to a component or an element B through at least one thin film transistor to transmit an electrical signal between the two components or elements.

[0037] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly. A capacitor refers to an element including at least a first electrode and a second electrode, and the first electrode of the capacitor can also be referred to as a first terminal of the capacitor and the second electrode of the capacitor can also be referred to as a second terminal of the capacitor.

[0038] In this specification, a control terminal can be a gate electrode, a first terminal can be a drain electrode, a second terminal can be a source electrode, or a first terminal can be a source electrode, and a second terminal can be a drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged.

[0039] In this specification, "parallel" means a state where an angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus, a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus, a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0040] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be changed into "a conductive film". Similarly, "an insulating film" can be changed into "an insulating layer".

[0041] In this specification, "formed in the same layer" means that two (or more) structures are formed by patterning at the same time, and the materials thereof can be the same or different. For example, the materials of precursors used for forming the two (or more) structures in the same layer are the same, and the materials finally formed can be the same or different.

[0042] FIG. 1 is a plan view of a display substrate according to an embodiment of the present disclosure.

[0043] Exemplarily, in an embodiment of the present disclosure, a display substrate 1000 is provided. Referring to FIG. 1, the display substrate 1000 includes a plurality of pixels PX, a plurality of gate lines GL, and a shift register GOA (also referred to as a gate driving circuit). The plurality of pixels PX are located in a display area AA of the display substrate 1000, and the shift register GOA is located in a non-display area NA of the display substrate 1000. The plurality of pixels PX are arranged in an array in a first direction X and a second direction Y, forming a plurality of rows and a plurality of columns of pixels. The plurality of gate lines GL extend along the first direction X and are arranged at intervals in the second direction Y. The plurality of gate lines GL are electrically connected to the plurality of pixels PX and the shift register GOA, respectively. The shift register can provide a gate driving signal to the pixels PX through the gate lines GL, so as to drive the pixels to emit light.

[0044] The shift register GOA can include a plurality of cascaded shift register units. For example, continuing to refer to FIG. 1, the shift register GOA includes a first-stage shift register unit GOA1, a second-stage shift register unit GOA2, and an Nth-stage shift register unit GOAN, where N is the total number of stages of the shift register units. At least one gate line GL is connected to the plurality of pixels PX in one pixel row, and at least one gate line GL connected to the pixel row is connected to at least one stage of the shift register units in the shift register GOA, so that the gate driving signal can be provided to the pixel row through the stage of the shift register units, and the pixel row is driven to emit light for display.

[0045] In some embodiments, the shift register GOA can be located in the non-display area NA on opposite sides of the display area AA. The shift registers GOA on the two sides can provide the same gate driving signal, achieving double-side driving of the pixels. The GOA design with double-side driving can reduce the influence of voltage drop in the gate lines, improve the uniformity of pixel display, and be beneficial to improving the display effect.

[0046] At least one pixel PX includes a pixel circuit 10 and a light emitting element L. The shift register GOA provides a gate signal to a transistor in the pixel circuit 10, so that the pixel circuit 10 can drive the light emitting element L to emit light.

[0047] Exemplarily, the pixel circuit 10 can include a plurality of transistors (such as thin film transistors TFT) and at least one capacitor Cst. For example, the pixel circuit 10 can be an “8T1C” circuit, a “7T1C” circuit, a “7T2C” circuit, a “3T1C” circuit, or a “5T1C” circuit, and the like, where “T” refers to a thin film transistor, and the number before “T” refers to the number of thin film transistors; “C” refers to a capacitor, and the number before “C” refers to the number of capacitors.

[0048] It can be understood that the circuit structure of the pixel circuit 10 is not specifically limited in the embodiments of the present disclosure. In the following embodiments of the present disclosure, only the pixel circuit of the “8T1C” circuit is taken as an example for exemplary description.

[0049] FIG. 2 is an equivalent circuit diagram of a pixel circuit of a single light emitting element in a display substrate according to an embodiment of the present disclosure.

[0050] Exemplarily, in the case where the pixel circuit 10 is the “8T1C” circuit. Referring to FIG. 2, the pixel circuit 10 can include a first initialization transistor M1, a compensation transistor M2, a drive transistor M3, a data writing transistor M4, a first light emitting control transistor M5, a second light emitting control transistor M6, a second initialization transistor M7, a third initialization transistor M8, and a storage capacitor C01.

[0051] The control electrode of the first initialization transistor M1 is electrically connected with the scan control signal end Ga, the first electrode of the first initialization transistor M1 is electrically connected with the first initialization signal end Vi1, and the second electrode of the first initialization transistor is electrically connected with the node O1.

[0052] The control electrode of the compensation transistor M2 is electrically connected with the scan control signal end Ga, the first electrode of the compensation transistor M2 is electrically connected with the node O1, and the second electrode of the compensation transistor M2 is electrically connected with the node O3.

[0053] The control electrode of the drive transistor M3 is electrically connected with the node O1, the first electrode of the drive transistor M3 is electrically connected with the node O2, and the second electrode of the drive transistor M3 is electrically connected with the node O3.

[0054] The control electrode of the data writing transistor M4 is electrically connected with the scan control signal end Ga, the first electrode of the data writing transistor M4 is electrically connected with the node O2, and the second electrode of the data writing transistor M4 is electrically connected with the data signal end Vdata.

[0055] The control electrode of the first light emitting control transistor M5 is electrically connected with the light emitting control signal end EM, the first electrode of the first light emitting control transistor M5 is electrically connected with the first power signal end VDD, and the second electrode of the first light emitting control transistor M5 is electrically connected with the node O2.

[0056] The control electrode of the second light emitting control transistor M6 is electrically connected with the light emitting control signal end EM, the first electrode of the second light emitting control transistor M6 is electrically connected with the node O3, and the second electrode of the second light emitting control transistor M6 is electrically connected with the node O4.

[0057] A control electrode of the second initialization transistor M7 is electrically connected with the light-emitting control signal terminal EM, a first electrode of the second initialization transistor M7 is electrically connected with the node O4, and a second electrode of the second initialization transistor M7 is electrically connected with the second initialization signal terminal Vi2.

[0058] A control electrode of the third initialization transistor M8 is electrically connected with the light-emitting control signal terminal EM, a first electrode of the third initialization transistor M8 is electrically connected with the node O2, and a second electrode of the third initialization transistor M8 is electrically connected with the third initialization signal terminal Vi3.

[0059] A first terminal of the storage capacitor C01 is electrically connected with the first power signal terminal VDD, and a second terminal of the storage capacitor C01 is electrically connected with the node O1.

[0060] A first electrode of the light-emitting element L is electrically connected with the node O4, and a second electrode of the light-emitting element L is electrically connected with the second power signal terminal VSS.

[0061] The scan control signal terminal Ga can receive a scan control signal from the shift register GOA, and the light-emitting control signal terminal EM can receive a light-emitting control signal from the shift register GOA, so as to control the on-off of the plurality of transistors in the pixel circuit 10, to realize the data writing in the pixel circuit, and to drive the light-emitting element L to emit light.

[0062] The scan control signal terminal Ga can receive one or more scan control signals for driving the on-off of different transistors in the pixel circuit 10 respectively. The light-emitting control signal terminal EM can receive one or more light-emitting control signals for driving the on-off of different transistors in the pixel circuit 10 respectively.

[0063] FIG. 3 is an equivalent circuit diagram of a pixel circuit of a single light-emitting element in a display substrate according to an embodiment of the present disclosure, and FIG. 4 is a structural block diagram of a display substrate according to an embodiment of the present disclosure.

[0064] For example, referring to FIG. 3, the scan control signal terminal Ga includes a first scan control signal terminal Ga1, and can receive one scan control signal, for example, a first scan control signal ga1. The light-emitting control signal terminal EM includes a first light-emitting control signal terminal EM1 and a second light-emitting control signal terminal EM2, and can receive multiple light-emitting control signals, for example, a first light-emitting control signal em1 and a second light-emitting control signal em2.

[0065] Referring to FIGS. 3 and 4, the shift register GOA includes a plurality of cascaded first shift register units GOA-Ga and a plurality of cascaded second shift register units GOA-EM. The first shift register units GOA-Ga are configured to provide scan control signals, and the second shift register units GOA-EM are configured to provide emission control signals. At least part of the plurality of transistors in the same pixel circuit 10 is electrically connected to the first shift register units GOA-Ga, and at least another part of the plurality of transistors in the same pixel circuit 10 is electrically connected to the second shift register units GOA-EM, to control the on-off of the plurality of transistors in the pixel circuit 10. For example, the first shift register units GOA-Ga are electrically connected to the first scan control signal terminal Ga1 in the pixel circuit 10, thereby providing the first scan control signal ga1 for the first initialization transistor M1, the compensation transistor M2, and the data writing transistor M4. The second shift register units GOA-EM include a first emission signal output module GOA-EM1 and a second emission signal output module GOA-EM2. The first emission signal output module GOA-EM1 is electrically connected to the first emission control signal terminal EM1 in the pixel circuit 10, thereby providing the first emission control signal em1 for the first emission control transistor M5 and the second emission control transistor M6. The second emission signal output module GOA-EM2 is electrically connected to the second emission control signal terminal EM2 in the pixel circuit, thereby providing the second emission control signal em2 for the second initialization transistor M7 and the third initialization transistor M8.

[0066] Exemplarily, the connection mode of the shift register GOA and the pixel circuit 10 shown in FIGS. 3 and 4 is taken as an example to illustrate the pixel driving process. In the refresh phase, the pixel circuit 10 controls the data writing transistor M4 and the compensation transistor M2 to be turned on for data writing under the control of the first scan control signal ga1; meanwhile, the first initialization transistor M1 in the pixel circuit of the next row of pixels is controlled to be turned on by the first scan control signal ga1, to refresh the node O1 in the next row of pixel circuits. In the holding frame phase, the pixel circuit 10 controls the second initialization transistor M7 and the third initialization transistor M8 to be turned on for resetting the voltage at the node O2 and the voltage at the node O4 under the control of the second emission control signal em2. At this time, the compensation transistor M2 is turned off under the control of the first scan control signal ga1, so that the voltage resetting at the nodes O2 and O4 does not affect the voltage at the node O1, thereby realizing low-frequency display.

[0067] In some embodiments, the display substrate has a local refresh function. That is, the display area of the display substrate can include a plurality of display subareas. By driving at least part of the plurality of display subareas by using the shift register, local refresh display can be realized, thereby more efficiently saving power consumption.

[0068] However, the display substrate with local refresh requires more types of scanning signals for the pixel circuit, which may cause the design of the shift register to become complex and the wiring space of the shift register to increase.

[0069] In the related art, the pixel circuit in the display substrate with the local refresh function is usually driven by the Low Temperature Polycrystalline Oxide (LTPO) technology. However, the local refresh function is less used in the display substrate with the pixel circuit driven by the Low Temperature Poly-Silicon (LTPS) technology.

[0070] FIG. 5A is an equivalent circuit diagram of a pixel circuit of a single light emitting element in a display substrate according to an embodiment of the present disclosure; FIG. 5B is a timing diagram of the pixel circuit according to the embodiment of FIG. 5A; and FIG. 6 is a structural block diagram of a display substrate according to an embodiment of the present disclosure.

[0071] For example, in some embodiments of the present disclosure, referring to FIG. 5A, the scan control signal end Ga can include a first scan control signal end Ga1 and a second scan control signal end Ga2, and can receive multiple scan control signals, such as a first scan control signal ga1 and a second scan control signal ga2. The light emitting control signal end EM includes a first light emitting control signal end EM1 and a second light emitting control signal end EM2, and can receive multiple light emitting control signals, such as a first light emitting control signal em1 and a second light emitting control signal em2.

[0072] At least a part of the plurality of transistors in the pixel circuit 10 can be LTPS transistors, or all of the plurality of transistors in the pixel circuit 10 can be LTPS transistors. For example, in the “8T1C” pixel circuit shown in FIG. 5A, the first initialization transistor M1, the compensation transistor M2, the driving transistor M3, the data writing transistor M4, the first light emitting control transistor M5, the second light emitting control transistor M6, the second initialization transistor M7, and the third initialization transistor M8 can all be LTPS transistors.

[0073] Referring to FIGS. 5A and 6 in combination, the shift register GOA includes a plurality of cascaded first shift register units GOA-Ga configured to provide the scan control signal. For example, the first shift register unit GOA-Ga can include a first scan signal output module GOA-Ga1 and a second scan signal output module GOA-Ga2.

[0074] The first scan signal output module GOA-Gal is configured to be electrically connected with the control electrode of the data writing transistor M4 in the pixel circuit 10. And / or, the first scan signal output module GOA-Gal is configured to be electrically connected with the control electrode of the compensation transistor M2 in the pixel circuit 10. For example, referring to FIG. 6, the first scan signal output module GOA-Gal includes a first cascade module Gate1 and a first shielding module SU1. A plurality of cascaded first scan signal output modules GOA-Gal are electrically connected through the first cascade module Gate1, realizing the transmission of the first cascade signal carry1. The first shielding module SU1 in the plurality of cascaded first scan signal output modules GOA-Gal is respectively electrically connected with the compensation transistor M2 and the data writing transistor M4 in the pixel circuit 10, thereby controlling the on-off of the compensation transistor M2 and the data writing transistor M4.

[0075] The second scan signal output module GOA-Ga2 is configured to be electrically connected with the control electrode of the first initialization transistor M1 in the pixel circuit 10. For example, the second scan signal output module GOA-Ga2 includes a second cascade module Gate2 and a second shielding module SU2. A plurality of cascaded second scan signal output modules GOA-Ga2 are electrically connected through the second cascade module Gate2, realizing the transmission of the second cascade signal carry2. The second shielding module SU2 in the plurality of cascaded second scan signal output modules GOA-Ga2 is respectively electrically connected with the first initialization transistor M1 in the pixel circuit 10, thereby controlling the on-off of the first initialization transistor M1.

[0076] Continuing to refer to FIG. 5A and FIG. 6, the shift register GOA further includes a plurality of cascaded second shift register units GOA-EM. The second shift register unit GOA-EM includes a first emission signal output module GOA-EM1 and a second emission signal output module GOA-EM2.

[0077] The first emission signal output module GOA-EM1 is configured to be electrically connected with the control electrode of the light-emitting control transistor in the pixel circuit 10. For example, the first emission signal output module GOA-EM1 is electrically connected with the first light-emitting control signal end EM1 in the pixel circuit 10, thereby providing the first light-emitting control signal em1 for the first light-emitting control transistor M5 and the second light-emitting control transistor M6.

[0078] The second light-emitting signal output module GOA-EM2 is configured to be electrically connected with the control electrode of the second initialization transistor M7 in the pixel circuit 10. And / or, the second light-emitting signal output module GOA-EM2 is configured to be electrically connected with the control electrode of the third initialization transistor M8 in the pixel circuit 10. For example, the second light-emitting signal output module GOA-EM2 is electrically connected with the second light-emitting control signal terminal EM2 in the pixel circuit, thereby providing the second light-emitting control signal em2 for the second initialization transistor M7 and the third initialization transistor M8.

[0079] In some embodiments, the display area of the display substrate can be locally refreshed, that is, the refresh frequency of multiple display sub-areas in the display area is different. In the display substrate with the local refresh function, the display area can include a high-frequency refresh area and a low-frequency refresh area. In combination with reference to FIGS. 5A and 6, the node O1 in the pixel circuit 10 of the first row of pixels in the low-frequency refresh area cannot be refreshed and reset, otherwise a bright line will be formed at the boundary between the high-frequency and low-frequency areas, resulting in poor display. In some embodiments of the present disclosure, by designing the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 to be independent of each other, different scan control signals can be provided for the first initialization transistor M1 and the compensation transistor M2, respectively. For example, the first shielding module SU1 is electrically connected with the first scan control signal terminal Ga1, thereby providing the first scan control signal ga1 for the compensation transistor M2. The second shielding module SU2 is electrically connected with the second scan control signal terminal Ga2, thereby providing the second scan control signal ga2 for the first initialization transistor M1. The first scan control signal ga1 and the second scan control signal ga2 can be different, thereby realizing separate control of the first initialization transistor M1 and the compensation transistor M2, so as to accurately control the reset and data writing of the high-frequency and low-frequency areas, thereby improving the display effect of the display substrate with the local refresh function.

[0080] Exemplarily, referring to FIG. 5B, in the first stage F1, the first scan control signal ga1 output by the first shielding module SU1 is a low-level signal, the second scan control signal ga2 output by the second shielding module SU2 is a low-level signal, the data writing transistor M4 and the compensation transistor M2 are controlled to be turned on, and data writing is performed; the second light-emitting control signal em2 is changed from a high level to a low level, and the node O2 and the node O4 are refreshed. Subsequently, the first light-emitting control signal em1 is changed from a high level to a low level, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are controlled to be turned on, so that the light-emitting element emits light. At the same time, the first cascade module Gate1 and the second cascade module Gate2 of the previous row of pixels transmit cascade signals to the shift register corresponding to the next row of pixels, so that the shift register corresponding to the next row of pixels starts to provide the gate driving signal for the pixels of the corresponding row. The second scan control signal ga2 corresponding to the next row of pixels controls the first initialization transistor M1 in the pixel circuit to be turned on, and the node O1 in the pixel circuit is refreshed.

[0081] In the second stage F2, the first scan control signal ga1 and the second scan control signal ga2 are sequentially changed to high-level signals, the data writing transistor M4 and the compensation transistor M2 are controlled to be turned off, and data writing is stopped. The second light-emitting control signal em2 is changed from a high level to a low level, and the node O2 and the node O4 are reset. Subsequently, the first light-emitting control signal em1 is changed from a high level to a low level, the first light-emitting control transistor M5 and the second light-emitting control transistor M6 are controlled to be turned on, so that the light-emitting element maintains the previous light-emitting state (also called frame retention display), and low-frequency display is realized. At the same time, the first cascade module Gate1 and the second cascade module Gate2 of the previous row of pixels can stop transmitting cascade signals to the shift register corresponding to the next row of pixels, so as to realize low-frequency local refresh display.

[0082] In the third stage F3, the process in the first stage F1 is repeated to control the pixel circuit to perform refresh display.

[0083] In the fourth stage F4, the process in the second stage F2 is repeated to control the pixel circuit to perform frame retention display, so as to realize low-frequency display.

[0084] Exemplarily, in the first stage F1 to the fourth stage F4, the first shielding signal ga1 and the second shielding signal ga2 can make the pixel circuit perform data refresh. That is, in FIG. 5B, the first shielding signal ga1 and the second shielding signal ga2 are valid level signals that can make the pixel circuit perform refresh.

[0085] Exemplarily, the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 in the first shift register unit each include two modules, one of which is used to transmit a cascade signal, and the other of which is used to transmit a scan control signal to the pixel circuit, and the cascade signal and the scan control signal do not affect each other. For example, the first cascade signal carry1 output by the first cascade module Gate1 and the first scan control signal ga1 of the first scan control signal end Ga1 do not affect each other. For another example, the second cascade signal carry2 output by the second cascade module Gate2 and the second scan control signal ga2 of the second scan control signal end Ga2 do not affect each other.

[0086] The shift register in the embodiment of FIG. 4 does not have a local refresh function, and thus only one scan control signal, for example, the first scan control signal ga1, is needed. The shift register in the embodiment of FIG. 6 needs to generate different first scan control signals ga1 and second scan control signals ga2 at the same time in order to realize the local refresh function. Therefore, the design of the shift register unit in the embodiment of FIG. 6 becomes more complex, more wirings are needed, and thus more layout space is needed.

[0087] FIG. 7 is a structural block diagram of a first scan signal output module according to an embodiment of the present disclosure; FIG. 8 is an equivalent circuit diagram of a first scan signal output module according to an embodiment of the present disclosure; FIG. 9A is one of timing diagrams of a shift register according to an embodiment of the present disclosure; and FIG. 9B is a flowchart of a driving method of a shift register according to an embodiment of the present disclosure.

[0088] In some embodiments, the equivalent circuit diagrams of the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 can be the same.

[0089] Exemplarily, in combination with reference to FIG. 5A, FIG. 6 and FIG. 8, the shift register includes a plurality of cascaded first shift register units GOA-Ga configured to provide scan control signals. The first shift register unit GOA-Ga can include a first scan signal output module GOA-Ga1 and a second scan signal output module GOA-Ga2. The first scan signal output module GOA-Ga1 is configured to control the pixel circuit 10 of the pixel to perform data refresh or not to refresh. The second scan signal output module GOA-Ga2 is configured to control the initialization of part of nodes in the pixel circuit 10, for example, to control the initialization of the node O1 in the pixel circuit 10 as shown in FIG. 5A.

[0090] Exemplarily, with reference to FIGS. 7 and 8, one of the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 can include the control sub-circuit 40, the first output sub-circuit 50, and the second output sub-circuit 60.

[0091] The control sub-circuit 40 is electrically connected with the first signal input terminal STV1, the first clock signal terminal GCK, the second clock signal terminal GCB, the first voltage terminal VGH, and the second voltage terminal VGL, and is configured to provide the first input signal stv1 of the first signal input terminal STV1 or the first voltage signal vgh of the first voltage terminal VHG to the first node N1, and provide the second voltage signal vg1 of the second voltage terminal VGL or the first clock signal gck of the first clock signal terminal GCK to the second node N2.

[0092] The first output sub-circuit 50 is electrically connected with the second clock signal terminal GCB, the first voltage terminal VGH, the second voltage terminal VGL, and the first signal output terminal Gc, and is configured to provide the first voltage signal vgh or the second clock signal gcb of the second clock signal terminal GCB to the first signal output terminal Gc under the control of the voltage of the first node N1 and the voltage of the second node N2. The first signal output terminal Gc can output the cascade signal carry. For example, the first signal output terminal Gc of the first output sub-circuit 50 can input the cascade signal carry to the control sub-circuit 40 of the next stage first shift register unit GOA-Ga.

[0093] Exemplarily, with reference to FIGS. 6 and 8, the first signal output terminal Gc of the n-th first shift register unit GOA-Ga is connected with the first signal input terminal STV1 of the n+i-th first shift register unit GOA-Ga, so as to transmit the cascade signal carry. Wherein, 1≤n≤N, i is an integer greater than or equal to 1, and N is the total number of stages of the shift register unit.

[0094] Exemplarily, with reference to FIG. 6, the cascade signal carry can include a first cascade signal carry1, so as to realize the cascade signal transmission between a plurality of cascaded first scan signal output modules GOA-Ga1.

[0095] Exemplarily, the cascade signal carry can also include a second cascade signal carry2, so as to realize the cascade signal transmission between a plurality of cascaded second scan signal output modules GOA-Ga2.

[0096] Exemplarily, in combination with reference to FIGS. 7-9A, the second output sub-circuit 60 is electrically connected with the first voltage terminal VGH, the second voltage terminal VGL, the shielding signal terminal EN and the second signal output terminal Ga, and is configured to provide the first voltage signal vgh or the shielding signal en of the shielding signal terminal EN to the second signal output terminal Ga under the control of the voltage of the first node N1 and the voltage of the second node N2. The shielding signal en can include a first shielding signal en1 and a second shielding signal en2.

[0097] Exemplarily, the shielding signal en is a valid level signal in the first refresh time period t01, the shielding signal en is changed from the valid level signal to an invalid level signal in the second refresh time period t02, and the second refresh time t02 period is after the first refresh time period t01.

[0098] It should be noted that the valid level signal in the shielding signal refers to a level signal capable of driving the pixel circuit to refresh, and the invalid level signal refers to a level signal incapable of driving the pixel circuit to refresh. For example, with reference to FIG. 9A, the valid level signal in the shielding signal en includes periodically changed high level signals and low level signals. The invalid level signal in the shielding signal en includes a continuous high level signal.

[0099] Exemplarily, the shielding signal en remains as the invalid level signal in the third refresh time period t03, and the third refresh time period t03 is after the second refresh time period t02.

[0100] By designing the shielding signal as the valid level signal in the first refresh time period t01, the shielding signal as the invalid level signal in the second refresh time period t02, and the shielding signal as the invalid level signal in the third refresh time period t03, the corresponding display area can be controlled to refresh data in the first refresh time period t01, stop refreshing in the second refresh time period t02, and keep the data not refreshing in the third refresh time period t03, so that the low-frequency local refresh display can be realized.

[0101] Exemplarily, with reference to FIG. 8, the equivalent circuit of one of the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 can be a “11T3C” circuit. One of the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 can include the control sub-circuit 40, the first output sub-circuit 50 and the second output sub-circuit 60.

[0102] Exemplarily, in combination with reference to FIGS. 6-8, the control sub-circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4 and a fifth transistor T5.

[0103] The control electrode of the first transistor T1 is electrically connected with the first clock signal terminal GCK, the first electrode of the first transistor T1 is connected with the first signal input terminal STV1, and the second electrode of the first transistor T1 is electrically connected with the first node N1.

[0104] The control electrode of the second transistor T2 is electrically connected with the first node N1, the first electrode of the second transistor T2 is electrically connected with the first clock signal terminal GCK, and the second electrode of the second transistor T2 is electrically connected with the second node N2.

[0105] The control electrode of the third transistor T3 is electrically connected with the first clock signal terminal GCK, the first electrode of the third transistor T3 is electrically connected with the second voltage terminal VGL, and the second electrode of the third transistor T3 is electrically connected with the second node N2.

[0106] The control electrode of the fourth transistor T4 is electrically connected with the second node N2, the first electrode of the fourth transistor T4 is electrically connected with the first voltage terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected with the third node N3. The control electrode of the fifth transistor T5 is electrically connected with the second clock signal terminal GCB, the first electrode of the fifth transistor T5 is electrically connected with the third node N3, and the second electrode of the fifth transistor T5 is electrically connected with the first node N1.

[0107] The first output sub-circuit 50 comprises a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1 and a second capacitor C2.

[0108] The control electrode of the sixth transistor T6 is electrically connected with the second node N2, the first electrode of the sixth transistor T6 is electrically connected with the first voltage terminal VGH, and the second electrode of the sixth transistor T6 is electrically connected with the first signal output terminal Gc.

[0109] The control electrode of the seventh transistor T7 is electrically connected with the fourth node N4, the first electrode of the seventh transistor T7 is electrically connected with the second clock signal terminal GCB, and the second electrode of the seventh transistor T7 is electrically connected with the first signal output terminal Gc.

[0110] The control electrode of the eighth transistor T8 is electrically connected with the second voltage terminal VGL, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4.

[0111] The first end (also can be called the first electrode plate) of the first capacitor C1 is electrically connected with the second node N2, and the second end (also can be called the second electrode plate) of the first capacitor C1 is electrically connected with the first voltage terminal VGH.

[0112] The first end of the second capacitor C2 is electrically connected with the control electrode of the seventh transistor T7, and the second end of the second capacitor C2 is connected with the first signal output terminal Gc.

[0113] Exemplarily, with reference to FIGS. 6 and 8, the plurality of cascaded first scan signal output modules GOA-Ga1 can be electrically connected through the first signal output end Gc in the first scan signal output module GOA-Ga1 to realize transmission of the first cascaded signal carry1. The plurality of cascaded second scan signal output modules GOA-Ga2 can be electrically connected through the first signal output end Gc in the second scan signal output module GOA-Ga2 to realize transmission of the second cascaded signal carry2.

[0114] Exemplarily, the second output sub-circuit 60 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a third capacitor C3.

[0115] The control electrode of the ninth transistor T9 is electrically connected with the second node N2, the first electrode of the ninth transistor T9 is electrically connected with the first voltage end VGH, and the second electrode of the ninth transistor T9 is electrically connected with the second signal output end Ga.

[0116] The control electrode of the tenth transistor T10 is electrically connected with the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected with the shielding signal end EN, and the second electrode of the tenth transistor T10 is electrically connected with the second output signal end Ga.

[0117] The control electrode of the eleventh transistor T11 is electrically connected with the second voltage end VGL, the first electrode of the eleventh transistor T11 is electrically connected with the first node N1, and the second electrode of the eleventh transistor T11 is electrically connected with the fifth node N5.

[0118] The first end of the third capacitor C3 is electrically connected with the control electrode of the tenth transistor T10, and the second end of the third capacitor C3 is electrically connected with the second signal output end Ga.

[0119] With reference to FIGS. 6 and 8, the second signal output end Ga is electrically connected with part of the transistors in the pixel circuit to provide a scan control signal for the pixel circuit, for example, a first scan control signal ga1 and a second scan control signal ga2. By controlling the potential of the first scan control signal ga1 and the second scan control signal ga2, the corresponding pixel can be controlled to be refreshed or not to be refreshed.

[0120] Exemplarily, referring to FIG. 8, the signal output by the second signal output terminal Ga is regulated by the second output sub-circuit 60, and one of the first voltage signal vgh or the shielding signal en can be output. The first voltage signal vgh can be used to reset the node potential of the second signal output terminal Ga. The shielding signal en can be used to control the pixel circuit to refresh, stop refreshing, or keep not refreshing, so as to realize local low-frequency refreshing display. For example, in combination with FIGS. 5-9A, when the shielding signal en is a valid level signal, the first scan control signal ga1 and the second scan control signal ga2 can be controlled to change from a high level signal to a low level signal in a part of time period, so as to control the first initialization transistor M1, the compensation transistor M2 and the data writing transistor M4 in the pixel circuit 10 to be turned on, write the data signal into the pixel circuit, and control the pixel circuit to refresh. When the shielding signal en is an invalid level signal, the first scan control signal ga1 and the second scan control signal ga2 can be controlled to keep as high level signals, so as to control the first initialization transistor M1, the compensation transistor M2 and the data writing transistor M4 in the pixel circuit 10 to be turned off, and control the pixel circuit to stop refreshing or keep not refreshing.

[0121] Exemplarily, the shielding signal en can include a first shielding signal en1 and a second shielding signal en2. The shielding signal terminals EN in the plurality of cascaded first shift register units GOA-Ga are alternatively connected to the first shielding signal en1 and the second shielding signal en2. For example, the shielding signal terminals EN of the plurality of cascaded first scan signal output modules GOA-Ga1 are alternatively connected to the first shielding signal en1 and the second shielding signal en2. And the shielding signal terminals EN of the plurality of cascaded second scan signal output modules GOA-Ga2 are alternatively connected to the first shielding signal en1 and the second shielding signal en2. By controlling the potential of the shielding signal en, the potential of the first scan control signal ga1 and the second scan control signal ga2 can be controlled, and then whether the pixel circuit is refreshed or not can be controlled.

[0122] Exemplarily, in some embodiments of the present disclosure, the driving method of the shift register can include the following S01-S03 steps.

[0123] In step S01, referring to FIGS. 5-9B, in the first refresh time period t01, the shielding signal en is a periodic active level signal, which controls the corresponding pixel to refresh data. For example, the first shielding signal en1 and the second shielding signal en2 are both active level signals, which can control the first scan control signal ga1 outputted by the second signal output end Ga in the first scan signal output module GOA-Ga1 to be a low level signal in a part of time period, so as to control the compensation transistor M2 and the data writing transistor M4 in the pixel circuit to be turned on; and control the second scan control signal ga2 outputted by the second signal output end Ga in the second scan signal output module GOA-Ga2 to be a low level signal in a part of time period, so as to control the first initialization transistor M1 in the pixel circuit to be turned on, and then control the corresponding pixel to refresh data.

[0124] In step S02, in the second refresh time period t02, the shielding signal en is changed from the active level signal to the inactive level signal, which controls the corresponding pixel to stop refreshing data. For example, the first shielding signal en1 and the second shielding signal en2 are changed from the active level signal to the inactive level signal, which controls the first scan control signal ga1 and the second scan control signal ga2 to be a high level signal, and then controls the corresponding pixel to stop refreshing data.

[0125] In step S03, in the third refresh time period t03, the shielding signal en remains the inactive level signal, which controls the corresponding pixel to keep data not refreshed. For example, the first shielding signal en1 and the second shielding signal en2 remain the inactive level signal, which controls the first scan control signal ga1 and the second scan control signal ga2 to be a high level signal, and then controls the corresponding pixel to keep data not refreshed.

[0126] In the first refresh time period t01, the second refresh time period t02 and the third refresh time period t03, the first cascade signal carry1 and the second cascade signal carry2 are not affected by the first shielding signal en1 and the second shielding signal en2, which can ensure that the cascade signals are normally transmitted between the plurality of cascaded first shift register units GOA-Ga, so as to ensure that the plurality of cascaded first shift register units GOA-Ga can drive and scan the plurality of rows of pixels in turn.

[0127] FIG. 10 is a partial planar schematic view of a shift register according to an embodiment of the present disclosure.

[0128] In some embodiments, referring to FIGS. 1, 6 and 10, the display substrate 1000 includes a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA includes a first region NA1 and a second region NA2 located on opposite sides of the display area AA. A plurality of cascaded first scan signal output modules GOA-Ga1 and a plurality of cascaded second scan signal output modules GOA-Ga2 are symmetrically arranged in the non-display area NA on both sides of the display area AA. For example, a plurality of cascaded first shift register units GOA-Ga in the shift register GOA are symmetrically distributed in the first region NA1 and the second region NA2 with respect to the display area AA.

[0129] For example, a plurality of cascaded second shift register units GOA-EM in the shift register GOA are symmetrically distributed in the first region NA1 and the second region NA2 with respect to the display area AA.

[0130] The symmetric arrangement of the shift register in the non-display area on both sides of the display area is beneficial to improve display uniformity and enhance display effect.

[0131] In some embodiments, the plurality of cascaded first scan signal output modules GOA-Ga1 and the plurality of cascaded second scan signal output modules GOA-Ga2 perform bilateral driving on the pixel circuit, so as to reduce the adverse effects of voltage drop on signals and improve driving effect.

[0132] For example, referring to FIGS. 6 and 10, the pixel circuit of a row of pixels is electrically connected to two first scan signal output modules GOA-Ga1 on the left and right sides, and the two first scan signal output modules GOA-Ga1 electrically connected to the same row of pixels are symmetrically distributed in the first region NA1 and the second region NA2 with respect to the display area AA. That is, the plurality of cascaded first scan signal output modules GOA-Ga1 on both sides perform bilateral driving on the pixel circuit.

[0133] For example, the pixel circuit of a row of pixels is electrically connected to two second scan signal output modules GOA-Ga2 on the left and right sides, and the two second scan signal output modules GOA-Ga2 electrically connected to the same row of pixels are symmetrically distributed in the first region NA1 and the second region NA2 with respect to the display area AA. That is, the plurality of cascaded second scan signal output modules GOA-Ga2 on both sides perform bilateral driving on the pixel circuit.

[0134] Referring to Figures 6 and 10, the second shift register unit GOA-EM includes multiple cascaded first light-emitting signal output modules GOA-EM1 and second light-emitting signal output modules GOA-EM2 located in the non-display areas on both sides of the display area. The first light-emitting signal output module GOA-EM1 is electrically connected to two adjacent rows of pixels and is configured to provide a first light-emitting control signal em1 to the pixel circuits of the adjacent rows of pixels. The second light-emitting signal output module GOA-EM2 is electrically connected to two adjacent rows of pixels and is configured to provide a second light-emitting control signal em2 to the pixel circuits of the adjacent rows of pixels. The first light-emitting signal output modules GOA-EM1 and GOA-EM2 corresponding to two adjacent rows of pixels are symmetrically distributed about the display area AA in the first region NA1 and the second region NA2. For example, referring to Figure 6, the first light-emitting signal output modules GOA-EM1 and GOA-EM2 can be located on different sides of the display area AA. For example, the first light-emitting signal output module GOA-EM1 is located in the first region NA1 on the left, and the second light-emitting signal output module GOA-EM2 is located in the second region NA2 on the right. The first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 can be symmetrical about the display area AA, thereby improving the uniformity of the display.

[0135] At least some transistors in two adjacent rows of pixel circuits are electrically connected to the same first light-emitting signal output module GOA-EM1; and at least another portion of transistors in two adjacent rows of pixel circuits are electrically connected to the same second light-emitting signal output module GOA-EM2, thereby achieving unilateral driving of the pixel circuits. For example, referring to Figures 5, 6, and 10, a first light-emitting signal output module GOA-EM1 located in the first region NA1 can be electrically connected to both the first light-emitting control transistor M5 and the second light-emitting control transistor M6 in the pixel circuits of the two rows of pixels. A second light-emitting signal output module GOA-EM2 located in the second region NA2 can be electrically connected to both the second initialization transistor M7 and the third initialization transistor M8 in the pixel circuits of the two rows of pixels.

[0136] Multiple cascaded first light-emitting signal output modules GOA-EM1 and second light-emitting signal output modules GOA-EM2 drive the pixel circuit on one side, which helps to reduce wiring space and facilitates the narrowing of the display substrate's bezel.

[0137] In some embodiments, referring to Figures 6 and 9A, a row of pixels is electrically connected to two second scan signal output modules GOA-Ga2. The shielding signals en corresponding to two adjacent rows of pixels are the first shielding signal en1 and the second shielding signal en2, respectively.

[0138] In the first refresh time period t01, the first shielding signal en1 and the second shielding signal en2 are periodic active level signals staggered by a stagger time ta. The stagger time ta is a time in which the potential of the active level signal in a single period of the periodic active level signal is equal to the active potential. For example, when the transistor in the circuit is a P-type transistor, the active potential is a low potential. The pixel circuits of two adjacent rows of pixels control the corresponding two rows of pixels to perform data refresh in turn in response to the first shielding signal en1 and the second shielding signal en2. The shift register connected to multiple rows of pixels alternately accesses the first shielding signal en1 and the second shielding signal en2, so that the multiple rows of pixels can be controlled to perform refresh in turn.

[0139] For example, in the first refresh time period t01, in combination with reference to FIGS. 8 and 9A, the shielding signal en in the shielding signal end EN connected to the tenth transistor T10 in the first shift register unit GOA-Ga is the same as one of the first clock signal gck in the first clock signal end GCK and the second clock signal gcb in the second clock signal end GCB. For example, the first shielding signal en1 is the same as the first clock signal gck, and the second shielding signal en2 is the same as the second clock signal gcb. At this time, the first scan control signal ga1 and the second scan control signal ga2 output by the second output signal end Ga are low level signals in part of the time period, control the first initialization transistor M1, the compensation transistor M2 and the data writing transistor M4 in the pixel circuit to be turned on, write the data signal into the pixel circuit, and control the pixel circuit to perform refresh.

[0140] Embodiments of the present disclosure take the example of a transistor being turned on under a low level signal (i.e., the transistor is a P-type transistor) to illustrate the driving mode of the shift register, but the present disclosure is not limited thereto. The transistor of the present disclosure can also be an N-type transistor, and accordingly, the transistor is turned on under a high level signal. Alternatively, the transistor of the present disclosure can include a combination of P-type transistors and N-type transistors.

[0141] In the second refresh time period t02, the first shielding signal en1 and the second shielding signal en2 are sequentially and intermittently changed from the active level signal to the inactive level signal. For example, the first shielding signal en1 is changed to the inactive level signal at the first time t1, and the second shielding signal en2 is changed to the inactive level signal at the second time t2. Accordingly, the first scan control signal ga1 and the second scan control signal ga2 output by the second signal output end Ga remain high level signals in the second refresh time period t02, and control the corresponding two rows of pixels to stop data refresh. For example, the second time t2 and the first time t1 can be staggered by a stagger time ta. The multiple cascaded first shift register units GOA-Ga sequentially drive the pixel circuits of multiple rows of pixels, so as to control the multiple rows of pixels to stop refresh.

[0142] In the third refresh time period t03, the first shielding signal en1 and the second shielding signal en2 remain as the inactive level signals, and accordingly, the first scan control signal ga1 and the second scan control signal ga2 remain as the high level signals in the third refresh time period t03, to control the corresponding two rows of pixels to keep data unrefreshed.

[0143] FIG. 11 is a plan view of a first scan signal output module GOA-Ga1 according to an embodiment of the present disclosure; FIG. 12 is a plan view of a second scan signal output module GOA-Ga2 according to an embodiment of the present disclosure; and FIG. 13 is a sectional view taken along line AA’ in FIG. 11.

[0144] Exemplarily, referring to FIG. 13, the display substrate includes a substrate substrate 1 and a first semiconductor layer 101, a first conductive layer 102, a second conductive layer 103, a third conductive layer 104 and a fourth conductive layer 105 which are sequentially stacked on the substrate substrate 1. The display substrate can further include a plurality of insulating layers between the plurality of conductive layers.

[0145] At least one of the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 includes a plurality of transistors and at least one capacitor. The active layers ACT of the plurality of transistors are located in the first semiconductor layer 101. The control electrodes G of the plurality of transistors and the first electrode plates ED1 of the at least one capacitor are located in the first conductive layer 102. The second electrode plates ED2 of the at least one capacitor are located in the second conductive layer 103. The first electrodes S and the second electrodes D of at least one of the plurality of transistors are located in the third conductive layer 104. The display substrate 1000 further includes a first clock signal line Gck and a second clock signal line Gcb extending along the second direction Y, at least one of which is located in the fourth conductive layer 105. The first clock signal line Gck is electrically connected with the first shift register unit GOA-Ga and is configured to provide a first clock signal gck. The second clock signal line Gcb is electrically connected with the first shift register unit GOA-Ga and is configured to provide a second clock signal gcb.

[0146] Exemplarily, in combination with reference to FIGS. 8, 11 and 12, at least one of the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 includes a first transistor T1 to an eleventh transistor T11, a first capacitor C1, a second capacitor C2 and a third capacitor C3. For example, the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 can both be “11T3C” circuits.

[0147] The active layers ACT of the first transistor T1 to the eleventh transistor T11 are located in the first semiconductor layer 101.

[0148] The control electrode G of the first transistor T1 to the eleventh transistor T11 and the first electrode plate ED1 of at least one of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are located in the first conductive layer 102.

[0149] The second electrode plate ED2 of at least one of the first capacitor C1, the second capacitor C2, and the third capacitor C3 is located in the second conductive layer 103.

[0150] The first electrode S and the second electrode D of at least one of the first transistor T1 to the eleventh transistor T11 are located in the third conductive layer 104.

[0151] The display substrate further includes a first signal input line, a first voltage line Vgh, a second voltage line Vgl, a first clock signal line Gck, a second clock signal line Gcb, a first shield signal line Enl, and a second shield signal line En2 extending along the second direction Y. At least one of the first signal input line, the first voltage line Vgh, the second voltage line Vgl, the first clock signal line Gck, the second clock signal line Gcb, the first shield signal line Enl, and the second shield signal line En2 is located in the fourth conductive layer 105.

[0152] The first signal input line is connected with the first signal input end STV1. The first voltage line Vgh is connected with the first voltage end VGH. The second voltage line Vgl is connected with the second voltage end VGL. The first clock signal line Gck is connected with the first clock signal end GCK. The second clock signal line Gcb is connected with the second clock signal end GCB. One of the first shield signal line Enl and the second shield signal line En2 is connected with the shield signal end EN. For example, the first shield signal line Enl and the second shield signal line En2 are alternately connected with the tenth transistor T10-1 in the plurality of cascaded first scan signal output modules GOA-Gal in the odd and even rows. For another example, the first shield signal line Enl and the second shield signal line En2 are alternately connected with the tenth transistor T10-2 in the plurality of cascaded second scan signal output modules GOA-Ga2 in the odd and even rows.

[0153] With reference to FIGS. 5A, 6, 8, and 11, the first scan signal output module GOA-Gal is configured to control the compensation transistor M2 and the data writing transistor M4 in the pixel circuit. The ninth transistor T9-1 and the tenth transistor T10-1 in the first scan signal output module GOA-Gal share a first active layer ACT1, and the first active layer ACT1 has a fourth width d4 in the first direction X.

[0154] With reference to FIGS. 5A, 6, 8 and 12, the second scan signal output module GOA-Ga2 is configured to control the first initialization transistor M1 in the pixel circuit. The ninth transistor T9-2 and the tenth transistor T10-2 in the second scan signal output module GOA-Ga2 share one second active layer ACT2. The second active layer ACT2 has a fifth width d5 in the first direction X.

[0155] Since the number of transistors driven by the ninth transistor T9-1 and the tenth transistor T10-1 in the first scan signal output module GOA-Ga1 is more than the number of transistors driven by the ninth transistor T9-2 and the tenth transistor T10-2 in the second scan signal output module GOA-Ga2, the driving load is greater, therefore, the fourth width d4 of the first active layer ACT1 is greater than the fifth width d5 of the second active layer ACT2, so as to ensure that the driving performance of the ninth transistor T9-1 and the tenth transistor T10-1 in the first scan signal output module GOA-Ga1 is higher than the driving performance of the ninth transistor T9-2 and the tenth transistor T10-2 in the second scan signal output module GOA-Ga2.

[0156] Exemplarily, the fourth transistor T4-1 and the fifth transistor T5-1 in the first scan signal output module GOA-Ga1 share one third active layer ACT3, and the third active layer ACT3 has a sixth width d6 in the first direction. The sixth width d6 is less than the fourth width d4.

[0157] Exemplarily, the fourth transistor T4-2 and the fifth transistor T5-2 in the second scan signal output module GOA-Ga2 share one fourth active layer ACT4, and the fourth active layer ACT4 has a seventh width d7 in the first direction. The seventh width d7 is less than the fifth width d5.

[0158] In some embodiments, with reference to FIG. 11, the fourth transistor T4 and the fifth transistor T5 of the first scan signal output module GOA-Ga1 no longer undertake the output function, and can be reduced in size, which is conducive to realizing narrow frame.

[0159] In some embodiments, with reference to FIG. 12, the fourth transistor T4 and the fifth transistor T5 of the second scan signal output module GOA-Ga2 no longer undertake the output function, and can be reduced in size, which is conducive to realizing narrow frame.

[0160] FIG. 14 is an equivalent circuit diagram of a second shift register unit according to an embodiment of the present disclosure; and FIG. 15 is a plan view of the second shift register unit according to an embodiment of the present disclosure.

[0161] Exemplarily, in the embodiment of the present disclosure, the second shift register unit GOA-EM includes a first light-emitting signal output module GOA-EM1 and a second light-emitting signal output module GOA-EM2. The equivalent circuit of one of the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 can be a “13T3C” circuit as shown in FIGS. 14 and 15.

[0162] Exemplarily, at least one of the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 includes twenty-first to thirty-third transistors. The twenty-first to thirty-third transistors can be sequentially numbered as Z1, Z2, …, Z13. At least one of the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 further includes a third output signal terminal Em configured to provide a light-emitting control signal. The second electrode of the twenty-ninth transistor Z9 is electrically connected to the third output signal terminal Em. The first electrode of the thirtieth transistor Z10 is electrically connected to the third output signal terminal Em.

[0163] Exemplarily, one of the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 can further include capacitors C001, C002 and C003.

[0164] Exemplarily, the second shift register unit GOA-EM is electrically connected to the second signal input terminal STV2, the first voltage terminal VGH, the second voltage terminal VGL, the third clock signal terminal ECK, the fourth clock signal terminal ECB, the fifth clock signal terminal ECX and the third signal output terminal Em. The third signal output terminal Em in the first light-emitting signal output module GOA-EM1 can provide a first light-emitting control signal em1 to the pixel circuit. The third signal output terminal Em in the second light-emitting signal output module GOA-EM2 can provide a second light-emitting control signal em2 to the pixel circuit.

[0165] The display substrate further includes a second signal input line Stv2, a third clock signal line Eck, a fourth clock signal line Ecb and a fifth clock signal line Ecx extending along the second direction. At least one of the second signal input line Stv2, the third clock signal line Eck, the fourth clock signal line Ecb and the fifth clock signal line Ecx is located in the fourth conductive layer 105.

[0166] The second signal input line Stv2 is connected with the second signal input terminal STV2. The third clock signal line Eck is connected with the third clock signal terminal ECK and is configured to provide a third clock signal. The fourth clock signal line Ecb is connected with the fourth clock signal terminal ECB and is configured to provide a fourth clock signal. The fifth clock signal line Eck is connected with the fifth clock signal terminal ECX and is configured to provide a fifth clock signal.

[0167] Exemplarily, the first clock signal line Gck, the second clock signal line Gcb, the third clock signal line Eck, the fourth clock signal line Ecb and the fifth clock signal line Eck are independent from each other.

[0168] FIG. 16 is a structural block diagram of a shift register according to some other embodiments of the present disclosure; FIG. 17 is a timing diagram of a shift register according to embodiments of the present disclosure; and FIG. 18 is a partial plan view of a shift register according to some other embodiments of the present disclosure.

[0169] In some embodiments of the present disclosure, similar to the shift register GOA shown in FIG. 6, the shift register GOA in FIG. 16 can include a plurality of cascaded first shift register units GOA-Ga and a plurality of cascaded second shift register units GOA-EM. The first shift register unit GOA-Ga can include a first scan signal output module GOA-Gal and a second scan signal output module GOA-Ga2. The second shift register unit GOA-EM includes a first light emitting signal output module GOA-EMl and a second light emitting signal output module GOA-EM2. The equivalent circuits of the first shift register unit GOA-Ga and the second shift register unit GOA-EM in the embodiment of FIG. 16 can be the same as those of the first shift register unit GOA-Ga and the second shift register unit GOA-EM in the embodiment of FIG. 6, which will not be repeated here.

[0170] Unlike the shift register of the embodiment of FIG. 6, in the shift register of the embodiment of FIG. 16, the second scan signal output modules of adjacent stages are connected with pixels in different rows. For example, one row of pixels is electrically connected with one second scan signal output module GOA-Ga2. That is, the second scan signal output module GOA-Ga2 can unilaterally drive the pixel circuit. For example, in combination with reference to FIG. 16 and FIG. 18, the pixels in the odd-numbered rows are electrically connected with the second scan signal output modules GOA-Ga2 located in the first area NA1, and the pixels in the even-numbered rows are electrically connected with the second scan signal output modules GOA-Ga2 located in the second area NA2. The two second scan signal output modules GOA-Ga2 corresponding to the two adjacent rows of pixels are symmetrically distributed in the first area NA1 and the second area NA2 about the display area AA, which is conducive to improving the display uniformity of the display substrate.

[0171] In the embodiment of FIG. 16, the second scan signal output module GOA-Ga2 can employ a single-side driving design for the pixel circuit, and thus the number of the second scan signal output module GOA-Ga2 can be reduced by half compared with the number of the second scan signal output module GOA-Ga2 in the embodiment of FIG. 6, which is conducive to reducing the space occupied by the shift register wiring.

[0172] For example, continuing to refer to FIG. 16, the first scan signal output modules on the left and right sides of the same row are connected with the same pixel row. For example, a row of pixels arranged along the first direction is electrically connected with two first scan signal output modules GOA-Ga1. That is, the first scan signal output module GOA-Ga1 performs double-side driving for the pixel circuit. The two first scan signal output modules GOA-Ga1 corresponding to the same row of pixels are symmetrically distributed in the first region NA1 and the second region NA2 about the display area AA, which is conducive to improving the display uniformity of the display substrate.

[0173] For example, the first emission signal output modules GOA-EM1 of adjacent stages are connected with different rows of pixels.

[0174] For example, the second emission signal output modules GOA-EM2 of adjacent stages are connected with different rows of pixels. Two adjacent rows of pixels are electrically connected with one first emission signal output module GOA-EM1; and two adjacent rows of pixels are electrically connected with one second emission signal output module GOA-EM2. That is, one second shift register unit GOA-EM can drive two rows of pixels. The first emission signal output module GOA-EM1 and the second emission signal output module GOA-EM2 perform single-side driving for the pixel circuit. The one first emission signal output module GOA-EM1 and the one second emission signal output module GOA-EM2 electrically connected with the two adjacent rows of pixels are symmetrically distributed in the first region NA1 and the second region NA2 about the display area. Through such a symmetric design, the display uniformity of the display substrate can be improved.

[0175] For example, continuing to refer to FIG. 18, at least one of the first emission signal output module GOA-EM1 and the second emission signal output module GOA-EM2 is spaced apart from the second scan signal output module GOA-Ga2 in the second direction Y and aligned with the second scan signal output module GOA-Ga2 in the first direction X. For example, in the first region NA1, a plurality of cascaded second scan signal output modules GOA-Ga2 and a plurality of cascaded first emission signal output modules GOA-EM1 are alternately arranged along the second direction Y. And / or, in the second region NA2, a plurality of cascaded second scan signal output modules GOA-Ga2 and a plurality of cascaded second emission signal output modules GOA-EM2 are alternately arranged along the second direction Y.

[0176] By designing the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 to be alternately arranged in the second direction Y and aligned in the first direction X with the second scan signal output module GOA-Ga2, the space occupied by the wiring in the first direction can be reduced, which is conducive to the narrow bezel of the display substrate. For example, compared with the shift register in the embodiment of FIG. 6, the shift register in the embodiment of FIG. 16 can reduce the width required for the wiring of about one first light-emitting signal output module GOA-EM1 in the first direction, thereby facilitating the narrow bezel of the display substrate.

[0177] For example, in combination with reference to FIGS. 16 and 17, one row of pixels is electrically connected with one second scan signal output module GOA-Ga2, that is, the second scan signal output module GOA-Ga2 adopts a single-side driving design. At this time, the shielding signals corresponding to the four adjacent rows of pixels are the first sub-shielding signal en1-L, the second sub-shielding signal en1-R, the third sub-shielding signal en2-L, and the fourth sub-shielding signal en2-R. The first sub-shielding signal en1-L and the second sub-shielding signal en1-R can be provided by the first shielding signal line En1 in odd and even rows, and the third sub-shielding signal en2-L and the fourth sub-shielding signal en2-R can be provided by the second shielding signal line En2 in odd and even rows.

[0178] In the first refresh time period t01, the first sub-shielding signal en1-L, the second sub-shielding signal en1-R, the third sub-shielding signal en2-L, and the fourth sub-shielding signal en2-R are effective level signals staggered by one stagger time ta in sequence, and the pixel circuits of the four adjacent rows of pixels control the corresponding four rows of pixels to perform data refresh in sequence in response to the first sub-shielding signal en1-L, the second sub-shielding signal en1-R, the third sub-shielding signal en2-L, and the fourth sub-shielding signal en2-R. For example, in the first refresh time period t01, in response to the first sub-shielding signal en1-L, the second sub-shielding signal en1-R, the third sub-shielding signal en2-L, and the fourth sub-shielding signal en2-R, the first shift register unit GOA-Ga provides the first sub-scan control signal ga1-L, the second sub-scan control signal ga2-R, the third sub-scan control signal ga3-L, and the fourth sub-scan control signal ga4-R for the four rows of pixels as shown in FIG. 17, respectively. The first sub-scan control signal ga1-L, the second sub-scan control signal ga2-R, the third sub-scan control signal ga3-L, and the fourth sub-scan control signal ga4-R are low-level signals in part of the first refresh time period t01, which can control the compensation transistor M2, the data writing transistor M4, and the first initialization transistor M1 in the pixel circuit to be turned on, thereby controlling the corresponding four rows of pixels to perform data refresh in sequence.

[0179] At the second refresh time period t02, the first sub-shield signal en1-L is switched to the invalid level signal at the first time t1, the second sub-shield signal en1-R is switched to the invalid level signal at the second time t2, the third sub-shield signal en2-L is switched to the invalid level signal at the third time t3, and the fourth sub-shield signal en2-R is switched to the invalid level signal at the fourth time t4, thereby controlling the corresponding four rows of pixels to stop data refresh in turn. The first time t1, the second time t2, the third time t3, and the fourth time t4 are sequentially spaced apart by a misalignment time ta.

[0180] At the third refresh time period t03, the first sub-shield signal en1-L, the second sub-shield signal en1-R, the third sub-shield signal en2-L, and the fourth sub-shield signal en2-R remain invalid level signals, thereby controlling the corresponding four rows of pixels to keep data from being refreshed.

[0181] Exemplarily, the first input signal stv1 can provide the first sub-input signal stv1-L and the second sub-input signal stv1-R in odd and even rows. The first clock signal gck can provide the first sub-clock signal gck-L and the second sub-clock signal gck-R in odd and even rows. The second clock signal gcb can provide the third sub-clock signal gcb-L and the fourth sub-clock signal gcb-R in odd and even rows.

[0182] Exemplarily, at the first refresh time period t01, the shield signal en accessed by the tenth transistor T10 in at least one of the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 is the same as the second clock signal gcb accessed by the fifth transistor T5. Alternatively, the shield signal en accessed by the tenth transistor T10 in at least one of the first scan signal output module GOA-Ga1 and the second scan signal output module GOA-Ga2 is the same as the first clock signal gck accessed by the second transistor T2.

[0183] Exemplarily, the embodiments of the present disclosure also provide a display substrate 1000. The display substrate 1000 includes a plurality of rows of pixels and a shift register GOA as described in any one of the preceding embodiments. It should be understood that the display substrate has the same beneficial effects as the shift register provided in the preceding embodiments.

[0184] Exemplarily, referring to FIG. 1, FIG. 16 and FIG. 18, it is shown that the display substrate 1000 comprises a display area AA and a non-display area NA surrounding the display area AA, the non-display area NA comprises a first region NA1 and a second region NA2 located at opposite sides of the display area AA. One row of pixels is electrically connected with one second scan signal output module GOA-Ga2, and two adjacent rows of pixels correspondingly are distributed in the first region NA1 and the second region NA2 of the non-display area NA symmetrically about the display area AA. At least one of the first light emitting signal output module GOA-EM1 and the second light emitting signal output module GOA-EM2 is distributed in the second direction with the second scan signal output module GOA-Ga2, and is aligned in the first direction.

[0185] By designing the second scan signal output module GOA-Ga2 as a single-side driving, and alternately arranging the first light emitting signal output module GOA-EM1 and the second light emitting signal output module GOA-EM2 in the non-display area, the number of wirings of the shift register can be reduced, and the wiring space in the non-display area can be fully utilized, thereby facilitating the narrow frame of the display substrate.

[0186] In some embodiments, two adjacent rows of pixels are electrically connected with one first light emitting signal output module GOA-EM1; and two adjacent rows of pixels are electrically connected with one second light emitting signal output module GOA-EM2. Referring to FIG. 18, one row of pixels has a first width d1 in the second direction Y, the first light emitting signal output module GOA-EM1 has a second width d2 in the second direction Y, and the second light emitting signal output module GOA-EM2 has a third width d3 in the second direction Y. Exemplarily, the first width d1 is substantially equal to the second width d2. And / or, the first width d1 is substantially equal to the third width d3.

[0187] It should be noted that "substantially equal" here means that the ratio of the two is between 0.8-1.2.

[0188] By matching the width of the first light emitting signal output module GOA-EM1 and the second light emitting signal output module GOA-EM2 in the second direction with one row of pixels, it is beneficial to save the wiring space while ensuring that the first light emitting signal output module GOA-EM1 and the second light emitting signal output module GOA-EM2 are connected with the pixel row correspondingly, and it is beneficial to realize the narrow frame of the display substrate.

[0189] Exemplarily, continuing to refer to FIG. 16 and FIG. 18, one row of pixels is electrically connected with two first scan signal output modules GOA-Ga1, and one row of pixels is electrically connected with one second scan signal output module GOA-Ga2. Therefore, the number of the first scan signal output modules GOA-Ga1 is about twice the number of the second scan signal output modules GOA-Ga2. By designing the second scan signal output module GOA-Ga2 as a single-side driving mode, the number of the second scan signal output modules GOA-Ga2 can be reduced, thereby reducing the number of wirings in the shift register, which is conducive to reducing the wiring space of the shift register and realizing the narrow frame of the display substrate.

[0190] FIG. 19 is a partial plan view of a shift register according to an embodiment of the present disclosure, in which one second scan signal output module and one second shift register unit are shown; FIG. 20 is a partial plan view of a shift register according to an embodiment of the present disclosure, in which two second scan signal output modules and two second shift register units are alternately arranged; FIG. 21A shows a plan view of a first semiconductor layer in the shift register of FIG. 19; FIG. 21B shows a plan view of a first conductive layer in the shift register of FIG. 19; FIG. 21C shows a plan view of a second conductive layer in the shift register of FIG. 19; FIG. 21D shows a plan view of a third conductive layer in the shift register of FIG. 19; and FIG. 21E shows a plan view of a fourth conductive layer in the shift register of FIG. 19.

[0191] Similar to the equivalent circuit of the second shift register unit GOA-EM in the embodiment of FIG. 15, in the embodiment of FIG. 19, the equivalent circuit of at least one of the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 can also be a “13T3C” circuit.

[0192] Exemplarily, referring to FIG. 19, at least one of the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 includes twenty-first to thirty-third transistors. The twenty-first to thirty-third transistors can be numbered as Z1, Z2, …, Z13 in sequence. At least one of the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 further includes capacitors C001, C002 and C003.

[0193] Different from the embodiment of FIG. 15, the arrangement of the transistors in the embodiment of FIG. 19 is different. For example, with reference to FIGS. 19 and 21A, the active layers ACZ9 and ACZ10 of the twenty-ninth transistor Z9 and the thirtieth transistor Z10 are arranged apart in the first direction X, and one side edge of the active layer ACZ9 of the twenty-ninth transistor Z9 and one side edge of the active layer ACZ10 of the thirtieth transistor Z10 are substantially aligned in the second direction Y.

[0194] In the embodiment of FIG. 15, the twenty-ninth transistor Z9 and the thirtieth transistor Z10 are arranged side by side in the second direction Y. The space occupied in the second direction is large.

[0195] In the embodiment of FIG. 19, the twenty-ninth transistor Z9 and the thirtieth transistor Z10 are arranged side by side in the first direction X. With reference to FIG. 21B, the gate G10 of the thirtieth transistor Z10 can be a 3-gate structure in parallel, so as to leave enough space for the wiring of the twenty-ninth transistor Z9. The active layer ACZ10 of the thirtieth transistor Z10 can be adaptively lengthened in the second direction Y, so as to ensure that the width-length ratio of the thirtieth transistor Z10 does not change.

[0196] Through such a design, the width of the first light-emitting signal output module GOA-EM1 and the second light-emitting signal output module GOA-EM2 in the second direction can be reduced, which can better adapt to the width of the pixel row, thereby saving the wiring space of the shift register and facilitating the narrow bezel of the display substrate.

[0197] For example, in some embodiments of the present disclosure, the first shift register unit GOA-Ga and the second shift register unit GOA-EM can share at least one first voltage line Vgh. For example, with reference to FIG. 19, the second scan signal output module GOA-Ga2 and the second shift register unit GOA-EM share at least one first voltage line Vgh.

[0198] For example, in some embodiments of the present disclosure, the first shift register unit GOA-Ga and the second shift register unit GOA-EM can share at least one first voltage line Vgh. For example, with reference to FIG. 19, the second scan signal output module GOA-Ga2 and the second shift register unit GOA-EM share at least one first voltage line Vgh.

[0199] For example, in some embodiments of the present disclosure, the first shift register unit GOA-Ga and the second shift register unit GOA-EM can share at least one first voltage line Vgh. For example, with reference to FIG. 19, the second scan signal output module GOA-Ga2 and the second shift register unit GOA-EM share at least one first voltage line Vgh.

[0200] In some embodiments, with reference to FIGS. 20 and 21E, the plurality of cascaded second scan signal output modules GOA-Ga2 includes an i-th second scan signal output module GOA-Ga2i and the i+1th second scan signal output module GOA-Ga2 i+1 The display substrate 1000 further comprises a first adapter k1 connecting the first signal output end Gc i of the i-th second scan signal output module GOA-Ga2 i and the first signal input end STV1 i+1 of the i+1th second scan signal output module GOA-Ga2 i+1 The first adapter k1 is located in the fourth conductive layer 105, extends along the second direction Y and penetrates through the second shift register unit GOA-EM between the i-th second scan signal output module GOA-Ga2 i and the i+1th second scan signal output module GOA-Ga2 i+1

[0201] Exemplarily, the plurality of cascaded second shift register units GOA-EM comprises an i-th second shift register unit GOA-EM i and an i+1th second shift register unit GOA-EM i+1 The i-th second shift register unit GOA-EM i is located between the i-th second scan signal output module GOA-Ga2 i and the i+1th second scan signal output module GOA-Ga2 i+1 The i+1th second scan signal output module GOA-Ga2 i+1 is located between the i-th second shift register unit GOA-EM i and the i+1th second shift register unit GOA-EM i+1 That is, the plurality of cascaded second shift register units GOA-EM and the plurality of cascaded second scan signal output modules GOA-Ga2 are arranged alternately in the second direction Y. Through such design, the area occupied by the wirings in the non-display area of the display substrate can be reduced, which is conducive to realizing narrow frame.

[0202] Exemplarily, in combination with reference to FIGS. 20-21E, the display substrate 1000 further comprises a second adapter k2, a third adapter k3 and a fourth adapter k4. The third output signal end Em i of the i-th second shift register unit GOA-EM i is connected to the second signal input end STV2 i+1 of the i+1th second shift register unit GOA-EM i+1 ​Connection. The second transfer part k2 is located in the third conductive layer 104, and the main part k21 of the second transfer part k2 extends along the second direction Y. The third transfer part k3 is located in the second conductive layer 103, and the third transfer part 103 extends along the first direction X. The fourth transfer part k4 is located in the third conductive layer 104.

[0203] Through such a design, the interlaced transmission of signals in the second shift register unit GOA-EM can be realized.

[0204] Exemplarily, continuing to refer to FIG. 19, the source S3 of the twenty-third transistor Z3, the gate G12 of the thirty-second transistor Z12, and the source S10 of the thirtieth transistor Z10 are connected and accessed to the unified second voltage line Vg1.

[0205] Exemplarily, in combination with FIG. 19 and FIG. 21A, the twenty-second transistor Z2 and the twenty-third transistor Z3 share the active layer ACZ23, which can reduce the influence of the jumper resistance.

[0206] Optionally, the embodiments of the present disclosure also provide a display device, which can include the shift register GOA or the display substrate 1000 described above. The display device can include, but is not limited to, electronic paper, mobile phones, tablets, displays, notebooks, digital photo frames, navigation devices, and any product or component with display function. It should be understood that the display device has the same beneficial effects as the shift register or the display substrate provided in the foregoing embodiments.

[0207] Although some embodiments of the general concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes can be made in these embodiments without departing from the principles and spirit of the general concept of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A shift register, comprising: a plurality of cascaded first shift register units configured to provide scan control signals; a plurality of cascaded second shift register units configured to provide light emitting control signals; the first shift register unit comprises a control sub-circuit, a first output sub-circuit and a second output sub-circuit, wherein a first signal output terminal of the first output sub-circuit inputs a cascade signal to the control sub-circuit of a next stage first shift register unit; the second output sub-circuit is configured to provide a first voltage signal or a shielding signal of a shielding signal terminal to a second signal output terminal; the first shift register unit comprises a first scan signal output module and a second scan signal output module; the second scan signal output modules of adjacent stages connect pixels of different rows, and two second scan signal output modules corresponding to two adjacent rows of pixels are symmetrically distributed about the display area to first and second areas on two sides of a non-display area; the second shift register unit comprises a first light emitting signal output module and a second light emitting signal output module, wherein at least one of the first light emitting signal output module and the second light emitting signal output module is spaced apart from the second scan signal output module in a second direction and aligned in a first direction.

2. The shift register of claim 1, wherein, In the first area, the plurality of cascaded second scan signal output modules and the plurality of cascaded first light emitting signal output modules are alternately arranged along the second direction; In the second area, the plurality of cascaded second scan signal output modules and the plurality of cascaded second light emitting signal output modules are alternately arranged along the second direction.

3. The shift register of claim 2, wherein, The first scan signal output modules on the left and right sides of the same row arranged along the first direction are connected to the same pixel row, wherein two first scan signal output modules corresponding to the same row of pixels are symmetrically distributed about the display area to the first and second areas.

4. The shift register of claim 3, wherein, The first light emitting signal output modules of adjacent stages connect pixels of different rows; and the second light emitting signal output modules of adjacent stages connect pixels of different rows, wherein one first light emitting signal output module and one second light emitting signal output module electrically connected to two adjacent rows of pixels are symmetrically distributed about the display area to the first and second areas.

5. The shift register of claim 4, wherein, One second shift register unit drives two rows of pixels.

6. The shift register of any of claims 1-5, wherein, The second scan signal output module is configured to be electrically connected to a control electrode of a first initialization transistor in a pixel circuit.

7. The shift register of claim 6, wherein, The first scan signal output module is configured to be electrically connected to a control electrode of a data writing transistor in a pixel circuit.

8. The shift register of claim 6, wherein, The first scan signal output module is configured to be electrically connected to a control electrode of a compensation transistor in a pixel circuit.

9. The shift register of claim 7 or 8, wherein, The first light emitting signal output module is configured to be electrically connected to a control electrode of a light emitting control transistor in a pixel circuit.

10. The shift register of claim 9, wherein, The second light emitting signal output module is configured to be electrically connected to a control electrode of a second initialization transistor in a pixel circuit.

11. The shift register of claim 10, wherein, The second light emitting signal output module is configured to be electrically connected to a control electrode of a third initialization transistor in a pixel circuit.

12. A display substrate, wherein, The shift register is arranged in a plurality of rows of pixels and as claimed in any one of claims 1-11. The display substrate comprises a display area and a non-display area surrounding the display area, the non-display area comprises a first area and a second area located on opposite sides of the display area, wherein the second scan signal output modules of adjacent stages are connected to different rows of pixels, and two second scan signal output modules corresponding to adjacent two rows of pixels are symmetrically distributed in the first area and the second area about the display area; at least one of the first light-emitting signal output module and the second light-emitting signal output module is spaced apart from the second scan signal output module in the second direction and aligned in the first direction. adjacent two rows of pixels are electrically connected to one first light-emitting signal output module; and the adjacent two rows of pixels are electrically connected to one second light-emitting signal output module; 13.The display substrate of claim 12, wherein, one row of pixels has a first width in the second direction, the first light-emitting signal output module has a second width in the second direction, and the second light-emitting signal output module has a third width in the second direction, wherein the first width is substantially equal to the second width; and / or, the first width is substantially equal to the third width. The first scan signal output modules on the left and right sides of the same row are connected to the same row of pixels, and the number of the first scan signal output modules is about twice the number of the second scan signal output modules. 14.The display substrate according to claim 12 or 13, wherein, The display substrate comprises: a substrate substrate; and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer are sequentially stacked on the substrate substrate; 15. The display substrate according to any one of claims 12-14, wherein, At least one of the first scan signal output module and the second scan signal output module comprises: a plurality of transistors and at least one capacitor; The active layer of the plurality of transistors is located in the first semiconductor layer; The control electrode of the plurality of transistors and the first electrode plate of at least one capacitor are located in the first conductive layer; The second electrode plate of at least one capacitor is located in the second conductive layer; The first electrode and the second electrode of at least one of the plurality of transistors are located in the third conductive layer; The display substrate further comprises: a first clock signal line and a second clock signal line extending in the second direction, at least one of the first clock signal line and the second clock signal line is located in the fourth conductive layer, wherein the first clock signal line is electrically connected to the first shift register unit and is configured to provide a first clock signal; and the second clock signal line is electrically connected to the first shift register unit and is configured to provide a second clock signal. At least one of the first scan signal output module and the second scan signal output module comprises: a first transistor to an eleventh transistor, a first capacitor, a second capacitor and a third capacitor; The display substrate further comprises a first shielding signal line and a second shielding signal line located in the fourth conductive layer, 16.The display substrate of claim 15, wherein, wherein the first shielding signal line and the second shielding signal line are alternately connected to the tenth transistor of a plurality of cascaded first scan signal output modules in odd and even rows; and ​ ​ The first shielding signal line and the second shielding signal line are alternately connected to the tenth transistors of the plurality of cascaded second scan signal output modules in odd and even rows. 17.The display substrate of claim 16, wherein, The ninth transistor and the tenth transistor in the first scan signal output module share a first active layer, and the first active layer has a fourth width in the first direction; The ninth transistor and the tenth transistor in the second scan signal output module share a second active layer, and the second active layer has a fifth width in the first direction, The fourth width is greater than the fifth width. 18.The display substrate of claim 17, wherein, The fourth transistor and the fifth transistor in the first scan signal output module share a third active layer, and the third active layer has a sixth width in the first direction, and the sixth width is less than the fourth width; And / or, The fourth transistor and the fifth transistor in the second scan signal output module share a fourth active layer, and the fourth active layer has a seventh width in the first direction, and the seventh width is less than the fifth width.

19. The display substrate of claim 13, wherein, At least one of the first light-emitting signal output module and the second light-emitting signal output module includes twenty-first to thirty-third transistors and a third output signal terminal configured to provide a light-emitting control signal; the second electrode of the twenty-ninth transistor is electrically connected to the third output signal terminal; the first electrode of the thirtieth transistor is electrically connected to the third output signal terminal, The active layer of the twenty-ninth transistor and the active layer of the thirtieth transistor are arranged in the first direction The active layer of the twenty-ninth transistor and the active layer of the thirtieth transistor are arranged in the first direction 20. The display substrate of claim 19, wherein, The twenty-second transistor and the twenty-third transistor share an active layer. 21.The display substrate of claim 20, wherein, The display substrate further comprises a third clock signal line and a fourth clock signal line in the fourth conductive layer; the third clock signal line is electrically connected to the second shift register unit and is configured to provide a third clock signal; The fourth clock signal line is electrically connected to the second shift register unit and is configured to provide a fourth clock signal, The first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are independent of each other.

22. The display substrate of claim 21, wherein, The display substrate further comprises a first voltage line and a second voltage line in the fourth conductive layer, The first shift register unit and the second shift register unit share the first voltage line; and / or The first shift register unit and the second shift register unit share the second voltage line.

23. The display substrate of claim 22, wherein, The plurality of cascaded second scan signal output modules includes an i-th second scan signal output module and an i+1-th second scan signal output module, i is a positive integer greater than or equal to 1; The display substrate further comprises a first adapter, the first adapter connects the first signal output terminal of the i-th second scan signal output module and the first signal input terminal in the i+1-th second scan signal output module, wherein The first adapter is located in the fourth conductive layer, extends along the second direction, and penetrates through the second shift register unit between the i-th second scan signal output module and the i+1-th second scan signal output module.

24. The display substrate of claim 23, wherein, The plurality of cascaded second shift register units comprises an i-th second shift register unit and an i+1-th second shift register unit, wherein the i-th second shift register unit is located between the i-th second scan signal output module and the i+1-th second scan signal output module; and the i+1-th second scan signal output module is located between the i-th second shift register unit and the i+1-th second shift register unit. The display substrate further comprises a second adapter, a third adapter, and a fourth adapter, wherein a third output signal terminal in the i-th second shift register unit is connected with a second signal input terminal in the i+1-th second shift register unit through the second adapter, the third adapter, and the fourth adapter. The second adapter is located in the third conductive layer, and a main body part of the second adapter extends along the second direction. The third adapter is located in the second conductive layer, and the third adapter extends along the first direction. The fourth adapter is located in the third conductive layer.

25. A driving method of the shift register according to any one of claims 1 to 11, the method comprising: in a first refresh time period, the shielding signal is a periodic active level signal, and the corresponding pixel is controlled to perform data refresh; in a second refresh time period, the shielding signal is changed from the active level signal to an inactive level signal, and the corresponding pixel is controlled to stop data refresh; in a third refresh time period, the shielding signal remains as the inactive level signal, and the corresponding pixel is controlled to keep data unrefreshed.

26. The method of claim 25, wherein, One row of pixels is electrically connected with two second scan signal output modules; and corresponding shielding signals of two adjacent rows of pixels are a first shielding signal and a second shielding signal, respectively. in the first refresh time period, the first shielding signal and the second shielding signal are periodic active level signals staggered by a stagger time, the stagger time is a time when the potential of the active level signal in a single period of the periodic active level signal is equal to an effective potential, and pixel circuits of the two adjacent rows of pixels control the two rows of pixels to perform data refresh in turn in response to the first shielding signal and the second shielding signal; in the second refresh time period, the first shielding signal is changed to the inactive level signal at a first time, and the second shielding signal is changed to the inactive level signal at a second time, and the two rows of pixels are controlled to stop data refresh, and the second time and the first time are separated by the stagger time; in the third refresh time period, the first shielding signal and the second shielding signal remain as the inactive level signal, and the two rows of pixels are controlled to keep data unrefreshed.

27. The method of claim 25, wherein, One row of pixels is electrically connected with one second scanning signal output module; the corresponding shielding signals of the four adjacent rows of pixels are a first sub-shielding signal, a second sub-shielding signal, a third sub-shielding signal and a fourth sub-shielding signal respectively; In the first refresh time period, the first sub-shielding signal, the second sub-shielding signal, the third sub-shielding signal and the fourth sub-shielding signal are effective level signals staggered by one displacement time in sequence, and the pixel circuits of the four adjacent rows of pixels control the corresponding four rows of pixels to perform data refresh in sequence in response to the first sub-shielding signal, the second sub-shielding signal, the third sub-shielding signal and the fourth sub-shielding signal; In the second refresh time period, the first sub-shielding signal changes to an invalid level signal at a first time, the second sub-shielding signal changes to an invalid level signal at a second time, the third sub-shielding signal changes to an invalid level signal at a third time, and the fourth sub-shielding signal changes to an invalid level signal at a fourth time, thereby controlling the corresponding four rows of pixels to stop data refresh, and the first time, the second time, the third time and the fourth time are sequentially separated by one displacement time; In the third refresh time period, the first sub-shielding signal, the second sub-shielding signal, the third sub-shielding signal and the fourth sub-shielding signal remain invalid level signals, thereby controlling the corresponding four rows of pixels to keep data unrefreshed.

28. The driving method according to any one of claims 25-27, wherein, In the first refresh time period, the shielding signal accessed by the tenth transistor in at least one of the first scanning signal output module and the second scanning signal output module is the same as the second clock signal accessed by the fifth transistor; or, The shielding signal accessed by the tenth transistor in at least one of the first scanning signal output module and the second scanning signal output module is the same as the first clock signal accessed by the second transistor.

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