Gate drive circuit and display panel

By employing a combination of multi-level gate drive sub-circuits and clock signals of different frequencies in the display panel, the high power consumption and signal quality problems caused by high-frequency operation of the gate drive circuit are solved, achieving both power consumption reduction and signal quality improvement.

WO2026065661A1 Publication Date: 2026-04-02WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO LTD
5 Cites 1 Cited by

Patent Information

Application Number
PCT/CN2024/129760
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-09-24
Filing Date
2024-11-04
Publication Date
2026-04-02

AI Technical Summary

Technical Problem

The gate drive circuit in the display panel operates at a high frequency for a long time when displaying dynamic and static images, resulting in high power consumption and affecting signal quality.

Method used

A multi-level gate driver sub-circuit is adopted, including a shift register module, a self-stabilizing module and an output module. It uses clock signals of different frequencies to control signal transmission and maintain node potential. By combining time-division transistors and different semiconductor materials, power consumption is reduced and signal quality is improved.

Benefits of technology

While reducing power consumption, the gate drive circuit maintains the cascading control capability, improves the quality of the gate control signal, reduces signal differences, and enhances the display effect.

✦ Generated by Eureka AI based on patent content.
Patent Text Reader

Abstract

A gate drive circuit (GM) and a display panel. The gate drive circuit comprises a shift register module (10), a self-stabilizing module (20) and at least two first output modules (30). A first transistor (T1) in the shift register module (10) and a second transistor (T2) in the self-stabilizing module (20) are controlled by a first clock signal to turn on in a time-division manner, and a semiconductor layer comprises different semiconductor materials. In a second time period, the frequency of the first clock signal is higher than the frequency of a second clock signal corresponding to the first output modules (30).
Need to check novelty before this filing date? Find Prior Art