Gate drive circuit and display panel

Abstract

A gate drive circuit (GM) and a display panel. The gate drive circuit comprises a shift register module (10), a self-stabilizing module (20) and at least two first output modules (30). A first transistor (T1) in the shift register module (10) and a second transistor (T2) in the self-stabilizing module (20) are controlled by a first clock signal to turn on in a time-division manner, and a semiconductor layer comprises different semiconductor materials. In a second time period, the frequency of the first clock signal is higher than the frequency of a second clock signal corresponding to the first output modules (30).

Description

Gate drive circuit, display panel

[0001] This application claims priority to the Chinese patent application No. 202411338618.9, filed on September 24, 2024, the disclosure of which is incorporated herein in its entirety as part of this application. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a gate drive circuit and a display panel. BACKGROUND

[0003] In a display panel, in order to realize the display function of a sub-pixel, a plurality of gate control signals need to be set to control the working state of the sub-pixel. However, when the display panel displays a dynamic picture and a static picture, the gate drive circuit remains in a high-frequency working state, which is not conducive to reducing power consumption. Moreover, the long-term high-frequency working state of the gate drive circuit is not conducive to maintaining the optimal use performance of the gate drive circuit, which easily affects the quality of the output signal of the gate drive circuit. SUMMARY

[0004] The embodiments of the present application provide a gate drive circuit and a display panel, which can improve the quality of the gate control signal output by the gate drive circuit and reduce power consumption.

[0005] The embodiments of the present application provide a gate drive circuit, which comprises a plurality of gate drive sub-circuits. The gate drive sub-circuit comprises a shift register module, a self-stabilizing module and at least two first output modules. The shift register module is electrically connected to a first node. The shift register module comprises a first transistor and is configured to control the signal transmitted to the first node according to a start signal and a first clock signal received by the control end of the first transistor. The self-stabilizing module is electrically connected to the first node and a second node. The self-stabilizing module comprises a second transistor and is configured to control the signal transmitted to the second node according to the signal of the first node and maintain the potential of the first node according to the signal of the second node and the first clock signal received by the control end of the second transistor. Each first output module is electrically connected to the first node and the second node. Each first output module is configured to output a first gate control signal according to a corresponding second clock signal, the signals of the first node and the second node. The semiconductor layers of the first transistor and the second transistor comprise different semiconductor materials, and the first transistor and the second transistor are configured to be turned on at different times according to the first clock signal. In a first time period, the frequency of the first clock signal is equal to the frequency of the second clock signal. In a second time period before or after the first time period, the frequency of the first clock signal is greater than the frequency of the second clock signal.

[0006] The application also provides a gate drive circuit, which comprises a plurality of clock lines and a plurality of gate drive sub-circuits, the plurality of clock lines comprises a first type of clock line and a second type of clock line, the number of the gate drive sub-circuits electrically connected to the first type of clock line is less than the number of the gate drive sub-circuits electrically connected to the second type of clock line. The gate drive circuit comprises a load capacitor, which is connected in series between the first type of clock line and a constant voltage terminal.

[0007] The application provides a display panel comprising any of the above-mentioned gate drive circuits. BRIEF DESCRIPTION OF DRAWINGS

[0008] FIGS. 1A-1F are structural schematic diagrams of the gate drive circuit provided by the embodiments of the application.

[0009] FIGS. 2A-2C are principle schematic diagrams of the gate drive sub-circuit provided by the embodiments of the application.

[0010] FIGS. 3A-3E are structural schematic diagrams of the gate drive sub-circuit provided by the embodiments of the application.

[0011] FIGS. 4A-4B are timing diagrams corresponding to the gate drive circuit provided by the embodiments of the application.

[0012] FIGS. 5A-5B are structural schematic diagrams of the display panel provided by the embodiments of the application.

[0013] FIG. 6 is a structural schematic diagram of a sub-pixel provided by the embodiments of the application.

[0014] FIG. 7 is a timing diagram corresponding to the sub-pixel provided by the embodiments of the application.

[0015] FIG. 8 is a principle schematic diagram of high-frequency and low-frequency picture display provided by the embodiments of the application.

[0016] FIG. 9 is a timing diagram of the gate control signal corresponding to a plurality of rows of sub-pixels provided by the embodiments of the application.

[0017] FIG. 10 is a principle schematic diagram of display brightness difference provided by the embodiments of the application.

[0018] FIG. 11 is a structural schematic diagram of a drive circuit layer provided by the embodiments of the application.

[0019] FIG. 12 is a structural schematic diagram of a load capacitor provided by the embodiments of the application.

[0020] FIG. 13 is a structural schematic diagram of another gate drive sub-circuit provided by the embodiments of the application.

[0021] FIG. 14 is a structural schematic diagram of a display device provided by the embodiments of the application. Embodiments of the application

[0022] For the purpose, technical solutions and effects of the present application to be clearer, more explicit, the following will be further described in detail with reference to the drawings and examples. It should be understood that the specific examples described herein are only used to explain the present application, and are not used to limit the present application, and each example can be combined with each other but not described one by one. The ordinal numbers such as the first / second in the paragraph related to the circuit module do not represent the logical time or importance order, the inclusive language is not exclusive, the computer non-volatile storage medium related to the method steps and the instructions / code for storing and executing such method steps, any combination between each embodiment can be implemented, etc. Those skilled in the art should understand that the embodiments of the present application can be modified or replaced equivalently without departing from the spirit and scope of the present application, and such modifications or equivalent replacements should be covered in the scope of the present application.

[0023] The present application provides a gate drive circuit, a display panel, the gate drive circuit comprises a shift register module, a self-stabilizing module and at least two first output modules, the shift register module electrically connected to the first node comprises a first transistor, the self-stabilizing module electrically connected to the first node and the second node comprises a second transistor, the control end of the first transistor and the second transistor is configured to receive a first clock signal, the semiconductor layer of the first transistor and the second transistor comprises different semiconductor materials, and the first transistor and the second transistor are turned on at different times, so as to control the signals of the first node and the second node through the self-stabilizing module and the shift register module, so that the first output module can generate a first gate control signal according to the second clock signal, the signal of the first node and the second node. When the frequency of the first clock signal is greater than the frequency of the second clock signal in the second period, the potential of the first node can be maintained stable by the self-stabilizing module according to the signal of the second node and the first clock signal received by the second transistor, the quality of the gate control signal output by the gate drive circuit can be improved, and the power consumption can be reduced.

[0024] Specifically, FIG. 1A~FIG. 1F are structural schematic diagrams of the gate drive circuit provided by the embodiments of the present application, the present application provides a gate drive circuit GM, comprising a plurality of gate drive sub-circuits GA and a plurality of clock lines CKL, the plurality of clock lines CKL are configured to transmit clock signals to the plurality of gate drive sub-circuits GA, and each gate drive sub-circuit GA is configured to output at least two first gate control signals Pscan.

[0025] Optionally, there is a phase difference between the plurality of first gate control signals Pscan output by each gate drive sub-circuit GA.

[0026] Among them, the plurality of clock lines CKL are configured to transmit a first clock signal and a second clock signal, or are configured to transmit a first sub-clock signal, a second clock signal and a third sub-clock signal.

[0027] It should be noted that IN1, IN2 and IN3 in FIGS. 1A-1E are respectively configured to receive corresponding second clock signals, and XCK is configured to receive a first clock signal. IN1 and IN2 in FIG. 1F are respectively configured to receive corresponding third sub-clock signals, XCK is configured to receive a second sub-clock signal, and ECK is configured to receive a first sub-clock signal.

[0028] FIGS. 2A-2C are schematic diagrams of a gate driving sub-circuit according to an embodiment of the present application. INX is configured to receive a corresponding second clock signal or a third sub-clock signal.

[0029] The gate driving sub-circuit GA includes a shift register module 10, a self-stabilization module 20, and at least two first output modules 30.

[0030] The shift register module 10 is electrically connected to a first node K1 in the gate driving sub-circuit GA, and is configured to control a signal transmitted to the first node K1 according to a start signal STV and a corresponding received clock signal.

[0031] The self-stabilization module 20 is electrically connected to the first node K1 and a second node K2 in the gate driving sub-circuit GA, and is configured to control a signal transmitted to the second node K2 according to a signal of the first node K1, and to maintain a potential of the first node K1 according to a corresponding received clock signal and a signal of the second node K2.

[0032] Each first output module 30 is electrically connected to the first node K1 and the second node K2, and is configured to receive a corresponding clock signal and output a first gate control signal Pscan according to signals of the first node K1 and the second node K2.

[0033] Optionally, the first m gate driving sub-circuits GA in the multi-stage gate driving circuit GM can take a start signal stv as the start signal STV, and the start signal STV corresponding to the nth gate driving sub-circuit GA(n) is a signal of the second node K2(n-A) in the (n-A)th gate driving sub-circuit GA(n-A). Wherein, m≥1, n>1, and A≥1.

[0034] The start signal STV corresponding to the first gate driving sub-circuit GA(1) is the start signal stv, which can be generated by a timing controller or the like, and the start signal STV corresponding to the nth gate driving sub-circuit GA(n) is a signal of the second node K2(n-1) in the (n-1)th gate driving sub-circuit GA(n-1).

[0035] Optionally, the shift register module 10 and the self-stabilization module 20 can be configured to receive the same clock signal, and the first output module 30 receives a clock signal different from the clock signal received by the shift register module 10, so that by controlling the frequency of the clock signal received by the first output module 30, the first gate control signal Pscan without an effective level is output by the partial gate drive sub-circuit GA, the power consumption is reduced, and the gate drive circuit GM can still achieve stage transfer control.

[0036] As shown in FIGS. 1A-1E and 2A-2C, the shift register module 10 and the self-stabilization module 20 are configured to receive a first clock signal, and the first output module 30 is configured to receive a second clock signal. The shift register module 10 is configured to control the signal transmitted to the first node K1 according to the start signal STV and the received first clock signal. The self-stabilization module 20 is configured to control the signal transmitted to the second node K2 according to the signal of the first node K1, and maintain the potential of the first node K1 according to the received first clock signal and the signal of the second node K2. Each first output module 30 is configured to receive a corresponding second clock signal, and output a first gate control signal Pscan according to the second clock signal, the signals of the first node K1 and the second node K2. Wherein, the frequency of the first clock signal is greater than or equal to the frequency of the second clock signal.

[0037] By receiving the first clock signal by the self-stabilization module 20 and the shift register module 10, and controlling the signals of the first node K1 and the second node K2, so that the first output module 30 can generate the first gate control signal Pscan according to the second clock signal, the signals of the first node K1 and the second node K2. Control the frequency of the first clock signal to be greater than the frequency of the second clock signal, and make the self-stabilization module 20 maintain the potential of the first node K1 according to the signal of the second node K2 and the first clock signal, which can improve the quality of the gate control signal output by the gate drive circuit GM and reduce power consumption.

[0038] In addition, in order to further reduce the power consumption of the gate drive circuit GM, the shift register module 10 and the self-stabilization module 20 can be configured to receive different clock signals, and the clock signal received by the first output module 30 is different from the clock signal received by the shift register module 10, so that by controlling the frequency of the clock signal received by the self-stabilization module 20 and the first output module 30, when the first gate control signal Pscan without an effective level is output by the partial gate drive sub-circuit GA, the self-stabilization module 20 remains in a low-frequency working state, the power consumption is reduced, but the gate drive circuit GM can still achieve stage transfer control.

[0039] As shown in FIG. 1F and FIG. 2A~2C, the shift register module 10 is configured to receive a first sub-clock signal, the self-holding module 20 is configured to receive a second sub-clock signal, and the first output module 30 is configured to receive a third sub-clock signal. The shift register module 10 is configured to control the signal transmitted to the first node K1 according to the start signal STV and the received first sub-clock signal. The self-holding module 20 is configured to control the signal transmitted to the second node K2 according to the signal of the first node K1, and maintain the potential of the first node K1 according to the received second sub-clock signal and the signal of the second node K2. Each first output module 30 is configured to output a first gate control signal Pscan according to the corresponding third sub-clock signal, the signals of the first node K1 and the second node K2. In the embodiment, the frequency of the first sub-clock signal is greater than or equal to the frequency of the second clock signal; and when the second sub-clock signal has an invalid pulse, the start time of the invalid pulse of the second sub-clock signal is the same as the start time of the valid pulse of the first sub-clock signal.

[0040] By making the shift register module 10 in the gate driving sub-circuit GA control the signal transmitted to the first node K1 according to the start signal STV and the first sub-clock signal, and then making the self-holding module 20 control the signal transmitted to the second node K2 according to the signal of the first node K1, the signal of the second node K2 is controlled by the first sub-clock signal and the signal of the first node K1, and is not affected by the second sub-clock signal. Therefore, when the frequency of the second sub-clock signal is reduced, the signal of the second node K2 is not affected by the second sub-clock signal, and the stage transmission control of the gate driving circuit GM is not affected. Moreover, reducing the frequency of the second sub-clock signal is beneficial to reducing the power consumption of the gate driving circuit GM. Therefore, the power consumption of the gate driving circuit GM can be reduced while maintaining the stage transmission control of the gate driving circuit GM. When the second sub-clock signal has an invalid pulse, the start time of the invalid pulse of the second sub-clock signal is controlled to be the same as the start time of the valid pulse of the first sub-clock signal, which can reduce the probability of the potential of the first node K1 deviating from the expected value (e.g., avoiding the first node K1 being pulled down or up at the same time).

[0041] Optionally, the gate driving sub-circuit GA includes a plurality of first output terminals, each first output terminal is electrically connected with a first output module 30, and the first gate control signal Pscan generated by each first output module 30 is output through a first output terminal. Optionally, the plurality of first output terminals include a first sub-output terminal Pout1, a second sub-output terminal Pout2, a third sub-output terminal Pout3, etc., as shown in FIG. 1A~1F.

[0042] As shown in FIG. 1A~1F, the plurality of gate driving sub-circuits GA can share the clock signals transmitted by the plurality of clock lines CKL as the corresponding clock signals, thereby reducing the number of clock signals used by the gate driving circuit GM.

[0043] Optionally, the number of clock lines CKL for transmitting the second clock signal or the third sub-clock signal to the multi-stage gate drive sub-circuit GA can be determined according to the number of the first output modules 30 included in the gate drive sub-circuit GA.

[0044] For example, if the gate drive sub-circuit GA includes X first output modules 30, Z clock lines CKL in the plurality of clock lines CKL are configured to transmit corresponding second clock signals or third sub-clock signals to the first output modules 30 of the multi-stage gate drive sub-circuit GA, where X≥2 and Z=2X.

[0045] Optionally, the phase difference between the first clock signals or the first sub-clock signals corresponding to two adjacent stages of the gate drive circuit GA is XH, so that the X first output modules 30 of each stage of the gate drive circuit GA can control the level of the first gate control signal Pscan within the corresponding active level output period. For example, taking the current stage of the gate drive circuit GA and the stage of the gate drive circuit GA cascaded before the current stage of the gate drive circuit GA as an example, the X first output modules 30 of the stage of the gate drive circuit GA cascaded before the current stage of the gate drive circuit GA start to output the corresponding first gate control signal Pscan only after the X first output modules 30 of the stage of the gate drive circuit GA cascaded before the current stage of the gate drive circuit GA all output the corresponding first gate control signal Pscan. Wherein, X≥2 and H is a unit time length.

[0046] The design of the clock signals transmitted by the plurality of clock lines CKL shared by the multi-stage gate drive sub-circuit GA as the corresponding second clock signals or the third sub-clock signals will be described below in conjunction with FIGS. 1A-1F.

[0047] For example, taking X=2 as an example. Accordingly, at least two first output modules 30 include a first sub-output module 301 and a second sub-output module 302; and the Z clock lines include a first clock line CKL1, a second clock line CKL2, a third clock line CKL3, and a fourth clock line CKL4.

[0048] The first clock line CKL1 is configured to transmit a corresponding second clock signal to the first sub-output module 301 in the 2k+1th gate driving sub-circuit GA(2k+1); the second clock line CKL2 is configured to transmit a corresponding second clock signal to the second sub-output module 302 in the 2k+1th gate driving sub-circuit GA(2k+1); the third clock line CKL3 is configured to transmit a corresponding second clock signal to the first sub-output module 301 in the 2k+2th gate driving sub-circuit GA(2k+2); and the fourth clock line CKL4 is configured to transmit a corresponding second clock signal to the second sub-output module 302 in the 2k+2th gate driving sub-circuit GA(2k+2), as shown in FIGS. 1A-1C and 1E. Wherein, k≥0.

[0049] Alternatively, the first clock line CKL1 is configured to transmit a corresponding third sub-clock signal to the first sub-output module 301 in the 2k+1th gate driving sub-circuit GA(2k+1); the second clock line CKL2 is configured to transmit a corresponding third sub-clock signal to the second sub-output module 302 in the 2k+1th gate driving sub-circuit GA(2k+1); the third clock line CKL3 is configured to transmit a corresponding third sub-clock signal to the first sub-output module 301 in the 2k+2th gate driving sub-circuit GA(2k+2); and the fourth clock line CKL4 is configured to transmit a corresponding third sub-clock signal to the second sub-output module 302 in the 2k+2th gate driving sub-circuit GA(2k+2), as shown in FIG. 1F.

[0050] Similarly, when X = 3, the clock lines CKL can further include a fifth clock line CKL5 and a sixth clock line CKL6, and the first output module 30 of the gate drive sub-circuit GA further includes a third sub-output module 303. Correspondingly, as shown in FIG. 1D, the first clock line CKL1 is configured to transmit a corresponding second clock signal to the first sub-output module 301 in the 2k+1th gate drive sub-circuit GA(2k+1); the second clock line CKL2 is configured to transmit a corresponding second clock signal to the second sub-output module 302 in the 2k+1th gate drive sub-circuit GA(2k+1); the third clock line CKL3 is configured to transmit a corresponding second clock signal to the third sub-output module 303 in the 2k+1th gate drive sub-circuit GA(2k+1); the fourth clock line CKL4 is configured to transmit a corresponding second clock signal to the first sub-output module 301 in the 2k+2th gate drive sub-circuit GA(2k+2); the fifth clock line CKL5 is configured to transmit a corresponding second clock signal to the second sub-output module 302 in the 2k+2th gate drive sub-circuit GA(2k+2); and the sixth clock line CKL6 is configured to transmit a corresponding second clock signal to the first sub-output module 301 in the 2k+2th gate drive sub-circuit GA(2k+2).

[0051] It can be understood that when X = 3, the connection form of the first output module 30 of the plurality of gate drive sub-circuits GA and the plurality of clock lines CKL is not limited to the form shown in FIG. 1D.

[0052] It can be understood that, referring to the design of FIGS. 1A-1F, a design corresponding to X > 2, in which the plurality of clock lines CKL transmit second clock signals or third clock signals to the plurality of gate drive sub-circuits GA, can also be obtained.

[0053] Alternatively, to further reduce the number of clock signals used by the gate drive circuit GM, the clock lines CKL used to transmit third clock signals to the plurality of gate drive sub-circuits GA can be multiplexed to transmit second clock signals to the plurality of gate drive circuits GM. For example, U clock lines in Z clock lines are configured to transmit corresponding second clock signals to the self-stabilization module 20 of the plurality of gate drive sub-circuits GA. Wherein, Z > U, U > 1. Alternatively, U = 2.

[0054] As shown in FIG. 1F, while the first clock line CKL1 to the fourth clock line CKL4 are configured to provide third clock signals to the plurality of gate drive sub-circuits GA, the first clock line CKL1 is further configured to transmit a corresponding second clock signal to the self-stabilization module 20 in the 2k+2th gate drive sub-circuit GA(2k+2), and the third clock line CKL3 is further configured to transmit a corresponding second clock signal to the self-stabilization module 20 in the 2k+1th gate drive sub-circuit GA(2k+1).

[0055] Optionally, Y clock lines of the plurality of clock lines CKL are configured to transmit corresponding first clock signals or first sub-clock signals to the plurality of gate driving sub-circuits GA. Wherein, Y can be equal to 2. Optionally, Y = U.

[0056] Optionally, to further reduce the number of clock signals used for gate driving, the clock line CKL used to transmit the second clock signals to the plurality of gate driving sub-circuits GA can be multiplexed to transmit the first clock signals to the plurality of gate driving circuits GM. That is, when the plurality of clock lines CKL are configured to transmit corresponding second clock signals to the first output modules 30 of the plurality of gate driving sub-circuits GA, Y clock lines of the plurality of clock lines CKL are configured to transmit corresponding first clock signals to the plurality of gate driving sub-circuits GA.

[0057] As shown in FIG. 1A and FIG. 1E, the first clock line CKL1~the fourth clock line CKL4 are configured to provide the second clock signals to the plurality of gate driving sub-circuits GA, and the first clock line CKL1 is further configured to transmit corresponding first clock signals to the shift register module 10 and the self-stabilization module 20 in the 2k+2th gate driving sub-circuit GA(2k+2), and the third clock line CKL3 is further configured to transmit corresponding first clock signals to the shift register module 10 and the self-stabilization module 20 in the 2k+1th gate driving sub-circuit GA(2k+1).

[0058] Optionally, the clock line CKL used to transmit the second clock signals can not be multiplexed to transmit the corresponding first clock signals to the plurality of gate driving sub-circuits GA, so that the first gate control signals Pscan output by the plurality of gate driving sub-circuits GA can not have an effective level when the frequency of the second clock signals is reduced, thereby realizing the design of partitioning and frequency reduction in the display panel when the gate driving circuit GM is applied to the display panel.

[0059] As shown in FIG. 1B~FIG. 1D, the Y clock lines include a first sub-line CKLa and a second sub-line CKLb, the first sub-line CKLa is configured to transmit corresponding first clock signals to the shift register module 10 and the self-stabilization module 20 in the 2k+1th gate driving sub-circuit GA(2k+1), and the second sub-line CKLb is configured to transmit corresponding first clock signals to the shift register module 10 and the self-stabilization module 20 in the 2k+2th gate driving sub-circuit GA(2k+2), so that the clock line used to transmit the second clock signals is not multiplexed to transmit the corresponding first clock signals to the plurality of gate driving sub-circuits GA.

[0060] For example, as shown in FIG. 1F, the Y clock lines include a first sub-line CKLa and a second sub-line CKLb. The first sub-line CKLa is configured to transmit a corresponding first sub-clock signal to the shift register module 10 in the gate drive sub-circuit GA(2k+1) of the 2k+1 stage. The second sub-line CKLb is configured to transmit a corresponding first sub-clock signal to the shift register module 10 in the gate drive sub-circuit GA(2k+2) of the 2k+2 stage. Thus, the corresponding first sub-clock signal is transmitted to the gate drive sub-circuit GA without multiplexing with the clock line transmitting the second sub-clock signal.

[0061] Thus, in the present application, the shift register module 10 and the self-stabilization module 20 can simultaneously receive the same clock signal, as shown in FIGS. 1A-1E. The shift register module 10 and the self-stabilization module 20 can also receive different clock signals, as shown in FIG. 1F. The clock line transmitting the clock signal to the first output module 30 of the gate drive sub-circuit GA and the clock line transmitting the clock signal to the self-stabilization module 20 can be shared, as shown in FIGS. 1A and 1E-1F. The clock line transmitting the clock signal to the first output module 30 of the gate drive sub-circuit GA and the clock line transmitting the clock signal to the shift register module 10 can be shared, as shown in FIGS. 1A and 1E. The clock line transmitting the clock signal to the first output module 30 of the gate drive sub-circuit GA and the clock line transmitting the clock signal to the self-stabilization module 20 and the shift register module 10 are not shared, as shown in FIGS. 1B-1D.

[0062] When the clock signal received by the shift register module 10 and the clock signal received by the first output module 30 are independent of each other, the frequency of the clock signal received by the first output module 30 can be controlled to be reduced in some time periods, so as to reduce the power consumption of the gate drive circuit GM. When the clock signal received by the shift register module 10 and the clock signal received by the self-stabilization module 20 are independent of each other, and the self-stabilization module 20 and the first output module 30 share the clock signal, the frequency of the clock signal received by the first output module 30 and the self-stabilization module 20 can be controlled to be reduced in some time periods, so as to further reduce the power consumption of the gate drive circuit GM.

[0063] Please continue to refer to FIG. 1A. Since the first clock line CKL1 is configured to transmit the corresponding first clock signal to the gate driving sub-circuit GA(2k+2) while being configured to transmit the corresponding second clock signal to the gate driving sub-circuit GA(2k+1), the usage frequency of the first clock line CKL1 is greater than that of the second clock line CKL2, resulting in that the load corresponding to the first clock line CKL1 is greater than that corresponding to the second clock line CKL2. Similarly, the load corresponding to the third clock line CKL3 is greater than that corresponding to the fourth clock line CKL4. Thus, when the plurality of clock lines CKL transmit the corresponding clock signals to the plurality of gate driving sub-circuits GA, the load difference between the plurality of clock lines CKL is caused, resulting in that the time delay difference exists between the first gate control signals Pscan generated by the plurality of gate driving sub-circuits GA, and the signal difference exists between the first gate control signals Pscan generated by the plurality of gate driving sub-circuits GA. When the gate driving circuit GM is applied to a display panel, the signal difference between the plurality of first gate control signals Pscan is likely to cause the display unevenness (such as the brightness difference between the odd and even rows).

[0064] Therefore, the load corresponding to the plurality of clock lines CKL can be adjusted by adjusting the matching relationship between the clock lines CKL and the plurality of gate driving sub-circuits GA, so as to improve the difference between the first gate control signals Pscan caused by the load difference of the clock lines CKL. As shown in FIGS. 1B-1D, Y clock lines in the plurality of clock lines CKL are configured to transmit the first clock signal to the plurality of gate driving sub-circuits GA, so as to reduce the load difference of the plurality of clock lines CKL, thereby reducing the signal difference between the first gate control signals Pscan generated by the plurality of gate driving sub-circuits GA.

[0065] Moreover, in the gate driving circuit GM shown in FIGS. 1B-1D, the first clock signal and the second clock signal are independent of each other, so that the frequency of the second clock signal can be adjusted in some time periods, and the frequency of the first gate control signal Pscan is reduced, thereby reducing the power consumption and realizing the stage transmission control of the gate driving circuit GM.

[0066] In addition, the load corresponding to the plurality of clock lines CKL can also be adjusted by adding capacitors, so as to improve the difference between the first gate control signals Pscan caused by the load difference of the clock lines CKL. As shown in FIGS. 1E-1F, the capacitors are added to the clock lines CKL with smaller loads, so as to reduce the load difference of the plurality of clock lines CKL, thereby reducing the signal difference between the first gate control signals Pscan generated by the plurality of gate driving sub-circuits GA.

[0067] Further, in the gate drive circuit GM shown in FIG. 1F, because the first sub clock signal and the second sub clock signal are independent of each other, the frequency of the second sub clock signal and the third sub clock signal can be adjusted in part of the period, so that the frequency of the first gate control signal Pscan is reduced, thereby reducing power consumption while realizing the stage transfer control of the gate drive circuit GM.

[0068] The specific structure and working principle of the gate drive sub-circuit GA are introduced first, and then the content of reducing the power consumption of the gate drive circuit GM and reducing the load difference corresponding to the clock line CKL is described in combination with the working principle of the gate drive circuit GM.

[0069] FIGS. 3A-3E are structural schematic diagrams of a gate drive sub-circuit provided by an embodiment of the present application, and the shift register module 10 includes a first transistor T1, and the control end of the first transistor T1 is configured to receive a first clock signal or a first sub clock signal.

[0070] The self-stabilizing module 20 includes a second transistor T2, and the control end of the second transistor T2 is configured to receive a first clock signal or a second sub clock signal.

[0071] Optionally, the semiconductor layers of the first transistor T1 and the second transistor T2 include different semiconductor materials. For example, the semiconductor layer of one of the first transistor T1 and the second transistor T2 includes a silicon semiconductor material, and the semiconductor layer of the other of the first transistor T1 and the second transistor T2 includes an oxide semiconductor material.

[0072] Optionally, the semiconductor layer of the first transistor T1 includes a silicon semiconductor material, and the semiconductor layer of the second transistor T2 includes an oxide semiconductor material, so that the drain current of the second transistor T2 is smaller than the drain current of the first transistor T1, thereby facilitating the maintenance of the stable potential of the first node K1.

[0073] Optionally, one of the first transistor T1 and the second transistor T2 is a P-type transistor, and the other of the first transistor T1 and the second transistor T2 is an N-type transistor, so as to control the signals transmitted to the first node K1 and the second node K2 according to the working state of the first transistor T1 and the second transistor T2. For example, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor.

[0074] Please continue to refer to FIGS. 3A-3E, the shift register module 10 includes a third transistor T3 and a fourth transistor T4.

[0075] The third transistor T3 includes a control end configured to receive a start signal STV, a first source-drain end electrically connected with a first power supply end NVGL, and a second source-drain end.

[0076] The fourth transistor T4 includes a control terminal receiving the start signal STV, a first source-drain terminal electrically connected with the second power supply terminal PVGH, and a second source-drain terminal electrically connected with the second source-drain terminal of the third transistor T3.

[0077] The first transistor T1 includes a first source-drain terminal electrically connected with the second source-drain terminal of the third transistor T3, and a second source-drain terminal electrically connected with the first node K1.

[0078] Optionally, the semiconductor layer of the third transistor T3 can include an oxide semiconductor material. The third transistor T3 can include two control terminals, and both of the control terminals are configured to receive the start signal STV. The third transistor T3 can be an N-type transistor.

[0079] Please continue to refer to FIGS. 3A-3E, the self-stabilizing module 20 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and the second transistor T2.

[0080] The fifth transistor T5 includes a control terminal electrically connected with the first node K1, a first source-drain terminal electrically connected with the second power supply terminal PVGH, and a second source-drain terminal electrically connected with the second node K2.

[0081] The sixth transistor T6 includes a control terminal electrically connected with the first node K1, a first source-drain terminal electrically connected with the third power supply terminal PVGL, and a second source-drain terminal electrically connected with the second node K2.

[0082] The seventh transistor T7 includes a control terminal electrically connected with the second node K2, a first source-drain terminal electrically connected with the second power supply terminal PVGH, and a second source-drain terminal.

[0083] The second transistor T2 includes a first source-drain terminal electrically connected with the first node K1, and a second source-drain terminal electrically connected with the second source-drain terminal of the seventh transistor T7.

[0084] Optionally, the semiconductor layer of the sixth transistor T6 can include an oxide semiconductor material. The sixth transistor T6 can include two control terminals, and both of the control terminals are electrically connected with the first node K1. The sixth transistor T6 can be an N-type transistor.

[0085] Optionally, the voltage supplied by the first power supply terminal NVGL and the voltage supplied by the third power supply terminal PVGL are less than the voltage supplied by the second power supply terminal PVGH.

[0086] Please continue to refer to FIGS. 3A-3E, the self-stabilizing module 20 further includes an eighth transistor T8, the eighth transistor T8 includes a control terminal electrically connected with the second node K2, a first source-drain terminal electrically connected with the first power supply terminal NVGL, and a second source-drain terminal electrically connected with the first node K1. The eighth transistor T8 is configured to control the electrical connection between the first node K1 and the first power supply terminal NVGL according to the signal of the second node K2.

[0087] Optionally, the semiconductor layer of the eighth transistor T8 can include an oxide semiconductor material. The eighth transistor T8 can include two control terminals, and both of the two control terminals are electrically connected with the second node K2. The eighth transistor T8 can be an N-type transistor.

[0088] Please continue to refer to FIGS. 3A-3E, each first output module 30 includes a first output transistor To1, a second output transistor To2, and a first capacitor C1.

[0089] The first output transistor To1 includes a control terminal electrically connected with the first node K1, a first source-drain terminal configured to receive a corresponding second clock signal or a third sub-clock signal, and a second source-drain terminal electrically connected with the first output terminal Pout of the gate driving sub-circuit GA for outputting a corresponding first gate control signal Pscan.

[0090] The second output transistor To2 includes a control terminal electrically connected with the second node K2, a first source-drain terminal electrically connected with the second power supply terminal PVGH, and a second source-drain terminal electrically connected with the second source-drain terminal of the first output transistor To1.

[0091] The first capacitor C1 is connected in series between the control terminal and the first source-drain terminal of the first output transistor To1.

[0092] Optionally, at least one first output module 30 can further be provided with a switching unit to control the number of effective pulses of the first gate control signal Pscan generated by the first output module 30.

[0093] As please continue to refer to FIGS. 3A-3E, at least one first output module 30 is provided with a switching unit, the switching unit includes a first switching transistor Ts1, the first switching transistor Ts1 includes a control terminal configured to receive a switching control signal SC, a first source-drain terminal electrically connected with the first node K1, and a second source-drain terminal electrically connected with the control terminal of the first output transistor To1.

[0094] Optionally, the control terminal of the first switch transistor Ts1 in the nth gate driving sub-circuit GA(n) is electrically connected with the second node K2 in the n-Bth gate driving sub-circuit GA(n-B), and B≥1. For example, the control terminal of the first switch transistor Ts1 in the nth gate driving sub-circuit GA(n) is electrically connected with the second node K2 in the n-2th gate driving sub-circuit GA(n-2), so that the corresponding switch control signal SC of the nth gate driving sub-circuit GA(n) is the signal of the second node K2 in the n-2th gate driving sub-circuit GA(n-2). The switch control signals SC corresponding to the 1st gate driving sub-circuit GA(1) and the 2nd gate driving sub-circuit GA(2) can be signals for keeping the first switch transistor Ts1 conducting. For example, the first switch transistor Ts1 is a P-type transistor, and the switch control signals SC corresponding to the 1st gate driving sub-circuit GA(1) and the 2nd gate driving sub-circuit GA(2) can be low-level signals. One of the first power supply terminal NVGL and the third power supply terminal PVGL can be a power supply terminal for supplying the low-level signals. Similarly, the first switch transistor Ts1 is an N-type transistor, and the switch control signals SC corresponding to the 1st gate driving sub-circuit GA(1) and the 2nd gate driving sub-circuit GA(2) can be high-level signals. The second power supply terminal PVGH can be a power supply terminal for supplying the high-level signals.

[0095] Optionally, in the same gate driving sub-circuit GA, the switch control signals SC received by the plurality of switch units are the same, so that the plurality of first output modules 30 in the same gate driving sub-circuit GA can control the corresponding second clock signals or third sub-clock signals to be transmitted to the required first output terminals Pout according to the same switch control signal SC.

[0096] Optionally, referring to FIGS. 2B-2C and 3B-3E, the gate driving circuit GM further includes a first frequency division control line FL1 for transmitting a first frequency division control signal FD1, and the gate driving sub-circuit GA further includes a first frequency division control module 40 electrically connected with the first node K1, the second node K2 and the first frequency division control line FL1, and electrically connected with the third node K3 and at least one first output module 30. The first frequency division control module 40 is configured to control the signal transmission between the first node K1 and the third node K3 according to the signal of the second node K2 and the first frequency division control signal FD1, so that the number of the gate driving sub-circuit GA corresponding to the output of the first gate control signal Pscan with or without an effective pulse can be controlled by the first frequency division control signal FD1 and the first frequency division control module 40. Accordingly, when the gate driving circuit GM is applied to a display panel, the position corresponding to the change of the refresh frequency in the display panel can be adjusted.

[0097] Optionally, the first frequency division control module 40 comprises a first frequency division transistor Tf1, a second frequency division transistor Tf2 and a second capacitor C2.

[0098] The first frequency division transistor Tf1 comprises a control terminal electrically connected with the second node K2 of the gate drive circuit GM of the current stage, and a first source-drain terminal electrically connected with the first frequency division control line FL1.

[0099] The second frequency division transistor Tf2 comprises a control terminal electrically connected with the second source-drain terminal of the first frequency division transistor Tf1, a first source-drain terminal electrically connected with the first node K1, and a second source-drain terminal electrically connected with the corresponding first output module 30.

[0100] The second capacitor C2 is connected in series between the control terminal of the second frequency division transistor Tf2 and the second source-drain terminal of the second frequency division transistor Tf2.

[0101] Wherein, when the first output module 30 comprises a first switch transistor Ts1, the second source-drain terminal of the second frequency division transistor Tf2 is electrically connected with the first source-drain terminal of the first switch transistor Ts1. When the first output module 30 does not comprise the first switch transistor Ts1, the second source-drain terminal of the second frequency division transistor Tf2 is electrically connected with the control terminal of the first output transistor To1.

[0102] Optionally, in order to maintain the invalid level of the first gate control signal Pscan stable, the gate drive sub-circuit GA further comprises a first stabilization module 50. As shown in FIGS. 2B-2C, the first stabilization module 50 is electrically connected between the second node K2 and the third node K3, and the first stabilization module 50 is configured to maintain the potential of the third node K3 stable according to the signal of the second node K2 and the first clock signal or the second sub-clock signal.

[0103] Optionally, referring to FIGS. 3B-3E, the first stabilization module 50 comprises a second switch transistor Ts2 and a first maintenance transistor Th1.

[0104] The second switch transistor Ts2 comprises a control terminal electrically connected with the second node K2, a first source-drain terminal electrically connected with the second power supply terminal PVGH, and a second source-drain terminal.

[0105] The first maintenance transistor Th1 comprises a control terminal configured to receive the first clock signal or the second sub-clock signal, a first source-drain terminal electrically connected with the third node K3, and a second source-drain terminal electrically connected with the second source-drain terminal of the second switch transistor Ts2. Wherein, the first source-drain terminal of the first maintenance transistor Th1 and the second source-drain terminal of the second frequency division transistor Tf2 are electrically connected with the third node K3.

[0106] To further reduce the layout space occupied by the gate drive circuit GM, the gate drive sub-circuit GA can output a second gate control signal Nscan in addition to the plurality of first gate control signals Pscan, so as to widen the application range of the gate drive circuit GM.

[0107] Please continue to refer to FIG. 2C, FIG. 3C and FIG. 3E, the gate drive circuit GM further comprises a second frequency division control line FL2 for transmitting a second frequency division control signal FD2, and the gate drive sub-circuit GA further comprises a second output module 60 and a second frequency division control module 70.

[0108] The second output module 60 is electrically connected with the first node K1, and the second output module 60 is configured to output a second gate control signal Nscan to the second output end Nout of the gate drive sub-circuit GA.

[0109] The second frequency division control module 70 is electrically connected with the first node K1 and the second node K2, and is electrically connected with the second output module 60 through the fourth node K4, and the second frequency division control module 70 is configured to control the signal transmission between the first node K1 and the fourth node K4 according to the second frequency division control signal FD2 and the signal of the second node K2.

[0110] Please continue to refer to FIG. 3C and FIG. 3E, the second frequency division module comprises a third frequency division transistor Tf3, a fourth frequency division transistor Tf4 and a third capacitor C3.

[0111] The third frequency division transistor Tf3 comprises a control end electrically connected with the second node K2 and a first source-drain end electrically connected with the second frequency division control line FL2.

[0112] The fourth frequency division transistor Tf4 comprises a control end electrically connected with the second source-drain end of the third frequency division transistor Tf3, a first source-drain end electrically connected with the first node K1, and a second source-drain end electrically connected with the fourth node K4 and the second output module 60.

[0113] The third capacitor C3 is connected in series between the control end of the fourth frequency division transistor Tf4 and the second source-drain end of the fourth frequency division transistor Tf4.

[0114] The required frequency division control signals are transmitted to the first frequency division control module 40 and the second frequency division control module 70 through the first frequency division control line FL1 and the second frequency division control line FL2 respectively, so as to realize independent control of the level states of the first gate control signal Pscan and the second gate control signal Nscan output by the gate drive unit.

[0115] Optionally, the plurality of gate drive sub-circuits GA share the same first frequency division control signal FD1 and the same second frequency division control signal FD2, so as to reduce the number of control signals used by the gate drive circuit GM.

[0116] Please continue to refer to FIG. 3C and FIG. 3E, the second output module 60 includes a third output transistor To3 and a fourth output transistor To4.

[0117] The third output transistor To3 includes a control end electrically connected with the fourth node K4, a first source-drain end electrically connected with the fourth power supply end NVGH, and a second source-drain end electrically connected with the second output end Nout outputting the second gate control signal Nscan of the gate driving sub-circuit GA.

[0118] The fourth output transistor To4 includes a control end electrically connected with the first node K1, a first source-drain end electrically connected with the first power supply end NVGL, and a second source-drain end electrically connected with the second output end Nout.

[0119] Optionally, in order to maintain the invalid level of the second gate control signal Nscan stable, the gate driving sub-circuit GA further includes a second stabilizing module 80. As shown in FIG. 2C, the second stabilizing module 80 is electrically connected with the second node K2 and the fourth node K4, and the second stabilizing module 80 is configured to control the potential of the fourth node K4 to maintain stable according to the first clock signal or the second sub-clock signal and the signal of the second node K2.

[0120] Optionally, please continue to refer to FIG. 3C and FIG. 3E, the second stabilizing module 80 includes a third switch transistor Ts3 and a second maintaining transistor Th2.

[0121] The third switch transistor Ts3 includes a control end electrically connected with the second node K2, and a first source-drain end electrically connected with the second power supply end PVGH.

[0122] The second maintaining transistor Th2 includes a control end configured to receive the first clock signal or the second sub-clock signal, a first source-drain end electrically connected with the second frequency dividing control module 70 and the second output module 60, and a second source-drain end electrically connected with the second source-drain end of the third switch transistor Ts3. Wherein, the first source-drain end of the second maintaining transistor Th2 and the second source-drain end of the fourth frequency dividing transistor Tf4 are electrically connected with the fourth node K4.

[0123] Optionally, the control ends of the first maintaining transistor Th1 and the second maintaining transistor Th2 and the control end of the second transistor T2 are configured to receive the same clock signal, so that the self-stabilizing module 20 maintains the potential of the first node K1 stable, the first stabilizing module 50 maintains the potential of the third node K3 stable, and the second stabilizing module 80 maintains the potential of the fourth node K4 stable.

[0124] The control terminals of the first and second sustain transistors Th1 and Th2 and the control terminal of the second transistor T2 can be electrically connected, so that the control terminals of the first and second sustain transistors Th1 and Th2 and the control terminal of the second transistor T2 are configured to receive the same clock signal.

[0125] The first and second sustain transistors Th1 and Th2 can be of the same transistor type as the second transistor T2, so that the first stabilization module 50 maintains the potential of the third node K3 stable when the self-stabilization module 20 maintains the potential of the first node K1 stable, and the second stabilization module 80 maintains the potential of the fourth node K4 stable.

[0126] Optionally, the semiconductor layers of the first and second sustain transistors Th1 and Th2 and the second transistor T2 comprise an oxide semiconductor material, and the first and second sustain transistors Th1 and Th2 and the second transistor T2 are N-type transistors.

[0127] Optionally, referring to FIGS. 3A-3E, the gate driving sub-circuit GA further comprises a reset module 90 electrically connected to the first node K1, and the reset module 90 is configured to control signal transmission between the second power supply terminal PVGH and the first node K1 according to a reset control signal Ctl.

[0128] Optionally, the reset module 90 comprises a reset transistor Tre including a control terminal configured to receive the reset control signal Ctl, a first source-drain terminal electrically connected to the second power supply terminal PVGH, and a second source-drain terminal electrically connected to the first node K1.

[0129] Optionally, when the gate driving circuit GM is applied to a display device, the reset module 90 is configured to be enabled when the display device is powered on and / or during a blanking interval.

[0130] It can be understood that each transistor included in the gate driving sub-circuit GA can be one of a P-type transistor and an N-type transistor. The semiconductor of each transistor included in the gate driving sub-circuit GA can be one of a silicon semiconductor and an oxide semiconductor.

[0131] FIGS. 4A-4B are timing diagrams corresponding to the gate driving circuit according to an embodiment of the present application. The working principle of the gate driving circuit GM is described with the gate driving sub-circuit GA adopting the circuit topology shown in FIG. 3C and the clock line CKL of FIGS. 1C and 1F as an example.

[0132] The first transistor T1, the fourth transistor T4, the fifth transistor T5, the seventh transistor T7, the first switch transistor Ts1, the second switch transistor Ts2, the third switch transistor Ts3, the first frequency division transistor Tf1 to the fourth frequency division transistor Tf4, the first output transistor To1 to the third output transistor To3 are P-type transistors, and the second transistor T2, the third transistor T3, the sixth transistor T6, the eighth transistor T8, the first holding transistor Th1, the second holding transistor Th2, and the fourth output transistor To4 are N-type transistors. The multi-stage gate drive sub-circuit GA includes two first output modules 30, the two first output modules 30 share a first frequency division control module 40, and the two first output modules 30 include a first sub-output module 301 and a second sub-output module 302. The third clock line CKL3 transmits a corresponding second clock signal or third sub-clock signal to the first sub-output module 301 of the pth gate drive sub-circuit GA(p), the fourth clock line CKL4 transmits a corresponding second clock signal or third sub-clock signal to the second sub-output module 302 of the pth gate drive sub-circuit GA(p), the first clock line CKL1 transmits a corresponding second clock signal or third sub-clock signal to the first sub-output module 301 of the (p+1)th gate drive sub-circuit GA(p+1), and the second clock line CKL2 transmits a corresponding second clock signal or third sub-clock signal to the second sub-output module 302 of the (p+1)th gate drive sub-circuit GA(p+1). The second sub-line CKLb transmits a corresponding first clock signal or first sub-clock signal to the pth gate drive sub-circuit GA(p), and the first sub-line CKLa transmits a corresponding first clock signal or first sub-clock signal to the (p+1)th gate drive sub-circuit GA(p+1). In FIG. 1F, the first clock line CKL1 transmits a corresponding second sub-clock signal to the pth gate drive sub-circuit GA(p), and the third clock line CKL3 transmits a corresponding second sub-clock signal to the (p+1)th gate drive sub-circuit GA(p+1). The second output module 60 of the pth gate drive sub-circuit GA outputs the pth second gate control signal Nscan(p), the first sub-output module 301 of the pth gate drive sub-circuit GA outputs the qth first gate control signal Pscan(q), and the second sub-output module 302 of the pth gate drive sub-circuit GA outputs the (q+1)th first gate control signal Pscan(q+1); p≥1, q=2p-1.

[0133] Please continue to refer to FIG. 1C, FIG. 1F, FIG. 3C and FIG. 4A, in the first stage t1, the first clock signal CK1 transmitted by the first clock line CKL1 and the clock signal CKb transmitted by the second sub-line CKLb have low levels, the second clock signal CK2~the fourth clock signal CK4 transmitted by the second clock line CKL2~the fourth clock line CKL4 have high levels, and the clock signal CKa transmitted by the first sub-line CKLa has a high level. The second node K2(p-1)~the second node K2(p-2) of the (p-1)th gate drive sub-circuit GA(p-1)~the (p-2)th gate drive sub-circuit GA(p-2) have high levels. The first frequency division control signal FD1 transmitted by the first frequency division control line FL1 and the second frequency division control signal FD2 transmitted by the second frequency division control line FL2 have low levels.

[0134] In the (p)th gate drive sub-circuit GA(p), the first transistor T1, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the third output transistor To3, the second frequency division transistor Tf2, and the fourth frequency division transistor Tf4 are turned on, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the first switch transistor Ts1, the second switch transistor Ts2, the third switch transistor Ts3, the first holding transistor Th1, the second holding transistor Th2, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off.

[0135] The (q)th first gate control signal Pscan(q)~the (q+13)th first gate control signal Pscan(q+13) maintain high levels. The (p)th second gate control signal Nscan(p) is high, and the (p+1)th second gate control signal Nscan(p+1)~the (p+6)th second gate control signal Nscan(p+6) maintain low levels.

[0136] The second stage t2: the first clock signal CK1, the second clock signal CK2, the fourth clock signal CK4, and the clock signal transmitted by the second sub-line CKLb have high levels, and the third clock signal CK3 and the clock signal transmitted by the first sub-line CKLa have low levels. The second node K2(p-1)~the second node K2(p-2) of the (p-1)th gate drive sub-circuit GA(p-1)~the (p-2)th gate drive sub-circuit GA(p-2) have high levels. The first frequency division control signal FD1 and the second frequency division control signal FD2 have low levels.

[0137] In the pth stage gate driving sub-circuit GA(p), the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the third output transistor To3, the second frequency dividing transistor Tf2, the fourth frequency dividing transistor Tf4, the first holding transistor Th1, and the second holding transistor Th2 are turned on, and the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the first switch transistor Ts1, the second switch transistor Ts2, the third switch transistor Ts3, the first frequency dividing transistor Tf1, the third frequency dividing transistor Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off.

[0138] The qth stage first gate control signal Pscan(q)~the q+13th stage first gate control signal Pscan(q+13) maintain high level. The pth stage second gate control signal Nscan(p)~the p+1th stage second gate control signal Nscan(p+1) are high level, and the p+2th stage second gate control signal Nscan(p+2)~the p+6th stage second gate control signal Nscan(p+6) maintain low level.

[0139] The third stage t3: the first clock signal CK1, the second clock signal CK2, the fourth clock signal CK4 have high level and the clock signal CKb transmitted by the second sub-line CKLb have high level, the third clock signal CK3 and the clock signal CKa transmitted by the first sub-line CKLa have low level. The second node K2(p-1)~the second node K2(p-2) of the p-1th stage gate driving sub-circuit GA(p-1)~the p-2th stage gate driving sub-circuit GA(p-2) have low level. The first frequency dividing control signal FD1 and the second frequency dividing control signal FD2 have low level.

[0140] In the pth stage gate driving sub-circuit GA(p), the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the first switch transistor Ts1, the first holding transistor Th1, the second holding transistor Th2, the second frequency dividing transistor Tf2, the fourth frequency dividing transistor Tf4, the third output transistor To3, and the first output transistor To1 are turned on, and the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the second switch transistor Ts2, the third switch transistor Ts3, the first frequency dividing transistor Tf1, the third frequency dividing transistor Tf3, the fourth output transistor To4, and the second output transistor To2 are turned off.

[0141] The qth first gate control signal Pscan(q) has a low level, and the q+1th~q+13th first gate control signals Pscan(q+1)~Pscan(q+13) have high levels. The pth~(p+3)th second gate control signals Nscan(p)~Nscan(p+3) have high levels, and the (p+4)th~(p+6)th second gate control signals Nscan(p+4)~Nscan(p+6) maintain low levels.

[0142] The fourth stage t4: the first clock signal CK1, the second clock signal CK2, the third clock signal CK3 and the clock signal CKb transmitted by the second sub-line CKLb have high levels, the fourth clock signal CK4 and the clock signal CKa transmitted by the first sub-line CKLa have low levels, the second nodes K2(p-1)~K2(p-2) of the (p-1)th~(p-2)th gate driving sub-circuits GA(p-1)~GA(p-2) have low levels, and the first and second frequency division control signals FD1 and FD2 have low levels.

[0143] In the (p+1)th gate driving sub-circuit GA(p+1), the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the second switch transistor Ts2, the third switch transistor Ts3, the first frequency division transistor Tf1, the third frequency division transistor Tf3, the fourth output transistor To4 and the second output transistor To2 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the first switch transistor Ts1, the first holding transistor Th1, the second holding transistor Th2, the second frequency division transistor Tf2, the third output transistor To3 and the first output transistor To1 are turned off.

[0144] The qth first gate control signal Pscan(q) has a high level, and the q+1th first gate control signal Pscan(q+1) has a low level. The q+2th~q+13th first gate control signals Pscan(q+2)~Pscan(q+13) maintain high levels. The pth~(p+3)th second gate control signals Nscan(p)~Nscan(p+3) maintain high levels. The (p+4)th~(p+6)th second gate control signals Nscan(p+4)~Nscan(p+6) maintain low levels.

[0145] Phase 5 t5: The first clock signal CK1 and the clock signal CKb transmitted by the second sub-line CKLb are at low level; the second clock signal CK2, the third clock signal CK3, the fourth clock signal CK4 and the clock signal CKa transmitted by the first sub-line CKLa are at high level; the second node K2(p-1) of the p-1 level gate driver sub-circuit GA(p-1) to the second node K2(p-2) of the p-2 level gate driver sub-circuit GA(p-2) are at low level; and the first frequency division control signal FD1 and the second frequency division control signal FD2 are at low level.

[0146] In the p-th stage gate driver sub-circuit GA(p), the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the first switching transistor Ts1, the second switching transistor Ts2, the third switching transistor Ts3, the second output transistor To2, the fourth output transistor To4, and the first to fourth frequency divider transistors Tf1 to Tf4 are turned on. The second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the first sustaining transistor Th1, the second sustaining transistor Th2, the first output transistor To1, and the third output transistor To3 are turned off.

[0147] The first gate control signals Pscan(q) to Pscan(q+1) of stage q and Pscan(q+3) to Pscan(q+13) of stage q+3 are high, while the first gate control signal Pscan(q+2) of stage q+2 is low. The second gate control signals Nscan(p+1) to Nscan(p+4) of stage p+1 are high, the second gate control signal Nscan(p) of stage p is low, and the second gate control signals Nscan(p+5) to Nscan(p+6) of stage p+6 remain low.

[0148] In stage 6 t6: the first clock signal CK1, the third clock signal CK3, the fourth clock signal CK4 and the clock signal CKa transmitted by the first sub-line CKLa are at a high level, the second clock signal CK2 and the clock signal CKb transmitted by the second sub-line CKLb are at a low level, the second node K2(p-1) of the p-1 stage gate driver sub-circuit GA(p-1) to the second node K2(p-2) of the p-2 stage gate driver sub-circuit GA(p-2) are at a low level, the first frequency division control signal FD1 is at a high level, and the second frequency division control signal FD2 is at a low level.

[0149] In the pth-stage gate drive sub-circuit GA(p) corresponding to FIG. 1C, the first transistor T1, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the second switch transistor Ts2, the third switch transistor Ts3, the first switch transistor Ts1, the second output transistor To2, the first frequency division transistor Tf1, the third frequency division transistor Tf3~the fourth frequency division transistor Tf4 are turned on, and the second transistor T2, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the first holding transistor Th1, the second holding transistor Th2, the first output transistor To1, the second frequency division transistor Tf2, the third output transistor To3 are turned off.

[0150] In the pth-stage gate drive sub-circuit GA(p) corresponding to FIG. 1F, the first transistor T1 is turned on, and the first holding transistor Th1 and the second holding transistor Th2 are turned on.

[0151] Thus, in the sixth stage t6, the pth-stage second gate control signal Nscan(p) has a low level. The q+3th-stage first gate control signal Pscan(q+3) has a low level, and the qth-stage first gate control signal Pscan(q)~the q+2th-stage first gate control signal Pscan(q+2) and the q+4th-stage first gate control signal Pscan(q+4)~the q+13th-stage first gate control signal Pscan(q+13) have high levels. The p+1th-stage second gate control signal Nscan(p+1)~the p+4th-stage second gate control signal Nscan(p+4) have high levels, and the p+5th-stage second gate control signal Nscan(p+5)~the p+6th-stage second gate control signal Nscan(p+6) maintain low levels.

[0152] The seventh stage t7: the first clock signal CK1, the second clock signal CK2, the fourth clock signal CK4 and the clock signal CKb transmitted by the second sub-line CKLb have high levels, the third clock signal CK3 and the clock signal CKa transmitted by the first sub-line CKLa have low levels, the second node K2(p-1) of the p-1th-stage gate drive sub-circuit GA(p-1)~the second node K2(p-2) of the p-2th-stage gate drive sub-circuit GA(p-2) have low levels, the first frequency division control signal FD1 is high level, and the second frequency division control signal FD2 is low level.

[0153] In the pth gate drive sub-circuit GA(p), the first transistor Tl is off. The (p+1)th gate drive sub-circuit GA(p+1) performs an action similar to that performed by the pth gate drive sub-circuit GA(p) at the fifth stage t5, the (p+2)th gate drive sub-circuit GA(p+2) performs an action similar to that performed by the (p+1)th gate drive sub-circuit GA(p+1) at the fifth stage t5, the (p+3)th gate drive sub-circuit GA(p+3) performs an action similar to that performed by the (p+2)th gate drive sub-circuit GA(p+2) at the fifth stage t5. The (p+4)th gate drive sub-circuit GA(p+4) performs an action similar to that performed by the (p+3)th gate drive sub-circuit GA(p+3) at the fifth stage t5.

[0154] In the (p+5)th gate drive sub-circuit GA(p+5), the first transistor Tl, the third transistor T3, the fifth transistor T5, the eighth transistor T8, the fourth frequency division transistor Tf4, and the third output transistor To3 are turned on, and the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the first switch transistor Ts1, the first holding transistor Thl, the second switch transistor Ts2, the second holding transistor Th2, the third switch transistor Ts3, the first to third frequency division transistors Tf1 to Tf3, the fourth output transistor To4, the first output transistor To1, and the second output transistor To2 are turned off.

[0155] In the (p+6)th gate drive sub-circuit GA(p+6), the third transistor T3, the second output transistor To2, and the fourth output transistor To4 are turned on, and the first transistor Tl, the first output transistor To1, and the third output transistor To3 are turned off.

[0156] The pth second gate control signal Nscan(p) to the (p+1)th second gate control signal Nscan(p+1) and the (p+6)th second gate control signal Nscan(p+6) maintain a low level. The (p+2)th second gate control signal Nscan(p+2) to the (p+5)th second gate control signal Nscan(p+5) have a high level. The (q+4)th first gate control signal Pscan(q+4) has a low level, and the qth first gate control signal Pscan(q) to the (q+3)th first gate control signal Pscan(q+3) and the (q+5)th first gate control signal Pscan(q+5) to the (q+13)th first gate control signal Pscan(q+13) have a high level.

[0157] The eighth stage t8: the clock signal CKb transmitted by the second sub-line CKLb has a low level, the first clock signal CK1~the fourth clock signal CK4 and the clock signal transmitted by the first sub-line CKLa have a high level, the second node K2(p-1)~the second node K2(p-2) of the gate driving sub-circuit GA(p-1)~the gate driving sub-circuit GA(p-2) of the p-1th stage have a low level, the first frequency division control signal FD1 has a high level, and the second frequency division control signal FD2 has a low level.

[0158] The pth second gate control signal Nscan(p)~the (p+4)th second gate control signal Nscan(p+4) have a low level, and the (q+1)th first gate control signal Pscan(q+1)~the (q+9)th first gate control signal Pscan(q+9) have a high level.

[0159] In the gate driving sub-circuit GA(p+5) of the (p+5)th stage, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the eighth transistor T8, the first switch transistor Ts1, the first holding transistor Th1, the second holding transistor Th2 and the third output transistor To3 are turned on, and the first transistor T1, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the second switch transistor Ts2, the third switch transistor Ts3, the first frequency division transistor Tf1~the third frequency division transistor Tf3, the fourth output transistor To4, the first output transistor To1 and the second output transistor To2 are turned off.

[0160] In the gate driving sub-circuit GA(p+6) of the (p+6)th stage corresponding to FIG. 1C, the first transistor T1 is turned on and the second transistor T2 is turned off. In the gate driving sub-circuit GA(p+6) of the (p+6)th stage corresponding to FIG. 1F, the first transistor T1 and the second transistor T2 are turned on.

[0161] The (p+5)th second gate control signal Nscan(p+5)~the (p+6)th second gate control signal Nscan(p+6) have a high level. The (q)th first gate control signal Pscan(q)~the (q+13)th first gate control signal Pscan(q+13) have a high level.

[0162] Similar to the eighth stage t8, in the ninth stage t9, the (q)th first gate control signal Pscan(q)~the (q+13)th first gate control signal Pscan(q+13) can correspondingly have a high level.

[0163] Therefore, according to the analysis of FIG. 4A, by controlling the first frequency division control signal FD1 to jump from the active level state of low level to the inactive level state of high level, the plurality of gate driving sub-circuits GA can be controlled to change from outputting the first gate control signal Pscan with low level to outputting the first gate control signal Pscan without low level. Thus, by controlling the level state of the first frequency division control signal FD1, the level state of the plurality of first gate control signals Pscan can be controlled to control whether the first gate control signal Pscan outputted by the plurality of gate driving sub-circuits GA has the active pulse. By adjusting the level change time of the first frequency division control signal FD1, the plurality of first gate control signals Pscan can be controlled to start without the active pulse at different stages.

[0164] Similarly, the working principle of the plurality of gate driving circuits GM corresponding to the first frequency division control signal FD1 jumping from high level to low level can also be obtained.

[0165] It can be understood that, referring to the working principle of the gate driving sub-circuit GA corresponding to the first frequency division control signal FD1 jumping between high level and low level, the working principle of the gate driving sub-circuit GA corresponding to the second frequency division control signal FD2 jumping between high level and low level can also be obtained, which will not be described herein.

[0166] By controlling the second frequency division control signal FD2 to jump from the active level state of low level to the inactive level state of high level, the second gate control signal Nscan outputted by the corresponding gate driving sub-circuit GA can be controlled to have no active pulse. Thus, by controlling the level state of the second frequency division control signal FD2, the level state of the plurality of second gate control signals Nscan can be controlled. By adjusting the level change time of the second frequency division control signal FD2, the plurality of second gate control signals Nscan can be controlled to start without the active pulse at different stages.

[0167] Similarly, referring to the analysis of FIG. 4A, the working principle of FIGS. 3A-3B and 3D-3E can also be obtained; or the working principle of the gate driving circuit GM shown in FIGS. 3A-3E corresponding to the change of the clock signal shown in FIG. 4B can also be obtained, which will not be described herein.

[0168] According to the above analysis, by setting the first clock signal CK1 to the fourth clock signal CK4 as direct current at the eighth stage t8 and the ninth stage t9, the first gate control signal Pscan outputted by the corresponding gate driving sub-circuit GA can be controlled to have no active pulse.

[0169] When the gate drive circuit GM comprises the first frequency division control module 40, by controlling the first frequency division control signal FD1 to jump from the active level state of low level to the inactive level state of high level, the first gate control signal Pscan output by the corresponding gate drive sub-circuit GA does not have an active pulse at the same time, and the first clock signal CK1~the fourth clock signal CK4 are set to direct current, that is, the frequency of the first clock signal CK1~the fourth clock signal CK4 is reduced, which is beneficial to reduce power consumption.

[0170] Therefore, corresponding to the first time period ta including the first stage t1~the seventh stage t7, the frequency of the clock signal CKa transmitted by the first sub-line CKLa and the frequency of the clock signal CKb transmitted by the second sub-line CKLb can be equal to the frequency of the first clock signal CK1~the fourth clock signal CK4. Corresponding to the second time period tb including the eighth stage t8 and the ninth stage t9, the frequency of the clock signal CKa transmitted by the first sub-line CKLa and the frequency of the clock signal CKb transmitted by the second sub-line CKLb can be greater than the frequency of the first clock signal CK1~the fourth clock signal CK4, so as to reduce power consumption when the first gate control signal Pscan output by the gate drive sub-circuit GA does not have an active level.

[0171] Correspondingly, corresponding to the designs of FIG. 1A~FIG. 1E, FIG. 2A~FIG. 2C and FIG. 3A~FIG. 3E, when the first clock signal is input to the control end of the first transistor T1 and the second transistor T2, the frequency of the first clock signal is equal to or greater than the frequency of the second clock signal. For example, during the first time period ta, the frequency of the first clock signal is equal to the frequency of the second clock signal. During the second time period tb before or after the first time period ta, the frequency of the first clock signal is greater than the frequency of the second clock signal, so that the self-stabilization module 20 maintains the potential of the first node K1 stable according to the signal of the second node K2 and the first clock signal received by the second transistor T2, and controls the first gate control signal Pscan output by the gate drive sub-circuit GA to have no active level, which can improve the quality of the gate control signal output by the gate drive circuit GM and reduce power consumption.

[0172] When the first clock signal is input to the control end of the first transistor T1 and the second transistor T2, the first transistor T1 and the second transistor T2 are configured to be turned on in time according to the first clock signal, so as to control the signals transmitted to the first node K1 and the second node K2 through the self-stabilization module 20 and the shift register module 10, thereby enabling the first output module 30 to generate the first gate control signal Pscan according to the second clock signal and the signals of the first node K1 and the second node K2.

[0173] Correspondingly, for the design corresponding to FIG. 1F, FIG. 2A-2C and FIG. 3A-3E, when the first clock signal is input to the control end of the first transistor T1 and the second clock signal is input to the control end of the second transistor T2, the frequency of the first clock signal can be equal to or greater than the frequency of the second clock signal. For example, in the first time period ta, the frequency of the first clock signal is equal to the frequency of the second clock signal. In the second time period tb before or after the first time period ta, the frequency of the first clock signal is greater than the frequency of the second clock signal, so that the signal of the second node K2 is controlled by the first clock signal and the signal of the first node K1, and is not affected by the second clock signal received by the self-stabilizing module 20. The frequency reduction of the second clock signal is conducive to reducing the power consumption of the gate drive circuit GM, and the frequency reduction of the second clock signal does not affect the signal of the second node K2 and the stage transmission control of the gate drive circuit GM. That is, in the second stage tb in which the first clock signal CK1 to the fourth clock signal CK4 are direct current, the starting signal STV corresponding to the gate drive sub-circuit GA is not affected, so that the stage transmission control of the gate drive circuit GM can be normally performed.

[0174] In the case where the first clock signal is input to the control end of the first transistor T1 and the second clock signal is input to the control end of the second transistor T2, if the first transistor T1 is a P-type transistor, the invalid level of the first clock signal corresponds to a high level, and the valid level of the first clock signal corresponds to a low level. If the first transistor T1 is an N-type transistor, the invalid level of the first clock signal corresponds to a low level, and the valid level of the first clock signal corresponds to a high level. Thus, in the case where the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor, the starting time of the invalid pulse of the second clock signal is the same as the starting time of the valid pulse of the first clock signal, that is, the time point at which the second clock signal has a falling edge is the same as the time point at which the first clock signal has a falling edge.

[0175] Similarly, in the case where the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor, or the first transistor T1 and the second transistor T2 are both N-type transistors or P-type transistors, the starting time of the invalid pulse of the second clock signal is the same as the starting time of the valid pulse of the first clock signal.

[0176] Optionally, in the case where the first clock signal is input to the control end of the first transistor T1 and the second clock signal is input to the control end of the second transistor T2, in order to control the second time period tb in which the frequency of the second clock signal is reduced, the self-stabilizing module 20 can still maintain the function of stabilizing the potential of the first node K1, and the level of the second clock signal can be set to the valid level for turning on the second transistor T2.

[0177] When the gate drive circuit GM adopts the design of FIG. 1A, the load corresponding to the first clock line CKL1 includes the load corresponding to the first output transistor To1 of the first sub output module 301 in the 2k+1th gate drive sub circuit GA(2k+1), and the load corresponding to the first transistor T1, the second transistor T2, the first sustain transistor Th1 and the second sustain transistor Th2 in the 2k+1th gate drive sub circuit GA(2k+1). The load corresponding to the second clock line CKL2 includes the load corresponding to the first output transistor To1 of the second sub output module 302 in the 2k+1th gate drive sub circuit GA(2k+1). Thus, the load corresponding to the first clock line CKL1 and the load corresponding to the second clock line CKL2 have a large difference. Similarly, the load corresponding to the third clock line CKL3 and the fourth clock line CKL4 also have a large difference, the load corresponding to the third clock line CKL3 and the second clock line CKL2 also have a large difference, and the load corresponding to the first clock line CKL1 and the fourth clock line CKL4 also have a large difference.

[0178] When the gate drive circuit GM adopts the design shown in FIG. 1B~FIG. 1C, the load corresponding to the first clock line CKL1 includes the load corresponding to the first output transistor To1 of the first sub output module 301 in the 2k+1th gate drive sub circuit GA(2k+1), the load corresponding to the second clock line CKL2 includes the load corresponding to the first output transistor To1 of the second sub output module 302 in the 2k+1th gate drive sub circuit GA(2k+1), the load corresponding to the third clock line CKL3 includes the load corresponding to the first output transistor To1 of the first sub output module 301 in the 2k+2th gate drive sub circuit GA(2k+2), and the load corresponding to the fourth clock line CKL4 includes the load corresponding to the first output transistor To1 of the second sub output module 302 in the 2k+2th gate drive sub circuit GA(2k+2). Thus, the load corresponding to the first clock line CKL1~the fourth clock line CKL4 is the load corresponding to the first output transistor To1. Thus, the difference in the load between the first clock line CKL1~the fourth clock line CKL4 is reduced, so that the difference between the first gate control signals Pscan output by the gate drive circuit GM is reduced, which is beneficial to improve the signal difference between the plurality of first gate drive signals.

[0179] Similarly, when the gate driving circuit GM adopts the design shown in FIG. 1D, the load corresponding to the first clock line CKL1 includes the load corresponding to the first output transistor To1 of the first sub output module 301 in the (2k+1)th gate driving sub circuit GA(2k+1), the load corresponding to the second clock line CKL2 includes the load corresponding to the first output transistor To1 of the second sub output module 302 in the (2k+1)th gate driving sub circuit GA(2k+1), the load corresponding to the third clock line CKL3 includes the load corresponding to the first output transistor To1 of the third sub output module 303 in the (2k+1)th gate driving sub circuit GA(2k+1), the load corresponding to the fourth clock line CKL4 includes the load corresponding to the first output transistor To1 of the first sub output module 301 in the (2k+2)th gate driving sub circuit GA(2k+2), the load corresponding to the fifth clock line CKL5 includes the load corresponding to the first output transistor To1 of the second sub output module 302 in the (2k+2)th gate driving sub circuit GA(2k+2), and the load corresponding to the sixth clock line CKL6 includes the load corresponding to the first output transistor To1 of the third sub output module 303 in the (2k+1)th gate driving sub circuit GA(2k+1). Thus, the loads corresponding to the first clock line CKL1 to the sixth clock line CKL6 are all the loads corresponding to the first output transistor To1. Thus, the difference in the loads between the first clock line CKL1 and the fourth clock line CKL4 is reduced, so that the difference between the first gate control signals Pscan output by the gate driving circuit GM is reduced, which is beneficial to improving the signal difference between the plurality of first gate control signals Pscan.

[0180] Thus, in the gate driving circuit GM, the shift register module 10 and the self-stabilizing module 20 of the multi-stage gate driving sub circuit GA all receive the first clock signal, and the plurality of first output modules 30 receive the corresponding second clock signal, which realizes independent design of the clock signals applied by the self-stabilizing module 20 and the first output module 30, and can improve the signal difference between the plurality of first gate control signals Pscan. Moreover, because the clock signals applied by the shift register module 10 and the first output module 30 are independent of each other, the frequency of the second clock signal can be set to be less than the frequency of the first clock signal in the second period tb, so as to reduce power consumption while not affecting the stage transmission control of the gate driving circuit GM.

[0181] In some embodiments, the gate driving circuit GM still adopts the design of FIG. 1A to reduce the design difficulty. Thus, based on the design of FIG. 1A and the like, the plurality of clock lines CKL can be divided according to the load size corresponding thereto, and a capacitor can be added according to the category of the clock line CKL to compensate for the load difference between the clock lines CKL.

[0182] Correspondingly, the gate drive circuit GM includes a plurality of clock lines CKL and a plurality of gate drive sub-circuits GA, the plurality of clock lines CKL includes a first type of clock line and a second type of clock line, the number of gate drive sub-circuits GA electrically connected to the first type of clock line is less than the number of gate drive sub-circuits GA electrically connected to the second type of clock line. Wherein, the gate drive circuit GM includes a load capacitor CL, the load capacitor CL is connected in series between the first type of clock line and the constant voltage terminal VC, so as to adjust the load size corresponding to the first type of clock line by setting the load capacitor CL corresponding to the first type of clock line, thereby adjusting the load difference corresponding to the first type of clock line and the second type of clock line.

[0183] Optionally, the constant voltage terminal VC can be one of the first voltage terminal NVGL, the second voltage terminal PVGH, the third voltage terminal PVGL, the fourth voltage terminal NVGH or the fifth voltage terminal. Wherein, the voltage supplied by the fifth voltage terminal is different from any one of the voltage supplied by the first voltage terminal NVGL to the fourth voltage terminal NVGH. The load capacitor CL set corresponding to the first type of clock line is configured to increase the load corresponding to the first type of clock line, so that the load difference corresponding to the first type of clock line and the second type of clock line is reduced.

[0184] As please continue to refer to FIG. 1E, the first type of clock line includes the second clock line CKL2 and the fourth clock line CKL4, and the second type of clock line includes the first clock line CKL1 and the third clock line CKL3. The load capacitor CL is provided between the second clock line CKL2 and the constant voltage terminal VC, and the load capacitor CL is provided between the fourth clock line CKL4 and the constant voltage terminal VC.

[0185] By setting the load capacitor CL corresponding to the second clock line CKL2 and the fourth clock line CKL4, the load size corresponding to the second clock line CKL2 and the fourth clock line CKL4 is adjusted, thereby adjusting the load difference between the second clock line CKL2, the fourth clock line CKL4 and the first clock line CKL1, the third clock line CKL3.

[0186] In addition, when the shift register module 10 corresponds to receive the first sub-clock signal, the self-stabilizing module 20 corresponds to receive the second sub-clock signal, the first output module 30 corresponds to receive the third sub-clock signal, and the plurality of clock lines CKL transmits the second sub-clock signal and the third sub-clock signal, the load corresponding to the plurality of clock lines CKL also has a difference, thereby affecting the first gate control signal Pscan output by the first output module 30. Based on this, the design of the load capacitor CL can also be introduced to improve the signal difference between the plurality of first gate control signals Pscan.

[0187] As shown in FIG. 1F, when the gate driving circuit GM is designed by using the clock line CKL, the load corresponding to the first clock line CKL1 includes the load corresponding to the first output transistor To1 of the first sub output module 301 in the 2k+1th gate driving sub circuit GA(2k+1), and the load corresponding to the second transistor T2, the first sustain transistor Th1 and the second sustain transistor Th2 in the 2k+2th gate driving sub circuit GA(2k+2). The load corresponding to the second clock line CKL2 includes the load corresponding to the first output transistor To1 of the second sub output module 302 in the 2k+1th gate driving sub circuit GA(2k+1). The load corresponding to the third clock line CKL3 includes the load corresponding to the first output transistor To1 of the first sub output module 301 in the 2k+2th gate driving sub circuit GA(2k+2), and the load corresponding to the second transistor T2, the first sustain transistor Th1 and the second sustain transistor Th2 in the 2k+1th gate driving sub circuit GA(2k+1). The load corresponding to the fourth clock line CKL4 includes the load corresponding to the first output transistor To1 of the second sub output module 302 in the 2k+2th gate driving sub circuit GA(2k+2). Thus, the load corresponding to the first clock line CKL1 and the second clock line CKL2 is different, the load corresponding to the second clock line CKL2 and the third clock line CKL3 is different, and the load corresponding to the third clock line CKL3 and the fourth clock line CKL4 is different.

[0188] As the first clock line CKL1 corresponds to the load in the 2k+1th gate driving sub circuit GA(2k+1) and the 2k+2th gate driving sub circuit GA(2k+2) simultaneously, the third clock line CKL3 corresponds to the load in the 2k+1th gate driving sub circuit GA(2k+1) and the 2k+2th gate driving sub circuit GA(2k+2) simultaneously, the second clock line CKL2 corresponds to the load in the 2k+1th gate driving sub circuit GA(2k+1) only, and the fourth clock line CKL4 corresponds to the load in the 2k+2th gate driving sub circuit GA(2k+2) only. Thus, the first type clock line can include the second clock line CKL2 and the fourth clock line CKL4, and the second type clock line can include the first clock line CKL1 and the third clock line CKL3. The load capacitor CL is arranged between the second clock line CKL2 and the constant voltage terminal VC, and the load capacitor CL is arranged between the fourth clock line CKL4 and the constant voltage terminal VC, so as to adjust the load size corresponding to the second clock line CKL2 and the fourth clock line CKL4, and thus adjust the load difference between the second clock line CKL2, the fourth clock line CKL4 and the first clock line CKL1, the third clock line CKL3.

[0189] When the shift register module 10 corresponds to receiving the first sub-clock signal, the self-stable module 20 corresponds to receiving the second sub-clock signal, the first output module 30 corresponds to receiving the third sub-clock signal, and the plurality of clock lines CKL are used to transmit the second sub-clock signal and the third sub-clock signal, a load capacitor CL is arranged on the first type of clock line, so that the signal difference between the plurality of first gate control signals Pscan caused by the load difference of the clock signal used by the first output module 30 can be improved. Moreover, because the clock signals used by the shift register and the self-stable module 20 are independent of each other, the frequency of the first sub-clock signal is greater than the frequency of the second sub-clock signal in the second time period tb, so that the frequency of the first sub-clock signal is greater than the frequency of the third sub-clock signal, thereby reducing the working frequency of the first output module 30 and the self-stable module 20, and reducing the power consumption of the gate drive circuit GM, and the stage transfer control of the gate drive circuit GM is not affected by the second sub-clock signal and the third sub-clock signal.

[0190] Therefore, compared with the design of the gate drive circuit GM shown in FIGS. 1A-1E, the design of the gate drive circuit GM shown in FIG. 1F can reduce the power consumption of the gate drive circuit GM to the greatest extent. The problem of the signal difference of the first gate control signal Pscan can be improved by adding the load capacitor CL when the gate drive circuit GM uses the design shown in FIG. 1F.

[0191] It can be understood that the capacitance value of the load capacitor CL can be determined according to actual use requirements.

[0192] FIGS. 5A-5B are structural schematic diagrams of a display panel provided by an embodiment of the present application. The present application further provides a display panel, which comprises any of the above-mentioned gate drive circuits GM.

[0193] Please continue to refer to FIGS. 5A-5B, the display panel further comprises a plurality of sub-pixels Spi, the plurality of sub-pixels Spi are electrically connected with the gate drive circuit GM, and the gate drive circuit GM is configured to output the first gate control signal Pscan to the plurality of sub-pixels Spi.

[0194] FIG. 6 is a structural schematic diagram of a sub-pixel provided by an embodiment of the present application; at least one sub-pixel Spi comprises a light emitting device Di and a pixel drive circuit for driving the light emitting device Di to emit light.

[0195] Optionally, the light emitting device Di comprises a light emitting diode. Optionally, the light emitting device Di comprises one of an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0196] The pixel driving circuit comprises a driving module and a data writing module. The driving module is electrically connected with the light emitting device Di, and is configured to generate a driving current to drive the light emitting device Di to emit light. The data writing module is electrically connected with the driving module, and is configured to transmit a data signal to the driving module according to a corresponding first gate control signal Pscan.

[0197] Optionally, the driving module comprises a driving transistor Tdr and a first storage capacitor Cst1, and the data writing module comprises a data transistor Tda.

[0198] The first source-drain terminal of the driving transistor Tdr is electrically connected with a first voltage terminal Vdd, and the second source-drain terminal of the driving transistor Tdr is electrically connected with the anode of the light emitting device Di. The cathode of the light emitting device Di is electrically connected with a second voltage terminal Vss. The voltage supplied by the first voltage terminal Vdd is greater than the voltage supplied by the second voltage terminal Vss. The first storage capacitor Cst1 is connected in series between the first voltage terminal Vdd and the control terminal of the driving transistor Tdr.

[0199] The data transistor Tda comprises a control terminal configured to receive a corresponding first gate control signal Pscan, a first source-drain terminal configured to receive a data signal transmitted by a corresponding data line DL, and a second source-drain terminal electrically connected with the first source-drain terminal of the driving transistor Tdr.

[0200] In the same gate driving sub-circuit GA, the plurality of first output modules 30 are electrically connected with the control terminals of the data transistors Tda of the sub-pixels Spi of the adjacent multiple rows. Each first output module 30 is electrically connected with the control terminals of the data transistors Tda of the sub-pixels Spi of at least one row, so as to control the conduction states of the data transistors Tda of the plurality of sub-pixels Spi by using the plurality of first gate control signals Pscan, thereby controlling the frequency of refreshing the display data of the plurality of sub-pixels Spi, so as to realize the design of partitioned frequency display of the display panel DP.

[0201] Optionally, each first output module 30 is connected with the control terminals of the data transistors Tda of the sub-pixels Spi of one row. In the same gate driving sub-circuit GA, there are X first output modules 30. The X first output modules 30 in the same gate driving sub-circuit GA are electrically connected with the control terminals of the data transistors Tda of the sub-pixels Spi of the adjacent X rows, so that the data transistors Tda of the adjacent multiple rows of sub-pixels Spi can be sequentially turned on or turned off according to the plurality of first gate control signals Pscan with phase difference, thereby sequentially realizing the refreshing operation of the data signal of the adjacent multiple rows of sub-pixels Spi when refreshing the display data.

[0202] Optionally, the same gate driving sub-circuit GA includes X first output modules 30, each first output module 30 is electrically connected with the control end of the data transistor Tda of one row of sub-pixels Spi, so that the Sth gate driving sub-circuit GA(S) is electrically connected with the control end of the data transistor Tda of the Lth to the L+(X-1)th row of sub-pixels Spi, so that the plurality of sub-pixels Spi can be driven by the gate driving circuit GM to realize display driving by using the line-by-line scanning technology. Wherein, S≥1, L=XS-(X-1).

[0203] It can be understood that in some embodiments, each first output module 30 can also be electrically connected with the control end of the data transistor Tda of a plurality of rows of sub-pixels Spi.

[0204] Please continue to refer to FIG. 6, at least one sub-pixel Spi includes a compensation transistor Tc, the compensation transistor Tc includes a control end, a first source-drain end electrically connected with the second source-drain end of the driving transistor Tdr, and a second source-drain end electrically connected with the control end of the driving transistor Tdr.

[0205] In some embodiments, in addition to outputting a plurality of first gate control signals Pscan, the gate driving sub-circuit GA can also output a second gate control signal Nscan. Thus, the second gate control signal Nscan output by the gate driving sub-circuit GA can be output to the control end of the compensation transistor Tc, so as to reduce the number of gate driving circuits GM required to match the sub-pixel Spi.

[0206] Optionally, when the second output module 60 of the gate driving sub-circuit GA outputs the second gate control signal Nscan to the compensation transistor Tc of a plurality of sub-pixels Spi in adjacent rows, the first gate control signal Pscan and the second gate control signal Nscan received by the same sub-pixel Spi can be output by the same gate driving sub-circuit GA, so that the data transistor Tda and the compensation transistor Tc of the same sub-pixel Spi can have a common conduction time, so that the data signal can be transmitted to the control end of the driving transistor Tdr, and the refresh operation of the display data of the sub-pixel Spi is realized.

[0207] Optionally, when the same gate driving sub-circuit GA includes X first output modules 30, the Sth gate driving sub-circuit GA(S) is electrically connected with the control end of the compensation transistor Tc of the Lth to the L+(X-1)th row of sub-pixels Spi, so that the data transistor Tda and the compensation transistor Tc of each sub-pixel Spi can have a common conduction time. Wherein, S≥1, L=XS-(X-1).

[0208] Please continue to refer to FIG. 6, the at least one sub-pixel Spi includes a reset transistor Tr, the reset transistor Tr includes a control terminal, a first source-drain terminal electrically connected with a reset line VLr, and a second source-drain terminal electrically connected with a control terminal of the driving transistor Tdr.

[0209] In some embodiments, when the gate driving sub-circuit GA simultaneously outputs a plurality of first gate control signals Pscan and second gate control signals Nscan, the second gate control signal Nscan output by each gate driving sub-circuit GA can be used to control the reset transistor Tr.

[0210] Optionally, when the same gate driving sub-circuit GA includes X first output modules 30, the S-2th gate driving sub-circuit GA (S-2) can be used to electrically connect the control terminal of the reset transistor Tr of the Lth to the L+(X-1)th sub-pixel Spi, so that the data transistor Tda and the reset transistor Tr of each sub-pixel Spi have independent conduction times.

[0211] It can be understood that, when the display device is provided with only one gate driving circuit GM simultaneously outputting a plurality of first gate control signals Pscan and second gate control signals Nscan, the plurality of second gate control signals Nscan can be used to control the compensation transistor Tc of the plurality of sub-pixels Spi, or can be used to control the reset transistor Tr of the plurality of sub-pixels Spi, or can be used to control the compensation transistor Tc and the reset transistor Tr of the plurality of sub-pixels Spi.

[0212] Optionally, when the plurality of second gate control signals Nscan are used to control the compensation transistor Tc and the reset transistor Tr of the plurality of sub-pixels Spi, the second gate control signal Nscan corresponding to the compensation transistor Tc and the reset transistor Tr in the same sub-pixel Spi can be supplied by gate driving sub-circuits GA of different orders.

[0213] Optionally, in some embodiments, two gate driving circuits GM simultaneously outputting a plurality of first gate control signals Pscan and second gate control signals Nscan can be provided, so that the reset transistor Tr and the compensation transistor Tc are controlled by the second gate control signals Nscan output by the two gate driving circuits GM, and the data transistor Tda can be controlled by the first gate control signal Pscan output by at least one of the two gate driving circuits GM.

[0214] As please continue to refer to FIG. 5A~FIG. 5B, the display panel comprises two gate driving circuits GM, the two gate driving circuits GM comprising a first gate driving circuit GM1 and a second gate driving circuit GM2. Wherein, GA1 represents a gate driving sub-circuit comprised by the first gate driving circuit GM1, and GA2 represents a gate driving sub-circuit comprised by the second gate driving circuit GM2.

[0215] The control end of the compensation transistor Tc of the plurality of sub-pixels Spi corresponds to receive the second gate control signal Nscan output by the plurality of gate driving sub-circuits GA1 of the first gate driving circuit GM1, and the control end of the reset transistor Tr of the plurality of sub-pixels Spi corresponds to receive the second gate control signal Nscan output by the plurality of gate driving sub-circuits GA2 of the second gate driving circuit GM2; the control end of the data transistor Tda of the plurality of sub-pixels Spi corresponds to receive the first gate control signal Pscan output by the plurality of gate driving sub-circuits GA1 of the first gate driving circuit GM1, and / or, receive the first gate control signal Pscan output by the plurality of gate driving sub-circuits GA2 of the second gate driving circuit GM2.

[0216] Optionally, the frequency division control lines applied by the first gate driving circuit GM1 and the second gate driving circuit GM2 are independent of each other, so as to realize independent control of whether the gate control signals output by the first gate driving circuit GM1 and the second gate driving circuit GM2 have effective pulses. As the first gate driving circuit GM1 corresponds to adopt the frequency division control signals transmitted by the first frequency division control line FL1 and the second frequency division control line FL2, so as to realize control of whether the gate control signals output have effective pulses. The second gate driving circuit GM2 corresponds to adopt the frequency division control signals transmitted by the third frequency division control line FL3 and the fourth frequency division control line FL4, so as to realize control of whether the gate control signals output have effective pulses.

[0217] Optionally, the compensation transistor Tc and the reset transistor Tr are silicon transistors or oxide transistors, and the compensation transistor Tc and the reset transistor Tr are P-type transistors or N-type transistors. Optionally, in order to reduce the leakage of the control end of the driving transistor Tdr to the output end of the driving transistor Tdr and the reset line VLr, the compensation transistor Tc and the reset transistor Tr are oxide transistors. In order to be compatible with the existing process, the compensation transistor Tc and the reset transistor Tr are N-type transistors. It can be understood that the active layer of the oxide transistor comprises indium gallium zinc oxide and the like.

[0218] Please continue to refer to FIG. 6, at least one sub-pixel Spi comprises a light-emitting control module electrically connected to the driving module and the light-emitting device Di, and the light-emitting control module is configured to control the on-off of the driving current flow path according to the light-emitting control signal EM.

[0219] Optionally, the light emitting control module comprises a light emitting control transistor, the light emitting control transistor is connected in series between the first voltage terminal and the second voltage terminal with the driving transistor and the light emitting device, and a control terminal of the light emitting control transistor is configured to receive the light emitting control signal EM.

[0220] Optionally, the light emitting control transistor comprises at least one of a first light emitting control transistor Te1 and a second light emitting control transistor Te2.

[0221] The first light emitting control transistor Te1 comprises a control terminal connected with the light emitting control line EML to receive the light emitting control signal EM, a first source-drain terminal electrically connected with the first voltage terminal Vdd, and a second source-drain terminal electrically connected with the first source-drain terminal of the driving transistor Tdr.

[0222] The second light emitting control transistor Te2 comprises a control terminal connected with the light emitting control line EML to receive the light emitting control signal EM, a first source-drain terminal electrically connected with the second source-drain terminal of the driving transistor Tdr, and a second source-drain terminal electrically connected with the anode of the light emitting device Di.

[0223] Please continue to refer to FIG. 6, the sub-pixel Spi comprises a first initial transistor Ti1, the first initial transistor Ti1 is configured to control the signal transmission between the light emitting device Di and the first initial line VL1 according to the first scanning signal Scan1.

[0224] Correspondingly, the first initial transistor Ti1 comprises a control terminal, a first source-drain terminal configured to receive the first initial signal transmitted by the first initial line VL1, and a second source-drain terminal electrically connected with the anode of the light emitting device Di.

[0225] Optionally, in some embodiments, the sub-pixel Spi further comprises a second storage capacitor Cst2 connected in series between the control terminal of the data transistor Tda and the control terminal of the driving transistor Tdr, as shown in FIG. 6.

[0226] Optionally, in some embodiments, in order to improve the threshold voltage offset of the driving transistor Tdr caused by the display frequency switching, the sub-pixel Spi further comprises a second initial transistor Ti2, the second initial transistor Ti2 comprises a control terminal, a first source-drain terminal configured to receive the second initial signal transmitted by the second initial line VL2, and a second source-drain terminal electrically connected with the first source-drain terminal of the driving transistor Tdr, as shown in FIG. 6.

[0227] The control terminal of the second initial transistor Ti2 can be electrically connected with the control terminal of the first initial transistor Ti1.

[0228] Please continue to refer to FIGS. 5A-5B, the display panel includes a scan driving module, the scan driving module is electrically connected with the plurality of sub-pixels Spi, and the scan driving module is configured to generate a plurality of scan signals according to clock signals transmitted by a first multiplexing clock line ML1 and a second multiplexing clock line ML2 to output to the plurality of sub-pixels Spi.

[0229] The first multiplexing clock line ML1 and the second multiplexing clock line ML2 are electrically connected with the gate driving circuit GM, and the first multiplexing clock line ML1 and the second multiplexing clock line ML2 are configured to transmit the first clock signal or the first sub-clock signal to the multi-stage gate driving sub-circuit GA, so that the gate driving circuit GM and the scan driving module multiplex the signals transmitted by the first multiplexing clock line ML1 and the second multiplexing clock line ML2, thereby facilitating the display panel to achieve a narrow frame design.

[0230] Optionally, the first multiplexing clock line ML1 includes a first sub-multiplexing clock line ML11, and the second multiplexing clock line ML2 includes a second sub-multiplexing clock line ML21. The scan driving module includes an emission driving circuit EGM. The emission driving circuit EGM includes a plurality of emission driving sub-circuits EA, and the emission driving sub-circuits EA are configured to generate an emission control signal EM according to clock signals transmitted by the first sub-multiplexing clock line ML11 and the second sub-multiplexing clock line ML21. The plurality of scan signals include the emission control signal EM.

[0231] Optionally, the first sub-multiplexing clock line ML11 and the second sub-multiplexing clock line ML21 transmit the first clock signal or the first sub-clock signal to the gate driving circuit GM, so that the gate driving circuit GM and the emission driving circuit EGM share the clock signals, thereby reducing the number of clock signals applied by the display panel, saving power consumption, and facilitating the realization of a narrow frame design of the display panel.

[0232] Optionally, the first multiplexing clock line ML1 includes a third sub-multiplexing clock line ML12, and the second multiplexing clock line ML2 includes a fourth sub-multiplexing clock line ML22. The scan driving module includes a scan driving circuit SGM, and the scan driving circuit SGM includes a plurality of scan driving sub-circuits SA. The scan driving sub-circuits SA are configured to generate a first scan signal Scan1 according to clock signals transmitted by the third sub-multiplexing clock line ML12 and the fourth sub-multiplexing clock line ML22. The plurality of scan signals include the first scan signal Scan1.

[0233] Optionally, the third sub-multiplexing clock line ML12 and the fourth sub-multiplexing clock line ML22 transmit the first clock signal or the first sub-clock signal to the gate driving circuit GM, so that the gate driving circuit GM and the scan driving circuit SGM share the clock signals, thereby reducing the number of clock signals applied by the display panel, saving power consumption, and facilitating the realization of a narrow frame design of the display panel.

[0234] Optionally, when the display panel includes one gate drive circuit GM, the gate drive circuit GM and the scan drive circuit SGM or the emission drive circuit EGM share the clock signal. When the display panel includes two gate drive circuits GM, one of the two gate drive circuits EM shares the clock signal with the scan drive circuit SGM, and the other of the two gate drive circuits EM shares the clock signal with the emission drive circuit EGM, so as to reduce the number of clock signals applied to the display panel, save power consumption, and facilitate the narrow-frame design of the display panel.

[0235] Please continue to refer to FIGS. 5A-5B for a schematic description taking the design form of the gate drive circuit GM shown in FIG. 1C as an example. The position distribution diagram of the gate drive circuit and the scan drive module corresponding to the design forms of the gate drive circuit GM shown in FIGS. 1A-1B and FIGS. 1D-1F can be obtained by referring to the design of FIG. 5B. As shown in FIG. 5B, INa and INb in the emission drive sub-circuit EA are configured to receive the clock signals transmitted by the first sub-multiplex line ML11 and the second sub-multiplex line ML21, and Eout in the emission drive sub-circuit EA is configured to output the light-emitting control signal. INc and INd in the scan drive sub-circuit SA are configured to receive the clock signals transmitted by the third sub-multiplex line ML12 and the fourth sub-multiplex line ML22, and Sout in the scan drive sub-circuit SA is configured to output the first scan signal Scan1.

[0236] The display panel includes a display area AA and first and second non-display areas NA1 and NA2 located on opposite sides of the display area AA. The display panel includes two gate drive circuits GM (i.e., a first gate drive circuit GM1 and a second gate drive circuit GM2).

[0237] The first and second sub-multiplex lines ML11 and ML21 are located in the first non-display area NA1 and electrically connected to the emission drive circuit EGM and one of the two gate drive circuits GM (e.g., the first gate drive circuit GM1) located in the first non-display area NA1. The third and fourth sub-multiplex lines ML12 and ML22 are located in the second non-display area NA2 and electrically connected to the scan drive circuit SGM and the other of the two gate drive circuits GM (e.g., the second gate drive circuit GM2) located in the second non-display area NA2, so as to reduce the number of clock signals applied to the display panel by multiplexing the clock signals of the gate drive circuit GM, the emission drive circuit EGM, and the scan drive circuit SGM, save power consumption, and facilitate the narrow-frame design of the display panel.

[0238] Optionally, the first and second non-display areas NA1 and NA2 can be non-display areas or display areas.

[0239] Please continue to refer to FIGS. 5A-5B and 6, the display panel includes a plurality of gate control lines, the plurality of gate control lines include a first gate control line SL1, a second gate control line SL2, a third gate control line SL3, and a fourth gate control line SL4.

[0240] Optionally, the first gate control line SL1 is electrically connected between the gate drive circuit GM and the control end of the data transistor Tda, so as to transmit the first gate control signal Pscan to the control end of the data transistor Tda. The second gate control line SL2 is electrically connected between the first gate drive circuit GM1 and the control end of the compensation transistor Tc, so as to transmit the corresponding second gate control signal Nscan to the control end of the compensation transistor Tc. The third gate control line SL3 is electrically connected between the second gate drive circuit GM2 and the control end of the reset transistor Tr, so as to transmit the corresponding second gate control signal Nscan to the control end of the reset transistor Tr. The fourth gate control line SL4 is electrically connected between the scan drive circuit SGM and the control end of the first initial transistor Ti1, so as to transmit the corresponding first scan signal Scan1 to the control end of the first initial transistor Ti1.

[0241] FIG. 7 is a timing diagram of the corresponding pixel driving circuit provided by the embodiment of the present application. Taking the compensation transistor Tc and the reset transistor Tr as N-type transistors, and the driving transistor Tdr, the data transistor Tda, the first light-emitting control transistor Te1, the second light-emitting control transistor Te2, the first initial transistor Ti1, and the second initial transistor Ti2 as P-type transistors as examples, the working principle of the pixel driving circuit is described. For the purpose of distinguishing the second gate control signal received by the control end of the compensation transistor Tc and the control end of the reset transistor Tr, the second gate control signal received by the control end of the reset transistor Tr is recorded as a first sub-gate control signal Nscan21, and the second gate control signal received by the control end of the compensation transistor Tc is recorded as a second sub-gate control signal Nscan22.

[0242] In the first reset stage Si1, the light-emitting control signal EM and the first gate control signal Pscan received by the data transistor Tda are high level, the first sub-gate control signal NScan21 received by the reset transistor Tr and the second sub-gate control signal NScan22 received by the compensation transistor Tc are low level, and the first scan signal Scan1 is low level. The first initial signal transmitted by the first initial line VL1 is transmitted to the anode of the light-emitting device Di, so as to reset the anode potential of the light-emitting device Di; the second initial signal transmitted by the second initial line VL2 is transmitted to the input end and the output end of the driving transistor Tdr, so as to reset the potential of the input end and the output end of the driving transistor Tdr.

[0243] In the second reset stage Si2, the first sub-gate control signal NScan21, the light emitting control signal EM, the first gate control signal Pscan, and the first scan signal Scan1 are high, and the second sub-gate control signal NScan22 is low. The reset transistor Tr is turned on, and the reset signal Vr is transmitted to the gate of the driving transistor Tdr to reset the potential of the control terminal of the driving transistor Tdr.

[0244] In the data writing stage Sw, the second sub-gate control signal NScan22, the light emitting control signal EM, and the first scan signal Scan1 are high, and the first sub-gate control signal NScan21 and the first gate control signal Pscan are low. The data transistor Tda and the compensation transistor Tc are turned on, and the data signal is transmitted to the control terminal of the driving transistor Tdr.

[0245] In the second reset stage Si2 and the data writing stage Sw, a stage of simultaneously turning on the reset transistor Tr and the compensation transistor Tc can be further included, so that the reset signal Vr can be transmitted to the output terminal and the input terminal of the driving transistor Tdr to reset the potential of the output terminal and the input terminal of the driving transistor Tdr.

[0246] In the third reset stage Si3, the light emitting control signal EM and the first gate control signal Pscan are high, the first sub-gate control signal NScan21, the second sub-gate control signal NScan22, and the first scan signal Scan1 are low, the first initial signal is transmitted to the anode of the light emitting device Di, and the second initial signal is transmitted to the input terminal and the output terminal of the driving transistor Tdr.

[0247] In the light emitting stage Sd, the first gate control signal Pscan and the first scan signal Scan1 are high, the light emitting control signal EM, the first sub-gate control signal NScan21, and the second sub-gate control signal NScan22 are low, the first light emitting control transistor Te1 and the second light emitting control transistor Te2 are turned on, and the driving transistor Tdr generates a driving current to drive the corresponding light emitting device Di to emit light.

[0248] In the fourth reset stage Si4 and the fifth reset stage Si5, the light emitting control signal EM and the first gate control signal Pscan are high, the first sub-gate control signal NScan21, the second sub-gate control signal NScan22, and the first scan signal Scan1 are low, the first initial signal is transmitted to the anode of the light emitting device Di, and the second initial signal is transmitted to the input terminal and the output terminal of the driving transistor Tdr.

[0249] The write frame WF includes a first reset stage Si1, a second reset stage Si2, a data write stage Sw, a third reset stage Si3, and a light emitting stage Sd, and the hold frame HF includes a fourth reset stage Si4, a fifth reset stage Si5, and the light emitting stage Sd.

[0250] FIG. 8 is a schematic diagram of a high-frequency and low-frequency picture display principle provided by the embodiment of the present application, which illustrates the write frame WF and the hold frame HF by taking a static picture display of the display panel DP as an example.

[0251] When the display panel DP is in the first display mode, the display panel DP has a first refresh frequency, and a display period of the display panel includes the write frame WF and the hold frame HF. When the display panel DP is in the second display mode, the display panel DP has a second refresh frequency, and a display period of the display panel includes the write frame WF. The first refresh frequency is less than the second refresh frequency.

[0252] The first display mode can be a low-frequency display mode, and the second display mode can be a high-frequency display mode.

[0253] When the display panel DP displays in the high-frequency display mode (for example, the second refresh frequency is equal to 1 Hz), the display panel DP needs to perform a refresh operation of display data once in 1 second, that is, 1 second includes 1 frame of picture, and the refresh operation of display data is performed for each frame of display (that is, the sub-pixel Spi matches the time sequence of the write frame WF shown in FIG. 7 for each frame). When the display panel DP displays in the low-frequency display mode (for example, the first refresh frequency is equal to 1 Hz), the display panel DP also includes 1 frame of picture in 1 second, but only the first frame of picture performs the refresh operation of display data (that is, the sub-pixel Spi only matches the time sequence of the write frame WF shown in FIG. 7 for the first frame F1), and the display data refresh operation is not performed for the 119 frames of picture continuous to the first frame F1 (that is, the sub-pixel Spi matches the time sequence of the hold frame HF shown in FIG. 7 for the 119 frames continuous to the first frame F1).

[0254] The frame in which the refresh operation of display data is performed can be recorded as a write frame WF, and the frame in which the refresh operation of display data is not performed can be recorded as a hold frame HF.

[0255] So, in the write frame WF, the second sub-gate control signal Nscan22 corresponding to the compensation transistor Tc, the first sub-gate control signal Nscan21 corresponding to the reset transistor Tr and the first gate control signal Pscan corresponding to the data transistor Tda all need to have an effective level, so that the original data signal stored in the control end of the driving transistor Tdr is overwritten by the newly written data signal, so that the sub-pixel Spi re-implements display according to the newly written data signal in the write frame WF. In the hold frame HF, the second sub-gate control signal Nscan22 corresponding to the compensation transistor Tc and the first sub-gate control signal Nscan21 corresponding to the reset transistor Tr of part of the sub-pixels Spi remain invalid, so that the compensation transistor Tc and the reset transistor Tr are turned off, so that the control end of the driving transistor Tdr does not store new data signals. In the hold frame HF, the first gate control signal Pscan corresponding to the data transistor Tda can remain the same frequency as the write frame WF. Alternatively, in the hold frame HF, the first gate control signal Pscan corresponding to the data transistor Tda can remain invalid, so that the first gate control signal Pscan corresponding to the data transistor Tda has a frequency lower than that in the write frame WF.

[0256] It can be understood that a working period of the gate drive circuit GM corresponds to a frame time.

[0257] FIG. 9 is a timing diagram of the gate control signals corresponding to the multiple rows of sub-pixels provided by the embodiment of the application, taking the matching design of each gate drive sub-circuit GA including two first output modules 30 as an example, and combining the analysis of FIG. 4A and FIG. 7 to describe the principle of implementing frequency division display by the display panel DP using the gate drive circuit GM.

[0258] In the first frame F1 of a display period, in order to make the control end of the driving transistor Tdr of the multiple sub-pixels Spi all write new data signals, the first clock signal and the second clock signal corresponding to the multiple gate drive sub-circuits GA, or the first sub-clock signal, the second sub-clock signal and the third sub-clock signal all remain high frequency, so that the multiple rows of sub-pixels Spi in the display panel DP all experience the write frame WF stage shown in FIG. 7.

[0259] In the second frame F2 of a display period, if the first row of sub-pixels Spi to the L-1th row of sub-pixels Spi of the display panel DP are displayed in the high-frequency display mode, and the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi are displayed in the low-frequency display mode, the first sub-gate control signal Nscan21, the second sub-gate control signal Nscan22, and the first gate control signal Pscan applied to the first row of sub-pixels Spi to the L-1th row of sub-pixels Spi all need to have effective pulses, so that the first row of sub-pixels Spi to the Lth row of sub-pixels Spi all experience the write frame WF stage shown in FIG. 7. The first sub-gate control signal Nscan21, the second sub-gate control signal Nscan22, and the first gate control signal Pscan applied to the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi all do not need to have effective pulses, so that the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi all experience the hold frame HF stage shown in FIG. 7. Accordingly, the first clock signal and the second clock signal, or the first sub-clock signal, the second sub-clock signal, and the third sub-clock signal applied to the gate driving sub-circuit GA for outputting the first sub-gate control signal Nscan21, the second sub-gate control signal Nscan22, and the first gate control signal Pscan to the first row of sub-pixels Spi to the L-1th row of sub-pixels Spi are all high-frequency. The first clock signal or the first sub-clock signal applied to the gate driving sub-circuit GA for outputting the first sub-gate control signal Nscan21, the second sub-gate control signal Nscan22, and the first gate control signal Pscan to the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi can be high-frequency, and the second clock signal or the second sub-clock signal and the third sub-clock signal can be low-frequency, so as to reduce the power consumption of the display panel. The second frame F2 is located after the first frame F1.

[0260] Thus, for the first row of sub-pixels Spi to the L-1th row of sub-pixels Spi, the second frame F2 is still the write frame WF, and for the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi, the second frame F2 is the hold frame HF. Therefore, corresponding to the second frame F2, the control end of the driving transistor Tdr of the first row of sub-pixels Spi to the L-1th row of sub-pixels Spi has data signal writing, and the control end of the driving transistor Tdr of the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi does not have data signal writing, so that the first row of sub-pixels Spi to the L-1th row of sub-pixels Spi and the Lth row of sub-pixels Spi and the subsequent rows of sub-pixels Spi have a difference in the refresh frequency corresponding to the second frame F2, so that the display panel DP realizes the frequency division display function.

[0261] After the second clock signal or the second sub-clock signal and the third sub-clock signal are reduced to low frequency in the second period tb, the stage transfer control of the gate drive circuit GM is still valid. Therefore, if the Lth row of sub-pixels Spi and the following rows of sub-pixels Spi are displayed in the low frequency display mode, the Lth row of sub-pixels Spi to the L+O-1th row of sub-pixels Spi, the L+Oth row of sub-pixels Spi and the following rows of sub-pixels Spi can still enter the high frequency display mode for display. That is, the first sub-gate control signal Nscan21, the second sub-gate control signal Nscan22 and the first gate control signal Pscan applied to the Lth row of sub-pixels Spi to the L+O-1th row of sub-pixels Spi do not need to have valid pulses, so that the Lth row of sub-pixels Spi to the L+O-1th row of sub-pixels Spi all experience the hold frame HF stage shown in FIG. 7. The first sub-gate control signal Nscan21, the second sub-gate control signal Nscan22 and the first gate control signal Pscan applied to the L+Oth row of sub-pixels Spi and the following rows of sub-pixels Spi all need to have valid pulses, so that the L+Oth row of sub-pixels Spi and the following rows of sub-pixels Spi all experience the write frame WF stage shown in FIG. 7. Accordingly, the first clock signal applied to the gate drive sub-circuit GA for outputting the first sub-gate control signal Nscan21, the second sub-gate control signal Nscan22 and the first gate control signal Pscan to the Lth row of sub-pixels Spi to the L+O-1th row of sub-pixels Spi can remain high frequency, and the second clock signal or the second sub-clock signal and the third sub-clock signal can be low frequency, so as to reduce the power consumption of the display panel. The first clock signal and the second clock signal or the first sub-clock signal, the second sub-clock signal and the third sub-clock signal applied to the gate drive sub-circuit GA for outputting the first sub-gate control signal Nscan21, the second sub-gate control signal Nscan22 and the first gate control signal Pscan to the L+Oth row of sub-pixels Spi and the following rows of sub-pixels Spi all remain high frequency. Therefore, in the same display period, the refresh frequency corresponding to different display areas can change from low to high, or from high to low.

[0262] In the write frame WF, the frequency of the first clock signal corresponding to each gate drive sub-circuit GA is equal to the frequency of the second clock signal, or the frequency of the first sub-clock signal corresponding to each gate drive sub-circuit GA is equal to the frequency of the second sub-clock signal, so that the multiple rows of sub-pixels Spi all perform the refresh operation of display data. In the hold frame HF, the frequency of the first clock signal corresponding to at least one gate drive sub-circuit GA is greater than the frequency of the second clock signal, or the frequency of the first sub-clock signal corresponding to at least one gate drive sub-circuit GA is greater than the frequency of the second sub-clock signal, so that at least one row of sub-pixels Spi does not perform the refresh operation of display data.

[0263] In the writing frame WF, the first clock signal or the first sub clock signal corresponding to each of the gate driving sub-circuit GA has a first frequency. In the holding frame HF, the first clock signal or the first sub clock signal corresponding to each of the gate driving sub-circuit GA has a second frequency. The first frequency is equal to the second frequency, so that the plurality of sub-pixels Spi perform the refresh operation of the display data.

[0264] In the writing frame WF, the second clock signal or the second sub clock signal corresponding to at least one of the gate driving sub-circuit GA has a third frequency; in the holding frame HF, the second clock signal or the second sub clock signal corresponding to the gate driving sub-circuit GA has a fourth frequency. The third frequency is greater than the fourth frequency, so that the sub-pixel of the gate driving sub-circuit GA does not perform the refresh operation of the display data in the holding frame HF.

[0265] Optionally, in the holding frame HF, the second clock signal or the second sub clock signal corresponding to at least one of the gate driving sub-circuit GA is in a level state for turning on the seventh transistor T7, so that the first node K1 of the gate driving sub-circuit GA maintains stable.

[0266] Similarly, the design of the gate driving circuit GM including three or more first output modules 30 can also be obtained to control the display panel to realize the frequency division display function.

[0267] FIG. 10 is a schematic diagram of the display brightness difference principle provided by the embodiment of the application. The inventor has actually verified the gate driving circuit GM of the application, in which the gate driving sub-circuit GA includes two first output modules 30 and one second output module 60. The first gate control signal Pscan generated by one of the two first output modules is received by the odd row sub-pixels, and the first gate control signal Pscan generated by the other of the two first output modules is received by the even row sub-pixels. The odd row sub-pixels and the even row sub-pixels in the display panel are controlled to perform display respectively, so as to obtain the display difference corresponding to the odd row sub-pixels and the even row sub-pixels.

[0268] For example, the gate driving circuit GM shown in FIG. 1A cooperates with the gate driving sub-circuit GA shown in FIG. 3C (i.e. corresponding to Type 1 in Table 2). In the gate driving sub-circuit GA, the first gate control signal Pscan generated by the first output module receiving the first clock signal CK1 transmitted by the first clock line CKL1 or the third clock signal CK3 transmitted by the third clock line CKL3 is received by the odd row sub-pixels, and the first gate control signal Pscan generated by the first output module receiving the second clock signal CK2 transmitted by the second clock line CKL2 or the fourth clock signal CK4 transmitted by the fourth clock line CKL4 is received by the even row sub-pixels. The adjacent two-stage gate driving sub-circuit GA forms a minimum repeating unit, and the parasitic capacitance of the minimum repeating unit corresponding to the first clock line CKL1 to the fourth clock line CKL4 is shown in Table 1. When the gate driving circuit GM is applied to a display panel, the display effects of five display panels are verified, and the luminance data shown in Table 2 is obtained.

[0269]

[0270] wherein the unit of the parasitic capacitance is femtofarad.

[0271]

[0272] wherein the unit of the odd row luminance and the even row luminance is nit. The gate driving sub-circuit of Type 2 adopts a design of 13T3C (i.e. 13 transistors and 3 capacitors) as shown in FIG. 13. That is, FIG. 13 is a structural schematic diagram of another gate driving sub-circuit of the present application, VGH and VGL represent the high voltage end and the low voltage end respectively, RL represents the reset signal, Tt1-Tt13 represent transistors, and Ct1-Ct3 represent capacitors. Cas(C) and Cas(C-1) represent the gate control signals output by the Cth gate driving sub-circuit and the C-1th gate driving sub-circuit respectively. When the transistors Tt1 and Tt6 access the clock signal transmitted by the first clock line CKL1, the transistors Tt3, Tt4 and Tt8 access the clock signal transmitted by the second clock line CKL2. When the transistors Tt1 and Tt6 access the clock signal transmitted by the second clock line CKL2, the transistors Tt3, Tt4 and Tt8 access the clock signal transmitted by the first clock line CKL1.

[0273] It is found by analysis that, when the display panel is designed by using the type 1 application, the load corresponding to the clock line CKL in the gate drive circuit GM has a difference problem, which causes the first gate control signal Pscan to have a time delay difference. The time delay of the first gate control signal Pscan is large, the effective time length of the data signal received by the sub-pixel corresponding to the first gate control signal Pscan is short, and the display brightness of the sub-pixel is high. When the first gate control signal Pscan output by the first sub-output module 301 of the gate drive sub-circuit GA is received by the odd row sub-pixel, and the first gate control signal Pscan output by the second sub-output module 302 of the gate drive sub-circuit GA is received by the even row sub-pixel, the load of the clock line CKL corresponding to the first gate control signal Pscan applied by the odd row sub-pixel is greater than the load of the clock line CKL corresponding to the first gate control signal Pscan applied by the even row sub-pixel. When the control end of the driving transistor Tdr in the odd row sub-pixel and the control end of the driving transistor Tdr in the even row sub-pixel are charged according to the same data signal in the data writing stage Sw, the charging amount corresponding to the control end of the driving transistor Tdr in the odd row sub-pixel and the control end of the driving transistor Tdr in the even row sub-pixel at the end of the data writing stage Sw is different. As shown in FIG. 10, the charging amount corresponding to the control end of the driving transistor Tdr in the odd row sub-pixel (i.e., corresponding to Q1 in FIG. 10) at the end of the data writing stage Sw is at the g1 point, and the charging amount corresponding to the control end of the driving transistor Tdr in the even row sub-pixel (i.e., corresponding to Q2 in FIG. 10) at the end of the data writing stage Sw is at the g2 point. Thus, the control end of the driving transistor Tdr in the odd row sub-pixel and the control end of the driving transistor Tdr in the even row sub-pixel have a charging difference at the end of the data writing stage Sw, which causes the odd row brightness and the even row brightness to have a difference problem. According to the data in Table 2, the difference between the odd row brightness and the even row brightness is about 3%.

[0274] Based on the similar verification method as type 1 and type 2, the display panel is designed by using the gate drive circuit GM shown in FIGS. 1B-1F and the gate drive sub-circuit GA shown in FIGS. 3A-3E, and actual verification is performed, and it is found that the difference between the odd row brightness and the even row brightness is about 0.5%. Thus, by using the gate drive circuit GM shown in FIGS. 1B-1F and the gate drive sub-circuit GA shown in FIGS. 3A-3E, the load difference between the clock lines CKL corresponding to the first output module 30 can be improved, and thus when the gate drive circuit GM shown in FIGS. 1B-1F is applied to the display panel, the difference between the odd row brightness and the even row brightness of the display panel can be improved.

[0275] It should be noted that when the load capacitor CL is added to improve the load difference between the clock lines CKL corresponding to the first output module 30, the two electrodes of the load capacitor CL can be prepared synchronously with the pixel drive circuit.

[0276] FIG. 11 is a structural schematic diagram of a driving circuit layer provided by an embodiment of the present application. The display panel includes a substrate 100 and a driving circuit layer on the substrate 100, and the driving circuit layer includes the pixel driving circuit described above. Optionally, the substrate includes glass, polyimide, etc.

[0277] The driving circuit layer includes a first semiconductor layer 1011, a first metal layer 1021, a second metal layer 1022, a second semiconductor layer 1012, a third metal layer 1023, and a fourth metal layer 1024.

[0278] The first semiconductor layer 1011 is on the substrate 100, and the first semiconductor layer 1011 includes an active pattern 1011a of the driving transistor Tdr. Optionally, the first semiconductor layer 1011 includes silicon semiconductor material.

[0279] The first metal layer 1021 is on the first semiconductor layer 1011, and the first metal layer 1021 includes a first electrode 1021a arranged corresponding to the active pattern 1011a of the driving transistor Tdr.

[0280] The second metal layer 1022 is on the first metal layer 1021, and the second metal layer 1022 includes a second electrode 1022a and a first gate electrode 1022b, the second electrode 1022a and the first gate electrode 1022b are arranged in a spaced manner, and the second electrode 1022a is arranged corresponding to the first electrode 1021a.

[0281] The second semiconductor layer 1012 is on the second metal layer 1022, and the second semiconductor layer 1012 includes an active pattern 1012a of the compensation transistor Tc or the reset transistor Tr, and the active pattern 1012a of the compensation transistor Tc or the reset transistor Tr is arranged corresponding to the first gate electrode 1022b. Optionally, the second semiconductor layer 1012 includes oxide semiconductor, etc. The oxide semiconductor includes indium gallium zinc oxide, etc.

[0282] The third metal layer 1023 is on the second semiconductor layer 1012, and the third metal layer 1023 includes a second gate electrode 1023a arranged corresponding to the first gate electrode 1022b.

[0283] The fourth metal layer 1024 is on the third metal layer 1023, and the fourth metal layer 1024 includes a first connecting electrode 1024a, a second connecting electrode 1024b, a third connecting electrode 1024c, and a fourth connecting electrode 1024d. The first connecting electrode 1024a and the second connecting electrode 1024b are electrically connected to the active pattern 1011a of the driving transistor Tdr, and the third connecting electrode 1024c and the fourth connecting electrode 1024d are electrically connected to the active pattern 1022a of the compensation transistor Tc or the reset transistor Tr.

[0284] Optionally, the first metal layer 1021 can include one electrode of the load capacitor CL, and the second metal layer 1022 can include the other electrode of the load capacitor CL.

[0285] In addition, any two or more of the first semiconductor layer 1011, the first metal layer 1021, the second metal layer 1022, the second semiconductor layer 1012, the third metal layer 1023, and the fourth metal layer 1024 can include electrodes of the load capacitor CL. Among them, because the first semiconductor layer 1011 and the first metal layer 1021 correspond to the position of the channel, the second semiconductor layer 1012 and the third metal layer 1023 form a channel, so the two electrodes of the load capacitor CL cannot be formed only by the first semiconductor layer 1011 and the first metal layer 1021, and the two electrodes of the load capacitor CL cannot be formed only by the second semiconductor layer 1012 and the third metal layer 1023.

[0286] It should be noted that any two or more of the first semiconductor layer 1011, the first metal layer 1021, the second metal layer 1022, the second semiconductor layer 1012, the third metal layer 1023, and the fourth metal layer 1024 include electrodes of the load capacitor CL can correspond to the design form as shown in FIG. 12. FIG. 12 is a structure diagram of the load capacitor provided by the embodiment of the application, taking the first metal layer 1021 including one electrode CLa of the load capacitor CL as an example, the second metal layer 1022 and the third metal layer 1023 can simultaneously include the other electrode CLb of the load capacitor CL, and the second metal layer 1022 and the third metal layer 1023 include the other electrode CLb which overlaps the one electrode CLa included by the first metal layer 1021.

[0287] It should be noted that the load capacitor CL can also adopt the design form of a single-layer capacitor. For example, in FIG. 11 and FIG. 12, the first metal layer 1021 includes one electrode of the load capacitor CL, the second metal layer 1022 or the third metal layer 1023 includes the other electrode of the load capacitor CL, and the other electrode overlaps the one electrode included by the first metal layer 1021.

[0288] In addition, the load capacitor CL can be designed in parallel in the vertical direction. For example, the first metal layer 1021 includes a first electrode part, the second metal layer 1022 includes a second electrode part arranged corresponding to the first electrode part, the third metal layer 1023 includes a third electrode part arranged corresponding to the second electrode part, and the first electrode part and the third electrode part are electrically connected, so that the electrodes of the load capacitor CL include the first electrode part, the second electrode part and the third electrode part.

[0289] Please continue to refer to FIG. 11, the driving circuit layer further comprises a first gate insulating layer 1031, a second gate insulating layer 1032, a first interlayer dielectric layer 1041, a third gate insulating layer 1033, a second interlayer dielectric layer 1042, and a first planar layer 105.

[0290] The first gate insulating layer 1031 is located between the first semiconductor layer 1011 and the first metal layer 1021, and the second gate insulating layer 1032 is located between the first metal layer 1021 and the second metal layer 1022. The first interlayer dielectric layer 1041 is located between the second metal layer 1022 and the second semiconductor layer 1012, the third gate insulating layer 1033 is located between the second semiconductor layer 1012 and the third metal layer 1023, the second interlayer dielectric layer 1042 is located between the third metal layer 1023 and the fourth metal layer 1024, and the first planar layer 105 is located on the fourth metal layer 1024.

[0291] The first connecting electrode 1024a and the second connecting electrode 1024b are electrically connected to the active pattern 1011a of the driving transistor Tdr through a via hole provided in the first gate insulating layer 1031, the second gate insulating layer 1032, the first interlayer dielectric layer 1041, the third gate insulating layer 1033, and the second interlayer dielectric layer 1042.

[0292] The third connecting electrode 1024c and the fourth connecting electrode 1024d are electrically connected to the active pattern 1012a of the compensation transistor Tc or the reset transistor Tr through a via hole provided in the third gate insulating layer 1033 and the second interlayer dielectric layer 1042.

[0293] Optionally, at least one of the first gate insulating layer 1031, the second gate insulating layer 1032, the first interlayer dielectric layer 1041, the second interlayer dielectric layer 1042, and the first planar layer 105 comprises at least one of tetraethyl orthosilicate (TEOS), silicon nitride, and silicon oxide. The first metal layer 1021, the second metal layer 1022, the third metal layer 1023, and the fourth metal layer 1024 comprise a low-resistance material such as Al, Ti, Mo, Cu, Ni, or an alloy thereof. The first metal layer 1021, the second metal layer 1022, the third metal layer 1023, and the fourth metal layer 1024 can be multiple layers or a single layer.

[0294] It can be understood that the display panel further comprises a light-emitting device layer and other unshown parts located on the driving circuit layer. The light-emitting device layer can comprise an anode layer, a cathode layer, and a light-emitting layer located between the cathode layer and the anode layer. The anode layer comprises an anode of a light-emitting device, and the anode is electrically connected to the driving circuit layer.

[0295] Fig. 14 is a structural schematic diagram of a display device provided by an embodiment of the present application. The present application also provides a display device comprising any of the above-mentioned gate drive circuits GM or any of the above-mentioned display panels.

[0296] Optionally, the display device comprises a timing controller Tcon configured to provide the required first clock signal and the second clock signal to the gate drive circuit GM, or configured to provide the required first sub-clock signal, the second sub-clock signal and the third sub-clock signal to the gate drive circuit GM.

[0297] Optionally, the display device comprises a source drive chip SIC configured to transmit a data signal to the data line.

[0298] The principles and implementation manners of the present application are described herein by using specific examples, and the above descriptions of the examples are only used to help understand the method of the present application and its core idea; meanwhile, for those skilled in the art, the specific implementation manners and application ranges will be changed according to the idea of the present application, and the above descriptions should not be understood as limiting the present application.

Claims

1. A gate drive circuit, wherein, The gate drive circuit comprises a plurality of gate drive sub-circuits, and each gate drive sub-circuit comprises: a shift register module electrically connected to the first node and comprising a first transistor configured to control a signal transmitted to the first node according to a start signal and a first clock signal received by a control terminal of the first transistor; a self-stabilization module electrically connected to the first node and the second node and comprising a second transistor configured to control a signal transmitted to the second node according to a signal of the first node and maintain a potential of the first node according to a signal of the second node and the first clock signal received by a control terminal of the second transistor; at least two first output modules, each electrically connected to the first node and the second node, and each configured to output a first gate control signal according to a corresponding second clock signal, a signal of the first node and a signal of the second node; wherein the semiconductor layers of the first transistor and the second transistor comprise different semiconductor materials, and the first transistor and the second transistor are configured to be turned on at different times according to the first clock signal; in a first time period, a frequency of the first clock signal is equal to a frequency of the second clock signal, and in a second time period before or after the first time period, the frequency of the first clock signal is greater than the frequency of the second clock signal.

2. The gate drive circuit according to claim 1, wherein The semiconductor layer of one of the first transistor and the second transistor comprises a silicon semiconductor material, and the semiconductor layer of the other of the first transistor and the second transistor comprises an oxide semiconductor material.

3. The gate drive circuit according to claim 1, wherein The gate drive circuit comprises X first output modules and a plurality of clock lines, Y clock lines of the plurality of clock lines are configured to transmit corresponding first clock signals to a plurality of gate drive sub-circuits, and Z clock lines of the plurality of clock lines are configured to transmit corresponding second clock signals to first output modules of the plurality of gate drive sub-circuits. wherein X≥2, Y=2, and Z=2X.

4. The gate drive circuit of claim 3, wherein, The at least two first output modules comprise a first sub-output module and a second sub-output module, the Y clock lines comprise a first sub-line and a second sub-line, and the Z clock lines comprise a first clock line, a second clock line, a third clock line and a fourth clock line. The first clock line is configured to transmit the corresponding second clock signal to the first sub-output module in the 2k+1-level gate driving sub-circuit; the second clock line is configured to transmit the corresponding second clock signal to the second sub-output module in the 2k+1-level gate driving sub-circuit; the third clock line is configured to transmit the corresponding second clock signal to the first sub-output module in the 2k+2-level gate driving sub-circuit; the fourth clock line is configured to transmit the corresponding second clock signal to the second sub-output module in the 2k+2-level gate driving sub-circuit; the first sub-line is configured to transmit the corresponding first clock signal to the shift register module and the self-stabilizing module in the 2k+1-level gate driving sub-circuit, and the second sub-line is configured to transmit the corresponding first clock signal to the shift register module and the self-stabilizing module in the 2k+2-level gate driving sub-circuit; k≥0.

5. The gate drive circuit of claim 1, wherein, The first output module comprises: a first output transistor comprising a control end electrically connected to the first node, a first source-drain end configured to receive the corresponding second clock signal, and a second source-drain end electrically connected to a first output end of the gate driving sub-circuit for outputting the corresponding first gate control signal; a second output transistor comprising a control end electrically connected to the second node, a first source-drain end electrically connected to a second power supply end, and a second source-drain end electrically connected to the second source-drain end of the first output transistor; and a first capacitor connected in series between the control end and the first source-drain end of the first output transistor.

6. The gate drive circuit of claim 1, wherein, The gate driving circuit further comprises a first frequency division control line for transmitting a first frequency division control signal, and the gate driving sub-circuit further comprises: a first frequency division control module electrically connected to the first node, the first frequency division control line and the second node, and electrically connected to at least one first output module through a third node, and configured to control the signal transmission between the first node and the third node according to the signal of the second node and the first frequency division control signal; and a first stabilizing module electrically connected to the second node and the third node, comprising a first maintaining transistor, and configured to maintain the potential of the third node according to the signal of the second node and the first clock signal received by the control end of the first maintaining transistor.

7. The gate drive circuit of claim 1, wherein, The gate driving circuit further comprises a second frequency division control line for transmitting a second frequency division control signal, and the gate driving sub-circuit further comprises: a second output module electrically connected to the first node and configured to output a second gate control signal; and a second frequency division control module electrically connected to the first node and the second node, and electrically connected to the second output module through a fourth node, and configured to control the signal transmission between the first node and the fourth node according to the second frequency division control signal and the signal of the second node.

8. The gate drive circuit of claim 7, wherein, The gate driving sub-circuit comprises: A second stable module is electrically connected to the second node and the fourth node, and includes a second maintaining transistor configured to maintain the potential of the fourth node according to the signal of the second node and the first clock signal received by the control end of the second maintaining transistor.

9. A gate drive circuit, wherein, The gate drive circuit includes a plurality of clock lines and a plurality of gate drive sub-circuits, the plurality of clock lines include first clock lines and second clock lines, the number of gate drive sub-circuits electrically connected to the first clock lines is less than the number of gate drive sub-circuits electrically connected to the second clock lines. The gate drive circuit includes a load capacitor, and the load capacitor is connected in series between the first clock lines and a constant voltage terminal.

10. The gate drive circuit of claim 9, wherein, The gate drive sub-circuit includes: A shift register module is electrically connected to a first node and includes a first transistor configured to control the signal transmitted to the first node according to a start signal and a clock signal received by the control end of the first transistor; A self-stable module is electrically connected to the first node and a second node and includes a second transistor configured to control the signal transmitted to the second node according to the signal of the first node and maintain the potential of the first node according to the signal of the second node and the clock signal received by the control end of the second transistor; At least two first output modules are electrically connected to the first node and the second node, and each first output module is configured to output a first gate control signal according to the clock signal transmitted by the corresponding clock line, the signal of the first node and the signal of the second node.

11. The gate drive circuit of claim 10, wherein, The control end of the first transistor and the control end of the second transistor are configured to receive a first clock signal; the gate drive circuit includes X first output modules, Y clock lines in the plurality of clock lines are configured to transmit corresponding first clock signals to a plurality of gate drive sub-circuits, and the plurality of clock lines are configured to transmit corresponding second clock signals to the first output modules of the plurality of gate drive sub-circuits. X≥2 and Y=2.

12. The gate drive circuit of claim 10, wherein, The at least two first output modules include a first sub-output module and a second sub-output module, and the plurality of clock lines include a first clock line, a second clock line, a third clock line and a fourth clock line. The first clock line is configured to transmit the corresponding second clock signal to the first sub-output module in the gate drive sub-circuit of the 2k+1 level, and is configured to transmit the corresponding first clock signal to the shift register module and the self-stabilizing module in the gate drive sub-circuit of the 2k+2 level; the second clock line is configured to transmit the corresponding second clock signal to the second sub-output module in the gate drive sub-circuit of the 2k+1 level; the third clock line is configured to transmit the corresponding second clock signal to the first sub-output module in the gate drive sub-circuit of the 2k+2 level, and is configured to transmit the corresponding first clock signal to the shift register module and the self-stabilizing module in the gate drive sub-circuit of the 2k+1 level; the fourth clock line is configured to transmit the corresponding second clock signal to the second sub-output module in the gate drive sub-circuit of the 2k+2 level; k≥0. The first clock line is configured to transmit the corresponding second clock signal to the first sub-output module in the gate drive sub-circuit of the 2k+1 level, and is configured to transmit the corresponding first clock signal to the shift register module and the self-stabilizing module in the gate drive sub-circuit of the 2k+2 level; the second clock line is configured to transmit the corresponding second clock signal to the second sub-output module in the gate drive sub-circuit of the 2k+1 level; the third clock line is configured to transmit the corresponding second clock signal to the first sub-output module in the gate drive sub-circuit of the 2k+2 level, and is configured to transmit the corresponding first clock signal to the shift register module and the self-stabilizing module in the gate drive sub-circuit of the 2k+1 level; the fourth clock line is configured to transmit the corresponding second clock signal to the second sub-output module in the gate drive sub-circuit of the 2k+2 level; k≥0.

13. The gate drive circuit of claim 10, wherein, The control end of the first transistor is configured to receive a first sub-clock signal, and the control end of the second transistor is configured to receive a second sub-clock signal; the gate drive circuit includes X first output modules, Y clock lines in the plurality of clock lines are configured to transmit the corresponding first sub-clock signal to the shift register module of the gate drive sub-circuit of the plurality of levels, Z clock lines in the plurality of clock lines are configured to transmit the corresponding third sub-clock signal to the first output module of the gate drive sub-circuit of the plurality of levels, and U clock lines in the Z clock lines are configured to transmit the corresponding second sub-clock signal to the self-stabilizing module of the gate drive sub-circuit of the plurality of levels. X≥2, Z=2X, Z>U, and Y=U.

14. The gate drive circuit of claim 13, wherein, The at least two first output modules include a first sub-output module and a second sub-output module; the Y clock lines include a first sub-line and a second sub-line, and the Z clock lines include a first clock line, a second clock line, a third clock line, and a fourth clock line. The first clock line is configured to transmit the corresponding third sub-clock signal to the first sub-output module in the gate drive sub-circuit of the 2k+1 level and transmit the corresponding second sub-clock signal to the self-stabilization module in the gate drive sub-circuit of the 2k+2 level; the second clock line is configured to transmit the corresponding third sub-clock signal to the second sub-output module in the gate drive sub-circuit of the 2k+1 level; the third clock line is configured to transmit the corresponding second sub-clock signal to the self-stabilization module in the gate drive sub-circuit of the 2k+1 level and transmit the corresponding third sub-clock signal to the first sub-output module in the gate drive sub-circuit of the 2k+2 level; the fourth clock line is configured to transmit the corresponding third sub-clock signal to the second sub-output module in the gate drive sub-circuit of the 2k+2 level; the first sub-line is configured to transmit the corresponding first sub-clock signal to the shift register module in the gate drive sub-circuit of the 2k+1 level, and the second sub-line is configured to transmit the corresponding first sub-clock signal to the shift register module in the gate drive sub-circuit of the 2k+2 level; k≥0. The first type of clock line includes the second clock line and the fourth clock line, and the load capacitor is arranged between the second clock line and the constant voltage terminal, and the load capacitor is arranged between the fourth clock line and the constant voltage terminal.

15. The gate drive circuit of claim 13, wherein, The frequency of the first sub-clock signal is greater than or equal to the frequency of the second sub-clock signal, and when the second sub-clock signal has an invalid pulse, the starting time of the invalid pulse of the second sub-clock signal is the same as the starting time of the valid pulse of the first sub-clock signal.

16. The gate drive circuit of claim 10, wherein, The gate drive circuit further comprises a first frequency division control line for transmitting a first frequency division control signal, and the gate drive sub-circuit further comprises: a first frequency division control module electrically connected to the first node, the first frequency division control line and the second node, and electrically connected to at least one first output module through a third node, and configured to control the signal transmission between the first node and the third node according to the signal of the second node and the first frequency division control signal; and a first stabilization module electrically connected to the second node and the third node, comprising a first maintenance transistor, configured to maintain the potential of the third node according to the signal of the second node and the clock signal received by the control end of the first maintenance transistor; The control end of the first maintenance transistor is electrically connected to the control end of the second transistor.

17. The gate drive circuit of claim 10, wherein, The gate drive circuit further comprises a second frequency division control line for transmitting a second frequency division control signal, and the gate drive sub-circuit further comprises: a second output module electrically connected to the first node and configured to output a second gate control signal; and A second frequency division control module is electrically connected with the first node and the second node, and is electrically connected with the second output module through a fourth node, and is configured to control signal transmission between the first node and the fourth node according to the second frequency division control signal and a signal of the second node.

18. The gate drive circuit of claim 17, wherein, The gate drive sub-circuit comprises: A second stabilizing module is electrically connected with the second node and the fourth node, and comprises a second maintaining transistor, and is configured to maintain the potential of the fourth node according to a signal of the second node and the clock signal received by a control end of the second maintaining transistor. The control end of the second maintaining transistor is electrically connected with the control end of the second transistor.

19. A display panel, wherein, The display panel comprises a display area and a first area and a second area located on opposite sides of the display area; the display panel comprises two gate drive circuits.

20. The display panel of claim 19, wherein, The display panel comprises a display area and a first area and a second area located on opposite sides of the display area; the display panel comprises two gate drive circuits. A plurality of sub-pixels are electrically connected with the gate drive circuit, and the gate drive circuit is configured to output the first gate control signal to the plurality of sub-pixels; A scan driving module is electrically connected with the plurality of sub-pixels, and is configured to generate a plurality of scan signals according to clock signals transmitted by a first multiplexing clock line and a second multiplexing clock line, and output the plurality of scan signals to the plurality of sub-pixels; The first multiplexing clock line and the second multiplexing clock line are electrically connected with the gate drive circuit, and the first multiplexing clock line and the second multiplexing clock line are configured to transmit the first clock signal to a plurality of gate drive sub-circuits.

21. The display panel of claim 20, wherein, The first multiplexing clock line comprises a first sub-multiplexing line, and the second multiplexing clock line comprises a second sub-multiplexing line; The scan driving module comprises an emission driving circuit, the emission driving circuit comprises a plurality of emission driving sub-circuits, and the emission driving sub-circuits are configured to generate light emission control signals according to the clock signals transmitted by the first sub-multiplexing clock line and the second sub-multiplexing clock line; The sub-pixel comprises a light emitting device, a driving transistor, and a light emission control transistor, the light emission control transistor is connected in series with the driving transistor and the light emitting device between a first voltage end and a second voltage end, and a control end of the light emission control transistor is configured to receive the light emission control signal; The plurality of scan signals comprise the light emission control signal.

22. The display panel of claim 21, wherein, The first multiplexing clock line comprises a third sub-multiplexing line, and the second multiplexing clock line comprises a fourth sub-multiplexing line; The scan driving module comprises a scan driving circuit, the scan driving circuit comprises a plurality of scan driving sub-circuits, and the scan driving sub-circuits are configured to generate first scan signals according to the clock signals transmitted by the third sub-multiplexing clock line and the fourth sub-multiplexing clock line; The sub-pixel comprises a first initial transistor, and the first initial transistor is configured to control signal transmission between the light emitting device and a first initial line according to the first scan signal; The plurality of scan signals comprise the first scan signal and the light emission control signal.

23. The display panel of claim 22, wherein, The display panel comprises a display area and a first area and a second area located on opposite sides of the display area; the display panel comprises two gate drive circuits. The first and second sub-multiplex lines are located in the first area and electrically connected to the emission driving circuit and one of the two gate driving circuits located in the first area; and the third and fourth sub-multiplex lines are located in the second area and electrically connected to the scan driving circuit and the other of the two gate driving circuits located in the second area.

Images