A gate driving circuit and a display panel

Abstract

The application discloses a kind of gate drive circuit and display panel, gate drive circuit includes a plurality of sequentially cascaded shift register units, shift register unit includes: first output control module, for according to start signal, the signal of first output end output of next stage shift register unit and the potential of second node, control the signal of first clock signal end access, the signal of third clock signal end access and the first potential transmission to first node;Second output control module is used for according to the potential of first node, the first potential transmission to second node;Second node is connected with second output end, and output module is used for according to the potential of first node, controls the signal of second clock signal end access transmission to first output end, according to the potential of second node, controls the first potential transmission to first output end;Third output control module is used for responding start signal control first potential transmission to second output end.Gate drive circuit can simultaneously output two different types of signals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a gate driving circuit and a display panel. BACKGROUND

[0002] At present, the pixel circuit in the driving backplane of liquid crystal display and electronic paper usually adopts 1T2C mode for driving. The driving signals commonly used in the 1T2C pixel circuit include a gate control signal, a data signal and a power signal. The data signal and the power signal are provided by a chip, and the gate control signal is provided by a gate driving circuit.

[0003] At present, the pixel circuit design in the prior art is simple, and the driving signal is single. Therefore, the existing gate driving circuit can still meet the requirement of the gate control signal required by the pixel circuit. However, for a complex pixel circuit such as a 4T1C or 7T1C pixel circuit of an active-matrix organic light emitting diode (AMOLED), the single signal output by the gate driving circuit cannot meet the design and driving display requirements. SUMMARY

[0004] The present application provides a gate driving circuit and a display panel. The gate driving circuit can output different types of signals, thereby being able to drive various types of pixel circuits and meet different user requirements.

[0005] According to an aspect of the present application, a gate driving circuit is provided, comprising: a plurality of shift register units connected in sequence, wherein each shift register unit comprises a start signal end, a first clock signal end, a second clock signal end, a third clock signal end, a first output end and a second output end, and wherein the first output signal output by the first output end of a previous shift register unit is input to the start signal end of a next shift register unit.

[0006] The shift register unit comprises:

[0007] a first output control module, configured to control the clock signal input to the first clock signal end, the clock signal input to the third clock signal end and the first potential transmitted to the first node according to the start signal, the first output signal output by the first output end of the next shift register unit connected to the current shift register unit and the potential of the second node.

[0008] a second output control module, configured to control the second potential transmitted to the second node and the second output end, and configured to transmit the first potential to the second node and the second output end according to the potential of the first node.

[0009] a first control terminal of the output module is connected with the first node, a second control terminal of the output module is connected with the second node, the second node is connected with a second output terminal of the shift register unit, and the output module is configured to control the first potential to be transmitted to the first output terminal according to a potential of the first node and a potential of the second node and the second output terminal;

[0010] the third output control module is configured to control the first potential to be transmitted to the second output terminal in response to the start signal.

[0011] Optionally, the first output control module comprises:

[0012] a first control unit configured to control the clock signal inputted from the first clock signal terminal to be transmitted to the first node according to a start signal inputted from the start signal terminal;

[0013] a second control unit configured to control the clock signal inputted from the third clock signal terminal to be transmitted to the first node according to a first output signal outputted from a first output terminal of a next stage shift register unit connected with the current stage shift register unit;

[0014] a third control unit configured to control the first potential to be transmitted to the first node according to a potential of the second node.

[0015] Optionally, the first control unit comprises a first transistor, a first electrode of the first transistor is connected with the first clock signal terminal, a second electrode of the first transistor is connected with the first node, and a gate electrode of the first transistor is connected with the start signal terminal;

[0016] the second control unit comprises a second transistor, a first electrode of the second transistor is connected with the third clock signal terminal, a second electrode of the second transistor is connected with the first node, and a gate electrode of the second transistor is connected with the first output signal outputted from the first output terminal of the next stage shift register unit connected with the current stage shift register unit;

[0017] the third control unit comprises a third transistor, a first electrode of the third transistor is connected with the first potential, a second electrode of the third transistor is connected with the first node N1, and a gate electrode of the third transistor is connected with the second node.

[0018] Optionally, the second output control module comprises:

[0019] a fourth control unit configured to control the first potential to be transmitted to the second node and the second output terminal, respectively, according to the potential of the first node;

[0020] a fifth control unit configured to transmit the second potential to the second node and the second output terminal, respectively.

[0021] Optionally, the fourth control unit comprises a fourth transistor, a first electrode of the fourth transistor being connected to the first potential, a second electrode of the fourth transistor being connected to the second node, and a gate electrode of the fourth transistor being connected to the first node;

[0022] the fifth control unit comprises a fifth transistor, a first electrode of the fifth transistor being connected to a gate electrode of the fifth transistor, a second electrode of the fifth transistor being connected to the second node, and a gate electrode of the fifth transistor being connected to the second potential;

[0023] a width-length ratio of the fourth transistor is greater than a width-length ratio of the fifth transistor.

[0024] Optionally, the third output control module comprises a sixth transistor, a first electrode of the sixth transistor being connected to the first potential, a second electrode of the sixth transistor being connected to the second output terminal, and a gate electrode of the sixth transistor being connected to the start signal terminal.

[0025] Optionally, the output module comprises:

[0026] a first output unit configured to control a clock signal inputted by the second clock signal terminal to be transmitted to the first output terminal according to the potential of the first node;

[0027] a second output unit configured to control the first potential to be transmitted to the first output terminal according to the potential of the second node;

[0028] the first output unit comprises a seventh transistor and a first capacitor, a first electrode of the seventh transistor being connected to the second clock signal terminal, a second electrode of the seventh transistor being connected to the first output terminal, and a gate electrode of the seventh transistor being connected to the first node; a first end of the first capacitor being connected to the gate electrode of the seventh transistor, and a second end of the first capacitor being connected to the first output terminal;

[0029] the second output unit comprises an eighth transistor, a first electrode of the eighth transistor being connected to the first potential, a second electrode of the eighth transistor being connected to the first output terminal, and a gate electrode of the eighth transistor being connected to the second node.

[0030] Optionally, the shift register unit further comprises a fourth output control module, configured to control the first potential to be transmitted to the first output end of the current stage shift register unit according to a first output signal output by the first output end of the next stage shift register unit connected to the current stage shift register unit.

[0031] The fourth output control module comprises a ninth transistor, a first pole of the ninth transistor being connected to the first potential, a second pole of the ninth transistor being connected to the first output end of the current stage shift register unit, and a gate of the ninth transistor being connected to the first output signal output by the first output end of the next stage shift register unit connected to the current stage shift register unit.

[0032] Optionally, the first output signal output by the first output end is a scanning signal, and the second output signal output by the second output end is a light-emitting control signal.

[0033] According to another aspect of the present application, a display panel is provided, comprising two above-mentioned gate driving circuits, a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line; wherein each odd stage shift register unit is included in one of the gate driving circuits, and each even stage shift register unit is included in the other of the gate driving circuits; the pulse transmitted on the first clock signal line, the pulse transmitted on the second clock signal line, the pulse transmitted on the third clock signal line and the pulse transmitted on the fourth clock signal line are sequentially delayed; the pulse of the start signal input to the start signal end of the first stage shift register unit and the pulse of the start signal input to the start signal end of the second stage shift register unit are sequentially delayed.

[0034] The first clock signal end of the (4k+1)th stage shift register unit is connected to the first clock signal line, the second clock signal end is connected to the second clock signal line, and the third clock signal end is connected to the third clock signal line.

[0035] The first clock signal end of the (4k+2)th stage shift register unit is connected to the second clock signal line, the second clock signal end is connected to the third clock signal line, and the third clock signal end is connected to the fourth clock signal line.

[0036] The first clock signal end of the (4k+3)th stage shift register unit is connected to the third clock signal line, the second clock signal end is connected to the fourth clock signal line, and the third clock signal end is connected to the first clock signal line.

[0037] The first clock signal end of the (4k+4)th stage shift register unit is connected to the fourth clock signal line, the second clock signal end is connected to the first clock signal line, and the third clock signal end is connected to the second clock signal line; k is an integer greater than or equal to 0.

[0038] The gate drive circuit in the embodiment can generate two kinds of output signals simultaneously through three output control modules and one output module, so as to meet the requirement of driving the pixel drive circuit connected with the shift register unit by using different types of signals. The shift register unit is redesigned, and the gate drive circuit has the ability to drive more complex pixel drive circuit under the condition of meeting the requirement of driving display of the existing LCD and electronic paper, so that the gate drive circuit has the function of driving various designs and display, and meets the requirement of different customers.

[0039] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0041] Figure 1 A structural schematic diagram of a shift register unit in a gate drive circuit provided by an embodiment of the present application is provided.

[0042] Figure 2 A structural schematic diagram of a shift register unit in another gate drive circuit provided by an embodiment of the present application is provided.

[0043] Figure 3 A circuit diagram of a shift register unit in another gate drive circuit provided by an embodiment of the present application is provided.

[0044] Figure 4 A driving timing diagram of a shift register unit in a gate drive circuit provided by an embodiment of the present application is provided.

[0045] Figure 5 A conduction state schematic diagram of a shift register unit in a gate drive circuit provided by an embodiment of the present application in the first stage is provided.

[0046] Figure 6 A conduction state schematic diagram of a shift register unit in a gate drive circuit provided by an embodiment of the present application in the second stage is provided.

[0047] Figure 7 A conduction state schematic diagram of a shift register unit in a gate drive circuit provided by an embodiment of the present application in the third stage is provided.

[0048] Figure 8 A schematic diagram of a conduction state of a shift register unit in a fourth stage in a gate drive circuit provided by an embodiment of the present application is shown in FIG. 7;

[0049] Figure 9 A structural schematic diagram of an N-type pixel drive circuit provided by an embodiment of the present application is shown in FIG. 8;

[0050] Figure 10 A structural schematic diagram of a P-type pixel drive circuit provided by an embodiment of the present application is shown in FIG. 9;

[0051] Figure 11 A structural schematic diagram of a shift register unit in another gate drive circuit provided by an embodiment of the present application is shown in FIG. 10;

[0052] Figure 12 A structural schematic diagram of a display panel provided by an embodiment of the present application is shown in FIG. 11;

[0053] Figure 13 A driving timing diagram of a display panel provided by an embodiment of the present application is shown in FIG. 12. DETAILED DESCRIPTION

[0054] In order to make the personnel in the art better understand the present application scheme, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the personnel in the art without creative labor should belong to the scope of protection of the present application.

[0055] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device that includes a series of steps or units does not have to be limited to only those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0056] Figure 1 A structural schematic diagram of a shift register unit in a gate drive circuit provided by an embodiment of the present application is shown in FIG. 7; Figure 1The gate drive circuit comprises a plurality of shift register units connected in cascade, and each shift register unit comprises a start signal terminal SIN, a first clock signal terminal K1, a second clock signal terminal K2, a third clock signal terminal K3, a first output terminal Gout1 and a second output terminal Gout2. In the two adjacent shift register units connected in cascade, the first output signal output by the first output terminal Gout1 of the former shift register unit is input to the start signal terminal SIN of the latter shift register unit as the start signal.

[0057] The shift register unit comprises:

[0058] The first output control module 10 is configured to control the clock signal input to the first clock signal terminal K1, the clock signal input to the third clock signal terminal K3 and the transmission of the first potential V1 to the first node N1 according to the start signal, the first output signal Gn+2 output by the first output terminal of the next shift register unit connected to the current shift register unit and the potential of the second node N2.

[0059] The second output control module 11 is configured to control the transmission of the second potential V2 to the second node N2 and the second output terminal Gout2 of the shift register unit, and to control the transmission of the first potential V1 to the second node N2 and the second output terminal Gout2 of the shift register unit according to the potential of the first node N1.

[0060] The first control terminal of the output module 12 is connected to the first node N1, the second control terminal of the output module 12 is connected to the second node N2, the second node N2 is connected to the second output terminal Gout2 of the shift register unit, and the output module 12 is configured to control the transmission of the clock signal input to the second clock signal terminal K2 to the first output terminal Gout1 of the shift register unit according to the potential of the first node N1, and to control the transmission of the first potential V1 to the first output terminal Gout1 of the shift register unit according to the potential of the second node N2 and the potential of the second output terminal Gout2 of the shift register unit.

[0061] The third output control module 13 is configured to control the transmission of the first potential V1 to the second output terminal Gout2 in response to the start signal.

[0062] The first output control module 10 comprises three control terminals and three input terminals. The first control terminal is connected to the start signal at the start signal terminal SIN, the second control terminal is connected to the first output signal Gn+2 outputted by the first output terminal Goutl of the next stage shift register unit, and the third control terminal is connected to the second node N2. The first input terminal is connected to the first clock signal terminal Kl, the second input terminal is connected to the third clock signal terminal K3, and the third input terminal is connected to the first potential VI. The first output control module 10 is used to control the clock signal inputted by the first clock signal terminal Kl, the clock signal inputted by the third clock signal terminal K3, and the transmission of the first potential VI to the first node Nl according to the start signal, the first output signal Gn+2 outputted by the first output terminal of the next stage shift register unit connected to the current stage shift register unit, and the potential of the second node N2. It can be indicated that when the start signal is a valid potential signal, the first output control module 10 transmits the clock signal inputted by the first clock signal terminal Kl to the first node Nl. When the first output signal Gn+2 outputted by the first output terminal of the next stage shift register unit is a valid potential, the first output control module 10 is used to transmit the clock signal inputted by the third clock signal terminal K3 to the first node Nl. When the second node N2 is a valid potential, the first output control module 10 is used to transmit the first potential VI to the first node Nl, that is, the first output control module 10 is used to control the potential of the first node Nl. For example, the first output control module 10 comprises a plurality of transistors, and the valid potential of a signal is the potential for controlling the transistor connected to the signal to be turned on. Taking the start signal as an example, the valid potential of the start signal is the potential for controlling the transistor connected to the start signal terminal SIN to be turned on.

[0063] The second output control module 11 is used to transmit the second potential V2 to the second node N2 and the second output terminal Gout2 of the shift register unit. The second output control module 11 comprises one control terminal and two output terminals. The control terminal is connected to the first node Nl, and one of the two output terminals is respectively connected to the second node N2 and the second output terminal Gout2 of the shift register unit, and the other is also respectively connected to the second node N2 and the second output terminal Gout2 of the shift register unit. The second output control module 11 is used to transmit the first potential VI to the second node N2 and the second output terminal Gout2 of the shift register unit according to the potential of the first node Nl. It can be indicated that when the potential of the first node Nl is a valid potential, the second output control module 11 is used to transmit the first potential VI to the second node N2 and the second output terminal Gout2 of the shift register unit.

[0064] The output module 12 is configured to transmit the clock signal inputted by the second clock signal terminal K2 to the first output terminal Gout1 of the shift register unit according to the potential of the first node N1. In other words, when the potential of the first node N1 is a valid potential, the output module 12 is configured to transmit the clock signal inputted by the second clock signal terminal K2 to the first output terminal Gout1 of the shift register unit. The output module 12 is configured to transmit the first potential V1 to the first output terminal Gout1 according to the potential of the second node N2 and the potential of the second output terminal Gout2 of the shift register unit. In other words, when the potential of the second node N2 or the potential of the second output terminal Gout2 is a valid potential, the output module 12 is configured to transmit the first potential V1 to the first output terminal Gout1 of the shift register unit.

[0065] The third output control module 13 includes a control terminal connected to the start signal terminal SIN. The third output control module 13 is configured to transmit the first potential V1 to the second output terminal Gout2 of the shift register unit and the second node N2 in response to the start signal inputted by the start signal terminal SIN. In other words, when the start signal is a valid potential, the third output control module 13 is configured to transmit the first potential V1 to the second output terminal Gout2 and the second node N2. In summary, the potential of the second output terminal Gout2 of the shift register unit is controlled by the third output control module 13 and the second output control module 11.

[0066] In the embodiment, the gate drive circuit can generate two kinds of output signals simultaneously through the three output control modules and the output module, so as to meet the requirement of driving the pixel drive circuit connected to the shift register unit by using different types of signals. The shift register unit is redesigned, and the gate drive circuit has the ability to drive more complex pixel drive circuits while meeting the requirements of the existing LCD and electronic paper display driving, so that the gate drive circuit has the function of driving various designs and displays, and meets the requirements of different customers.

[0067] On the basis of the above embodiment, Figure 2 Another structure diagram of the shift register unit in the gate drive circuit is provided in the embodiment of the present application, as shown in Figure 1 and Figure 2 Optionally, the first output control module 10 includes:

[0068] The first control unit 101 is configured to transmit the clock signal inputted by the first clock signal terminal K1 to the first node N1 according to the start signal inputted by the start signal terminal SIN.

[0069] The second control unit 102 is configured to control the clock signal inputted from the third clock signal terminal K3 to be transmitted to the first node N1 according to the first output signal Gn+2 outputted from the first output terminal of the next stage shift register unit connected to the current stage shift register unit;

[0070] The third control unit 103 is configured to control the first potential V1 to be transmitted to the first node N1 according to the potentials of the second node N2 and the second output terminal Gout2.

[0071] The first control unit 101 is a switch unit, which is turned on to connect the first clock signal terminal K1 to the first node N1 to transmit the clock signal inputted from the first clock signal terminal K1 to the first node N1 in response to the active potential of the start signal inputted from the start signal terminal SIN, and is turned off to disconnect the first clock signal terminal K1 from the first node N1 in response to the inactive potential of the start signal inputted from the start signal terminal SIN. The second control unit 102 is a switch unit, which is turned on to connect the third clock signal terminal K3 to the first node N1 in response to the active potential of the first output signal Gn+2 outputted from the first output terminal of the next stage shift register unit connected to the current stage shift register unit, and is turned off to disconnect the third clock signal terminal K3 from the first node N1 in response to the inactive potential of the first output signal Gn+2 outputted from the first output terminal of the next stage shift register unit connected to the current stage shift register unit. The third control unit 103 is a switch unit, which is turned on to transmit the first potential V1 to the first node N1 in response to the active potential of the second node N2, and is turned off to disconnect the first potential V1 from the first node N1 in response to the inactive potential of the second node N2. The first output control module 10 only includes three switch units, and thus has a simple structure and is easy to implement.

[0072] With reference to the first output control module 10, Figure 1 and Figure 2 Optionally, the second output control module 11 includes:

[0073] The fourth control unit 111 is configured to control the first potential V1 to be transmitted to the second node N2 and the second output terminal Gout2 of the shift register unit respectively according to the potential of the first node N1.

[0074] The fifth control unit 112 is configured to transmit the second potential V2 to the second node N2 and the second output terminal Gout2 of the shift register unit respectively.

[0075] The fourth control unit 111 is a switch unit, which is turned on in response to the valid potential of the first node N1, and transmits the first potential V1 to the second node N2 and the second output end Gout2 of the shift register unit respectively. The fifth control unit 112 can be a unidirectional conducting unit or a normally open switch unit, which is used for transmitting the second potential V2 to the second node N2 and the second output end Gout2 of the shift register unit. The second output control module 11 only includes two units, which is simple in structure and easy to implement.

[0076] The third output control module 13 is a switch module, which is turned on in response to the valid potential of the start signal end SIN, and transmits the first potential V1 to the second node N2 and the second output end Gout2 of the shift register unit respectively, and is turned off in response to the invalid potential of the start signal end SIN, and cuts off the connection between the first potential V1 and the second node N2 and the second output end Gout2 of the shift register unit.

[0077] With reference to the above Figure 1 and Figure 2 Optionally, the output module 12 includes:

[0078] The first output unit 121 is used for controlling the transmission of the clock signal accessed by the second clock signal end K2 to the first output end Gout1 of the shift register unit according to the potential of the first node N1.

[0079] The second output unit 122 is used for controlling the transmission of the first potential V1 to the first output end Gout1 of the shift register unit according to the potential of the second node N2.

[0080] The first output unit 121 is a switch unit, which is turned on in response to the valid potential of the first node N1, and is used for connecting the second clock signal end K2 and the first output end Gout1, and is turned off in response to the invalid potential of the first node N1, and is used for cutting off the connection between the second clock signal end K2 and the first output end Gout1. The second output unit 122 is a switch unit, which is turned on in response to the valid potential of the second node N2, and is used for transmitting the first potential V1 to the first output end Gout1, and is turned off in response to the invalid potential of the second node N2, and is used for cutting off the connection between the first potential V1 and the first output end Gout1. The output module includes two switch units, which is simple in structure and easy to implement.

[0081] On the basis of the above embodiments, the embodiment of the present application provides a specific circuit of a shift register unit in a gate drive circuit, Figure 3 Another circuit diagram of a shift register unit in a gate drive circuit is provided for the embodiment of the present application, with reference to Figure 2 and Figure 3Optionally, the first control unit 101 comprises a first transistor T1, a first electrode of the first transistor T1 is connected with the first clock signal terminal K1, a second electrode of the first transistor T1 is connected with the first node N1, and a gate of the first transistor T1 is connected with the start signal terminal SIN;

[0082] The second control unit 102 comprises a second transistor T2, a first electrode of the second transistor T2 is connected with the third clock signal terminal K3, a second electrode of the second transistor T2 is connected with the first node N1, and a gate of the second transistor T2 is connected with a first output signal Gn+2 outputted by a first output terminal of a next stage shift register unit connected with the current stage shift register unit;

[0083] The third control unit 103 comprises a third transistor T3, a first electrode of the third transistor T3 is connected with the first potential V1, a second electrode of the third transistor T3 is connected with the first node N1, and a gate of the third transistor T3 is connected with the second node N2.

[0084] The first transistor T1, the second transistor T2 and the third transistor T3 can be both N-type transistors and P-type transistors. The N-type transistor is turned on in response to a high level of the gate and is turned off in response to a low level of the gate, and the P-type transistor is turned on in response to a low level of the gate and is turned off in response to a high level of the gate.

[0085] The fourth control unit 111 comprises a fourth transistor T4, a first electrode of the fourth transistor T4 is connected with the first potential V1, a second electrode of the fourth transistor T4 is connected with the second node N2 and the second output terminal Gout2 of the shift register unit respectively, and a gate of the fourth transistor T4 is connected with the first node N1.

[0086] The fifth control unit 112 comprises a fifth transistor T5, a first electrode of the fifth transistor T5 is connected with a gate of the fifth transistor T5, a second electrode of the fifth transistor T5 is connected with the second node N2 and the second output terminal Gout2 of the shift register unit respectively, and the gate of the fifth transistor T5 is connected with the second potential V2.

[0087] The width-length ratio of the fourth transistor T4 is greater than the width-length ratio of the fifth transistor T5.

[0088] The fourth transistor T4 and the fifth transistor T5 can be both N-type transistors and P-type transistors. The fifth transistor T5 is connected in a diode form and is used for transmitting the second potential V2 to the second node N2 and the second output terminal Gout2 of the shift register unit. The width-length ratio of the fourth transistor T4 is greater than the width-length ratio of the fifth transistor T5, so that the transmission voltage capacity of the fourth transistor T4 is greater than the transmission voltage capacity of the fifth transistor T5, and the first potential V1 transmitted by the fourth transistor T4 is dominant when the fourth transistor T4 and the fifth transistor T5 are turned on at the same time.

[0089] The third output control module 13 comprises a sixth transistor T6, the first electrode of the sixth transistor T6 is connected to the first potential V1, the second electrode of the sixth transistor T6 is connected to the second output end Gout2 of the shift register unit, and the gate of the sixth transistor T6 is connected to the start signal end SIN. The sixth transistor T6 can be an N-type transistor or a P-type transistor. The third output control module 13 only comprises one transistor, and the structure is simple and easy to realize.

[0090] The first output unit 121 comprises a seventh transistor T7 and a first capacitor C1. The first electrode of the seventh transistor T7 is connected to the second clock signal end K2, the second electrode of the seventh transistor T7 is connected to the first output end Gout1 of the shift register unit, and the gate of the seventh transistor T7 is connected to the first node N1. The first end of the first capacitor C1 is connected to the gate of the seventh transistor T7, and the second end of the first capacitor C1 is connected to the first output end Gout1 of the shift register unit.

[0091] The second output unit 122 comprises an eighth transistor T8. The first electrode of the eighth transistor T8 is connected to the first potential V1, the second electrode of the eighth transistor T8 is connected to the first output end Gout1, and the gate of the eighth transistor T8 is connected to the second node N2 and the second output end Gout2 of the gate drive circuit.

[0092] The eighth transistor T8 and the seventh transistor T7 can be N-type transistors or P-type transistors.

[0093] The eight transistors in the shift register unit can all be P-type transistors. Correspondingly, the first potential V1 is high, the second potential V2 is low, and the corresponding shift register unit is suitable for driving a P-type pixel drive circuit. Alternatively, the eight transistors in the shift register unit can all be N-type transistors. Correspondingly, the first potential V1 is low, the second potential V2 is high, and the corresponding shift register unit is suitable for driving an N-type pixel drive circuit. In the present embodiment, the first potential V1 is low, the second potential V2 is high, and the shift register unit drives an N-type pixel drive circuit as an example to illustrate the working process of the shift register unit. Figure 4 A driving timing diagram of a shift register unit in a gate drive circuit provided by the embodiment of the present application is shown in the following table, Figure 4 The timing diagram shown can be used to drive Figure 2 or Figure 3The shift register unit shown in the embodiment is an exemplary output shift register unit, in which each transistor is an N-type transistor, the first potential V1 is a low level, the second potential V2 is a high level, and the absolute values of the first potential V1 and the second potential V2 are equal. The working process of the shift register unit includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4 in sequence, and the working process of each stage is as follows:

[0094] Figure 5 Fig. 1 is a schematic diagram of the conduction state of the shift register unit in the first stage of the gate drive circuit according to an embodiment of the present application, in which the “X” mark indicates that the transistor is turned off, and the reference Figure 2-5 In the first stage t1, the start signal input by the start signal end SIN is a high level, the first transistor T1 (the first control unit 101) is controlled to be turned on, the high level input by the first clock signal end K1 is written to the first node N1, the pre-charging of the seventh transistor T7 (the first output unit 121) is completed, the sixth transistor T6 (the third output control module 13) is controlled to be turned on, and the first potential V1 is written to the second output end Gout2 of the shift register unit. The high level of the first node N1 controls the fourth transistor T4 (the fourth control unit 111) to be turned on, and the first potential V1 is written to the second node N2. Although the fifth transistor T5 (the fifth control unit 112) is turned on to write the second potential V2 to the second node N2, the writing voltage capacity of the fourth transistor T4 is greater than that of the fifth transistor T5, and therefore the second node N2 is at a low level. The eighth transistor T8 (the second output unit 122) is turned off in response to the low level of the second node N2. The third transistor T3 (the third control unit 103) is turned off in response to the low level of the second node N2. The first output signal Gn+2 output by the first output end of the next stage shift register unit connected to the current stage shift register unit is at a low level, and the second transistor T2 (the second control unit 102) is controlled to be turned off. Therefore, in the first stage t1, the first output end Gout1 of the current stage shift register unit maintains the low level output in the last stage of the previous frame, and the second output end Gout21 outputs a low level.

[0095] Figure 6 Fig. 2 is a schematic diagram of the conduction state of the shift register unit in the second stage of the gate drive circuit according to an embodiment of the present application, for reference Figure 2-4 and Figure 6 In the second stage t2, the start signal input by the start signal end SIN is a low level, and the first transistor T1 (the first control unit 101) and the sixth transistor T6 (the third output control module 13) are controlled to be turned off. The first node N1 is at a high level, the fourth transistor T4 (the fourth control unit 111) is turned on in response to the high level of the first node N1, the first potential V1 is written to the second node N2 and the second output end Gout2 of the shift register unit.

[0096] The third transistor T3 (the third control unit 103) is turned off in response to a low level of the second node N2.

[0097] The eighth transistor T8 (the second output unit 122) is turned off in response to a low level of the second node N2. The first output signal Gn+2 outputted by the first output end of the next stage shift register unit connected to the current stage shift register unit is low, which controls the second transistor T2 (the second control unit 102) to be turned off. The seventh transistor T7 (the first output unit 121) is turned on in response to a high level of the first node N1, so as to transmit the high level inputted by the second clock signal end K2 to the first output end Gout1 of the current stage shift register unit. When the second clock signal end K2 is switched from the first potential V1 to the second potential V2, the first end of the first capacitor C1, i.e. the first node N1, is also lifted to the same height of potential due to the capacitor characteristic, so that the potential of the first node N1 is lifted to a potential greater than (2*V2) by the bootstrap action of the first capacitor C1. The potential of the first node N1 is lifted, so that the fourth transistor T4 is more open, and the first potential V1 is more fully written to the second output end Gout2 of the current stage shift register unit, so that the potential of the second output end Gout2 is lower than that in the first stage t1.

[0098] Figure 7 A conductive state diagram of the shift register unit in the third stage in a gate drive circuit provided by the embodiment of the present application is shown in FIG. 6. Figure 2-4 and Figure 7In the third stage t3, the signal inputted into the start signal terminal SIN is low, and the first transistor T1 (the first control unit 101) and the sixth transistor T6 (the third output control module 13) are controlled to be turned off. The first output signal Gn+2 outputted from the first output terminal of the next stage shift register unit connected to the current stage shift register unit is high, and the second transistor T2 (the second control unit 102) is controlled to be turned on, so as to write the high level inputted from the third clock signal terminal K3 into the first node N1. The fourth transistor T4 (the fourth control unit 111) is turned on in response to the high level of the first node N1, so as to write the first potential V1 into the second node N2 and the second output terminal Gout2 of the shift register unit. The third transistor T3 (the third control unit 103) and the eighth transistor T8 (the second output unit 122) are turned off in response to the low level of the second node N2. The seventh transistor T7 (the first output unit 121) is turned on in response to the high level of the first node N1, so as to transmit the low level inputted from the second clock signal terminal K2 to the first output terminal Gout1 of the current stage shift register unit. Wherein, the potential of the first node N1 is decreased from the potential greater than (2*V2) in the second stage t2 to the potential V2. After the potential of the first node N1 is decreased, the opening degree of the fourth transistor T4 is decreased, and thus the potential of the second output terminal Gout2 of the current stage shift register unit is increased, but is still low after the increase.

[0099] Figure 8 A schematic diagram of the conduction state of the shift register unit in the gate drive circuit in the fourth stage is provided for the embodiment of the present application, referring to Figure 2-4 、 Figure 8 In the fourth stage t4, the signal inputted into the start signal terminal SIN is low, and the first transistor T1 (the first control unit 101) and the sixth transistor T6 (the third output control module 13) are controlled to be turned off. The first output signal Gn+2 outputted from the first output terminal of the next stage shift register unit connected to the current stage shift register unit is high, and the second transistor T2 (the second control unit 102) is controlled to be turned on, so as to write the low level inputted from the third clock signal terminal K3 into the first node N1. The fourth transistor T4 (the fourth control unit 111) is turned off in response to the low level of the first node N1. The fifth transistor T5 (the fifth control unit 112) is turned on to write the second potential V2 into the second node N2. The eighth transistor T8 (the second output unit 122) is turned on in response to the high level of the second node N2, so as to transmit the first potential V1 to the first output terminal Gout1 of the current stage shift register unit. The third transistor T3 (the third control unit 103) is turned on in response to the high level of the second node N2, so as to transmit the first potential V1 to the first node N1. Thus, in the fourth stage t4, the first output terminal Gout1 of the current shift register unit outputs low level, and the second output terminal Gout2 outputs high level.

[0100] In summary, the shift register unit can output two types of signals as shown in the first output end Gout1 and the second output end Gout2 simultaneously to meet the requirement of driving multiple types of signals in the pixel driving circuit. Figure 4 In summary, the shift register unit can output two types of signals as shown in the first output end Gout1 and the second output end Gout2 simultaneously to meet the requirement of driving multiple types of signals in the pixel driving circuit.

[0101] The display panel further comprises a plurality of sub-pixels and pixel driving circuits connected to the sub-pixels in addition to the gate driving circuit, and the pixel driving circuits are used to drive the sub-pixels to emit light. In the present embodiment, one shift register unit is connected to the pixel driving circuits in one row of sub-pixels to provide the pixel driving circuits with gate control signals such as scanning signals and light-emitting control signals. Figure 9 A structural diagram of an N-type pixel driving circuit provided by an embodiment of the present application is shown in FIG. 4. Figure 9The pixel driving circuit comprises a driving transistor M1, a data writing transistor M2, a light emitting control transistor M3, an initialization transistor M4 and a storage capacitor, each of which is an N-type transistor. The storage capacitor Cst is connected between the gate and the second electrode of the driving transistor T1. The light emitting device LD, the light emitting control transistor M3 and the driving transistor M1 are connected in series between the first power supply Elvdd and the second power supply Elvss, wherein the voltage of the first power supply Elvdd is greater than the voltage of the second power supply Elvss. The data writing transistor M2 is connected between the data line Data and the gate of the driving transistor M1, and is used for writing the data voltage into the driving transistor M1 in response to the active potential of the first scanning signal S1. The initialization transistor M4 is connected between the first electrode of the driving transistor M1 and the initialization signal line Vref, and is used for writing the initialization voltage into the first electrode of the driving transistor in response to the active potential of the second scanning signal S2. The light emitting control transistor M3 is used for turning on in the light emitting stage in response to the active potential of the light emitting control signal EM, so that the driving current generated by the driving transistor M1 according to the data voltage can drive the light emitting device LD to emit light. The first output signal output by the first output end of the shift register unit is a scanning signal such as the first scanning signal S1 or the second scanning signal S2, wherein the first scanning signal S1 is used for controlling the data writing transistor M2 to write the data voltage into the driving transistor M1, and the second scanning signal S2 is used for controlling the initialization transistor M4 of the pixel driving circuit to write the initialization voltage into the driving transistor M1. The second output signal output by the second output end of the shift register unit is the light emitting control signal EM, which controls the light emitting control transistor M3 to turn on, so as to form a conduction path of the driving current in the light emitting stage. In one frame, the time length of the non-active pulse of the second output signal output by the second output end Gout2 is greater than the time length of the active pulse of the first output signal output by the first output end Gout1. The non-active pulse of the second output signal is a pulse for controlling the transistors in the pixel driving circuit connected to the second output end Gout2 to turn off. The active pulse of the first output signal is a pulse for controlling the transistors in the pixel driving circuit connected to the first output end Gout1 to turn on. In other embodiments, the pixel driving circuit can be a 5T1C circuit or a 7T1C circuit or other pixel driving circuit accessing the scanning signal and the light emitting control signal, which is not limited herein. The shift register unit in the embodiment comprises N-type transistors, and is suitable for the pixel driving circuit with all N-type transistors. In other optional embodiments, the first output signal and the second output signal output by the shift register unit provided in the embodiment can also be used to drive the P-type pixel driving circuit, Figure 10 A structure diagram of a P-type pixel driving circuit provided in an embodiment of the present application is shown in FIG. 4, Figure 10 , Figure 10 and Figure 9The difference lies in that the driving transistor M1, the data writing transistor M2, the light emitting control transistor M3 and the initialization transistor M4 are all P-type transistors, the driving transistor M1, the light emitting control transistor M3 and the light emitting device LD are connected in series between the first power supply Elvdd and the second power supply Elvss in sequence, and the initialization transistor M4 is connected between the first electrode of the light emitting device LD and the initialization signal line Vref.

[0102] In another alternative embodiment, another structure of the shift register unit is provided, Figure 11 A structure diagram of the shift register unit in another gate drive circuit provided by the embodiment of the present application is shown in Fig. 4. Figure 11 Optionally, the shift register unit further comprises a fourth output control module 14, which is configured to control the transmission of the first potential V1 to the first output end Gout1 of the current stage shift register unit according to the first output signal Gn+2 output by the first output end of the next stage shift register unit connected to the current stage shift register unit. The fourth output control module 14 can be a switching module, which connects the first potential V1 to the first output end Gout1 of the current stage shift register unit when turned on, and disconnects the first potential V1 from the first output end Gout1 of the current stage shift register unit when turned off.

[0103] Further, the fourth output control module 14 comprises a ninth transistor T9, the first electrode of which is connected to the first potential V1, the second electrode of which is connected to the first output end Gout1 of the current stage shift register unit, and the gate of which is connected to the first output signal Gn+2 output by the first output end of the next stage shift register unit connected to the current stage shift register unit. The ninth transistor T9 is turned off in response to the low level of the first output signal Gn+2 output by the first output end of the next stage shift register unit connected to the current stage shift register unit in the first stage t1 and the second stage t2, and is turned on in response to the high level of the first output signal Gn+2 output by the first output end of the next stage shift register unit connected to the current stage shift register unit in the third stage t3 and the fourth stage t4, so as to transmit the first potential V1 to the first output end Gout1 of the current stage shift register unit.

[0104] The embodiment of the present application further provides a display panel, Figure 12 A structure diagram of the display panel provided by the embodiment of the present application is shown in Fig. 5. Figure 12The display panel comprises the gate driving circuit, the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 in the above-mentioned embodiments; the odd-numbered stage shift register units are included in one of the gate driving circuits, and the even-numbered stage shift register units are included in the other gate driving circuit; the pulse SCK1 transmitted on the first clock signal line CLK1, the pulse SCK2 transmitted on the second clock signal line CLK1, the pulse SCK3 transmitted on the third clock signal line CLK3 and the pulse SCK4 transmitted on the fourth clock signal line CLK4 are sequentially delayed; the pulse of the start signal STV1 inputted to the start signal end SIN of the first stage shift register unit 151 and the pulse of the start signal STV2 inputted to the start signal end SIN of the second stage shift register unit 152 are sequentially delayed;

[0105] The first clock signal end K1 of the (4k+1)th stage shift register unit is connected with the first clock signal line CLK1, the second clock signal end K2 is connected with the second clock signal line CLK2, and the third clock signal end K3 is connected with the third clock signal line CLK3;

[0106] The first clock signal end K1 of the (4k+2)th stage shift register unit is connected with the second clock signal line CLK2, the second clock signal end K2 is connected with the third clock signal line CLK3, and the third clock signal end K3 is connected with the fourth clock signal line CLK4;

[0107] The first clock signal end K1 of the (4k+3)th stage shift register unit is connected with the third clock signal line CLK3, the second clock signal end K2 is connected with the fourth clock signal line CLK4, and the third clock signal end K3 is connected with the first clock signal line CLK1;

[0108] The first clock signal end K1 of the (4k+4)th stage shift register unit is connected with the fourth clock signal line CLK4, the second clock signal end K2 is connected with the first clock signal line CLK1, and the third clock signal end K3 is connected with the second clock signal line CLK2; k is an integer greater than or equal to 0.

[0109] Odd-level shift register units are connected to the corresponding odd-numbered row sub-pixels, and even-level shift register units are connected to the corresponding even-numbered row sub-pixels. One shift register unit is connected to one row of sub-pixels 16. For example, the first-level shift register unit 151 is connected to the first row of sub-pixels, the second-level shift register unit 152 is connected to the second row of sub-pixels, the third-level shift register unit 153 is connected to the third row of sub-pixels, the fourth-level shift register unit 154 is connected to the fourth row of sub-pixels, the fifth-level shift register unit 155 is connected to the fifth row of sub-pixels, the sixth-level shift register unit 156 is connected to the sixth row of sub-pixels, and so on. If the current-level shift register unit in the above gate driving circuit is the nth-level shift register unit, then the next-level shift register unit connected to the current-level shift register unit is the (n+2)th-level shift register unit, where n is an integer greater than or equal to 1. Figure 13 This is a driving timing diagram of a display panel provided in an embodiment of the present invention, with reference to... Figure 12 and Figure 13 , Figure 13 The example illustrates: the potential of the first node N11 of the first-stage shift register unit, the potential of the first output signal G11 output from the first output terminal Gout1 of the first-stage shift register unit, and the potential of the second output signal G21 output from the second output terminal Gout2 of the first-stage shift register unit; the potential of the first node N12 of the second-stage shift register unit, the potential of the first output signal G12 output from the first output terminal Gout1 of the second-stage shift register unit, and the potential of the second output signal G22 output from the second output terminal Gout2 of the second-stage shift register unit. The potentials of the first node N13 of the third-stage shift register unit, the first output signal G13 output from the first output terminal Gout1 of the third-stage shift register unit, and the second output signal G23 output from the second output terminal Gout2 of the third-stage shift register unit; the potentials of the first node N14 of the fourth-stage shift register unit, the first output signal G14 output from the first output terminal Gout1 of the fourth-stage shift register unit, and the fourth output signal G24 output from the second output terminal Gout2 of the fourth-stage shift register unit. The working process of each shift register unit can be referred to... Figure 3 The shift register shown adopts Figure 4 The timing-driven process shown will not be elaborated further here. The beneficial effects of the display panel are the same as those of the gate driving circuit, and will not be elaborated further here. Additionally, the gate driving circuit can be located on one side of the non-display bezel of the display panel, with one shift register unit connected to each row of sub-pixels, achieving single-sided driving. In other optional embodiments, gate driving circuits can be located on both sides of the non-display bezel of the display panel, with each row of sub-pixels driven by two shift register units located on either side of that row of sub-pixels, achieving double-sided driving.

[0110] It should be understood that the various forms of flow illustrated above can be used to reorder, add or delete steps. For example, the steps described in the present application can be performed in parallel, in series, in a different order, or any combination thereof, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0111] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A gate driving circuit, characterized in that, include: Multiple cascaded shift register units are provided. Each shift register unit includes a start signal terminal, a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a first output terminal, and a second output terminal. In the case of two adjacent cascaded shift register units, the first output signal output by the first output terminal of the preceding shift register unit is used as the start signal input to the start signal terminal of the following shift register unit. The shift register unit includes: The first output control module is used to control the clock signal connected to the first clock signal terminal, the clock signal connected to the third clock signal terminal, and the first potential to be transmitted to the first node based on the start signal, the first output signal output from the first output terminal of the next-level shift register unit connected to the current-level shift register unit, and the potential of the second node. The second output control module is used to control the transmission of the second potential to the second node and the second output terminal, and is also used to transmit the first potential to the second node and the second output terminal according to the potential of the first node. The first control terminal of the output module is connected to the first node, the second control terminal of the output module is connected to the second node, the second node is connected to the second output terminal of the shift register unit, and the output module is used to control the clock signal connected to the second clock signal terminal to be transmitted to the first output terminal according to the potential of the first node, and to control the first potential to be transmitted to the first output terminal according to the potential of the second node and the potential of the second output terminal. The third output control module is used to respond to the start signal and control the transmission of the first potential to the second output terminal.

2. The gate driving circuit according to claim 1, characterized in that, The first output control module includes: The first control unit is configured to control the clock signal connected to the first clock signal terminal to be transmitted to the first node according to the start signal connected to the start signal terminal. The second control unit is used to control the clock signal connected to the third clock signal terminal to be transmitted to the first node according to the first output signal output by the first output terminal of the next-level shift register unit connected to the current-level shift register unit. The third control unit is used to control the transmission of the first potential to the first node based on the potential of the second node.

3. The gate driving circuit according to claim 2, characterized in that, The first control unit includes a first transistor, the first terminal of the first transistor is connected to the first clock signal terminal, the second terminal of the first transistor is connected to the first node, and the gate of the first transistor is connected to the start signal terminal; The second control unit includes a second transistor, the first terminal of the second transistor is connected to the third clock signal terminal, the second terminal of the second transistor is connected to the first node, and the gate of the second transistor is connected to the first output signal output from the first output terminal of the next-level shift register unit connected to the current-level shift register unit. The third control unit includes a third transistor, the first terminal of which is connected to the first potential, the second terminal of which is connected to the first node N1, and the gate of which is connected to the second node.

4. The gate driving circuit according to claim 1, characterized in that, The second output control module includes: The fourth control unit is used to control the transmission of the first potential to the second node and the second output terminal respectively, based on the potential of the first node; The fifth control unit is used to transmit the second potential to the second node and the second output terminal, respectively.

5. The gate driving circuit according to claim 4, characterized in that, The fourth control unit includes a fourth transistor, the first terminal of the fourth transistor is connected to a first potential, the second terminal of the fourth transistor is connected to the second node, and the gate of the fourth transistor is connected to the first node; The fifth control unit includes a fifth transistor, the first terminal of the fifth transistor is connected to the gate of the fifth transistor, the second terminal of the fifth transistor is connected to the second node, and the gate of the fifth transistor is connected to a second potential; The aspect ratio of the fourth transistor is greater than that of the fifth transistor.

6. The gate driving circuit according to claim 1, characterized in that, The third output control module includes a sixth transistor, the first terminal of which is connected to a first potential, the second terminal of which is connected to a second output terminal, and the gate of which is connected to a start signal terminal.

7. The gate driving circuit according to claim 1, characterized in that, The output module includes: The first output unit is used to control the clock signal connected to the second clock signal terminal to be transmitted to the first output terminal according to the potential of the first node. The second output unit is used to control the transmission of the first potential to the first output terminal according to the potential of the second node; The first output unit includes a seventh transistor and a first capacitor. The first terminal of the seventh transistor is connected to the second clock signal terminal, the second terminal of the seventh transistor is connected to the first output terminal, and the gate of the seventh transistor is connected to the first node. The first terminal of the first capacitor is connected to the gate of the seventh transistor, and the second terminal of the first capacitor is connected to the first output terminal. The second output unit includes an eighth transistor, the first terminal of which is connected to the first potential, the second terminal of which is connected to the first output terminal, and the gate of which is connected to the second node.

8. The gate driving circuit according to claim 1, characterized in that, The shift register unit further includes a fourth output control module, which is used to control the first potential to be transmitted to the first output terminal of the current shift register unit according to the first output signal output by the first output terminal of the next-level shift register unit connected to the current shift register unit. The fourth output control module includes a ninth transistor. The first terminal of the ninth transistor is connected to a first potential, the second terminal of the ninth transistor is connected to the first output terminal of the current stage shift register unit, and the gate of the ninth transistor is connected to the first output signal output from the first output terminal of the next stage shift register unit connected to the current stage shift register unit.

9. The gate driving circuit according to any one of claims 1-8, characterized in that, The first output signal output from the first output terminal is a scanning signal, and the second output signal output from the second output terminal is a light emission control signal.

10. A display panel comprising two gate driving circuits as described in any one of claims 1-9, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; wherein one of the gate driving circuits includes odd-numbered shift register units, and the other gate driving circuit includes even-numbered shift register units; pulses transmitted on the first clock signal line, pulses transmitted on the second clock signal line, pulses transmitted on the third clock signal line, and pulses transmitted on the fourth clock signal line are sequentially delayed; pulses of a start signal connected to the start signal terminal of the first-level shift register unit and pulses of a start signal connected to the start signal terminal of the second-level shift register unit are sequentially delayed; The first clock signal terminal of the (4k+1)th stage shift register unit is connected to the first clock signal line, the second clock signal terminal is connected to the second clock signal line, and the third clock signal terminal is connected to the third clock signal line. The first clock signal terminal of the (4k+2)th stage shift register unit is connected to the second clock signal line, the second clock signal terminal is connected to the third clock signal line, and the third clock signal terminal is connected to the fourth clock signal line; The first clock signal terminal of the (4k+3)th stage shift register unit is connected to the third clock signal line, the second clock signal terminal is connected to the fourth clock signal line, and the third clock signal terminal is connected to the first clock signal line. The first clock signal terminal of the (4k+4)th shift register unit is connected to the fourth clock signal line, the second clock signal terminal is connected to the first clock signal line, and the third clock signal terminal is connected to the second clock signal line; k is an integer greater than or equal to 0.

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