A display panel and display device

Abstract

This application discloses a display panel and a display device, comprising: a driving circuit including multiple cascaded shift register units; each shift register unit includes a driving control circuit, a cascading circuit, a refresh control circuit, an isolation circuit, and a reset circuit; the driving control circuit is electrically connected to an input terminal, a first clock terminal, a first driving node, and a second driving node; the cascading circuit is electrically connected to the first driving node, the second driving node, a first voltage terminal, a second voltage terminal, and a cascading terminal; the refresh control circuit is electrically connected to the cascading terminal, the refresh control terminal, a first auxiliary node, and a scanning terminal; the isolation circuit is electrically connected to the first driving node, the first auxiliary node, the second auxiliary node, and an auxiliary voltage terminal; and the reset circuit is electrically connected to the second auxiliary node, the reset voltage terminal, and the scanning terminal. By adopting the above technical solution, the performance of the driving circuit can be improved, and the display effect can be enhanced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, the application scenarios of display devices are becoming increasingly diverse, and users' display needs are also becoming more varied. For users who need to display multiple application scenarios simultaneously on terminal products, some interfaces on the display screen need to be displayed at high frequency to ensure smooth picture, while other interfaces need to be displayed at low frequency to reduce product power consumption.

[0003] Currently, display devices can achieve segmented frequency display by controlling the scanning signal output by the driving circuit to provide effective pulses of the scanning signal to pixels in the high-frequency display area and ineffective levels of the scanning signal to pixels in the low-frequency display area during the refresh phase of a frame. However, the performance of the driving circuit still needs to be improved to enhance the display effect. Summary of the Invention

[0004] This application provides a display panel and a display device to improve the performance of the driving circuit and enhance the display effect.

[0005] According to one aspect of this application, a display panel is provided, comprising: a driving circuit; the driving circuit includes a plurality of cascaded shift register units; The shift register unit includes a drive control circuit, a transmission circuit, a refresh control circuit, an isolation circuit, and a reset circuit; The drive control circuit is electrically connected to the input terminal, the first clock terminal, the first drive node, and the second drive node, respectively. The cascade circuit is electrically connected to the first driving node, the second driving node, the first voltage terminal, the second voltage terminal, and the cascade terminal, respectively; wherein, the cascade terminal of the i-th stage shift register unit is electrically connected to the input terminal of the j-th stage shift register unit, i≠j, and i and j are both positive integers; The refresh control circuit is electrically connected to the transmission terminal, the refresh control terminal, the first auxiliary node, and the scanning terminal, respectively. The isolation circuit is electrically connected to the first driving node, the first auxiliary node, the second auxiliary node, and the auxiliary voltage terminal, respectively. The reset circuit is electrically connected to the second auxiliary node, the reset voltage terminal, and the scanning terminal, respectively.

[0006] According to another aspect of this application, a display device is provided, comprising: the aforementioned display panel.

[0007] The technical solution of this application, by setting a drive control circuit and a cascading circuit in the shift register unit, can realize the sequential driving of the shift register unit; by setting a refresh control circuit, under the control of the refresh control signal, the scan signal and the cascading signal can be selectively synchronized or desynchronized, so that some pixels in the same display frame can be refreshed and some pixels cannot be refreshed, realizing the segmentation and frequency division of the display panel, thereby reducing the power consumption of the display panel; the refresh control circuit can also selectively synchronize or desynchronize the signal at the first auxiliary node with the signal at the second drive node under the control of the refresh control signal, and on this basis, the interval The circuit interruption can cause the signal of the second auxiliary node to be out of sync with the signal of the first driving node for at least part of the time when the signal of the first auxiliary node is invalid. In this way, when the refresh control circuit causes the effective pulse of the transmission signal at the transmission end to be out of sync with the scanning signal at the scanning end, the reset circuit can reset the scanning signal at the scanning end to an invalid level, so that the scanning signal is stably maintained at an invalid level. This helps to improve the reliability of the driving circuit and avoids the scanning signal at the scanning end from floating and fluctuating greatly due to parasitic capacitance when the transmission signal at the transmission end is at an effective level and the scanning signal at the scanning end is at an invalid level, thus affecting the display effect.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a top view of a display panel provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the first type of shift register unit provided in the embodiments of this application; Figure 3 This is a timing diagram of the first type of shift register unit provided in the embodiments of this application; Figure 4 This is a timing diagram of the second type of shift register unit provided in the embodiments of this application; Figure 5 This is a timing diagram of the third type of shift register unit provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of the second type of shift register unit provided in the embodiments of this application; Figure 7 This is a timing diagram of a display panel in multi-frequency driving mode provided in an embodiment of this application; Figure 8 This is a timing diagram of a driving circuit under a second display frame provided in an embodiment of this application; Figure 9 This is a schematic diagram of the circuit structure of the first type of pixel provided in the embodiments of this application; Figure 10 This is a schematic diagram of the circuit structure of the second type of pixel provided in the embodiments of this application; Figure 11 This is a timing diagram of a pixel provided in an embodiment of this application; Figure 12 This is a schematic diagram of the structure of the third shift register unit provided in the embodiments of this application; Figure 13 This is a schematic diagram of the structure of the fourth shift register unit provided in the embodiments of this application; Figure 14 This is a schematic diagram of the structure of the fifth shift register unit provided in the embodiments of this application; Figure 15 This is a schematic diagram of the sixth shift register unit provided in the embodiments of this application; Figure 16 This is a schematic diagram of the structure of the seventh shift register unit provided in the embodiments of this application; Figure 17 This is a schematic diagram of the structure of the eighth shift register unit provided in the embodiments of this application; Figure 18 This is a schematic diagram of the structure of the ninth shift register unit provided in the embodiments of this application; Figure 19 This is a schematic diagram of the tenth shift register unit provided in the embodiments of this application; Figure 20 This is a schematic diagram of the structure of the eleventh shift register unit provided in the embodiments of this application; Figure 21 This is a schematic diagram of the structure of the twelfth shift register unit provided in the embodiments of this application; Figure 22 This is a schematic diagram of the thirteenth shift register unit provided in this application embodiment; Figure 23 This is a schematic diagram of the structure of the fourteenth shift register unit provided in the embodiments of this application; Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] Figure 1 This is a top view structural diagram of a display panel provided in an embodiment of this application, with reference to... Figure 1 The display panel 001 includes a driving circuit 10, multiple scan lines SL, multiple data lines DL, and multiple pixels P located in the display area AA. At least some of the pixels P located in the same row can be electrically connected to the same scan line SL, and at least some of the pixels P located in the same column can be electrically connected to the same data line DL.

[0014] The driving circuit 10 includes multiple cascaded shift register units 20. The first-stage shift register unit 20 can receive a start signal as an input signal. Starting from the second stage, the input signal of each stage shift register unit 20 can come from the previous stage shift register unit 20, but is not limited to the previous stage shift register unit 20. In at least part of the display frame, the scan signals output by each stage shift register unit 20 can be shifted sequentially. The shift register unit 20 is electrically connected to at least one scan line SL to provide a scan signal for the scan line SL. For example, when the scan signal transmitted on the scan line SL is at an active level, some transistors in a row of pixels P electrically connected to the scan line SL can be turned on, so that the row of pixels P electrically connected to the scan line SL can receive the data signal transmitted on the data line DL and display it as a corresponding grayscale according to the data signal, thereby refreshing the pixels P electrically connected to the scan line SL.

[0015] The display panel 001 may include an LED display, and the pixel P may include a writing transistor, a driving transistor, a storage capacitor, and a light-emitting element (LED), etc. Figure 1 (Not shown in the image); or, the display panel 001 may also include a liquid crystal display, and the pixel P may include a write transistor, a liquid crystal capacitor, a storage capacitor, a pixel electrode, and a common electrode, etc. Figure 1 (not shown in the image), the embodiments of this application do not limit the type of display panel or the specific structure of the pixel P.

[0016] In an optional embodiment, the driving circuit 10 further includes a source driving circuit 30, which is electrically connected to multiple data lines DL to provide data signals to the data lines DL. For example, during the pixel refresh time of a row of pixels P, the source driving circuit 30 can provide multiple data signals to the multiple data lines DL, enabling the row of pixels P to be displayed as the corresponding grayscale based on the data signals provided by the source driving circuit 30. During the pixel refresh time of the next row of pixels P, the source driving circuit 30 can again provide multiple data signals to the multiple data lines DL, enabling the next row of pixels P to be displayed as the corresponding grayscale based on the data signals again provided by the source driving circuit 30, thereby achieving row-by-row refresh of pixels P in the display panel 001.

[0017] It should be noted that, Figure 1 The figure only shows the driving circuit 10 located in the non-display area AA' outside the display area AA. In other feasible embodiments, the driving circuit 10 may also be located in the display area AA. In addition, the figure only shows the driving circuit 10 located on the left and lower sides of the display area AA. In other feasible embodiments, the driving circuit 10 may also be located on other sides of the display area AA, or simultaneously on one, three, or four sides of the display area AA. The embodiments of this application do not limit the position of the driving circuit 10.

[0018] It should also be noted that, Figure 1 The illustration only shows a portion of the structure and signal traces of the display panel 001. In other feasible embodiments, the display panel 001 may also include other structures and other signal traces, which are not limited in this application.

[0019] Figure 2 This is a schematic diagram of the structure of the first shift register unit provided in the embodiments of this application, with reference to... Figure 2The shift register unit 20 includes a drive control circuit 210, a transmission circuit 220, a refresh control circuit 230, an isolation circuit 240, and a reset circuit 250. The drive control circuit 210 is electrically connected to the input terminal IN, the first clock terminal CK, the first drive node NA, and the second drive node NB, respectively. The stage transfer circuit 220 is electrically connected to the first driving node NA, the second driving node NB, the first voltage terminal VGH, the second voltage terminal VGL, and the stage transfer terminal NEXT, respectively. Among them, the stage transfer terminal NEXT of the i-th stage shift register unit 20(i) is electrically connected to the input terminal IN of the j-th stage shift register unit 20(j), i≠j, and i and j are both positive integers. The refresh control circuit 230 is electrically connected to the stage transfer terminal NEXT, the refresh control terminal Ctrl, the first auxiliary node NP, and the scan terminal GOUT, respectively. The isolation circuit 240 is electrically connected to the first driving node NA, the first auxiliary node NP, the second auxiliary node ND, and the auxiliary voltage terminal VG23, respectively. The reset circuit 250 is electrically connected to the second auxiliary node ND, the reset voltage terminal VG24, and the scan terminal GOUT, respectively.

[0020] Specifically, the drive control circuit 210 can control the signals of the first drive node NA and the second drive node NB based on the input signal of the input terminal IN and the first clock signal of the first clock terminal CK; the cascading circuit 220 can control the cascading signal of the cascading terminal NEXT based on the signals of the first drive node NA and the second drive node NB; the refresh control circuit 230 can control the signals of the first auxiliary node NP and the scan signal of the scan terminal GOUT based on the cascading signal of the cascading terminal NEXT and the refresh control signal of the refresh control terminal Ctrl; the isolation circuit 240 can control the signal of the second auxiliary node ND based on the signals of the first drive node NA and the first auxiliary node NP; and the reset circuit 250 can control the scan signal of the scan terminal GOUT based on the signal of the second auxiliary node ND.

[0021] For example, Figure 3 This is a timing diagram of the first type of shift register unit provided in the embodiments of this application. Figure 4 This is a timing diagram of the second type of shift register unit provided in the embodiments of this application, wherein, Figure 3 The timing of the intermediate shift register unit can control the refreshing of the pixels electrically connected to the shift register unit. Figure 4 The timing of the intermediate shift register unit can control the pixels electrically connected to this shift register unit to stop refreshing. (Reference) Figures 2-4In the same shift register unit 20, after the input signal at the input terminal IN jumps to an effective level V1, the drive control circuit 210 can control the signal of the first drive node NA to be an ineffective level V2' and the signal of the second drive node NB to be an effective level V2 according to the effective level V1 of the input signal and the first clock signal of the first clock terminal CK, thereby causing the cascade circuit 220 to control the cascade signal of the cascade terminal NEXT to be an effective level V1; after the input signal at the input terminal IN jumps to an ineffective level V1', the drive control circuit 210 can control the signal of the first drive node NA to be an effective level V2 and the signal of the second drive node NB to be an ineffective level V2' according to the ineffective level V1' of the input signal and the first clock signal of the first clock terminal CK, thereby causing the cascade circuit 220 to control the cascade signal of the cascade terminal NEXT to be an ineffective level V1'. The NEXT terminal can be electrically connected to the IN terminal of the next-level shift register unit 20, so that the NEXT signal can be used as the input signal of the next-level shift register unit 20, thereby realizing the sequential shifting of the effective pulses of the input signal, that is, realizing the sequential driving of each level of the shift register unit 20.

[0022] In this context, the effective level V1 and the invalid level V1' are relative to the input signal at the input terminal IN and the transmission signal at the transmission terminal NEXT. In one embodiment, the effective level V1 and the invalid level V1' can be the same as the effective level and invalid level of the scan signal at the scan terminal GOUT. That is, the effective level V1 and the effective level of the scan signal are at the same potential level (high level or low level), and the invalid level V1' and the invalid level of the scan signal are at the same potential level (low level or high level). In this case, the effective level V1 and the effective level of the scan signal can be used to control the conduction of some transistors in the drive control circuit 210 and the conduction of some transistors in the pixel circuit electrically connected to the shift register unit 20. The invalid level V1' and the invalid level of the scan signal can be used to control the cutoff of some transistors in the drive control circuit 210 and the cutoff of some transistors in the pixel P electrically connected to the shift register unit 20. The effective level V2 and the invalid level V2' are relative to the signals at the first driving node NA and the second driving node NB. The effective level V2 and the invalid level V2' of the signals at the first driving node NA and the second driving node NB can be used to control the conduction and cutoff of some transistors in the shift register unit 20.

[0023] It is understandable that the driving of each shift register unit 20 is not affected by the refresh control signal of the refresh control terminal Ctrl and the scan signal of the scan terminal GOUT. That is, regardless of the level of the refresh control signal and the scan signal, each shift register unit 20 can be driven in sequence.

[0024] refer to Figure 2 and Figure 3When the refresh control signal at the refresh control terminal Ctrl is at an effective level V3, the refresh control circuit 230 can be controlled to work normally, synchronizing the scan signal at the scan terminal GOUT with the transmission signal at the transmission terminal NEXT. When the transmission signal at the transmission terminal NEXT jumps to an effective level V1, the refresh control circuit 230 can control the scan signal at the scan terminal GOUT to an effective level V5 based on the effective level V3 of the refresh control signal, thus achieving synchronization between the scan signal at the scan terminal GOUT and the transmission signal at the transmission terminal NEXT. Thus, when the refresh control signal is at an effective level V3, each level of the shift register unit 20 is driven sequentially, and the cascading terminals NEXT of each level of the shift register unit 20 sequentially output effective pulses of the cascading signal, the scanning terminals GOUT of each level of the shift register unit 20 can also sequentially output effective pulses of the scanning signal, thereby achieving full-screen refresh of the display panel 001. In addition, during the refresh phase of a frame, the refresh control signal of the refresh control terminal Ctrl can be controlled to be at an effective level V3 for a certain period of time, so that when the cascading terminals NEXT of some shift register units 20 output effective pulses of the cascading signal, their scanning terminals GOUT can synchronously output effective pulses of the scanning signal, thereby achieving partial refresh of the display panel 001.

[0025] Continue to refer to Figure 2 and Figure 3 When the refresh control signal at the refresh control terminal Ctrl is at a valid level V3, the refresh control circuit 230 can also synchronize the signal at the first auxiliary node NP with the signal at the second driving node NB. The signal at the second driving node NB affects the transmission signal at the transmission terminal NEXT. When the transmission circuit 220 controls the transmission signal at the transmission terminal NEXT according to the first driving node NA and the second driving node NB, the refresh control circuit 230 can control the signal at the first auxiliary node NP based on the valid level V3 of the refresh control terminal Ctrl and the transmission signal at the transmission terminal NEXT, so that the signal at the first auxiliary node NP is synchronized with the signal at the second driving node NB.

[0026] When the signal at the first auxiliary node NP is synchronized with the signal at the second driving node NB, the signal at the first auxiliary node NP can switch between an effective level V4 and an ineffective level V4'. When the signal at the first auxiliary node NP is an effective level V4, the isolation circuit 240 can synchronize the signal at the second auxiliary node ND with the signal at the first driving node NA based on the effective level V4 at the first auxiliary node NP. At this time, the reset circuit 250 can synchronously control the scan signal of the scan terminal GOUT according to the signal at the second auxiliary node ND that is synchronized with the signal at the first driving node NA, which is beneficial to achieve synchronization between the scan signal of the scan terminal GOUT and the transmission signal of the transmission terminal NEXT. In one embodiment, the signal at the auxiliary voltage terminal VG23 can be the effective level V4 of the second auxiliary node ND, so that when the signal at the first driving node NA is an effective level V2, the second auxiliary node ND can be stably at an effective level V4. In another embodiment, the signal at the auxiliary voltage terminal VG23 can be the ineffective level V4' of the second auxiliary node ND, so that when the signal at the first driving node NA is an ineffective level V2', the second auxiliary node ND can be stably at an ineffective level V4'.

[0027] refer to Figure 2 and Figure 4 When the refresh control signal at the refresh control terminal Ctrl is at an invalid level V3', the refresh control circuit 230 can be controlled to stop normal operation, causing the scan signal at the scan terminal GOUT and the transmission signal at the transmission terminal NEXT to be out of sync for at least a portion of the time. When the transmission signal at the transmission terminal NEXT jumps to an active level V1, the refresh control circuit 230 can, based on the invalid level V3' of the refresh control terminal Ctrl, control the scan signal at the scan terminal GOUT to jump to an active level V5 out of sync, and the scan signal can remain at an invalid level V5', thus achieving asynchrony between the scan signal at the scan terminal GOUT and the transmission signal at the transmission terminal NEXT. Thus, when the refresh control signal is at an invalid level V3', and each level of shift register unit 20 is driven sequentially, and the cascade terminal NEXT of each level of shift register unit 20 sequentially outputs valid pulses of the cascade signal, the scanning terminal GOUT of the shift register unit 20 can not output valid pulses of the scanning signal, thereby realizing the frequency reduction drive of the display panel 001, which is beneficial to reducing the power consumption of the display panel. Alternatively, during the refresh phase of a frame, the refresh control signal of the refresh control terminal Ctrl can be controlled to be at an invalid level V3' for a certain period of time, so that when the cascade terminal NEXT of some shift register units 20 outputs valid pulses of the cascade signal, its scanning terminal GOUT can output valid pulses of the scanning signal asynchronously, thereby realizing the local frequency reduction drive of the display panel 001, thus realizing the segmented frequency of the display panel, which is beneficial to reducing the power consumption of the display panel and reducing the impact on the display effect.

[0028] Continue to refer to Figure 2and Figure 4 When the refresh control terminal Ctrl is at an invalid level V3', the refresh control circuit 230 can also make the signal at the first auxiliary node NP and the signal at the second driving node NB asynchronous for at least a portion of the time. When the cascading circuit 220 controls the cascading signal of the cascading terminal NEXT according to the first driving node NA and the second driving node NB, the refresh control circuit 230 can, based on the invalid level V3' of the refresh control terminal Ctrl, not control the signal at the first auxiliary node NP according to the cascading signal of the cascading terminal NEXT. That is, the signal at the first auxiliary node NP is not affected by the cascading signal of the cascading terminal NEXT. Regardless of the potential level of the cascading signal output by the cascading terminal NEXT, the signal at the first auxiliary node NP can be maintained at a certain potential level. For example, when the cascading terminal NEXT outputs a valid pulse of the cascading signal, the signal at the first auxiliary node NP can remain unchanged and continue to be maintained at the potential when the cascading terminal NEXT is at an invalid level V1', making the signal at the first auxiliary node NP asynchronous with the signal at the second driving node NB.

[0029] When the signal at the first auxiliary node NP is out of sync with the signal at the second driving node NB, the signal at the first auxiliary node NP can remain at an invalid level V4'. The isolation circuit 240 can isolate the connection between the second auxiliary node ND and the first driving node NA based on the invalid level V4' at the first auxiliary node NP, so that the signal at the second auxiliary node ND is out of sync with the signal at the first driving node NA for at least a portion of the time. At this time, the reset circuit 250 no longer controls the scanning signal of the scanning terminal GOUT synchronously according to the signal at the first driving node NA. For example, when the transmission signal at the transmission terminal NEXT is at an effective level V1 and the scanning signal at the scanning terminal GOUT is at an invalid level V5', the signal at the second auxiliary node ND is out of sync with the signal at the first driving node NA, which is beneficial to maintaining the stability when the scanning signal is at an invalid level V5'.

[0030] It is understandable that even when the refresh control terminal Ctrl is at an invalid level V3', there may still be periods where the scan signal of the scan terminal GOUT is synchronized with the transmission signal of the transmission terminal NEXT, and / or the signal at the first auxiliary node NP is synchronized with the signal at the second drive node NB. For example, refer to... Figure 4Before the refresh control signal at the refresh control terminal Ctrl transitions to an invalid level V3' (during this stage, the refresh control signal at the refresh control terminal Ctrl is at an active level V3), the cascading signal at the cascading terminal NEXT and the scanning signal at the scanning terminal GOUT can both be at invalid levels (V1' and V5'), and the signals at the second driving node NB and the first auxiliary node NP can also both be at invalid levels (V2' and V4'). Then, in this state, the refresh control signal at the refresh control terminal Ctrl can transition from an active level V3 to an invalid level V3', and the refresh control signal at the refresh control terminal Ctrl transitions to an invalid level V3'. After step 3' (at this stage, the refresh control signal of the refresh control terminal Ctrl is at an invalid level V3'), the scan signal of the scan terminal GOUT can remain at an invalid level V5', and the signal of the first auxiliary node NP can remain at an invalid level V4'. When the cascading signal has not changed to an effective level V1, the scan signal of the scan terminal GOUT and the cascading signal of the cascading terminal NEXT can be synchronized, both at invalid levels (V5' and V1'). When the signal of the second driving node NB has not changed to an effective level V2, the signal at the first auxiliary node NP and the signal at the second driving node NB can be synchronized, both at invalid levels (V4' and V2').

[0031] Similarly, when the refresh control terminal Ctrl is at an invalid level V3', there may be a period of time during which the signal at the second auxiliary node ND is synchronized with the signal at the first driving node NA. For example, the isolation circuit 240 can isolate the connection between the second auxiliary node ND and the first driving node NA based on the invalid level V4' of the first auxiliary node NP, so that the signal at the second auxiliary node ND is maintained at a certain potential level (valid level or invalid level). When the signal at the first driving node NA jumps to that potential level (valid level or invalid level), the signal at the second auxiliary node ND and the signal at the first driving node NA can be synchronized to the same potential level (valid level or invalid level).

[0032] Among them, the effective level V3 and the invalid level V3' are relative to the refresh control signal at the refresh control terminal Ctrl. The effective level V3 and the invalid level V3' of the refresh control signal can be used to control the conduction and cutoff of some transistors in the refresh control circuit 230. The effective level V4 and the invalid level V4' are relative to the signal at the first auxiliary node NP and the signal at the second auxiliary node ND. The effective level V4 and the invalid level V4' of the signal at the first auxiliary node NP and the signal at the second auxiliary node ND can also be used to control the conduction and cutoff of some transistors in the shift register unit 20. In one embodiment, the effective level V4 and the invalid level V4' can be the same as the effective level V2 and the invalid level V2', that is, the effective level V4 and the effective level V2 are at the same potential level (high level or low level), and the invalid level V4' and the invalid level V2' are at the same potential level (low level or high level). The effective level V5 and the invalid level V5' are relative to the scan signal at the scan terminal GOUT. The effective level V5 and the invalid level V5' of the scan signal can be used to control the conduction and cutoff of some transistors in the pixel circuit electrically connected to the shift register unit 20. In one embodiment, the effective level V5 and the invalid level V5' can be the same as the effective level V1 and the invalid level V1', that is, the effective level V1 and the effective level V1 are at the same potential level (high level or low level), and the invalid level V5' and the invalid level V5' are at the same potential level (low level or high level).

[0033] "Synchronous" means that two signals are both high or both low at the same time. "Asynchronous" means that one signal is high and the other is low. "Synchronous" or "asynchronous" usually refers to two signals with the same effective and invalid potential levels, such as the scan signal of the scan end GOUT and the stage transmission signal of the stage transmission end NEXT, the signal of the first auxiliary node NP and the signal of the second driving node NB, and the signal of the second auxiliary node NP and the signal of the first driving node NB.

[0034] In one embodiment, when the refresh control terminal Ctrl is at an invalid level V3', regardless of whether the transmission signal of the transmission terminal NEXT is at an effective level V1 or an invalid level V1', the scan signal of the scan terminal GOUT can remain at an invalid level V5', causing the pixel electrically connected to the shift register unit 20 to stop refreshing; at the same time, when the refresh control terminal Ctrl is at an invalid level V3', regardless of whether the signal at the first driving node NA is at an effective level V2 or an invalid level V2', the signal at the second auxiliary node ND can remain at an effective level V4, enabling the reset circuit 250 to continuously transmit the reset voltage terminal VG24 signal to the scan terminal GOUT, which is beneficial to improving the stability when the scan signal of the scan terminal GOUT is at an invalid level V5'.

[0035] Specifically, when the refresh control terminal Ctrl is at an invalid level V3', the refresh control circuit 230 can make the scan signal of the scan terminal GOUT and the transmission signal of the transmission terminal NEXT asynchronous for at least a portion of the time. That is, when the transmission circuit 220 outputs a valid pulse of the transmission signal, the refresh control circuit 230 can not transmit a valid pulse of the scan signal, so that the scan signal of the scan terminal GOUT remains at an invalid level V5'. When the refresh control terminal Ctrl is at an invalid level V3', it can also make the first auxiliary control node NP and the second drive node NB asynchronous for at least a portion of the time. The isolation circuit 240 can make the signal at the second auxiliary node ND and the signal at the first drive node NA asynchronous for at least a portion of the time based on the signal at the first auxiliary node NP. At this time, the signal at the second auxiliary node ND can be at an valid level V4. The reset circuit 250 can continuously transmit the reset voltage terminal VG24 to the scan terminal GOUT under the control of the second auxiliary node ND, so that the scan signal remains at an invalid level V5'.

[0036] In this way, the scanning signal received by some pixels in the same display frame can always be at an invalid level V5', thereby controlling the refreshing of those pixels to stop, realizing the segmentation and frequency division of the display panel, and helping to reduce the power consumption of the display panel; at the same time, it can also improve the stability of the scanning signal of the scanning end GOUT, especially when the scanning signal of the scanning end GOUT is not synchronized with the transmission signal of the transmission end NEXT, it can effectively improve the stability of the scanning signal of the scanning end GOUT, and keep the scanning signal of the scanning end GOUT stably at an invalid level V5'.

[0037] It is understandable that if the shift register unit 20 does not have an isolation circuit 240, and instead the reset circuit 250 is directly electrically connected to the first drive node NA ( Figure 2 (not shown in the image), which is equivalent to the second auxiliary node ND being continuously short-circuited with the first driving node NA, such as... Figure 5As shown, the refresh control terminal Ctrl is at an invalid level V3', and the second auxiliary node ND and the first driving node NA maintain the same potential. When the cascading signal of the cascading terminal NEXT is at an effective level V1, although the refresh control circuit 230 is controlled by the refresh control signal of the refresh control terminal Ctrl, it can make the scanning signal of the scanning terminal GOUT asynchronous with the cascading signal of the cascading terminal NEXT, and the scanning signal of the scanning terminal GOUT can continue to be at an invalid level V5'. However, the second auxiliary node ND and the first driving node NA received by the reset circuit 250 are both at invalid levels V2', which causes the reset circuit 250 to be unable to continuously and stably transmit the voltage signal of the reset voltage terminal VG24 to the scanning terminal GOUT during this stage. At this time, the scanning signal of the scanning terminal GOUT is floating (is a passive signal), and its potential is easily affected by other signals and fluctuates. For example, there is parasitic capacitance between the scan line SL and other signal lines or other components. The coupling effect of parasitic capacitance will cause the potential of the scanning signal of the scanning terminal GOUT, which is electrically connected to the scan line, to be disturbed, thereby affecting the display effect of the display panel.

[0038] It should be noted that the five sets of effective and ineffective levels (V1, V1', V2, V2', V3, V3', V4, V4', V5, V5') mentioned above refer to different signals. The effective levels of these different signals can be at the same potential level (both high or both low) or they can be different. For example, effective levels V1 and V5 can be at the same potential level (both high), and in this case, ineffective levels V1' and V5' can be at the same potential level (both low). Similarly, effective levels V2, V3, and V4 can be at the same potential level (both low), and in this case, ineffective levels V2', V3', and V4' can be at the same potential level (both high). Effective levels V1 and V2 can be one high and the other low, and ineffective levels V1' and V2' can be one low and the other high, but this is not a limitation. In other feasible implementations, effective levels V1 to V5 can also all be at the same potential level.

[0039] It should also be noted that high level and low level refer to the potential levels used to control the turn-on or turn-off of the module / transistor, but are not limited to a fixed potential. For example, electrical signals from +15V to +30V that can control the module / transistor to the same state can all be high-level signals, and electrical signals from -10V to -5V that can control the module / transistor to the same state can all be low-level signals. Therefore, even if the effective levels V1 and V5 are both high, and the effective levels V2, V3, and V4 are all low, the specific potentials of the effective levels V1 and V5 can be different, and the specific potentials of the effective levels V2, V3, and V4 can be different when the signal sources are different. Of course, the specific potentials of the effective levels V1 and V5 can also be the same, and the specific potentials of the effective levels V2, V3, and V4 can also be the same.

[0040] This application does not limit the potential levels or specific potentials of the effective levels V1 to V5. For ease of explanation, unless otherwise specified, this application will use the example of effective levels V1 and V5 being high and effective levels V2, V3, and V4 being low.

[0041] In this embodiment, by setting a drive control circuit and a cascading circuit in the shift register unit, the shift register unit can be driven sequentially. By setting a refresh control circuit, the scan signal and the cascading signal can be selectively synchronized or desynchronized under the control of the refresh control signal, so that some pixels in the same display frame can be refreshed while others are not refreshed, realizing the segmentation and frequency division of the display panel to reduce the power consumption of the display panel. The refresh control circuit can also selectively synchronize or desynchronize the signal at the first auxiliary node with the signal at the second drive node under the control of the refresh control signal. On this basis, the power is isolated. When the signal of the first auxiliary node is at an invalid level, the signal of the second auxiliary node will be out of sync with the signal of the first driving node for at least a portion of the time. In this way, when the refresh control circuit causes the effective pulse of the transmission signal at the transmission end to be out of sync with the scanning signal at the scanning end, the reset circuit can reset the scanning signal at the scanning end to an invalid level, so that the scanning signal is stably maintained at an invalid level. This is beneficial to improving the reliability of the driving circuit and avoiding the situation where the transmission signal at the transmission end is at an effective level but the scanning signal at the scanning end is at an invalid level, the scanning signal at the scanning end will float and be affected by parasitic capacitance, resulting in large fluctuations and affecting the display effect.

[0042] In an optional embodiment, Figure 6 This is a schematic diagram of the structure of the second type of shift register provided in the embodiments of this application, with reference to... Figure 6The reset circuit 250 includes a reset transistor T28; the first terminal of the reset transistor T28 is electrically connected to the reset voltage terminal VG24, the second terminal of the reset transistor T28 is electrically connected to the scan terminal GOUT, and the gate of the reset transistor T28 is electrically connected to the second auxiliary node ND.

[0043] Specifically, the reset transistor T28 is used to control whether the reset voltage signal of the reset voltage terminal VG24 is transmitted to the scan terminal GOUT according to the signal of the second auxiliary node ND. When the second auxiliary node ND is at an active level V4, the reset transistor T28 is turned on, so that the reset voltage signal of the reset voltage terminal VG24 is transmitted to the scan terminal, thereby keeping the scan signal of the scan terminal GOUT at an inactive level V5'; when the second auxiliary node ND is at an inactive level V4', the reset transistor T28 is turned off, and the reset voltage terminal VG24 stops transmitting the reset voltage signal to the scan terminal.

[0044] For example, when the invalid level V5' of the scan signal at the scan terminal GOUT is low, the reset voltage signal at the reset voltage terminal VG24 is also low. In other embodiments, when the invalid level V5' of the scan signal at the scan terminal GOUT is high, the reset voltage signal at the reset voltage terminal VG24 can also be high. By adjusting the signal of the second auxiliary node ND, the reset transistor T28 can be controlled to transmit the reset voltage signal of the reset voltage terminal VG24 to the scan terminal GOUT, making the scan signal of the scan terminal GOUT invalid level V5'. Furthermore, by setting the isolation circuit 240, even when the effective pulse of the stage transmission signal is not synchronized to the scan signal of the scan terminal, the reset transistor T28 can continue to transmit the reset voltage signal of the reset voltage terminal VG24 to the scan terminal GOUT. In this way, during the stage when the stage transmission signal of the stage transmission terminal NEXT is at an effective level V1 and the scan signal of the scan terminal GOUT remains at an invalid level V5', the scan terminal GOUT is less likely to be in a floating state, thereby reducing the influence of parasitic capacitance, leakage current and other signal coupling on the scan signal, which is beneficial to improving the stability of the scan signal.

[0045] In one embodiment, the reset transistor T28 can be a P-type transistor. In this case, the effective level V4 of the second auxiliary node ND is low, and the invalid level V4' is high. In another embodiment, the reset transistor T28 can also be an N-type transistor. In this case, the effective level V4 of the second auxiliary node ND is high, and the invalid level V4' is low. For ease of description, unless otherwise specified, the embodiments in this application are described using P-type gold transistors in the shift register unit 20 as an example. In this case, the effective levels V2, V3, and V4 are all low, and the invalid levels V2', V3', and V5' are all high, as an example for illustrative purposes.

[0046] In optional embodiments, continue to refer to Figure 4 In the same shift register unit 20, when the cascading signal of the cascading end NEXT is at an effective level V1 and the scanning signal of the scanning end GOUT is at an invalid level V5', the signal of the first driving node NA is at an invalid level V2' and the signal of the second auxiliary node ND is at an effective level V4.

[0047] For example, in the same shift register unit 20, when the refresh control signal of the refresh control terminal Ctrl is at an invalid level V3', the refresh control circuit 230 can be controlled to stop normal operation. In this mode, the drive control circuit 210 can still control the signal of the second drive node NB to be at an effective level V2 and the signal of the first drive node NA to be at an invalid level V2', so that the transmission signal of the transmission terminal NEXT is at an effective level V1, and the transmission circuit 220 can still control the transmission terminal NEXT to output the effective pulse of the transmission signal normally; however, the refresh control circuit 230 can control the signal of the first auxiliary node NP to remain at an invalid level V4' according to the effective level V1 of the transmission terminal NEXT and the invalid level V3' of the refresh control terminal Ctrl. At this time, the scan signal of the scan terminal GOUT will not synchronously jump to an effective level V5, but will continue to remain at an invalid level V5'. Meanwhile, the isolation circuit 240 can disconnect the second auxiliary node ND from the first driving node NA based on the invalid level V4' of the signal of the first auxiliary node NP, so that the signal of the second auxiliary node ND is out of sync with the signal of the first driving node NA. The signal of the second auxiliary node ND remains at the valid level V4, so that the reset circuit 250 can continue to conduct and continuously transmit the voltage signal of the reset voltage terminal VG24 to the scanning terminal GOUT, thereby making the scanning signal of the scanning terminal GOUT stably maintain an invalid level V5', thereby improving the reliability of the circuit and avoiding the floating of the scanning terminal GOUT and the large fluctuations caused by parasitic capacitance when the transmission signal of the transmission terminal NEXT is at the valid level V1 and the scanning signal of the scanning terminal GOUT is at the invalid level V5'.

[0048] For example, continue to refer to Figure 6The stage transmission circuit 220 includes a first stage transmission transistor T9 and a second stage transmission transistor T10. The first terminal of the first stage transmission transistor T9 is connected to the first voltage terminal VGH. The gate of the first stage transmission transistor T9 is connected to the second driving node NB. The second terminal of the first stage transmission transistor T9 and the first terminal of the second stage transmission transistor T10 are connected to the stage transmission terminal NEXT. The gate of the second stage transmission transistor T10 is electrically connected to the first driving node NA. The second terminal of the second stage transmission transistor T10 is connected to the second voltage terminal VGL. The first voltage signal of the first voltage terminal VGH can be consistent with the effective level V1 of the stage transmission terminal NEXT, both being high. The second voltage signal of the second voltage terminal VGL can be consistent with the ineffective level V1' of the stage transmission terminal NEXT, both being low. In an optional embodiment, the second voltage terminal VGL can be multiplexed with the reset voltage terminal VG24. In this case, the ineffective level V1' can be equal to the ineffective level V5'.

[0049] refer to Figure 4 and Figure 6 In the same shift register unit 20, when the refresh control signal of the refresh control terminal Ctrl is invalid level V3', after the input terminal IN inputs an effective level V1, the first drive node NA can normally jump to invalid level V2', and the second drive node NB can normally jump to effective level V2, so that the first stage transmission transistor T9 is turned on and the second stage transmission transistor T10 is turned off. The stage transmission terminal NEXT can output the first voltage signal of the first voltage terminal VGH and jump to effective level V1. At this time, the refresh control circuit 230 stops working normally, and the first auxiliary node NP remains invalid level V4', so that the isolation circuit 240 isolates the first drive node NA and the second auxiliary node ND. The second auxiliary node ND can continue to remain effective level V4, so that the reset transistor T28 is turned on, and the scan terminal GOUT can output the reset voltage signal of the reset voltage terminal V24, which is stably maintained at invalid level V5', so as to improve the stability when the scan signal of the scan terminal GOUT is invalid level V5'.

[0050] In optional embodiments, continue to refer to Figure 3 In the same shift register unit 20, when the cascading signal of the cascading end NEXT and the scanning signal of the scanning end GOUT are both at valid levels (V1, V5), the signals of the first driving node NA and the second auxiliary node ND are both at invalid levels (N2', N4').

[0051] For example, refer to Figure 3 and Figure 6In the same shift register unit 20, when the refresh control signal of the refresh control terminal Ctrl is at an effective level V3, the refresh control circuit 230 can be controlled to work normally. In this mode, the drive control circuit 210 can control the signal of the second drive node NB to be at an effective level V2, control the signal of the first drive node NA to be at an ineffective level V2', and make the transmission signal of the transmission terminal NEXT at an effective level V1. The refresh control circuit 230 can control the signal of the first auxiliary node NP to be at an effective level V4 according to the effective level V1 of the transmission terminal NEXT and the effective level V3 of the refresh control terminal Ctrl, so that the scan signal of the scan terminal GOUT and the transmission signal of the transmission terminal NEXT are synchronized to be at effective levels (V1 and V5). At the same time, the isolation circuit 240 can control the signal of the second auxiliary node ND to be synchronized with the ineffective level V2' of the signal of the first drive node NA according to the effective level V4 of the first auxiliary node NP. When the signal of the second auxiliary node ND is at an ineffective level V4', the reset circuit 250 is turned off, and the voltage signal of the reset voltage terminal VG24 is stopped from being transmitted to the scan terminal GOUT. Thus, the isolation circuit 240 can control the potential of the second auxiliary node ND and the potential of the first driving node NA to remain synchronized for at least part of the time period, both being invalid levels (V4' and V2'), so that when the scanning end GOUT outputs an effective level V1 at the stage transmission end NEXT, it can stably output an effective level V5 of the scanning signal, thereby avoiding the reset circuit 250 resetting the scanning end GOUT, which would affect the pulse width of the effective pulse of the scanning signal and thus affect the charging rate when the pixel circuit is refreshed.

[0052] In optional embodiments, continue to refer to Figure 3 In the same shift register unit 20, when the cascading signal of the cascading terminal NEXT is invalid at level V1', the scanning signal of the scanning terminal GOUT is also invalid at level V5'. The signal of the first driving node NA includes an effective level V2, and the signal of the second auxiliary node ND is an effective level V4.

[0053] For example, refer to Figure 3 , Figure 4 and Figure 6When the transmission signal at the NEXT terminal returns to an invalid level V1', the drive control circuit 210 controls the signal of the second drive node NB to return to an invalid level V2', and controls the signal of the first drive node NA to return to an effective level V2 for at least a portion of the time. Simultaneously, when the refresh control terminal Ctrl is at an invalid level V3', regardless of the level of the transmission signal at the NEXT terminal, the scan signal at the GOUT terminal can be at an invalid level V5'; regardless of the level of the second drive node NB, the first auxiliary node NP can remain at an invalid level V4'; and regardless of the level of the first drive node NA, the second auxiliary node ND can remain at an effective level V4, thus activating the reset circuit 250 and ensuring stability when the scan signal at the GOUT terminal is at an invalid level V5'.

[0054] Meanwhile, when the refresh control terminal Ctrl is at an effective level V3, the refresh control circuit 230 can control the scan signal of the scan terminal GOUT to be synchronized with the signal of the cascade terminal NEXT, both at ineffective levels (V1', V5'), based on the ineffective level V1' of the cascade signal of the cascade terminal NEXT and the effective level V3 of the refresh control terminal Ctrl. The signal of the first auxiliary node NP is synchronized with the signal of the second driving node NB, both at ineffective levels (V4', V2'). The isolation circuit 240 can isolate the connection between the second auxiliary node ND and the first driving node NA based on the ineffective level V4' of the first auxiliary node NP, controlling the signal of the second auxiliary node ND to remain at an effective level V4, so that the reset circuit 250 is turned on, thereby controlling the scan signal of the scan terminal GOUT to be stably at an ineffective level V5'. In other words, when the refresh control terminal Ctrl is at an effective level V3, and the scan signal of the scan terminal GOUT is synchronized with the signal of the cascade terminal NEXT, both at ineffective levels (V1', V5'), the second auxiliary node ND can always be at an effective level V4, regardless of the level of the signal of the first driving node NA.

[0055] The scanning signal of the scanning end GOUT can change synchronously with the transmission signal of the transmission end NEXT, so that the pixels electrically connected to the shift register unit 20 can be refreshed.

[0056] In summary, when the transmission signal of the transmission terminal NEXT is at an invalid level V1', regardless of the potential level of the refresh control signal of the refresh control terminal Ctrl, i.e., regardless of whether the refresh control circuit 230 is working properly, the scan signal of the scan terminal GOUT can be synchronously at an invalid level V5'. Furthermore, when both the transmission signal of the transmission terminal NEXT and the scan signal of the scan terminal GOUT are at invalid levels (V1', V5'), the signal of the first driving node NA includes an effective level V2. The signal of the first driving node NA may be at an invalid level V2' for some time periods, but regardless of the level of the signal of the first driving node NA, the signal of the second auxiliary node ND can be maintained at an effective level V4. This allows the reset circuit 250 to continuously transmit the voltage signal of the reset voltage terminal VG24 to the scan terminal according to the effective level V4 of the second auxiliary node ND, so that the scan signal of the scan terminal GOUT is stably maintained at an invalid level V5', thereby improving the reliability of the circuit and avoiding large fluctuations caused by the floating of the scan terminal GOUT and the influence of parasitic capacitance.

[0057] Understandably, when the cascading signal at the NEXT terminal is at an effective level V1, if the refresh control terminal Ctrl is at an effective level V3, then the signal of the first auxiliary node NP is at an effective level V4, and the signal of the second auxiliary node ND is at an ineffective level V4', allowing the scan signal at the GOUT terminal to be at an effective level V5. Conversely, if the refresh control terminal Ctrl is at an effective level but ineffective level V3', then the signal of the first auxiliary node NP is at an ineffective level V4', and the signal of the second auxiliary node ND is at an effective level V4, allowing the scan signal at the GOUT terminal to stably remain at an ineffective level V5'. In other words, when the cascading signal at the NEXT terminal is at an effective level V1 and the scan signal at the GOUT terminal is at an ineffective level V5', the scan signal at the GOUT terminal can also stably maintain an ineffective level V5', thereby improving circuit reliability and preventing the GOUT terminal from floating and experiencing large fluctuations due to parasitic capacitance.

[0058] Optionally, the display panel includes a multi-frequency driving mode, with both the effective level of the transmission signal and the effective level of the scan signal being high. For example, the driving circuit includes z cascaded shift register units 20. Figure 7 This is a timing diagram of a display panel in multi-frequency driving mode provided in an embodiment of this application, with reference to... Figure 7The multi-frequency drive display mode includes multiple display cycles DC; the display cycle DC includes a first display frame DA (01) and a second display frame DA (02); the first display frame DA (01) is located before the second display frame DA (02); the first display frame DA (01) includes a refresh phase tf; during the refresh phase tf of the first display frame DA (01), the refresh control terminal Ctrl includes an effective level V3, and the pass signal of the pass terminal NEXT of each level shift register unit 20 and the scan signal of the scan terminal GOUT both include an effective level V5; the second display frame DA (02) The second display frame DA (02) includes a refresh phase tf and a hold phase tk. During the refresh phase tf, the refresh control terminal Ctrl includes an effective level V3, and the pass signal of the pass terminal NEXT of the partial shift register unit 20 and the scan signal of the scan terminal GOUT both include effective levels (V1 or V5). During the hold phase tk, the refresh control terminal Ctrl includes an invalid level V3', the pass signal of the pass terminal NEXT of the partial shift register unit 20 includes an effective level V1, and the scan signal of the scan terminal GOUT is an invalid level V5'.

[0059] In the multi-frequency driving mode, different areas of the display panel can have different refresh rates. The display area AA can include a low-frequency display area A02 and a high-frequency display area A01. The refresh rate of pixels located in the low-frequency display area A02 is lower than that of pixels located in the high-frequency display area A01. The multi-frequency driving mode includes at least one first display frame DA (01) and one or more second display frames DA (02). In the second display frame DA (02), pixels located in the low-frequency display area A02 are not refreshed and maintain the grayscale of the previous display frame, while pixels located in the high-frequency display area A01 can be refreshed to the grayscale of the current display frame. The second display frame DA (02) includes a refresh phase tf and a hold phase tk. The refresh phase tk refers to the phase in which the driving circuit can output effective pulses of the scanning signal to control at least some pixels P to be refreshed. The hold phase refers to the phase in which the driving circuit cannot output effective pulses of the scanning signal, but can control at least some pixels to stop refreshing and hold the grayscale of the previous display frame. In both the refresh phase tf and the hold phase tk, the shift register unit 20 is driven, that is, the shift register unit 20 outputs effective pulses of the transmission signal.

[0060] For example, the refresh control signals received by the refresh control terminal Ctrl at each level of the shift register unit 20 can be multiplexed, that is, each level of the shift register unit 20 can receive the same refresh control signal. The shift register unit 20 includes a first shift register unit 201 for providing scan signals to pixels P of the high-frequency display area A01 (e.g., Figure 7The first i shift register units 20) and the second shift register unit 202 (e.g., for providing scanning signals to pixel P of the low-frequency display area A02) Figure 7 (i+1th to zth shift register units 20). During the refresh phase tf of the first display frame DA (01), the refresh control terminal Ctrl is at an effective level V3, so that the scan signals of the scan terminals GOUT of the first shift register unit 201 and the second shift register unit 202 are synchronously output with the cascading signal of the cascading terminal NEXT to control the pixels P of the high-frequency display area A01 and the low-frequency display area A02 to be refreshed.

[0061] During the refresh phase of the second display frame DA(02), the refresh control terminal Ctrl is at an effective level V3. The scan signal of the scan terminal GOUT of the first shift register unit 201 is synchronously outputting effective pulses with the cascading signal of the cascading terminal NEXT to control the refresh of pixel P in the high-frequency display area A01. During this phase, the input terminal IN of the second shift register unit 202 has not yet received an effective pulse, and both the cascading terminal NEXT and the scan terminal GOUT of the second shift register unit 202 are at invalid levels (V1', V5'). 2) During the holding phase tk, the refresh control terminal Ctrl is at an invalid level V3', the cascading terminal NEXT of the second shift register unit 202 can output a valid pulse, and the scan signal of the scan terminal GOUT of the second shift register unit 202 remains at an invalid level V5' to control the pixel P of the low-frequency display area A02 to stop refreshing. During this phase, the first shift register unit 201 has already been driven and has also output a valid pulse. The cascading terminal NEXT and the scan terminal GOUT of the first shift register unit 201 are both at invalid levels (V1', V5'). Thus, during the holding phase tk, although the cascading terminal NEXT of the second shift register unit 202 still outputs a valid pulse of the cascading signal to ensure the sequential shifting of the input signal and the sequential driving of each shift register unit 20, the scan terminal GOUT will not output a valid pulse of the scan signal, thereby stopping the corresponding pixel P from refreshing and maintaining the data signal of the previous display frame, which is beneficial to the low power consumption of the display panel 001.

[0062] In summary, during the refresh phase tf of the first display frame DA (01), the refresh control terminal Ctrl includes an effective level V3. The transmission signals of the transmission terminals NEXT of the first shift register unit 201 and the second shift register unit 202, and the scan signals of the scanning terminal GOUT are synchronized and both include effective levels (V1, V5). Pixels P electrically connected to the first shift register unit 201 and the second shift register unit 202 can all be refreshed, that is, pixels P in both the high-frequency display area A01 and the low-frequency display area A02 are refreshed. During the refresh phase tf of the second display frame DA (02), the refresh control terminal Ctrl includes an effective level V3. The transmission signals of the transmission terminals NEXT of the first shift register unit 201 and the scan signals of the scanning terminal GOUT are synchronized and both include effective levels (V1, V5). Pixel P, which is electrically connected to the first shift register unit 201, can be refreshed, that is, pixel P in the high-frequency display area A01 is refreshed; during the holding phase tk of the second display frame DA (02), the refresh control terminal Ctrl includes an invalid level V3', the cascade terminal NEXT output by the second shift register unit 202 outputs an effective level v1 for the cascade signal, and the scanning terminal GOUT is always an invalid level V5'. Pixel P, which is electrically connected to the second shift register unit 202, stops refreshing, that is, pixel P in the low-frequency display area A02 stops refreshing. In this way, pixel P in the high-frequency display area A02 can be refreshed at a higher frequency in the display cycle DC, and pixel P in the low-frequency display area A01 can be refreshed at a lower frequency in the display cycle DC, realizing zone-frequency division and multi-frequency driving of the display panel 001.

[0063] It should be noted that the above embodiments only exemplify a display cycle DC including a first display frame DA (01) and a second display frame DA (02). The refresh frequency of the pixels located in the high-frequency display area A01 is twice the refresh frequency of the pixels located in the low-frequency display area A01, and the refresh frequency of the pixels located in the low-frequency display area A02 is reduced to half the refresh frequency of the pixels located in the high-frequency display area A01. In other optional embodiments, the display cycle DC may include a first display frame DA (01) and d second display frames DA (02) ( Figure 7 (not shown in the image), the refresh rate of the pixel located in the low-frequency display area A02 can be reduced to 1 / (d+1) of the refresh rate of the pixel located in the high-frequency display area A01; where d is a positive integer.

[0064] It should also be noted that the above embodiments only exemplify that the second display frame DA (02) includes a refresh phase tf and a hold phase tk, and the refresh phase tf is located before the hold phase tk. In other embodiments, the second display frame DA (02) may also include multiple refresh phases tf and / or multiple hold phases tk, and the display area AA may have multiple high-frequency display areas A01 and / or multiple low-frequency display areas A02; in the second display frame DA (02), the refresh phase tf may also be located after the hold phase tk, so that the high-frequency display area A01 is located below the low-frequency display area A02. That is to say, by designing the timing change of the refresh control signal of the refresh control terminal Ctrl in the second display frame DA (02), the segmented frequency driving of different display areas in the display panel 001 can be flexibly realized. Therefore, on the basis of ensuring the normal transmission drive of the shift register unit 20, it is possible to use the potential of the refresh control signal to control the scanning signal of the scanning terminal GOUT, and selectively refresh the pixel P in different display areas, so that any display area can become a high-frequency display area A01 and any display area can become a low-frequency display area A02 (similarly, the first shift register unit 201 and the second shift register unit 202 in the shift register unit 20 are also not fixed and are controlled by the timing of the refresh control signal). Among them, the pixel P in the high-frequency display area A01 can be refreshed in each display frame in the display period DC, and the pixel P in the low-frequency display area A02 can maintain the display grayscale of the first display frame DA (01) in the second display frame DA (02), thereby taking into account both display effect and power consumption performance.

[0065] In an optional embodiment, during the refresh phase tk, in the shift register unit 20 that can simultaneously output the effective level of the cascade signal and the effective level of the scan signal, the first auxiliary node NP includes an effective level and the second auxiliary node ND includes an invalid level; during the hold phase tk, in the shift register unit 20 that only outputs the effective level of the cascade signal, the first auxiliary node NP is an invalid level and the second auxiliary node ND is an effective level.

[0066] For example, taking a driving circuit comprising z cascaded shift register units 20 where both the effective level of the transmission signal and the effective level of the scan signal are high, Figure 8 This is a timing diagram of a drive control circuit under a second display frame provided in an embodiment of this application, with reference to... Figure 6 , Figure 7 and Figure 8During the refresh phase tf of the second display frame DA (02), in the first shift register unit 201, both the transmission signal of the transmission terminal NEXT and the scan signal of the scan terminal GOUT include valid levels (V1, V5). When the drive control circuit 210 controls the signal of the first drive node NA to be invalid level V2' and the signal of the second drive node NB to be valid level V2, under the control of the valid level V3 of the refresh control terminal Ctrl, the refresh control circuit 230 can control the signal of the first auxiliary node NP to be valid level V4. Under the control of the valid level V4 of the first auxiliary node NP, the isolation circuit 240 can connect the first drive node NA and the second auxiliary node ND, making the signal of the second auxiliary node ND invalid level V4'. Thus, when the refresh control circuit 230 makes the scan signal of the scan terminal GOUT output a valid level V5, the second auxiliary node ND can be invalid level V4', the reset circuit 250 stops transmitting the voltage signal of the reset voltage terminal VG24 to the scan terminal GOUT, and the first shift register unit 201 can normally output the valid pulse of the scan signal of the scan terminal GOUT.

[0067] Continue to refer to Figure 6 , Figure 7 and Figure 8 During the holding phase tk of the second display frame DA (02), in the first shift register unit 202, the transmission signal of the transmission terminal NEXT includes an effective level V1, while the scanning signal of the scanning terminal GOUT does not include an effective level V5 and is an ineffective level V5'. When the drive control circuit 210 controls the signal of the first drive node NA to be an ineffective level V2' and the signal of the second drive node NB to be an effective level V2, under the control of the ineffective level V3' of the refresh control terminal Ctrl, the refresh control circuit 230 can control the signal of the first auxiliary node NP to be an ineffective level V4'. Under the control of the ineffective level V4' of the first auxiliary node NP, the isolation circuit 240 can isolate the first drive node NA and the second auxiliary node ND, so that the signal of the second auxiliary node ND remains at an effective level V4. Thus, when the refresh control circuit 230 stops outputting the effective level V5 of the scan signal at the scan terminal GOUT, causing the scan signal at the scan terminal GOUT to be out of sync with the transmission signal at the transmission terminal NEXT, the second auxiliary node ND can be at the effective level V4. The reset circuit 250 can transmit the voltage signal of the reset voltage terminal VG24 to the scan terminal GOUT, so that the scan signal at the scan terminal GOUT is stably maintained at the ineffective level V5', which is beneficial to improving the stability and reliability of the circuit and avoiding fluctuations caused by the floating of the scan terminal GOUT.

[0068] It is understandable that during the refresh phase tf of the first display frame DA (01), in the first shift register unit 201 and the second shift register unit 202, the transmission signal of the transmission terminal NEXT and the scan signal of the scan terminal GOUT both include valid levels (V1, V5), the signal of the first driving node NA is invalid level V2', and the signal of the second driving node NB is valid level V2. Therefore, the signals of the first auxiliary node NP can all include valid level V4, and the signals of the second auxiliary node ND can all include invalid level V4'. Figure 8 (not shown in the image), the first shift register unit 201 and the second shift register unit 202 can normally output valid pulses of the scan signal of the scan terminal GOUT.

[0069] Based on the above embodiments, Figure 9 This is a schematic diagram of the circuit structure of the first type of pixel provided in an embodiment of this application. (Reference) Figure 9 Pixel P includes a driving transistor M3, a writing transistor M2, an initialization transistor M5, a storage capacitor C, and a light-emitting element LED. The writing transistor M2 and the initialization transistor M5 are electrically connected to the driving transistor M3, the storage capacitor C is electrically connected to the gate of the driving transistor M3, and the light-emitting element LED is electrically connected to the output current path of the driving transistor M3. The first terminal of the writing transistor M2 is electrically connected to the data line DL to receive the data signal Data. The second terminal of the writing transistor M2 is electrically connected to the gate of the driving transistor M3 at the first node N01, and the gate of the writing transistor M2 is electrically connected to the first scan line SPL to receive the first scan signal. The first terminal of the initialization transistor M5 receives the initialization signal Vref1. The second terminal of the initialization transistor M5 is electrically connected to the gate of the driving transistor M3 at the first node N01, and the gate of the initialization transistor M5 is electrically connected to the second scan line SN1L to receive the second scan signal. The gate of the driving transistor M3 is electrically connected to the first node N01. The first terminal of the driving transistor M3 receives the first power supply signal PVDD, and the second terminal of the driving transistor M3 is electrically connected to the first terminal of the light-emitting element LED. The second terminal of the light-emitting element LED receives the second power supply signal PVEE. One plate of the storage capacitor C receives the first power supply signal PVDD, and the other plate is electrically connected to the first node N01.

[0070] Understandably, the initialization transistor M5 is used to write the initialization signal Vref1 to the first node N01 during the initialization phase, thereby initializing the gate of the driving transistor M3; the writing transistor M2 is used to write the data signal Data on the data line DL to the first node N01 during the writing phase; the storage capacitor C is used to store the voltage signal on the first node N01 to maintain the stability of the gate potential of the driving transistor M3; and the driving transistor M3 controls the magnitude of the driving current flowing through the light-emitting element LED according to its gate potential, thereby controlling the brightness of the light-emitting element LED.

[0071] In an optional implementation, the scan line SL includes a first scan line SPL and a second scan line SN1L. The shift register circuit 20 provided in this application embodiment can be electrically connected to the second scan line SN1L to provide a second scan signal to the gate of the initialization transistor M5 in pixel P.

[0072] For example, taking the initialization transistor M5 as a P-type transistor and the effective level V5 of the scan terminal GOUT as high, refer to... Figures 6-9 During the refresh phase tk of the second display frame DA (02), the scan terminal GOUT of the first shift register unit 201 can output an effective level V5 of the scan signal to control the initialization transistor M5 to turn on, so as to write the initialization signal Vref1 into the first node N01 and initialize the gate of the driving transistor M3. During the hold phase tk of the second display frame DA (02), the scan terminal GOUT of the second shift register unit 202 can output an invalid level V5' of the scan signal to control the initialization transistor M5 to turn off, so as to stop the initialization of the gate of the driving transistor M3, and enable the first node N01 to maintain the data signal Data written in the previous display frame.

[0073] The scanning signal of the scanning terminal GOUT can be directly used to control the initialization transistor M5 in pixel P to turn on or off. Therefore, when the scanning terminal GOUT output by the shift register unit is at an invalid level, the scanning signal of the scanning terminal GOUT has high stability, which can avoid the initialization transistor M5 from being mis-turned due to fluctuations in the scanning signal of the scanning terminal GOUT. This helps to ensure that the first node N01 can stably maintain the data signal Data written in the previous display frame, thereby improving the display stability and display effect of pixel P in the low-frequency display area A02.

[0074] Based on the above embodiments, Figure 10 This is a schematic diagram of the circuit structure of the second type of pixel provided in an embodiment of this application. (Reference) Figure 10The pixel P circuit includes a driving transistor M3, an initialization transistor M5, a reset transistor M7, a threshold compensation transistor M4, a write transistor M2, a first light-emitting control transistor M1, a second light-emitting control transistor M6, a bias transistor M8, and a light-emitting element LED.

[0075] Figure 11 This is a timing diagram of a pixel provided in an embodiment of this application, which can be specifically referred to as... Figure 10 The circuit structure of the pixel is shown. (Reference) Figure 10 and Figure 11 Within a display frame cycle, the signals on the light emission control line EML, the second scan line SPL, the second scan line SN1L, the third scan line SN2L, and the reset line SP*L connected to the transistor in pixel P change sequentially to achieve pixel P initialization, threshold compensation, data writing, bias adjustment, and light emission display. The driving transistor M3 is used to provide driving current to the light-emitting element LED according to the written data signal; the initialization transistor M5 is used to receive the second scan signal of the second scan line SN1L and initialize the first node N01 using the initialization signal Vref1; the reset transistor M7 is used to receive the reset signal of the reset line SP*L and reset the third node N03 using the reset signal Vref2; the threshold compensation transistor M4 is used to receive the third scan signal of the third scan line SN2L and perform threshold voltage compensation on the driving module 10; the writing transistor M2 is used to receive the first scan signal of the first scan line SPL and write the data signal on the data line DL to the second node N03; the first light-emitting control transistor M1 and the second light-emitting control transistor M6 are used to receive the light-emitting control signal on the light-emitting control line EML and control the light-emitting current path between the driving module 10 and the light-emitting element LED to be turned on or off; the bias transistor M8 is used to receive the reset signal of the reset line SP*L and adjust the bias of the second node N02 or the third node N03 of the driving module 10 using the bias signal DVHL.

[0076] In an optional implementation, the scan line SL may include a first scan line SPL, a second scan line SN1L, a third scan line SN2L, a light emission control line EML, and a reset line SP*L. The shift register circuit 20 provided in this embodiment may also be electrically connected to the third scan line SN2L to provide a third scan signal to the gate of the compensation transistor M4 in pixel P. The scan signal of the scan terminal GOUT can be directly used to control the compensation transistor M4 in pixel P to be turned on or off. Therefore, when the scan terminal GOUT output by the shift register unit is at an invalid level, the scan signal of the scan terminal GOUT has high stability, which can avoid the scan signal of the scan terminal GOUT from fluctuating and causing the compensation transistor M4 to be mis-turned on. This helps to ensure that the first node N01 can stably maintain the data signal Data written in the previous display frame, thereby improving the display stability and display effect of pixel P in the low-frequency display area A02.

[0077] It is understood that the scan signal output from the scan terminal GOUT of the shift register circuit 20 provided in this application embodiment can be used to control the conduction or cutoff of transistors in pixel P. For example, the scan terminal GOUT of the shift register circuit 20 provided in this application embodiment can be connected to the gate of the initialization transistor M5 to control the initialization transistor M5 to conduct or cut off during the initialization phase; it can also be connected to the gate of the threshold compensation transistor M4 to control the threshold compensation transistor M4 to conduct or cut off during the compensation phase. However, it is not limited to this. In other embodiments, the scan terminal GOUT of the shift register circuit 20 provided in this application embodiment can also be connected to the gate of the write transistor M2 or the gate of other transistors that need to be controlled by the scan timing. By improving the stability of the scan signal output from the scan terminal GOUT, the conduction or cutoff of transistors in pixel P can be accurately controlled, thereby improving the display effect of the display panel 001.

[0078] Optional, Figure 12 This is a schematic diagram of the structure of the third shift register unit provided in the embodiments of this application, with reference to... Figure 12 The isolation circuit 240 includes an isolation unit 241 and an isolation auxiliary unit 242. The isolation unit 241 is electrically connected to the first driving node NA and the second auxiliary node ND, respectively. The isolation unit 241 is used to control the signal of the second auxiliary node ND according to the signal of the first driving node NA. The isolation auxiliary unit 242 is electrically connected to the first auxiliary node NP, the second auxiliary node ND and the auxiliary voltage terminal VG23, respectively. The isolation auxiliary unit 242 is used to control the signal of the second auxiliary node ND according to the signal of the first auxiliary node NP and the auxiliary voltage signal of the auxiliary voltage terminal VG23.

[0079] Specifically, the isolation circuit 240 can establish a potential relationship between the first driving node NA and the second auxiliary node ND through the isolation unit 241, and can also perform auxiliary control on the potential of the second auxiliary node ND under the control of the first auxiliary node NP through the isolation auxiliary unit 242, thereby realizing that the second auxiliary node ND and the first driving node NA are synchronized or asynchronous at least for part of the time period.

[0080] In one embodiment, the isolation unit 241 can selectively connect or disconnect the second auxiliary node ND from the first driving node NA based on the signal of the first driving node NA, thereby achieving synchronization or desynchronization between the second auxiliary node ND and the first driving node NA. (See reference) Figure 4 , Figure 5 and Figure 12 When the first driving node NA is at an effective level V2, the isolation unit 241 can control the second auxiliary node ND to also be at an effective level V4, so that the first driving node NA and the second auxiliary node ND are synchronized. For example, during the period when the transmission signal of the transmission end NEXT is at an ineffective level V1' and the scan signal of the scan end GOUT is at an ineffective level V5', the first driving node NA can be at an effective level V2, and the second auxiliary node ND can also be at an effective level V2. When the first driving node NA is at an effective level V2 and the transmission signal of the transmission end NEXT is at an ineffective level V1', the second auxiliary node ND can be at an effective level V2, thereby continuously transmitting the voltage signal of the reset voltage terminal VG24 to the scan end GOUT through the reset circuit 250, stabilizing the scan signal of the scan end GOUT to an ineffective level V5', ensuring the stability of the scan signal when the transmission signal of the transmission end NEXT is at an ineffective level V1' and the scan signal of the scan end GOUT is at an ineffective level V5'.

[0081] Continue to refer to Figure 4 , Figure 5 and Figure 12 When the first driving node NA is at an invalid level V2', the isolation unit 241 can disconnect the connection between the first driving node NA and the second auxiliary node ND, causing the second auxiliary node ND to float. The second auxiliary node ND remains at an effective level V4. Even if the first driving node NA and the second auxiliary node ND are out of sync, for example, during the period when the cascading signal of the cascading end NEXT outputs an effective pulse but the scanning signal of the scanning end GOUT does not output an effective pulse, the first driving node NA is at an invalid level V2', which is beneficial for the cascading end NEXT to output an effective level. The second auxiliary node ND being at an effective level V4 can ensure the stability when the scanning end GOUT is at an invalid level, so as to control the reset circuit 250 to be turned on, thereby making the scanning signal of the scanning end GOUT stably maintain an invalid level V5'.

[0082] Thus, when the first driving node NA is at an effective level V2, the isolation unit 241 can synchronize the second auxiliary node ND with the first driving node NA to an effective level V2. It can also disconnect the connection between the second auxiliary node ND and the first driving node NA when the first driving node NA is at an ineffective level V2', and continue to maintain an effective level V2. The potential of the second auxiliary node ND is no longer completely limited by the first driving node NA, which is beneficial to continuously control the reset circuit 250 to conduct when the scan signal of the scan end GOUT is at an ineffective level V5', thereby improving the stability when the scan signal of the scan end GOUT is at an ineffective level V5'.

[0083] In another embodiment, the isolation auxiliary unit 242 can perform auxiliary control on the potential of the second auxiliary node ND based on the signal of the first auxiliary node NP and the auxiliary voltage signal of the auxiliary voltage terminal VG23. When the first auxiliary node NP is at an active level V2, the isolation auxiliary unit 242 can control the second auxiliary node ND to be at an inactive level V4'; when the first auxiliary node NP is at an inactive level V2', the isolation auxiliary unit 242 can control the second auxiliary node ND to be at an active level V4. That is, the isolation auxiliary unit 242 can perform reverse control on the second auxiliary node ND according to the potential change of the first auxiliary node NP, so that the first auxiliary node NP and the second auxiliary node ND correspond to different potential states.

[0084] For example, continue to refer to Figure 4 , Figure 5 and Figure 12 During the period when the scanning end GOUT does not output a valid pulse (including the period when the transmission end NEXT is at an invalid level V1' and the period when the transmission end NEXT is at an valid level V1), the first auxiliary node NP can be at an invalid level V2', and the second auxiliary node ND can be at a valid level V2, turning on the reset circuit 250, thereby keeping the scanning signal of the scanning end GOUT stably at an invalid level V5'; during the period when the scanning end GOUT outputs a valid pulse, the first auxiliary node NP can be at a valid level V2, and the second auxiliary node ND can be at an invalid level V2', turning off the reset circuit 250, thereby enabling the scanning signal of the scanning end GOUT to output a valid level V5. Thus, the isolation auxiliary unit 242 can work with the isolation unit 241 to further optimize the control logic of the second auxiliary node ND, improving the stability of the scanning signal of the scanning end GOUT.

[0085] In summary, by configuring the isolation circuit 240, which includes an isolation unit 241 and an isolation auxiliary unit 242, it is possible to connect the first driving node NA and the second auxiliary node ND for at least a portion of the time, and also to isolate them for at least a portion of the time. Simultaneously, it is possible to perform auxiliary control on the potential of the second auxiliary node ND based on the first auxiliary node NP. Thus, when the cascade terminal NEXT and the scanning terminal GOUT synchronously output valid pulses, the reset circuit 250 is ensured to be off; when the scanning terminal GOUT remains at an invalid level V5', the reset circuit 250 is ensured to be on, thereby enabling the scanning terminal GOUT to output valid pulses normally. When no valid pulses are output, the invalid level V5' is stably maintained, thereby improving the operational reliability and display stability of the shift register unit.

[0086] In an alternative embodiment, Figure 13 This is a schematic diagram of the structure of the fourth shift register unit provided in the embodiments of this application, with reference to... Figure 13 The isolation unit 241 includes an isolation transistor T22; the first terminal and gate of the isolation transistor T22 are both coupled to the first driving node NA, and the second terminal of the isolation transistor T22 is electrically connected to the second auxiliary node ND.

[0087] The coupling can be a direct electrical connection or an indirect electrical connection. Specifically, the first terminal and gate of the blocking transistor T22 can be directly connected to the first driving node NA, or they can be electrically connected to the first driving node NA through other conductive nodes or structures. The blocking transistor T22 can control the conduction or isolation relationship between the first driving node NA and the second auxiliary node ND according to the signal state of the first driving node NA.

[0088] Specifically, short-circuiting the first terminal and gate of the isolation transistor T22 can form a diode connection of the transistor. The first terminal of the isolation transistor T22 is equivalent to the negative terminal of the diode, and the second terminal of the isolation transistor T22 is equivalent to the positive terminal of the diode.

[0089] For example, taking the blocking transistor T22 as a P-type transistor, with active levels V2 and V4 being low and inactive levels V2' and V4' being high, refer to... Figure 3 , Figure 4 and Figure 13During the period when the transmission terminal NEXT is at an invalid level V1' and the scan terminal GOUT is at an invalid level V5', the first driving node NA is at a valid low level (valid level V2), which disconnects the conduction between the first and second terminals of the isolation transistor T22, synchronizing the second auxiliary node ND with the first driving node NA. The signal of the second auxiliary node ND can also be at a low level (valid level V4). At this time, the reset circuit 250 can be turned on under the control of the second auxiliary node ND and continuously transmit the voltage signal of the reset voltage terminal VG24 to the scan terminal GOUT, thereby ensuring that when the transmission signal of the transmission terminal NEXT is at an invalid level V1' and the scan signal of the scan terminal GOUT is at an invalid level V5', the scan signal of the scan terminal GOUT can be stably maintained at an invalid level V5'.

[0090] During the period when the cascading terminal NEXT is at an active level V1 and the scanning terminal GOUT is at an inactive level V5', in order for the cascading circuit to output the active level of the cascading terminal NEXT normally, the first driving node NA is at an inactive high level (inactive level V2'). At this time, the first and second terminals of the blocking transistor T22 are cut off, thus isolating the first driving node NA from the second auxiliary node ND. The second auxiliary node ND no longer follows the potential change of the first driving node NA, but can continue to remain at a low level (active level V24). In this way, the reset circuit 250 can still remain on under the control of the second auxiliary node ND and continuously provide the reset voltage signal VG24 to the scanning terminal GOUT, thereby making the scanning terminal GOUT stably maintain an inactive level V5' and preventing the scanning terminal GOUT from being in a floating state.

[0091] It is understood that the blocking transistor T22 can be a P-type transistor or an N-type transistor. The type of transistor can be set according to actual needs, and this application embodiment does not limit this.

[0092] Optional, Figure 14 This is a schematic diagram of the structure of the fifth shift register unit provided in the embodiments of this application, with reference to... Figure 14 The drive control circuit 210 includes a first drive unit 211 and a second drive unit 212. The first drive unit 211 is electrically connected to the input terminal IN, the first clock terminal CK, and the first drive node NA, respectively. The first drive unit 211 is used to control the signal of the first drive node NA according to the input signal of the input terminal IN and the first clock signal of the first clock terminal CK. The second drive unit 212 is electrically connected to the first drive node NA, the first clock terminal CK, and the second drive node NB. The second drive unit 212 is used to control the signal of the second drive node NB according to the signal of the first drive node NA and the first clock signal of the first clock terminal CK.

[0093] Example, reference Figure 14The first driving unit 211 includes a first input transistor T4 and a first driving transistor T8. The gate of the first input transistor T4 receives a first clock signal, its first terminal receives an input signal, and its second terminal is electrically connected to the input node N1. The first terminal of the first driving transistor T8 is electrically connected to the input node N01, its gate is connected to the second voltage terminal VGL, and its second terminal is electrically connected to the first driving node NA. The first input transistor T4 can be turned on or off under the control of the first clock signal. When the first input transistor T4 is on, it transmits the input signal from the input terminal IN to the first driving node NA. Under normal conditions, the first driving transistor T8 is on. Furthermore, the first driving transistor T8 can protect the device electrically connected to the other node when the potential of either the input node N1 or the first driving node NA is abnormal. The first driving unit 211 can control the first driving node NA to switch between an effective level V2 and an ineffective level V2' according to the input signal and the first clock signal.

[0094] For example, please refer to the following: Figure 14 The second driving unit 212 includes a first control transistor T5, a second control transistor T2, a third control transistor T1, a fourth control transistor T3, a fifth control transistor T6, a sixth control transistor T7, and a second capacitor C2. The gate of the first control transistor T5 receives a first clock signal, its first terminal is connected to the second voltage terminal VGL, and its second terminal is electrically connected to node N3. The gate of the second control transistor T2 is electrically connected to the input node N1, its first terminal receives the first clock signal, and its second terminal is electrically connected to node N3. The first terminal of the third control transistor T1 is electrically connected to node N3, its gate is connected to the second voltage terminal VGL, and its second terminal is electrically connected to node N4. The second capacitor C2 is connected between nodes N4 and N2. The gate of the fourth control transistor T3 is electrically connected to node N4, its first terminal is electrically connected to node N2, and its second terminal receives the second clock signal from the second clock terminal XCK. The gate of the fifth control transistor T6 is electrically connected to the first driving node NA, the first terminal of the fifth control transistor T6 receives the first voltage terminal VGH, and the second terminal of the fifth control transistor T6 is electrically connected to the second driving node NB. The first terminal of the sixth control transistor T7 is electrically connected to node N2, and the second terminal of the sixth control transistor T7 is electrically connected to the second driving node NB.

[0095] The first control transistor T5 can be turned on or off under the control of the first clock signal, and when the first control transistor T5 is turned on, it transmits the voltage signal of the second voltage terminal VGL to node N3; the second control transistor T2 can be turned on or off under the joint control of the signal from the input node N1 and the first clock signal, and when the second control transistor T2 is turned on, it transmits the first clock signal to node N3; the third control transistor T1 can protect the devices electrically connected to the other node when the potential of either node N3 or node N4 is abnormal. The second capacitor C2 is used to maintain the potential difference between node N4 and node N2 to enhance the coupling effect of the second driving unit 212 and improve the speed and stability of the second driving node NB during switching.

[0096] The fourth control transistor T3 can be turned on or off according to the signal from node N4, and when the fourth control transistor T3 is on, it transmits the second clock signal to node N2; the fifth control transistor T6 can be turned on or off according to the signal from input node N1, and when the fifth control transistor T6 is on, it transmits the voltage signal of the first voltage terminal VGH to the second driving node NB; the sixth control transistor T7 can transmit the potential at node N2 to the second driving node NB. Thus, the second driving unit 212 can control the second driving node NB to switch between the active level V2 and the inactive level V2' according to the signal from the first driving node NA, the first clock signal, and the voltage signals from the relevant voltage terminals.

[0097] It is understood that the second driving unit 212 can be coupled to the first driving node NA, where the coupling can be a direct electrical connection or an indirect electrical connection, enabling the basic function of controlling the second driving node NB based on the signal from the first driving node NA. In practical applications, the second driving unit 212 can also be electrically connected to other nodes or ports as needed to further optimize the switching process and potential stability of the second driving node NB. Furthermore, the driving control circuit 210 may also include a first capacitor C1, connected to the second driving node NB and the first voltage terminal VGH, which helps improve the potential stability of the second driving node NB.

[0098] In one embodiment, the second driving unit 212 may retain only the basic connection relationships related to the first driving node NA, the first clock terminal CK, and the second driving node NB, thereby realizing the basic function of controlling the second driving node NB according to the signal of the first driving node NA. Furthermore, the gate and first electrode of the blocking transistor T22 may also be directly electrically connected to the first driving node NA, thereby enabling the blocking transistor T22 to directly control the signal of the second auxiliary node ND according to the signal of the first driving node NA. This configuration also enables the control requirement of synchronizing or desynchronizing the first driving node NA and the second auxiliary node ND at least for a portion of the time, thus achieving the basic technical effect of this application.

[0099] Optional, Figure 15 This is a schematic diagram of the sixth shift register unit provided in the embodiments of this application, with reference to... Figure 15 The first driving unit 211 includes an input subunit 2111, an input auxiliary subunit 2112, and a pull-down auxiliary subunit 2113. The input subunit 2111 is electrically connected to the input terminal IN, the first clock terminal CK, and the first driving node NA, respectively. The input subunit 2111 is used to control the signal of the first driving node NA according to the input signal of the input terminal IN and the first clock signal of the first clock terminal CK. The input auxiliary subunit 2112 is electrically connected to the input terminal IN, the first clock terminal, and the first pull-down node N_1, respectively. The input auxiliary subunit 2112 is used to control the signal of the first driving node NA according to the input signal of the input terminal IN and the first clock signal of the first clock terminal CK. The input signal IN and the first clock signal of the first clock terminal CK control the signal of the first pull-down node N_1; the pull-down auxiliary subunit 2113 is electrically connected to the first pull-down node N_1, the second clock terminal XCK and the first drive node NA respectively; the pull-down auxiliary subunit 2113 is used to control the signal of the first drive node NA according to the signal of the first pull-down node N_1 and the second clock signal of the second clock terminal XCK; wherein, the absolute value of the voltage when the signal of the first pull-down node N_1 is at an invalid level is greater than the absolute value of the voltage when the signal of the first drive node NA is at an invalid level.

[0100] For example, the input subunit 2111 may include a first input transistor T4 and a first driving transistor T8. The gate of the first input transistor T4 receives a first clock signal, its first terminal receives an input signal, and its second terminal is electrically connected to the input node N1; the first terminal of the first driving transistor T8 is electrically connected to the input node N1, its gate receives a second voltage terminal VGL, and its second terminal is electrically connected to the first driving node NA. Therefore, the input subunit 2111 can write the input signal to the input node N1 and control the potential of the first driving node NA under the control of the first clock signal.

[0101] The input auxiliary subunit 2112 may include a second input transistor T14 and a transmission transistor T15. The gate of the second input transistor T14 receives a first clock signal, the first terminal receives the input signal, and the second terminal is electrically connected to the input auxiliary node N1'. The first terminal of the transmission transistor T15 is electrically connected to the input auxiliary node N1', the second terminal is electrically connected to the first pull-down node N_1, and the gate receives the second voltage terminal VGL. In this way, under the control of the first clock signal, the input auxiliary subunit 2112 can first transmit the input signal to the input auxiliary node N1', and then transmit it to the first pull-down node N_1 via the transmission transistor T15, thereby establishing the potential state of the first pull-down node N_1.

[0102] The pull-down auxiliary subunit 2113 can be electrically connected to the first pull-down node N_1, the second clock terminal XCK, and the first drive node NA. It is used to perform auxiliary pull-down control on the first drive node NA based on the signal from the first pull-down node N_1 and the second clock signal from the second clock terminal XCK. Therefore, after the input signal at the input terminal IN and the first clock signal establish the potential of the first pull-down node N_1, the pull-down auxiliary subunit 2113 can further control the potential change of the first drive node NA with the cooperation of the second clock signal.

[0103] By introducing an input auxiliary subunit 2112, a pull-down auxiliary subunit 2113, and a first pull-down node N_1 into the first driving unit 211, the pull-down capability of the first driving node NA can be enhanced. When both the first pull-down node N_1 and the first driving node NA are at the active level V2, the absolute value of the voltage of the first pull-down node N_1 when it is at the inactive level is greater than the absolute value of the voltage of the first driving node NA when its signal is at the inactive level; that is, the potential of the first pull-down node N_1 is lower than that of the first driving node NA. Thus, the first pull-down node N_1 can provide a stronger pull-down reference for the first driving node NA, which is beneficial for the first driving node NA to be pulled down quickly and fully to the active level, thereby improving the switching speed and stability of the first driving node NA. Therefore, by setting up the input subunit 2111, the input auxiliary subunit 2112, and the pull-down auxiliary subunit 2113, it is possible not only to establish the first driving node NA with the input signal, but also to perform auxiliary pull-down control on the first driving node NA through the first pull-down node N_1, so that the first driving node NA has better stability and reliability when switching between the effective level V2 and the ineffective level V2'.

[0104] In one embodiment, reference Figure 15The pull-down auxiliary subunit 2113 includes a first pull-down transistor T16, a second pull-down transistor T11, and a pull-down coupling capacitor C3. The first terminal and gate of the first pull-down transistor T16 are electrically connected to the first plate of the pull-down coupling capacitor C3 at the first pull-down node N_1, and the second terminal of the first pull-down transistor T16 is electrically connected to the first driving node NA. The first terminal of the second pull-down transistor T11 is electrically connected to the second clock terminal XCK, and the second terminal of the second pull-down transistor T11 is electrically connected to the second plate of the pull-down coupling capacitor C3 at the second pull-down node N_2. The gate of the second pull-down transistor T11 is electrically connected to the first pull-down node N_1.

[0105] Specifically, the first pull-down transistor T16 can be turned on or off under the signal control of the first pull-down node N_1. When the first pull-down transistor T16 is turned on, it transmits the potential of the first pull-down node N_1 to the first driving node NA, thereby pulling down the first driving node NA. The second pull-down transistor T11 can be turned on or off under the signal control of the first pull-down node N_1. When the second pull-down transistor T11 is turned on, it transmits the second clock signal to the second pull-down node N_2. The pull-down coupling capacitor C3 is connected between the first pull-down node N_1 and the second pull-down node N_2. It is used to drive the potential of the first pull-down node N_1 to change further through coupling when the potential of the second pull-down node N_2 changes. Thus, after the first pull-down node N_1 establishes an effective level, the pull-down auxiliary subunit 2113 can further enhance the pull-down capability of the first driving node NA with the cooperation of the second clock signal.

[0106] For example, when the first pull-down node N_1 is at an active level and the second pull-down transistor T11 is turned on, the transition of the second clock signal will be coupled to the first pull-down node N_1 through the second pull-down node N_2 and the pull-down coupling capacitor C3, further reducing the potential of the first pull-down node N_1. At this time, the first pull-down transistor T16 continues to be turned on, thereby transmitting this lower potential to the first driving node NA, allowing the first driving node NA to be pulled down more fully to an active level. In other words, the pull-down auxiliary subunit 2113 can not only establish a pull-down path between the first pull-down node N_1 and the first driving node NA, but also enhance the pull-down depth of the first driving node NA by utilizing the coupling effect of the second clock signal and the pull-down coupling capacitor C3.

[0107] By introducing a first pull-down node N_1 and a pull-down auxiliary subunit 2113, when both the first pull-down node N_1 and the first drive node NA are at active levels, the potential of the first pull-down node N_1 can be lower than that of the first drive node NA. Thus, the first pull-down node N_1 can provide a stronger pull-down reference for the first drive node NA, which facilitates the rapid and sufficient pull-down of the first drive node NA to an active level, improving the switching speed and stability of the first drive node NA.

[0108] In an alternative implementation, continue to refer to Figure 15 The pull-down auxiliary subunit 2113 may further include a third pull-down transistor T12. The gate of the third pull-down transistor T12 is electrically connected to node N3, the first terminal receives the first voltage terminal VGH, and the second terminal is electrically connected to the second pull-down node N_2. The third pull-down transistor T12 can be used in conjunction with the first pull-down transistor T16, the second pull-down transistor T11, and the pull-down coupling capacitor C3 to assist in establishing or adjusting the potential of the second pull-down node N_2, thereby further improving the pull-down effect of the first pull-down node N_1 on the first driving node NA.

[0109] For example, when the first pull-down node N_1 is in a non-conducting control state, the third pull-down transistor T12 can pre-charge or raise the potential of the second pull-down node N_2 to cooperate with the coupling effect of the pull-down coupling capacitor C3 and reduce the adverse effect of the second clock signal on the first pull-down node N_1 during non-target periods. During the target pull-down period, the second pull-down transistor T11 and the pull-down coupling capacitor C3 can use the second clock signal to further couple and pull down the first pull-down node N_1. Thus, the third pull-down transistor T12 can cooperate with the first pull-down transistor T16, the second pull-down transistor T11, and the pull-down coupling capacitor C3 to enhance the pull-down capability and improve the potential stability of the first pull-down node N_1 and the first driving node NA.

[0110] In another alternative implementation, refer to Figure 15 The first terminal of the isolation transistor T22 is electrically connected to the first driving node NA; the gate of the isolation transistor T22 is electrically connected to the first pull-down node N_1.

[0111] For example, taking the blocking transistor T22 as a P-type transistor, with both the effective level V2 of the first driving node NA and the effective level V4 of the second auxiliary node ND being low, the blocking transistor T22 can be turned on or off according to the signal of the first pull-down node N_1. When the blocking transistor T22 is on, it transmits the potential of the first driving node NA to the second auxiliary node ND. Since the potential of the first pull-down node N_1 is lower than that of the first driving node NA, using the first pull-down node N_1 to control the gate of the blocking transistor T22 is beneficial to make the blocking transistor T22 conduct more fully, thereby making the potential of the second auxiliary node ND even lower. In this way, it can be avoided that when the gate of the blocking transistor T22 is directly connected to the first driving node NA, the potential of the second auxiliary node ND is affected by the threshold voltage and satisfies ND=NA+|Vth|, which is not conducive to the reset circuit 250 transmitting the reset voltage signal to the scan terminal GOUT. By connecting the gate of the isolation transistor T22 to the first pull-down node N_1, which has a lower potential, the second auxiliary node ND can be pulled down more fully, which is beneficial to the stable conduction of the reset module and maintains the stability of the scan signal at the scan terminal GOUT when it is at the invalid level V5'.

[0112] Optional, Figure 16 This is a schematic diagram of the structure of the seventh shift register unit provided in the embodiments of this application, with reference to... Figure 16 The first terminal and gate of the isolation transistor T22 are both electrically connected to the first pull-down node N_1.

[0113] Specifically, the isolation transistor T22 can directly control the signal of the second auxiliary node ND based on the signal of the first pull-down node N_1, and when the isolation transistor T22 is turned on, it directly transmits the potential of the first pull-down node N_1 to the second auxiliary node ND. Since the potential of the first pull-down node N_1 itself is lower than that of the first driving node NA, compared to the method where the first terminal of the isolation transistor T22 is connected to the first driving node NA, the method where both the first terminal and the gate of the isolation transistor T22 are connected to the first pull-down node N_1 allows the second auxiliary node ND to obtain an even lower potential. This is more conducive to the reset module stably transmitting the reset voltage signal of the reset voltage terminal VG24 to the scan terminal GOUT, thereby improving the stability of the scan signal of the scan terminal GOUT when it is at the invalid level V5', and avoiding fluctuations in the scan signal of the scan terminal GOUT due to insufficient reset.

[0114] It is understandable that connecting the first terminal of the isolation transistor T22 to the first driving node NA and its gate to the first pull-down node N_1, or connecting both the first terminal and the gate of the isolation transistor T22 to the first pull-down node N_1, allows for more effective pull-down control of the second auxiliary node ND by utilizing the lower potential of the first pull-down node N_1. Compared to the method where the gate of the isolation transistor T22 is directly connected to the first driving node NA, both connection methods avoid the potential of the second auxiliary node ND being limited by both the first driving node NA and the threshold voltage. This facilitates the reset circuit 250 in continuously and stably transmitting the reset voltage signal to the scan terminal GOUT when the scan signal at the scan terminal GOUT is at an invalid level V5', thereby improving the operational reliability of the shift register unit and the stability of the scan signal.

[0115] Optional, Figure 17 This is a schematic diagram of the eighth shift register unit provided in the embodiments of this application, with reference to... Figure 17 The isolation auxiliary unit 242 includes an isolation auxiliary transistor T23; the first terminal of the isolation auxiliary transistor T23 is electrically connected to the auxiliary voltage terminal VG23, the second terminal of the isolation auxiliary transistor T23 is electrically connected to the second auxiliary node ND, and the gate of the isolation auxiliary transistor T23 is electrically connected to the first auxiliary node NP; wherein, the signal of the auxiliary voltage terminal VG23 is the invalid level V2' of the second auxiliary node ND.

[0116] Specifically, the isolation auxiliary transistor T23 can be turned on or off according to the signal of the first auxiliary node NP. When the isolation auxiliary transistor T23 is on, it transmits the voltage signal of the auxiliary voltage terminal VG23 to the second auxiliary node ND. The signal of the auxiliary voltage terminal VG23 is the invalid level V2' of the second auxiliary node ND. Therefore, when the isolation auxiliary transistor T23 is on, the second auxiliary node ND can be established as the invalid level V2'; when the isolation auxiliary transistor T23 is off, the second auxiliary node ND no longer receives the voltage signal of the auxiliary voltage terminal VG23.

[0117] In one embodiment, when the first auxiliary node NP is at an active level V2, the auxiliary transistor T23 is turned off, thereby transmitting the inactive level V2' of the auxiliary voltage terminal VG23 to the second auxiliary node ND, making the second auxiliary node ND inactive level V2'. Thus, the reset circuit can stop transmitting the reset voltage signal to the scan terminal GOUT when the second auxiliary node ND is inactive level V2', thereby releasing the low-level holding of the scan signal at the scan terminal GOUT, allowing the scan signal at the scan terminal GOUT to jump to an active level V5 when the stage transmission signal at the stage transmission terminal NEXT is at an active level V1.

[0118] During the refresh phase, for the shift register unit 20 that can output a valid pulse of the cascade signal from the cascade terminal NEXT, the first auxiliary node NP can be at a valid level V2. At this time, the auxiliary transistor T23 is turned on, and the second auxiliary node ND is controlled to be at an invalid level V2'. The reset circuit stops providing a reset voltage signal to the scan terminal GOUT. As a result, the scan signal of the scan terminal GOUT is no longer pulled low by the reset path, and can output a valid level (V1 or V5) synchronously with the cascade signal of the cascade terminal NEXT under the control of the refresh control circuit, so that the pixel electrically connected to the shift register unit can be refreshed normally.

[0119] It is understandable that by setting the isolation auxiliary transistor T23, an inverse control relationship can be established between the first auxiliary node NP and the second auxiliary node ND. That is, when the first auxiliary node NP is at an active level V2, the isolation auxiliary transistor T23 is turned on, and the second auxiliary node ND is at an inactive level V2'; when the first auxiliary node NP is at an inactive level V2', the isolation auxiliary transistor T23 is turned off, and the second auxiliary node ND is no longer directly controlled by the auxiliary voltage terminal VG23. This facilitates the timely shutdown of the reset circuit 250 during the period when the scan terminal GOUT outputs an active level V5, thereby preventing the reset path from continuing to provide a low-level signal to the scan terminal GOUT and ensuring that the scan terminal GOUT can stably output active pulses.

[0120] In one implementation, Figure 18 This is a schematic diagram of the ninth shift register unit provided in the embodiments of this application, with reference to... Figure 18 The isolation auxiliary transistor T23 is a dual-gate transistor.

[0121] Specifically, compared to a single-gate transistor, using a dual-gate transistor as the isolation auxiliary transistor T23 enhances the control capability of the isolation auxiliary transistor T23 over the channel, thereby reducing the leakage current of the device in the off state. Thus, when the isolation auxiliary transistor T23 is turned off, the leakage current between the auxiliary voltage terminal VG23 and the second auxiliary node ND can be reduced, preventing the potential of the second auxiliary node ND from drifting due to leakage current.

[0122] By setting the isolation auxiliary transistor T23 as a dual-gate transistor, the potential stability of the second auxiliary node ND can be improved, allowing the second auxiliary node ND to more accurately maintain the target level in different operating stages. Especially during the stage when the scan signal at the scan terminal GOUT remains at the invalid level V5', improving the potential stability of the second auxiliary node ND is beneficial to the stable operation of the reset circuit 250, thereby further improving the stability of the scan signal and the operational reliability of the shift register unit.

[0123] In another embodiment, Figure 19This is a schematic diagram of the tenth shift register unit provided in the embodiments of this application, with reference to... Figure 19 The isolation auxiliary unit 242 also includes an isolation transistor T29; the first terminal of the isolation transistor T29 is electrically connected to the second terminal of the isolation auxiliary transistor T23, the second terminal of the isolation transistor T29 is electrically connected to the second auxiliary node ND, and the gate signal of the isolation transistor T29 is an effective level V2.

[0124] For example, the gate of isolation transistor T29 can be connected to a second voltage terminal VGL, and the potential of the second voltage terminal VGL can be an effective level V2. The gate signal of isolation transistor T29 is also an effective level V2, allowing it to remain on, thereby establishing a transmission path between the isolation auxiliary transistor T23 and the second auxiliary node ND. Thus, the potential output from the isolation auxiliary transistor T23 to the second auxiliary node ND no longer directly acts on the second auxiliary node ND, but is transmitted via the isolation transistor T29. Since there is a certain voltage difference between the source and drain of isolation transistor T29, a voltage buffer can be formed between the isolation auxiliary transistor T23 and the second auxiliary node ND.

[0125] By setting an isolation transistor T29 between the isolation auxiliary transistor T23 and the second auxiliary node ND, the voltage difference between the gate and the second electrode of the isolation auxiliary transistor T23 can be reduced. For example, taking the invalid level V2' as high and the effective level V2 as low, when the first auxiliary node NP is high (invalid level V2') and the second auxiliary node ND is low (effective level V2), if the second electrode of the isolation auxiliary transistor T23 is directly electrically connected to the second auxiliary node ND, there may be a large voltage difference between the gate and the second electrode of the isolation auxiliary transistor T23. However, by setting the isolation transistor T29, the voltage drop across the isolation transistor T29 can share this voltage difference, thereby avoiding the isolation auxiliary transistor T23 from bearing an excessively large voltage difference between its gate and the second electrode. In this way, on the one hand, it helps to reduce the risk of overvoltage damage to the isolation auxiliary transistor T23 and improve the reliability of the device; on the other hand, it also helps to improve the overall working stability of the isolation auxiliary unit 242, thereby further ensuring the accurate potential control of the second auxiliary node ND and ensuring that the reset circuit 250 can be stably turned on or off during the corresponding working stage.

[0126] Optional, Figure 20 This is a schematic diagram of the eleventh shift register unit provided in the embodiments of this application, with reference to... Figure 20The refresh control circuit 230 includes a control unit 231, a synchronization unit 232, and a refresh unit 233. The control unit 231 is electrically connected to the cascading terminal, the refresh control terminal, and the refresh control node N7, respectively. The control unit 231 is used to control the signal of the refresh control node N7 according to the cascading signal of the cascading terminal NEXT and the refresh control terminal Ctrl of the refresh control terminal. The synchronization unit 232 is electrically connected to the refresh control node N7, the second drive node NB, and the first auxiliary node NP, respectively. The synchronization unit 232 is used to control the signal of the first auxiliary node NP according to the signal of the refresh control node N7 and the signal of the second drive node NB. The refresh unit 233 is electrically connected to the first auxiliary node NP, the refresh voltage terminal VG25, and the scan terminal, respectively. The refresh unit 233 is used to control the scan signal of the scan terminal GOUT according to the signal of the first auxiliary node NP and the refresh voltage signal of the refresh voltage terminal VG25.

[0127] Specifically, control unit 231 controls the signal of refresh control node N7 based on the refresh control signal of refresh control terminal Ctrl and the cascading signal of cascading terminal NEXT. In one embodiment, when the cascading signal of cascading terminal NEXT is at an invalid level V1', control unit 231 can write refresh control terminal Ctrl to refresh control node N7, that is, the potential of refresh control node N7 can jump synchronously with the potential of refresh control terminal Ctrl; when the cascading signal of cascading terminal NEXT has jumped to an effective level V1, control unit 231 stops writing refresh control terminal Ctrl to refresh control node N7, the potential of refresh control terminal Ctrl stops jumping, and the potential of refresh control node N7 remains synchronized with the potential of refresh control terminal Ctrl. In this way, it is possible to avoid refresh control terminal Ctrl continuing to write to refresh control node N7 while the cascading signal of cascading terminal NEXT is at an effective level V1, thereby avoiding incomplete effective pulses output by scan signal of scan terminal GOUT, which is beneficial to ensuring the integrity and stability of scan signal output by scan terminal GOUT.

[0128] Synchronization unit 232 is used, under the control of refresh control node N7, to selectively synchronize or desynchronize the signal of the first auxiliary node NP with the signal of the second drive node NB. In one embodiment, when refresh control node N7 is at an active level, synchronization unit 232 can synchronize the first auxiliary node NP with the second drive node NB; when refresh control node N7 is at an inactive level, synchronization unit 232 can desynchronize the first auxiliary node NP with the second drive node NB. Thus, refresh control node N7 can determine whether the first auxiliary node NP follows the change of the second drive node NB, thereby further determining whether the scan signal of the scan terminal GOUT is synchronized with the cascading signal of the cascading terminal NEXT. Optionally, synchronization unit 232 can also be electrically connected to the first drive node NA and / or to the cascading terminal NEXT to further optimize the establishment process and potential stability of the first auxiliary node NP according to actual design requirements.

[0129] The refresh unit 233 is used to control the output state of the scanning terminal GOUT according to the signal of the first auxiliary node NP. For example, the refresh unit 233 can be an output transistor. When the first auxiliary node NP is at an active level V4, the refresh unit 233 is turned on, transmitting the refresh voltage signal of the refresh voltage terminal VG25 to the scanning terminal GOUT, thereby causing the scanning terminal GOUT to output an active level V5, thus refreshing one row of pixels connected to the scanning terminal GOUT. When the first auxiliary node NP is at an inactive level V4', the refresh unit 233 is turned off, and the scanning terminal GOUT does not output an active level V5, but remains at an inactive level V5'. It should be noted that the scanning terminal GOUT not outputting an active level V5 does not necessarily mean that the display frame is in the hold phase; it may simply mean that the current pass signal of the pass terminal NEXT has not yet changed to an active level V1, and the corresponding row of pixels has not yet reached the refresh time.

[0130] It is understandable that by setting up control unit 231, synchronization unit 232, and refresh unit 233, a hierarchical control relationship can be formed between refresh control terminal Ctrl, refresh control node N7, first auxiliary node NP, and scan terminal GOUT. Specifically, control unit 231 determines the signal of refresh control node N7 based on the refresh control signal of refresh control terminal Ctrl and the transmission signal of transmission terminal NEXT; synchronization unit 232 determines whether the first auxiliary node NP is synchronized with the second drive node NB based on the signal of refresh control node N7; and refresh unit 233 determines whether the scan signal of scan terminal GOUT is at a valid level V5 based on the signal of first auxiliary node NP. In this way, it is possible to selectively control whether the scan signal of scan terminal GOUT is synchronized or not synchronized with the transmission signal of transmission terminal NEXT.

[0131] For example, refer to Figure 3 , Figure 4 and Figure 20 When the transmission signal at the transmission terminal NEXT is at an invalid level V1' and the refresh control signal at the refresh control terminal Ctrl is at an active level V3, the control unit 231 is turned on, the refresh control node N7 is at an active level, and the first auxiliary node NP and the second drive node NB are synchronized. If the second drive node NB jumps to an active level V2, the transmission signal at the transmission terminal NEXT jumps to an active level V1, the control unit 231 is turned off, the refresh control node N7 remains at an active level, the first auxiliary node NP jumps to an active level V4, turning on the refresh unit 233, thereby controlling the scan signal at the scan terminal GOUT to synchronize with the transmission signal at the transmission terminal NEXT. The output is valid (V1 or V5). When the cascading signal at the cascading end NEXT is invalid (V1') and the refresh control signal at the refresh control end Ctrl is invalid (V3'), the control unit 231 is turned on. When the refresh control node N7 is invalid and the first auxiliary node NP and the second drive node NB are out of sync, even if the second drive node NB jumps to valid (V2), the cascading signal at the cascading end NEXT outputs valid (V1), the refresh control node N7 remains invalid, and the first auxiliary node NP remains invalid, keeping the refresh unit 233 off. This ensures that the scan signal at the scan end GOUT remains invalid (V5'). Thus, a segmented frequency drive effect can be achieved where some pixels are refreshed and others are not in the same display frame.

[0132] By configuring the refresh control circuit 230, including the control unit 231, the synchronization unit 232, and the refresh unit 233, it can not only control whether the scanning end GOUT outputs a valid level V5 according to the refresh control signal of the refresh control terminal Ctrl, but also selectively synchronize or desynchronize the scanning signal of the scanning end GOUT with the stage transmission signal of the stage transmission end NEXT, while ensuring the normal transmission of the stage transmission signal of the stage transmission end NEXT. This facilitates the implementation of zoned frequency driving of the display panel, reduces the power consumption of the display panel, and improves the accuracy and stability of the scan signal output.

[0133] In an alternative embodiment, Figure 21 This is a schematic diagram of the twelfth type of shift register unit provided in the embodiments of this application, with reference to... Figure 21 The control unit 231 includes a control transistor T24; the first terminal of the control transistor T24 is electrically connected to the refresh control terminal Ctrl, the second terminal of the control transistor T24 is electrically connected to the refresh control node N7, and the gate of the control transistor T24 is electrically connected to the stage transmission terminal NEXT; when the stage transmission signal of the stage transmission terminal NEXT is an invalid level V1', the refresh control terminal Ctrl and the refresh control node N7 are connected.

[0134] Specifically, the effective and ineffective levels of the NEXT transmission signal and the GOUT scan signal are the same. However, the effective and ineffective levels of these signals are relative to the pixel transistors connected to them and the input transistors of the next-level shift register unit, not to other components within the shift register unit. Therefore, when the NEXT transmission signal is ineffective (V1'), the control transistor T24 is turned on, thus transmitting the refresh control signal (Ctrl) to the refresh control node N7 ahead of time. After the NEXT transmission signal has transitioned to the effective level (V1), the control transistor T24 is turned off, stopping the writing of the refresh control signal (Ctrl) to the refresh control node N7.

[0135] This configuration allows the refresh control signal of the refresh control terminal Ctrl to be pre-written to the refresh control node N7 before the refresh signal of the NEXT terminal outputs an effective level V1, enabling the refresh control node N7 to establish the target potential in advance. Therefore, when the second drive node NB transitions, the synchronization unit 232 can promptly control the synchronization or desynchronization of the first auxiliary node NP and the second drive node NB. This avoids the refresh control signal only starting to be transmitted to the refresh control node N7 after the refresh signal of the NEXT terminal has already output an effective level V1, which would cause a lag in the synchronization control between the first auxiliary node NP and the second drive node NB. Consequently, the effective level V5 of the scan signal output of the GOUT terminal would be significantly delayed relative to the refresh signal of the NEXT terminal, affecting the pulse width of the effective pulse of the scan signal of the GOUT terminal and the charging rate of the pixel circuit.

[0136] Furthermore, by writing the refresh control signal into the refresh control node N7 in advance when the cascading signal at the cascading terminal NEXT is at an invalid level V1', it is possible to pre-control the synchronization or desynchronization of the first auxiliary node NP and the second drive node NB before the cascading signal at the cascading terminal NEXT changes. Thus, if the corresponding shift register unit does not need to output an effective level V1 of the scan signal in a subsequent period, the first auxiliary node NP and the second drive node NB can be kept desynchronized before the cascading terminal NEXT outputs an effective level V1. This avoids adjusting the potential of the refresh control node N7 after the cascading terminal NEXT has already output a valid high level, which would cause the first auxiliary node NP and the second drive node NB to briefly synchronize during the adjustment process. This would result in the scan terminal GOUT briefly going high when it should be low, forming a spike pulse, which could cause the pixel transistor to mis-turn on, resulting in incorrect data signals being written to the pixel circuit. This improves the driving stability of the shift register unit and the display reliability.

[0137] In another alternative embodiment, reference continues... Figure 21The synchronization unit 232 includes a first synchronization transistor T25 and a second synchronization transistor T26; the first terminal of the first synchronization transistor T25 is electrically connected to the second driving node NB, the second terminal of the first synchronization transistor T25 is electrically connected to the first auxiliary node NP, and the gate of the first synchronization transistor T25 is electrically connected to the refresh control node N7; the first terminal of the second synchronization transistor T26 is electrically connected to the refresh voltage terminal VG25, the second terminal of the second synchronization transistor T26 is electrically connected to the scan terminal, and the gate of the second synchronization transistor T26 is electrically connected to the first auxiliary node NP or the stage terminal NEXT.

[0138] Specifically, the first synchronization transistor T25 is used to establish or disconnect the transmission path between the second driving node NB and the first auxiliary node NP under the control of the refresh control node N7. When the refresh control node N7 is active, the first synchronization transistor T25 is turned on, allowing the signal of the second driving node NB to be transmitted to the first auxiliary node NP, thereby synchronizing the first auxiliary node NP with the second driving node NB; when the refresh control node N7 is inactive, the first synchronization transistor T25 is turned off, causing the first auxiliary node NP to be desynchronized with the second driving node NB. Thus, the first synchronization transistor T25 can selectively control whether the first auxiliary node NP follows the changes of the second driving node NB according to the signal of the refresh control node N7.

[0139] The second synchronization transistor T26 is used to reset the first auxiliary node NP when it is out of sync with the second driving node NB. The second synchronization transistor T26 can be turned on or off under the signal control of the first driving node NA or the cascade terminal NEXT. When the second synchronization transistor T26 is on, it transmits the voltage signal of the refresh voltage terminal VG25 to the first auxiliary node NP, thereby controlling the first auxiliary node NP to be at an invalid level V4'. Thus, when the first auxiliary node NP is out of sync with the second driving node NB, the second synchronization transistor T26 can maintain the first auxiliary node NP at an invalid level V4', preventing the scan terminal GOUT from outputting a valid level V5.

[0140] It should be noted that the effective levels of the second driving node NB and the first driving node NA or the cascade terminal NEXT do not overlap. That is, when the first driving node NA or the cascade terminal NEXT is active, the second driving node NB is inactive (V2'). At this time, if the second synchronization transistor T26 is turned on, it can transmit the refresh voltage signal VG25 to the first auxiliary node NP, making the first auxiliary node NP inactive (V4'). Since the second driving node NB is already inactive at this time, whether the first auxiliary node NP is synchronized with the second driving node NB or not will not affect the final result of the first auxiliary node NP being inactive (V4'). Therefore, the second synchronization transistor T26 can use the signal from the first driving node NA or the cascade terminal NEXT to reset the first auxiliary node NP at an appropriate time.

[0141] Furthermore, the gate of the second synchronization transistor T26 is connected to the first driving node NA or the cascade terminal NEXT, allowing the first auxiliary node NP to be reset using the signal from the first driving node NA or the cascade terminal NEXT. Since the first auxiliary node NP needs to remain at an invalid level V4' for most of the time within a frame, by setting the second synchronization transistor T26, the first auxiliary node NP can be restored to the invalid level V4' in a timely manner during the corresponding period, preventing the first auxiliary node NP from being maintained in an undesirable potential state due to residual charge from the previous period.

[0142] By setting the first synchronization transistor T25 and the second synchronization transistor T26, the synchronization unit 232 can selectively synchronize or desynchronize the first auxiliary node NP with the second driving node NB under the control of the refresh control node N7. Furthermore, when the first auxiliary node NP and the second driving node NB are desynchronized, the second synchronization transistor T26 can control the first auxiliary node NP to an invalid level V4'. This ensures that when a valid pulse for the scan terminal GOUT is required, the first auxiliary node NP can promptly follow the changes in the second driving node NB; when a valid pulse for the scan terminal GOUT is not required, the first auxiliary node NP can stably maintain an invalid level V4', thereby improving the accuracy and stability of the scan signal output control.

[0143] In yet another alternative embodiment, reference continues to... Figure 21 The refresh unit 233 includes a refresh transistor T27; the first terminal of the refresh transistor T27 is electrically connected to the stage terminal NEXT or the refresh voltage terminal VG25, the second terminal of the refresh transistor T27 is electrically connected to the scan terminal GOUT, and the gate of the refresh transistor T27 is electrically connected to the first auxiliary node NP.

[0144] Specifically, refresh transistor T27 can be turned on or off under the signal control of the first auxiliary node NP. When refresh transistor T27 is turned on, it transmits the stage transmission signal of stage transmission terminal NEXT or the refresh voltage signal of refresh voltage terminal VG25 to the scan terminal. That is, when refresh transistor T27 is located between stage transmission terminal and scan terminal, refresh transistor T27 can determine whether stage transmission terminal and scan terminal are connected under the control of the first auxiliary node NP; when refresh transistor T27 is connected to refresh voltage terminal VG25 and scan terminal, refresh transistor T27 can provide refresh voltage signal of refresh voltage terminal VG25 to scan terminal GOUT under the control of the first auxiliary node NP.

[0145] In one embodiment, when the first auxiliary node NP is at an active level V4, the refresh transistor T27 is turned on, thereby causing the scan terminal to output an active level V1; when the first auxiliary node NP is at an inactive level V4', the refresh transistor T27 is turned off, causing the scan terminal to stop outputting an active level V1 and maintain an inactive level V1'. Thus, the refresh transistor T27 can selectively control the scan terminal GOUT to output an active level V1 or maintain an inactive level V1' based on the signal of the first auxiliary node NP.

[0146] For example, during the period when the corresponding pixel row needs to be refreshed, the first auxiliary node NP can be at an effective level V4, turning on the refresh transistor T27, thereby transmitting the effective level V1 of the stage transmission terminal NEXT or the refresh voltage signal of the refresh voltage terminal VG25 to the scanning terminal, making the scan signal of the scanning terminal GOUT at an effective level V5, so as to control the corresponding pixel row to be refreshed; during the period when the corresponding pixel row does not need to be refreshed, the first auxiliary node NP can be at an ineffective level V4', turning off the refresh transistor T27, so that the scanning terminal GOUT does not output an effective level V5, but remains at an ineffective level V5'.

[0147] Therefore, by setting the refresh transistor T27, the refresh unit 233 can determine whether the scanning end outputs an effective level under the control of the first auxiliary node NP. On the one hand, this is beneficial for timely transmission of the stage transmission signal or refresh voltage signal to the scanning end when refresh is needed, so as to realize the normal refresh of the corresponding pixel row; on the other hand, it is also beneficial for keeping the scan signal of the scanning end GOUT at an invalid level V5' when refresh is not needed, thereby realizing the segmented frequency driving of pixels in different areas of the display panel.

[0148] In yet another alternative embodiment, Figure 22 This is a schematic diagram of the thirteenth shift register unit provided in the embodiments of this application, with reference to... Figure 22The shift register unit 20 also includes a first holding capacitor C6 and a second holding capacitor C7. The first holding capacitor C6 is connected between the first auxiliary node NP and the refresh voltage terminal VG25, and the second coupling capacitor C7 is connected between the first control node N8 and the second auxiliary node ND.

[0149] Specifically, the first holding capacitor C6 is used to maintain the potential of the first auxiliary node NP. In one embodiment, after the synchronization unit 232 establishes the target potential of the first auxiliary node NP, the first holding capacitor C6 can maintain the potential relationship between the first auxiliary node NP and the refresh voltage terminal VG25, thereby helping to reduce the potential fluctuations of the first auxiliary node NP caused by parasitic coupling or leakage current, and improving the potential stability of the first auxiliary node NP. In this way, it is beneficial to ensure that the refresh unit 233 is stably turned on or off according to the target potential of the first auxiliary node NP.

[0150] The second holding capacitor C7 is used to maintain the potential of the refresh control node N7. For example, after the control unit 231 establishes the refresh control signal to the refresh control node N7, the second holding capacitor C7 can maintain the potential relationship between the refresh control node N7 and the second voltage terminal VGL or the first voltage terminal VGH, thereby reducing potential fluctuations in the refresh control node N7 due to parasitic coupling or leakage current during subsequent timing changes, and improving the potential stability of the refresh control node N7. This facilitates the stable control of the refresh control node N7 to synchronize or desynchronize the first auxiliary node NP and the second driving node NB.

[0151] Optional, continue to refer to Figure 22 The shift register unit 20 also includes a reset coupling capacitor C4; the first plate of the reset coupling capacitor C4 is electrically connected to the scanning end, and the second plate of the reset coupling capacitor C4 is electrically connected to the second auxiliary node ND.

[0152] Specifically, the reset coupling capacitor C4 is used to couple and control the second auxiliary node ND when the potential at the scan terminal changes. For example, when the scan signal at the scan terminal GOUT recovers from the active level V1 to the inactive level V1', i.e., the scan terminal is pulled low, the reset coupling capacitor C4 can further reduce the potential of the second auxiliary node ND through coupling, thereby making the reset transistor T28 in the reset circuit more fully conductive. This helps reduce the conduction delay of the reset path, allowing the reset voltage signal at the reset voltage terminal VG24 to be transmitted to the scan terminal more quickly, thus improving the response speed and stability when the scan signal recovers to the inactive level V5'.

[0153] It should be noted that the reset coupling capacitor C4 is typically used when an isolation circuit 240 is provided between the first driving node NA and the second auxiliary node ND. It is understood that when the isolation circuit 240 is provided, the second auxiliary node ND can be asynchronous with the first driving node NA at least for a portion of the time. Therefore, the pull-down effect of the reset coupling capacitor C4 on the second auxiliary node ND will not directly affect the potential change of the first driving node NA. Thus, the reset coupling capacitor C4 can effectively enhance the pull-down effect of the second auxiliary node ND without interfering with the potential of the first driving node NA.

[0154] If no isolation circuit 240 is provided between the first driving node NA and the second auxiliary node ND, the potential fluctuations of the scanning terminal GOUT may further affect the potential of the first driving node NA through the second auxiliary node ND while the reset coupling capacitor C4 remains at an invalid level V1', thus affecting the pull-down process of the cascade signal of the cascade terminal NEXT. For example, when the cascade terminal NEXT is at an active level V1 and the scanning terminal GOUT is at an invalid level V5', the second auxiliary node ND and the first driving node NA are short-circuited, both at invalid levels, and the scanning terminal GOUT is floating. At this time, the signal fluctuations of the scanning terminal GOUT may be coupled to the first driving node NA through the reset coupling capacitor C4, creating an additional effect on the first driving node NA, which is detrimental to the normal operation of the cascade terminal NEXT. Therefore, the reset coupling capacitor C4 is usually placed in a structure in which the first driving node NA and the second auxiliary node ND are isolated by the isolation circuit 240.

[0155] It should be noted that the refresh control circuit 230 in the shift register unit 20 provided in this application embodiment is not limited to the circuit structure described above. In other optional embodiments, Figure 23 This is a schematic diagram of the structure of the fourteenth shift register unit provided in the embodiments of this application, with reference to... Figure 23 The refresh control circuit 230 may also include a first control transistor M15, a second control transistor M16, a third control transistor M17, a first pull-up transistor M18, a second pull-up transistor M19, and a holding transistor M21.

[0156] Specifically, the gate of the first control transistor M15 is electrically connected to the stage transmission terminal, the first terminal is electrically connected to the refresh control terminal, and the second terminal is electrically connected to the first control node N8. Thus, the first control transistor M15 can turn on when the stage transmission signal at the stage transmission terminal NEXT is invalid, transmitting the control signal from the refresh control terminal Ctrl to the first control node N8; when the stage transmission signal at the stage transmission terminal NEXT is valid, the first control transistor M15 turns off, thereby stopping the writing of the control signal from the refresh control terminal Ctrl to the first control node N8.

[0157] The gate of the second control transistor M16 is electrically connected to the stage transmission terminal, the first terminal is electrically connected to the second control node N10, and the second terminal is electrically connected to the second voltage terminal VGL. Therefore, when the stage transmission signal at the stage transmission terminal NEXT is at an active level, the second control transistor M16 can control the conduction relationship between the second control node N10 and the second voltage terminal VGL according to the signal at the stage transmission terminal, thereby establishing or releasing the low level of the second control node N10.

[0158] The gate of the third control transistor M17 is electrically connected to the first control node N8, its first terminal is electrically connected to the third control node N9, and its second terminal is electrically connected to the second control node N10. Therefore, the third control transistor M17 can control the conduction relationship between the third control node N9 and the second control node N10 according to the signal from the first control node N8, thereby enabling the second control node N10 to establish a corresponding potential under the combined action of the first control node N8 and the third control node N9.

[0159] The gate of the first pull-up transistor M18 is electrically connected to the stage terminal, its first terminal is electrically connected to the first voltage terminal VGH, and its second terminal is electrically connected to the third control node N9. The gate of the second pull-up transistor M19 is electrically connected to the first control node N8, its first terminal is electrically connected to the first voltage terminal VGH, and its second terminal is electrically connected to the third control node N9. Therefore, the first pull-up transistor M18 and the second pull-up transistor M19 can selectively transmit the voltage signal of the first voltage terminal VGH to the third control node N9 according to the signals from the stage terminal and the first control node N8, thereby establishing a high level at the third control node N9.

[0160] The gate of output transistor M21 is electrically connected to the third control node N9, its first terminal is electrically connected to the first voltage terminal VGH, and its second terminal is electrically connected to the scan terminal. Thus, output transistor M21 can be turned on or off under the signal control of the third control node N9. When output transistor M21 is on, it transmits the voltage signal of the first voltage terminal VGH to the scan terminal, thereby causing the scan terminal to output an effective level. When output transistor M21 is off, the scan terminal stops outputting an effective level.

[0161] Understandably, by setting the first control transistor M15, the control signal of the refresh control terminal Ctrl can be written to the first control node N8 before the cascade terminal outputs a valid level, thus allowing the first control node N8 to establish the target potential in advance. This facilitates timely control of the relevant transistors' on / off states based on the signal from the first control node N8, avoiding the situation where the refresh control signal is written to the first control node N8 after the cascade terminal has already output a valid level, which could lead to a delay in the output of the valid pulse at the scan terminal or abnormal spikes in the output.

[0162] Furthermore, during periods when a valid level of the scan signal needs to be output, the first control node N8 can be set to a valid level, and the cascade terminal NEXT can also output a valid level. This causes the first pull-up transistor M18 and the second pull-up transistor M19 to transmit the voltage signal at the high-level terminal VGH to the third control node N9, making the third control node N9 set to an invalid level. At this time, the output transistor M21 is turned on under the control of the third control node N9, thereby transmitting the voltage signal at the first voltage terminal VGH to the scan terminal. During periods when a valid level of the scan signal does not need to be output, the third control node N9 can remain at a valid level, turning off the output transistor M21, thereby stopping the scan terminal from outputting a valid level.

[0163] Based on the same inventive concept, embodiments of this application also provide a display device. Figure 24 This is a schematic diagram of the structure of a display device provided in an embodiment of this application, such as... Figure 24 The display device 002 includes the display panel 001 provided in any embodiment of this application. The display device 002 provided in the embodiments of this application can be... Figure 24 The mobile phone shown can also be any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet, digital camera, smart bracelet, smart glasses, in-vehicle display, medical device, industrial control equipment, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0164] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, include: The driving circuit includes multiple cascaded shift register units. The shift register unit includes a drive control circuit, a transmission circuit, a refresh control circuit, an isolation circuit, and a reset circuit. The drive control circuit is electrically connected to the input terminal, the first clock terminal, the first drive node, and the second drive node, respectively. The cascading circuit is electrically connected to the first driving node, the second driving node, the first voltage terminal, the second voltage terminal, and the cascading terminal, respectively; wherein, the cascading terminal of the i-th stage shift register unit is electrically connected to the input terminal of the j-th stage shift register unit, i≠j, and i and j are both positive integers; The refresh control circuit is electrically connected to the transmission terminal, the refresh control terminal, the first auxiliary node, and the scanning terminal, respectively. The isolation circuit is electrically connected to the first driving node, the first auxiliary node, the second auxiliary node, and the auxiliary voltage terminal, respectively. The reset circuit is electrically connected to the second auxiliary node, the reset voltage terminal, and the scanning terminal, respectively.

2. The display panel according to claim 1, characterized in that, In the same shift register unit, when the cascading signal at the cascading end is at an active level and the scanning signal at the scanning end is at an inactive level, the signal of the first driving node is at an inactive level and the signal of the second auxiliary node is at an active level.

3. The display panel according to claim 1, characterized in that, In the same shift register unit, when both the transmission signal at the transmission end and the scanning signal at the scanning end are at valid levels, the signals of the first driving node and the second auxiliary node are at invalid levels.

4. The display panel according to claim 1, characterized in that, In the same shift register unit, when the cascading signal of the cascading end is at an invalid level, the scanning signal of the scanning end is also at an invalid level. The signal of the first driving node includes an effective level, and the signal of the second auxiliary node is at an effective level.

5. The display panel according to claim 1, characterized in that, The display panel includes a multi-frequency driving display mode; The multi-frequency driven display mode includes multiple display cycles; the display cycle includes a first display frame and a second display frame; the first display frame is located before the second display frame; The first display frame includes a refresh phase; during the refresh phase of the first display frame, the refresh control signal includes an active level, and the cascading signal at the cascading end and the scanning signal at the scanning end of each of the shift register units include active levels. The second display frame includes a refresh phase and a hold phase; during the refresh phase of the second display frame, the refresh control signal includes an active level, and the cascading signal and the scan signal of some of the shift register units both include active levels; during the hold phase of the second display frame, the refresh control signal includes an inactive level, the cascading signal of some of the shift register units includes an active level, and the scan signal is an inactive level.

6. The display panel according to claim 5, characterized in that, In the refresh phase, in the shift register unit that can simultaneously output the effective level of the transmission signal and the effective level of the scan signal, the first auxiliary node includes an effective level and the second auxiliary node includes an invalid level. During the holding phase, in the shift register unit that only outputs the effective level of the cascade signal, the first auxiliary node is at an invalid level and the second auxiliary node is at an effective level.

7. The display panel according to claim 1, characterized in that, The isolation circuit includes an isolation unit and an isolation auxiliary unit; The isolation unit is electrically connected to the first driving node and the second auxiliary node respectively; the isolation unit is used to control the signal of the second auxiliary node according to the signal of the first driving node; The isolation auxiliary unit is electrically connected to the first auxiliary node, the second auxiliary node, and the auxiliary voltage terminal, respectively; the isolation auxiliary unit is used to control the signal of the second auxiliary node according to the signal of the first auxiliary node and the auxiliary voltage signal of the auxiliary voltage terminal.

8. The display panel according to claim 7, characterized in that, The isolation unit includes an isolation transistor; The first electrode and gate of the isolation transistor are both coupled to the first driving node, and the second electrode of the isolation transistor is electrically connected to the second auxiliary node.

9. The display panel according to claim 8, characterized in that, The drive control circuit includes a first drive unit and a second drive unit; The first driving unit is electrically connected to the input terminal, the first clock terminal, and the first driving node, respectively; The first driving unit is used to control the signal of the first driving node according to the input signal of the input terminal and the first clock signal of the first clock terminal; The second driving unit is electrically connected to the first driving node, the first clock terminal, and the second driving node; The second driving unit is used to control the signal of the second driving node according to the signal of the first driving node and the first clock signal of the first clock terminal.

10. The display panel according to claim 9, characterized in that, Both the first electrode and the gate of the isolation transistor are electrically connected to the first driving node.

11. The display panel according to claim 9, characterized in that, The first driving unit includes an input subunit, an input auxiliary subunit, and a pull-down auxiliary subunit; The input subunit is electrically connected to the input terminal, the first clock terminal, and the first driving node, respectively. The input subunit is used to control the signal of the first driving node according to the input signal of the input terminal and the first clock signal of the first clock terminal; The input auxiliary subunit is electrically connected to the input terminal, the first clock terminal, and the first pull-down node, respectively; the input auxiliary subunit is used to control the signal of the first pull-down node according to the input signal of the input terminal and the first clock signal of the first clock terminal; The pull-down auxiliary subunit is electrically connected to the first pull-down node, the second clock terminal, and the first driver node, respectively. The pull-down auxiliary subunit is used to control the signal of the first drive node according to the signal of the first pull-down node and the second clock signal of the second clock terminal; Specifically, the absolute value of the voltage when the signal of the first pull-down node is at an invalid level is greater than the absolute value of the voltage when the signal of the first drive node is at an invalid level.

12. The display panel according to claim 11, characterized in that, The pull-down auxiliary subunits respectively include a first pull-down transistor, a second pull-down transistor, and a pull-down coupling capacitor; The first terminal and gate of the first pull-down transistor are both electrically connected to the first plate of the pull-down coupling capacitor at the first pull-down node, and the second terminal of the first pull-down transistor is electrically connected to the first driving node. The first terminal of the second pull-down transistor is electrically connected to the second clock terminal, the second terminal of the second pull-down transistor is electrically connected to the second plate of the pull-down coupling capacitor at the second pull-down node, and the gate of the second pull-down transistor is electrically connected to the first pull-down node.

13. The display panel according to claim 11, characterized in that, The first terminal of the isolation transistor is electrically connected to the first driving node; The gate of the isolation transistor is electrically connected to the first pull-down node.

14. The display panel according to claim 11, characterized in that, Both the first electrode and the gate of the isolation transistor are electrically connected to the first pull-down node.

15. The display panel according to claim 7, characterized in that, The isolation auxiliary unit includes an isolation auxiliary transistor; The first terminal of the isolation auxiliary transistor is electrically connected to the auxiliary voltage terminal, the second terminal of the isolation auxiliary transistor is electrically connected to the second auxiliary node, and the gate of the isolation auxiliary transistor is electrically connected to the first auxiliary node. The signal at the auxiliary voltage terminal is the invalid level of the second auxiliary node.

16. The display panel according to claim 15, characterized in that... The isolation auxiliary transistor is a dual-gate transistor.

17. The display panel according to claim 15, characterized in that... The isolation auxiliary unit also includes an isolation transistor; The first terminal of the isolation transistor is electrically connected to the second terminal of the isolation auxiliary transistor, the second terminal of the isolation transistor is electrically connected to the second auxiliary node, and the gate signal of the isolation transistor is at an active level.

18. The display panel according to claim 7, characterized in that, In the same shift register unit, when the signal of the first auxiliary node is at an invalid level, the signal of the second auxiliary node is at an effective level.

19. The display panel according to claim 1, characterized in that, The refresh control circuit includes a control unit, a synchronization unit, and a refresh unit; The control unit is electrically connected to the cascading end, the refresh control end, and the refresh control node, respectively; the control unit is used to control the signal of the refresh control node according to the cascading signal of the cascading end and the refresh control signal of the refresh control end. The synchronization unit is electrically connected to the refresh control node, the second drive node, and the first auxiliary node, respectively; the synchronization unit is used to control the signal of the first auxiliary node according to the signal of the refresh control node and the signal of the second drive node; The refresh unit is electrically connected to the first auxiliary node, the refresh voltage terminal, and the scanning terminal, respectively; the refresh unit is used to control the scanning signal of the scanning terminal according to the signal of the first auxiliary node and the refresh voltage signal of the refresh voltage terminal.

20. The display panel according to claim 19, characterized in that, The control unit includes a control transistor; The first terminal of the control transistor is electrically connected to the refresh control terminal, the second terminal of the control transistor is electrically connected to the refresh control node, and the gate of the control transistor is electrically connected to the stage terminal. When the transmission signal at the transmission terminal is at an invalid level, the refresh control terminal and the refresh control node are connected.

21. The display panel according to claim 19, characterized in that, The synchronization unit includes a first synchronization transistor and a second synchronization transistor; The first terminal of the first synchronous transistor is electrically connected to the second driving node, the second terminal of the first synchronous transistor is electrically connected to the first auxiliary node, and the gate of the first synchronous transistor is electrically connected to the refresh control node. The first terminal of the second synchronization transistor is electrically connected to the refresh voltage terminal, the second terminal of the second synchronization transistor is electrically connected to the scan terminal, and the gate of the second synchronization transistor is electrically connected to the first auxiliary node or the stage terminal.

22. The display panel according to claim 19, characterized in that, The refresh unit includes a refresh transistor; The first terminal of the refresh transistor is electrically connected to the stage terminal or the refresh voltage terminal, the second terminal of the refresh transistor is electrically connected to the scan terminal, and the gate of the refresh transistor is electrically connected to the first auxiliary node.

23. The display panel according to claim 1, characterized in that, The shift register unit also includes a reset coupling capacitor; The first plate of the reset coupling capacitor is electrically connected to the scanning end, and the second plate of the reset coupling capacitor is electrically connected to the second auxiliary node.

24. The display panel according to claim 1, characterized in that, The reset circuit includes a reset transistor; The first terminal of the reset transistor is electrically connected to the reset voltage terminal, the second terminal of the reset transistor is electrically connected to the scan terminal, and the gate of the reset transistor is electrically connected to the second auxiliary node.

25. A display device, characterized in that, Includes the display panel as described in any one of claims 1-24.

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