Display panel and display device

Abstract

The present invention discloses a display panel and a display device. The display panel includes: a pixel circuit, a light-emitting element, and a data line; the data line is electrically connected to the pixel circuit, and the data line is used to transmit a data signal and an identification signal to the pixel circuit; the pixel circuit is electrically connected to the light-emitting element, and the pixel circuit is used to drive the light-emitting element; the pixel circuit includes a judgment unit and a data register; the judgment unit is used to judge whether the signal transmitted by the data line is an identification signal, if so, prevent the identification signal from being transmitted to the data register, if not, control the signal transmitted by the data line to be written into the data register. By adopting the technical solution of the present invention, on the premise of meeting the low-power consumption requirements of the display panel, the display accuracy of the display panel can be ensured, and the display effect of the display panel can be improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] With the development of display technologies, display panels are increasingly widely used, and users' requirements for the display quality of display panels are also getting higher and higher. To meet users' requirements for the display quality of display panels, the size of light-emitting elements in display panels is getting smaller and the number of light-emitting elements included in display panels is getting larger, thereby improving the resolution of display panels and enabling display panels to have richer and more delicate display images.

[0003] However, due to the requirement of low power consumption of display panels, the light-emitting accuracy of light-emitting elements in display panels is affected, thereby affecting the display effect of display panels. Summary of the Invention

[0004] The present invention provides a display panel and a display device to ensure that the display panel has high display quality on the premise that the display panel has low power consumption.

[0005] According to one aspect of the present invention, there is provided a display panel, including: a pixel circuit, a light-emitting element, and a data line;

[0006] The data line is electrically connected to the pixel circuit, and the data line is used to transmit a data signal and an identification signal to the pixel circuit;

[0007] The pixel circuit is electrically connected to the light-emitting element, and the pixel circuit is used to drive the light-emitting element;

[0008] The pixel circuit includes a judgment unit and a data register;

[0009] The judgment unit is used to judge whether the signal transmitted by the data line is the identification signal. If so, the judgment unit prevents the identification signal from being transmitted to the data register. If not, the judgment unit controls the signal transmitted by the data line to be written into the data register.

[0010] According to another aspect of the present invention, there is provided a display device, including: the above-mentioned display panel.

[0011] In the technical solution of the present invention, by providing a judgment unit and a data register in the pixel circuit, the judgment unit is used to judge whether the signal transmitted on the data line is an identification signal. When the signal transmitted on the data line is an identification signal, the judgment unit can prevent the identification signal from being transmitted to the data register, so as to prevent the influence of the identification signal transmitted to the data register on the accuracy of the data signal stored in the data register. When the signal transmitted on the data line is not an identification signal, the judgment unit can control the signal transmitted on the data line to be written into the data register, ensuring that the signal stored in the data register can control the light-emitting element to emit light accurately. In this way, the accuracy of the displayed image of the display panel can be improved, and then the display quality of the display panel can be improved, especially the display effect of the low-power display panel can be improved.

[0012] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0014] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 is a schematic structural diagram of a pixel circuit of a display panel provided by an embodiment of the present invention;

[0016] Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0017] Figure 4 is a schematic structural diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0018] Figure 5 is a schematic structural diagram of a pixel circuit in yet another display panel provided by an embodiment of the present invention;

[0019] Figure 6 is a schematic structural diagram of a pixel circuit in yet another display panel provided by an embodiment of the present invention;

[0020] Figure 7 is a schematic structural diagram of yet another display panel provided by an embodiment of the present invention;

[0021] Figure 8 It is a schematic structural diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0022] Figure 9 It is a schematic diagram of a pulse clock signal provided by an embodiment of the present invention;

[0023] Figure 10 It is a schematic diagram of another pulse clock signal provided by an embodiment of the present invention;

[0024] Figure 11 It is a schematic structural diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0025] Figure 12 It is a schematic diagram of a pulse clock signal and a second data clock signal provided by an embodiment of the present invention;

[0026] Figure 13 It is a schematic structural diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0027] Figure 14 It is a schematic structural diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0028] Figure 15 It is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0029] Figure 16 It is a schematic structural diagram of a pixel circuit in another display panel provided by an embodiment of the present invention;

[0030] Figure 17 It is a schematic structural diagram of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0031] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0032] It should be noted that the terms "first", "second", etc. in the description, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a system, product or device comprising a series of units does not necessarily have to be limited to those units clearly listed, but may include other units not clearly listed or inherent to these products or devices.

[0033] In the prior art, display panels with high-quality display and lighting requirements usually adopt a Pulse Width Modulation (PWM) driving method. Especially for display panels using Micro Light Emitting Diodes (Micro LED) as light-emitting elements, they usually use a pixel circuit to drive the light-emitting elements to emit light. This pixel circuit can be, for example, a Micro Integrated Circuit (Micro IC). At this time, by providing a corresponding data signal to the pixel circuit and storing the data signal in a data register, the pixel circuit can generate a corresponding pulse signal according to the data signal stored in the data register during the light-emitting stage of the light-emitting element, so as to control the light-emitting duration of the light-emitting element and achieve the effect of controlling the display and lighting brightness of the display panel.

[0034] However, in the prior art, each pixel circuit in the same column shares a data line for transmitting data signals. And for a display panel using a Micro IC as the pixel circuit, the data signals received by the pixel circuit are usually digital signals, so that the signals transmitted on this data line will frequently switch between high level and low level. Since the data line itself has resistance and forms a parasitic capacitance with other conductive structures, when the signals transmitted on the data line frequently switch between high level and low level, it is equivalent to repeatedly charging and discharging the data signal, and there will be current passing through the data line. In this way, there will be energy loss, which is not conducive to the low power consumption of the display panel. Although by making the data line transmit a fixed level, such as a fixed high level or a fixed low level, during certain time periods, the power consumption caused by the frequent switching of the signals transmitted on the data line can be effectively reduced. However, the fixed level transmitted on the data line will affect the accuracy of the data signal stored in the data register, thereby affecting the display and lighting accuracy of the light-emitting element, and further affecting the display effect of the display panel.

[0035] To solve the above technical problems, an embodiment of the present invention provides a display panel, which includes a pixel circuit, a light-emitting element, and a data line; the data line is electrically connected to the pixel circuit, and the data line is used to transmit a data signal and an identification signal to the pixel circuit; the pixel circuit is electrically connected to the light-emitting element, and the pixel circuit is used to drive the light-emitting element; the pixel circuit includes a judgment unit and a data register; the judgment unit is used to judge whether the signal transmitted by the data line is the identification signal, and if so, prevent the identification signal from being transmitted to the data register, and if not, control the signal transmitted by the data line to be written into the data register.

[0036] By adopting the above technical solution, by setting a judgment unit and a data register in the pixel circuit, the judgment unit is used to judge whether the signal transmitted by the data line is an identification signal, and when the signal transmitted by the data line is an identification signal, the judgment unit can prevent the identification signal from being transmitted to the data register to prevent the identification signal from being transmitted to the data register and affecting the accuracy of the data signal stored in the data register; when the signal transmitted by the data line is not an identification signal, the judgment unit can control the signal transmitted on the data line to be written into the data register to ensure that the signal stored in the data register can control the light-emitting element to emit light accurately. In this way, the accuracy of the displayed image of the display panel can be improved, and further the display quality of the display panel can be improved, especially the display effect of the low-power display panel.

[0037] The above is the core idea of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. Hereinafter, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention.

[0038] Figure 1 is a schematic structural diagram of a display panel provided by an embodiment of the present invention, Figure 2 is a schematic structural diagram of a pixel circuit of a display panel provided by an embodiment of the present invention. With reference to Figure 1 and Figure 2 , the display panel 100 includes a pixel circuit 10, a light-emitting element 20, and a data line 30; wherein, the data line 30 is electrically connected to the pixel circuit 10, and the data line 30 is used to transmit a data signal and an identification signal to the pixel circuit 10; the pixel circuit 10 is electrically connected to the light-emitting element 20, and the pixel circuit 10 is used to drive the light-emitting element 20; the pixel circuit 10 includes a judgment unit 11 and a data register 12; the judgment unit 11 is used to judge whether the signal transmitted by the data line 30 is an identification signal, and if so, prevent the identification signal from being transmitted to the data register 12, and if not, control the signal transmitted by the data line 30 to be written into the data register 12.

[0039] Among them, the display panel 100 may include a plurality of pixel circuits 10 arranged in an array. At least some of the pixel circuits 10 in the same column may be electrically connected to the same data line 30. At this time, the data line 30 can transmit the data signals of each pixel circuit 10 electrically connected thereto in a time-sharing manner. The data line 30 can transmit different data signals according to needs, and different data signals can represent different display gray levels. Among them, the data signal can be composed of an 8-bit binary digital signal. The data line 30 can serially transmit each digital signal of the data signals of different pixel circuits 10. For example, the data line 30 transmitting a high level represents "1", and transmitting a low level represents "0". By switching the number and order of the high and low levels transmitted by the data line 30, the transmission of different data signals can be realized. The data line 30 can also transmit an identification signal, and the identification signal can also be composed of an 8-bit binary digital signal. The 8-bit binary digital signal composition can be all "1" or "0", so that when the data line 30 transmits the identification signal, only the high level or the low level needs to be continuously transmitted. Thus, when there is no need to update the data signals stored in the data registers 12 in each pixel circuit 10, the data line 30 can be controlled to transmit the identification signal, thereby reducing the power consumption of the display panel 100.

[0040] It can be understood that the data signals transmitted by the data line 30 can be switched between 0 and 255, that is, 256 display gray levels from 0 to 255 can be identified by binary digital signals. Correspondingly, the above is only an exemplary example of the identification signal. In an optional embodiment, when the data line 30 transmits the identification signal, the signal transmitted by the data line 30 can also be switched between the high level and the low level. On the premise of meeting low power consumption, the embodiments of the present invention do not make specific limitations on the identification signal transmitted by the data line 30.

[0041] In addition, when the data line 30 transmits an identification signal, if the identification signal is written into the data register 12, the signal stored in the data register 12 will be changed to the identification signal, so that when the light-emitting element 20 is controlled to emit light according to the signal stored in the data register 12, the accuracy of the light display of the light-emitting element 20 will be affected. In this way, by setting the judgment unit 11 between the data register 12 and the data line 30, the judgment unit 11 can control whether the signal transmitted on the data line 30 is written into the data register 12; that is, if the signal transmitted by the data line 30 is an identification signal, it can be determined that there is no need to update the signal stored in the data register 12. At this time, the judgment unit 11 can prevent the signal transmitted by the data line 30 from being transmitted to the data register 12, so that the signal stored in the data register 12 remains stable, so that when the light-emitting element 20 is controlled to emit light according to the signal stored in the data register 12, the light-emitting element 20 can emit light stably and accurately; if the signal transmitted by the data line 30 is not an identification signal, the signal transmitted by the data line 30 is a data signal, and it can be determined that the signal stored in the data register 12 needs to be updated. At this time, the judgment unit 11 can control the signal transmitted by the data line 30 to be written into the data register 12 to realize the update of the signal stored in the data register 12, so that when the light-emitting element 20 is controlled to emit light according to the signal stored in the data register 12, the light-emitting element 20 can also emit light accurately and stably.

[0042] In this embodiment, a judgment unit and a data register are set in the pixel circuit, and the judgment unit is used to judge whether the signal transmitted by the data line is an identification signal. When the signal transmitted by the data line is an identification signal, the judgment unit can prevent the identification signal from being transmitted to the data register, so as to prevent the identification signal from being transmitted to the data register and affecting the accuracy of the data signal stored in the data register; and when the signal transmitted by the data line is not an identification signal, the judgment unit can control the signal transmitted on the data line to be written into the data register, ensuring that the signal stored in the data register can control the light-emitting element to emit light accurately, thereby improving the accuracy of the picture displayed by the display panel, and further improving the display quality of the display panel, especially improving the display effect of the low-power display panel.

[0043] It should be noted that Figure 1 The accompanying drawings are merely exemplary of the embodiments of the present invention. Figure 1 In the figure, each pixel circuit 10 is only exemplarily shown to be electrically connected to one light emitting element 20. In the embodiment of the present invention, Figure 3As shown, each pixel circuit 10 can be electrically connected to one or more groups of light-emitting elements 20, and each group of light-emitting elements 20 can include a plurality of light-emitting elements 20 connected in series or in parallel. In the embodiments of the present invention, the number of light-emitting elements 20 electrically connected to each pixel circuit 10 is not specifically limited. For the convenience of description, in the embodiments of the present invention, it is taken as an example that each pixel circuit 20 is electrically connected to one light-emitting element 20 to exemplarily illustrate the technical solutions of the embodiments of the present invention.

[0044] Optionally, continuing to refer to Figure 1 and Figure 2 , the signal transmitted by the data line 30 can be determined by the display screen of the display panel 100. At this time, the data line 30 can be used to transmit the data signal of the current frame display screen when the current frame display screen of the display panel 100 is different from the previous frame display screen, and to transmit the identification signal when the current frame display screen of the display panel 100 is the same as the previous frame display screen.

[0045] Specifically, when the display panel 100 displays a screen, it will update the displayed screen at a certain refresh rate, and the refresh rate is the number of frames of the display screen that the display panel 100 can display per unit time. For example, when the refresh rate of the display panel 100 is 60 Hz, the display panel 100 can display 60 frames of display screens in one second, but the content of the display screen displayed by the display panel 100 does not change 60 times per second. For example, when the display panel 100 is in the standby state or displays other non-dynamic screens, the display panel 100 will display the same content for a long time. At this time, within a period of time, the data signals of each frame of display screen are the same. At this time, it is not necessary to update the signals stored in the data register 12 of each pixel circuit 10 according to the refresh rate of the display panel 100. For example, the signals stored in the data register 12 can be updated only when the first frame of the display screen of this content is displayed, and in the subsequent frames of the display screen of the same content, only the signals stored in the data register 12 need to be maintained.

[0046] Thus, when the display screen of the current frame is the same as that of the previous frame, the display screens of the current frame and the previous frame are of the same content, and the data signal of the display screen of the current frame is the same as the data signal in the display screen of the previous frame. Therefore, it is only necessary to keep the data signal stored in the data register 12 unchanged. At this time, the data line 30 can be controlled to transmit an identification signal, so that the signal transmitted by the data line 30 does not need to frequently switch between high and low levels, which is beneficial to the low power consumption of the display panel 100. Moreover, the judgment unit 11 in the pixel circuit 10 will prevent the signal transmitted by the data line 30 from being written into the data register 12 to prevent the identification signal transmitted by the data line 30 from affecting the signal in the data register 12. When the display screen of the current frame is different from that of the previous frame, the display screens of the current frame and the previous frame are of different content, and the data signal of the display screen of the current frame is different from the data signal in the display screen of the previous frame. Therefore, it is necessary to update the data signal stored in the data register 12. At this time, the data line 30 can be controlled to transmit the data signal of the display screen of the current frame, and the judgment unit 11 in the pixel circuit 10 will control the signal transmitted by the data line 30 to be written into the data register 12, so that when the light-emitting element 20 emits light according to the signal in the data register 12, the display content of the display screen of the current frame can be presented, thereby improving the accuracy of the display screen displayed by the display panel 100.

[0047] In an alternative embodiment, Figure 4 is a schematic structural diagram of a pixel circuit in another display panel provided by an embodiment of the present invention. As Figure 4 shown, the pixel circuit 10 further includes a pulse generation unit 13 and a switch 14; the pulse generation unit 13 is configured to generate a pulse signal according to the signal stored in the data register 12; the switch 14 is configured to control the time for providing a driving current to the light-emitting element 20 under the control of the pulse signal.

[0048] Specifically, the light-emitting element 20 is, for example, one of an organic light-emitting diode (OLED), a micro light-emitting diode (micro LED), and a mini light-emitting diode (mini LED). At this time, the light-emitting element 20 is a current-driven element, and a corresponding driving current needs to be provided to the light-emitting element 20 so that the light-emitting element 20 can display light. By providing a pulse generation unit 13 in the pixel circuit 10, the pulse generation unit 13 can generate a pulse signal according to the signal stored in the data register 12. The pulse signal can include an effective level and an invalid level. When the pulse signal generated by the pulse generation unit 13 is at the effective level, the switch 14 can be controlled to provide a driving current to the light-emitting element 20, so that the light-emitting element 20 emits light; when the pulse signal generated by the pulse generation unit 13 is at the invalid level, the switch 14 can be controlled to stop providing a driving current to the light-emitting element 20, so that the light-emitting element 20 stops emitting light; thus, by controlling the ratio of the effective level in the pulse signal generated by the pulse generation unit 13, that is, the duty cycle of the pulse signal, the time for the switch 14 to provide a driving current to the light-emitting element 20 can be controlled, and thus the light-emitting duration of the light-emitting element 20 can be controlled. Since the overall light-emitting brightness presented by the light-emitting element 20 is related not only to the magnitude of the driving current but also to the light-emitting time of the light-emitting element 20. Usually, within a certain time, the longer the light-emitting duration of the light-emitting element 20, the higher the light-emitting brightness presented by the light-emitting element 20, that is, the higher the display gray scale, and vice versa, the lower the display gray scale. Therefore, by controlling the light-emitting duration of the light-emitting element 20, the gray scale of the light-emitting brightness presented by the light-emitting element 20 can be controlled. In this way, when different data signals corresponding to different display gray scales are stored in the data register 12, the pulse generation unit 13 can generate pulse signals with different duty cycles, so that the time for the switch 14 to provide a driving current to the light-emitting element 20 is different, and the display brightness that the light-emitting element 20 can present is different.

[0049] Among them, the switch 14 can be a three-terminal device. For example, the switch can include but is not limited to a transistor. The transistor can be an N-type transistor or a P-type transistor; when the transistor is an N-type transistor, the effective level of the pulse signal is a high level, and the invalid level of the pulse signal is a low level; when the transistor is a P-type transistor, the effective level of the pulse signal is a low level, and the invalid level of the pulse signal is a high level; the specific structure of the switch 14 in the embodiments of the present invention is not specifically limited.

[0050] It can be understood that, such as Figure 4As shown, the control terminal of switch 14 can be electrically connected to the pulse signal output terminal of pulse generation unit 13, the input terminal of switch 14 can be electrically connected to positive power supply VDD, the output terminal of switch 14 can be electrically connected to the anode of light-emitting element 20, and the cathode of light-emitting element 20 can be electrically connected to negative power supply VEE. At this time, switch 14 can generate a driving current according to the pulse signal provided by pulse generation unit 13 and the positive power supply signal. Or, as Figure 5 shown, in another exemplary embodiment, the control terminal of switch 14 is electrically connected to the pulse signal output terminal of pulse generation unit 13, the input terminal of switch 14 receives current source Id, the output terminal of switch 14 is electrically connected to the anode of light-emitting element 20, and the cathode of light-emitting element 20 is grounded. At this time, switch 14 can control current source Id to transmit to light-emitting element 20 according to the pulse signal generated by pulse generation unit 13. Or, as Figure 6 shown, in yet another exemplary embodiment, the control terminal of switch 14 is electrically connected to the pulse signal output terminal of pulse generation unit 13, the input terminal of switch 14 is electrically connected to positive power supply VDD, the output terminal of switch 14 is electrically connected to the anode of light-emitting element 20 through current source Id, and the cathode of light-emitting element 20 is electrically connected to negative power supply VEE. At this time, switch 14 can control the current path between positive power supply VDD and negative power supply VEE according to the pulse signal generated by pulse generation unit 13 to control current source Id to transmit to light-emitting element 20.

[0051] It should be noted that Figure 4 - Figure 6 are all exemplary drawings of the embodiments of the present invention,[[]] Figure 3 - Figure 5 only exemplarily show the connection manner between switch 14 and light-emitting element 20, and the manner in which switch 14 controls the supply of driving current to light-emitting element 20 according to the pulse signal generated by pulse generation unit 13. In the embodiments of the present invention, on the premise that switch 14 can control the supply of driving current to light-emitting element 20 according to the pulse signal generated by pulse generation unit 13, the embodiments of the present invention do not make specific limitations thereon. For ease of description, the embodiments of the present invention are all described by taking the Figure 6 shown structure as an example of the embodiments of the present invention.

[0052] In addition, it should also be noted that Figure 6The current source Id shown can be provided by a power supply module in the display panel. Among them, all pixel circuits 10 in the display panel can share the same power supply module, or each pixel circuit 10 can have its own power supply module. The embodiments of the present invention do not make specific limitations on this. In an exemplary embodiment, if each pixel circuit 10 has its own power supply module, the power supply module can provide corresponding power signals according to the data signals of each pixel circuit 10 to further adjust the display emission brightness of the light-emitting elements 20 controlled by each pixel circuit 10, so that each light-emitting element 20 can have more levels of brightness adjustment, further improving the display quality of the display panel.

[0053] In an alternative embodiment, Figure 7 is a schematic structural diagram of another display panel provided by an embodiment of the present invention, Figure 8 is a schematic structural diagram of a pixel circuit in another display panel provided by an embodiment of the present invention. With reference to Figure 7 and Figure 8 , the display panel 100 may include a pulse clock line 40; at this time, the pulse generation unit 13 includes a counter 131 and a second comparator 132; the counter 131 is used to output a count value according to the pulse clock signal transmitted by the pulse clock line 40; the second comparator 132 is used to generate a pulse signal according to the comparison result between the count value and the signal stored in the data register 12.

[0054] Among them, the input end of the counter 131 is electrically connected to the pulse clock line 40. The counter 131 can receive the pulse clock signal transmitted by the pulse clock line 40 and count the number of pulses of the pulse clock signal. In an exemplary embodiment, the counter 131 can add 1 to the count value when each rising edge or falling edge of the pulse clock signal transmitted by the pulse clock line 40 arrives; alternatively, the counter 30 can also count the pulse duration of the pulse clock signal. At this time, the timer 30 can add 1 to the count value at fixed intervals when the pulse clock line 40 transmits the effective level of the pulse clock signal.

[0055] Exemplarily, when the counter 131 counts the number of pulses of the pulse clock signal PWMCK transmitted by the pulse clock line 40, the pulse clock signal PWMCK transmitted by the pulse clock line 40 may include a high level and a low level that alternately change at a fixed period (as shown in Figure 9 ), or the pulse clock signal PWMCK transmitted by the pulse clock line 40 may include a high level and a low level that alternately change at a non-fixed period (as shown in Figure 10as shown); wherein, the high level can be the effective level of the pulse clock signal PWMCK, and the low level can be the ineffective level of the pulse clock signal PWMCK. At this time, the counter 131 can increment the count value when the rising edge of the pulse clock signal PWMCK arrives. Conversely, the counter 131 can increment the count value when the falling edge of the pulse clock signal PWMCK arrives.

[0056] It can be understood that the second comparator 132 can include a count value input terminal, a data signal input terminal, and a pulse signal output terminal; the count value input terminal can be electrically connected to the output terminal of the counter 131 to obtain the counting result output by the counter 131, the data signal input terminal can be electrically connected to the output terminal of the data register 12 to obtain the data signal stored in the data register 12, and the pulse signal output terminal can be electrically connected to the control terminal of the switch 14 to provide a pulse signal to the switch 14. The structure of the second comparator 132 and its connection manner can be designed as needed, and the embodiments of the present invention do not make specific limitations thereto.

[0057] It should be noted that Figure 7 only the exemplary drawings of the embodiments of the present invention are shown, Figure 7 exemplarily shows that each pixel circuit 10 in the same row is electrically connected to the same pulse clock line 40. In the embodiments of the present invention, it can also be that some pixel circuits 10 in the same row are electrically connected to the same pulse clock line 40, or all pixel circuits 10 are electrically connected to the same pulse clock line 40, or different pixel circuits 10 are electrically connected to different pulse clock lines 40. On the premise of being able to achieve the core inventive point of the embodiments of the present invention, the embodiments of the present invention do not make specific limitations on the connection manner between the pixel circuit 10 and the pulse clock line 40. For ease of description, the embodiments of the present invention take the example that each pixel circuit 10 in the same row is electrically connected to the same pulse clock line 40 to illustrate the technical solutions of the embodiments of the present invention by way of example.

[0058] In an exemplary embodiment, taking the counter 131 as an example to count the rising edge of the pulse clock signal PWMCK transmitted on the pulse clock line 40, after the counter 131 counts the pulse clock signal PWMCK transmitted on the pulse clock line 40, it will output the corresponding count value as the counting result to the second comparator 132; meanwhile, since the data register 12 stores a data signal, this data signal can represent the display gray level of the light-emitting element 20 electrically connected to the pixel circuit 10, that is, the second comparator 132 can determine the current display gray level of the light-emitting element 20 according to the signal stored in the data register 12, or the data register 12 provides the current display gray level value to the second comparator 132 according to the signal stored therein; the second comparator 132 compares whether the count value of the counter 131 is equal to the gray level value corresponding to the data signal stored in the data register 12, and when the count value of the counter 131 is not equal to the gray level value corresponding to the data signal stored in the data register 12, the pulse signal output terminal of the second comparator 132 can continuously output the effective level of the pulse signal to the switch 14, so that the switch 14 controls the driving current to be provided to the light-emitting element 20, making the light-emitting element 20 in the light-emitting state; and when the count value of the counter 131 is equal to the gray level value corresponding to the data signal stored in the data register 12, the pulse signal output by the pulse signal output terminal of the second comparator 132 can flip from the effective level to the invalid level and continuously maintain this invalid level. When the switch 14 receives this invalid level, it will stop providing the driving current to the light-emitting element 20, making the light-emitting element 20 in the non-light-emitting state; when the count value of the counter 131 is equal to the gray level value corresponding to the data signal stored in the data register 12, the pulse clock signal PWMCK will maintain a low level for a period of time. At this time, the count value of the counter 131 remains unchanged, and after reaching the counting period of the counter 131, the count value of the counter 131 can be automatically cleared and re-counted according to the number of rising edges of the pulse clock signal PWMCK; thus, the duty cycle of the pulse signal provided to the switch 14 can be controlled, and thus the light-emitting duration of the light-emitting element 20 can be controlled.

[0059] It should be noted that the above only gives an exemplary description of the working principles of the counter 131 and the second comparator 132. In the embodiments of the present invention, the working principles of the counter 131 and the second comparator 132 are not limited to this. On the premise that the functions of the counter 131 and the second comparator 132 can be satisfied, the embodiments of the present invention do not specifically limit the working principles of the counter 131 and the second comparator 132.

[0060] Optionally, Figure 11 is a schematic structural diagram of a pixel circuit in another display panel provided by the embodiments of the present invention, as Figure 11As shown, the determination unit 11 includes a first comparator 111 and a transmission gate 112; the first comparator 111 is used to compare the signal transmitted by the data line 30 with a reference value. If it is the first result, it controls the transmission gate 112 to write the signal transmitted by the data line 30 into the data register 12. If it is the second result, it controls the transmission gate 112 to prevent the signal transmitted by the data line 30 from being written into the data register 12.

[0061] Specifically, the first comparator 111 may include a reference value input terminal, a data input terminal, and a control signal output terminal. The reference value input terminal can receive the reference value REF. The data input terminal can be electrically connected to the data line 30 to receive the data signal or identification signal transmitted by the data line. The control signal output terminal can be electrically connected to the control terminal of the transmission gate 112 to control the conduction or disconnection of the transmission gate 112; the input terminal of the transmission gate 112 can be electrically connected to the data line 30, and the output terminal of the transmission gate 112 can be electrically connected to the data register 112; when the transmission gate 112 is in the conduction state, the transmission gate 112 is in a low resistance state, and the signal transmitted by the data line 30 can be transmitted through the transmission gate 112 to the data register 12, so that the data register 12 can store the signal transmitted by the data line 30; when the transmission gate 112 is in the disconnection state, the transmission gate 112 is in a high resistance state, and the signal transmitted by the data line 30 cannot be transmitted through the transmission gate 112 to the data register 12, and the signal stored in the data register 12 remains unchanged.

[0062] Among them, the first comparator 111 can compare the signal transmitted by the data line 30 with a reference value. The reference value can be a specific value, so that there is a specific difference between the reference value and the identification signal. In this way, when the difference between the signal transmitted by the data line 30 and the reference value is this specific difference, it can be determined that the signal transmitted on the data line 30 is an identification signal, and the first comparator 111 outputs a control signal to control the transmission gate 112 to be in the off state, so that the transmission gate 112 can prevent the signal transmitted by the data line 30 from being transmitted to the data register 12; when the difference between the signal transmitted by the data line 30 and the reference is not this specific difference, it can be determined that the signal transmitted by the data line 30 is not an identification signal, that is, the signal transmitted by the data line 30 is a data signal. The first comparator 111 outputs a control signal to control the transmission gate 112 to be in the on state, so that the signal transmitted by the data line 30 can be written into the data register 12 through the transmission gate 112, and the signal in the data register 12 is updated to ensure that the light-emitting element 20 can emit light accurately and stably according to the signal stored in the data register 12, improving the display accuracy of the display panel, and thus improving the display effect of the display panel.

[0063] It can be understood that both the reference value REF and the signal transmitted by the data line 30 can be digital signals, and they can both be composed of binary digits. At this time, by comparing the magnitude of the reference value REF with the signal transmitted by the data line 30, the corresponding comparison result (the first result or the second result) can be determined.

[0064] In an optional embodiment, the reference value REF can be the same as the identification signal. At this time, the first result is that the signal transmitted by the data line 30 is different from the reference value REF, that is, the difference between the reference value REF and the signal transmitted by the data line 30 is not 0; the second result is that the signal transmitted by the data line 30 is the same as the reference value REF, that is, the difference between the reference value REF and the signal transmitted by the data line 30 is 0.

[0065] In other optional embodiments, the identification signal can include N-bit identification data; the reference value REF can include M bits of the identification data; M < N, and both M and N are positive integers; at this time, the first result is that the first M-bit digital signals of the signal transmitted by the data line 30 are different from the reference value REF; the second result is that the first M-bit digital signals of the signal transmitted by the data line 30 are the same as the reference value REF. In this way, only the first M bits of the signal transmitted by the data line 30 need to be compared with the reference value REF, which is beneficial to improving the operation speed of the first comparator 111, shortening the operation time of the first comparator 111, and thus beneficial to shortening the time of the pre-stage (such as the data signal writing stage) of a frame of display screen, and further capable of relatively increasing the time of the light-emitting stage (providing a pulse signal to the switch 14) in a frame of display screen, which is beneficial to increasing the adjustment range of the display and light-emitting brightness of the display panel.

[0066] In an exemplary embodiment, N can be equal to 8, M can be equal to 1, and the digital signal can be a binary digit. In this way, the first comparator 111 only needs to compare the relationship between the first digit signal of the signal transmitted by the data line 30 and the reference value REF to determine the comparison result.

[0067] Optionally, in combination with reference Figure 7 and Figure 11 , the second data clock line 50, and the second data clock line 50 is used to transmit the second data clock signal PWMD2; the data storage unit 12 is used to control the writing of the signal transmitted by the data line 30 under the control of the second data clock signal PWMD2 transmitted by the second data clock line 50 and the judgment unit.

[0068] Specifically, since the data line 30 is electrically connected to at least some of the pixel circuits 10 in the same row, the data line 30 does not transmit data signals of only one pixel circuit 10 but transmits data signals of each pixel circuit 10 in the same column in a time-sharing manner. At this time, in order to prevent the data signals of each pixel circuit 10 electrically connected to the same data line 30 from influencing each other, each pixel circuit 10 electrically connected to the same data line can be electrically connected to different second data clock lines 50 respectively, and within the display time of a frame of display picture, the second data clock signal PWMD2 transmitted by each second data clock line 50 can include a valid signal and an invalid signal, and different second data clock lines 50 are made to transmit the valid signal of the second clock signal PWMD2 in time division, so that when the judgment unit 11 controls the signal transmitted by the data line 30 to be transmitted to the data register 12, and the second data clock line 50 transmits the valid signal of the second clock signal PWMD2, the data register 12 stores the signal transmitted by the data line 30; and when the second data clock line 50 transmits the invalid signal of the second clock signal PWMD2, regardless of whether the judgment unit 11 controls the signal transmitted by the data line 30 to be transmitted to the data register 12, the data register 12 does not store the signal transmitted by the data line 30. In this way, the data line 30 can provide data signals to each pixel circuit 10 in time division, and prevent the data signals of each pixel circuit electrically connected to the same data line 30 from influencing each other. The valid signal of the second clock signal PWMD2 can be a continuous high level signal or a continuous pulse signal, and the invalid signal of the second clock signal PWMD2 can be a continuous low level signal; vice versa. The embodiment of the present invention does not specifically limit the valid signal and invalid signal of the second clock signal PWMD2.

[0069] In an optional embodiment, the second data clock line 50 can reuse the pulse clock line 40. In this case, the same pulse clock line 40 can transmit the pulse clock signal PWMCK and the second clock signal PWMD2 in a time-sharing manner. In the first time period T1, the pulse clock line 40 can transmit the second clock signal PWMD2 so that the data register 12 determines whether to store the signal transmitted by the data line 30; in the second time period T2, the pulse clock line 40 can transmit the pulse clock signal PWMCK so that the counter 131 can count according to the pulse clock signal PWMCK (such as Figure 12 In this way, the number of signal lines provided in the display panel 100 can be reduced, which is helpful to simplify the structure of the display panel 100.

[0070] Based on the above embodiment, optionally, Figure 13 is a schematic diagram of a structure of a pixel circuit in another display panel provided by an embodiment of the present invention, such as Figure 13As shown in the figure, the determination unit 11 further includes a pre-storage register 113 disposed between the data line 30, the first comparator 111, and the transmission gate 112; the pre-storage register 113 is used to pre-store the signal transmitted by the data line 30.

[0071] Specifically, the signal transmitted by the data line 30 can be pre-stored in the pre-storage register 113, so that the first comparator 111 can call the signal stored in the pre-storage register 113, compare the signal stored in the pre-storage register 113 with the reference value REF, and then control the conduction or disconnection of the transmission gate 112; when the transmission gate 112 is conducting, the signal stored in the pre-storage register 113 can be transmitted to the data register 12; when the transmission gate 112 is disconnected, the signal stored in the pre-storage register 113 can be prevented from being transmitted to the data register 12. Among them, the pre-storage register 113 can be electrically connected to the data line 30, the data input terminal of the first comparator 111, and the input terminal of the transmission gate 112 respectively. With such a setting, the time for the data line 30 to transmit the signal can be separated from the comparison time of the first comparator 111, preventing the two from affecting each other, which is beneficial to improving the accuracy of the comparison result determined by the first comparator 111, and further beneficial to improving the accuracy of the signal stored in the data register 12.

[0072] Optionally, referring to Figure 7 and Figure 13 , the display panel 100 further includes a first data clock line 60; the first data clock line 60 is used to transmit the first data clock signal PWMD1, and within the display time of one frame of the display screen, the first data clock signal PWMD1 includes valid signals and invalid signals; at this time, the pre-storage register 113 is used to pre-store the signal transmitted by the data line 30 when the first data clock line 60 transmits the valid signal of the first data clock signal PWMD1.

[0073] Specifically, the display panel 100 may include multiple first data clock lines 60, and each pixel circuit 10 electrically connected to the same data line 30 may be electrically connected to different first data clock lines 60 respectively, that is, when at least some pixel circuits 10 in the same column are electrically connected to the same data line 30, at least some pixel circuits 10 in the same row may be electrically connected to the same data clock line 60. Different first data clock lines 60 can transmit the valid signals of the first data clock signal PWMD1 in a time-sharing manner, so that the signals transmitted by the data line 30 can be stored in the pre-storage registers 113 of each pixel circuit 10 in a time-sharing manner, preventing the signals stored in the pre-storage registers 113 in the pixel circuits 10 electrically connected to the same data line 30 from affecting each other.

[0074] It can be understood that when the display panel 100 includes the first data clock line 60, the second data clock line 50 may or may not be provided in the display panel 100. As Figure 13 shown, when only the first data clock line 60 is provided in the display panel 100, the signals transmitted by the data line 30 are stored in the pre-storage register 113 in a time-sharing manner. At this time, whether the signals stored in the data register 12 are updated is completely controlled by whether the transmission gate 112 transmits the signals on the data line 30. That is, when the transmission gate 112 controls the signals on the data line 30 to be transmitted to the data register 12, the signals in the data register 12 are updated, and when the transmission gate 112 blocks the signals on the data line 30 from being transmitted to the data register 12, the signals in the data register 12 remain unchanged; as Figure 14 shown, when both the first data clock line 60 and the second data clock line 50 are included, even if the transmission gate 112 controls the signals on the data line 30 to be transmitted to the data register 12, the data register 12 will not directly store the signals on the data line 30. Instead, when the second data clock signal PWMD2 transmitted by the second data clock line 50 is a valid signal, the signals transmitted by the transmission gate 112 will be stored. Among them, the valid signal of the first data clock signal PWMD1 may be the same as or different from the valid signal of the second data clock signal PWMD2, and the invalid signal of the first data clock signal PWMD1 may be the same as or different from the invalid signal of the second data clock signal PWMD2. The embodiments of the present invention do not make specific limitations on this.

[0075] In an optional embodiment, the first data clock line 60 and the second data clock line 50 electrically connected to the same pixel circuit 10 may be the same signal line; and when the display panel 100 includes a pulse clock line, the first data clock line 60 may also multiplex the pulse clock line to simplify the structure of the display panel. On the premise of being able to implement the core inventive points of the embodiments of the present invention, the embodiments of the present invention do not make specific limitations on the setting methods of each signal line.

[0076] In another optional embodiment, Figure 15 is a schematic structural diagram of another display panel provided by the embodiments of the present invention, Figure 16 is a schematic structural diagram of a pixel circuit in another display panel provided by the embodiments of the present invention. With reference to Figure 15 and Figure 16, the display panel 100 further includes an input control line 70, which is configured to transmit a non - enabling level of an input control signal when the data line 30 transmits an identification signal, and transmit an enabling level of the input control signal when the data line 30 transmits a data signal of the current frame display picture; at this time, the determination unit 11 may include a pre - storage register 114 and a transmission gate 115; the pre - storage register 114 is configured to store the input control signal transmitted by the input control line 70; the transmission gate 115 is configured to control the signal transmitted by the data line 30 to be written into the data register 12 when the input control signal stored in the pre - storage register 114 is at the enabling level, and prevent the signal transmitted by the data line 30 from being written into the data register 12 when the input control signal stored in the pre - storage register 114 is at the non - enabling level.

[0077] Specifically, when the current frame display picture of the display panel 100 is the same as the previous frame display picture, the display content of the display panel 100 does not need to be changed. At this time, the data line 30 can transmit an identification signal, the input control line 70 can transmit a non - enabling level of the input control signal, and store the non - enabling level of the input control signal in the pre - storage register 114; when the current frame display picture of the display panel 100 is different from the previous frame display picture, the display content of the display panel 100 needs to be changed. At this time, the data line 30 can transmit a data signal of the current frame display picture, the input control line 70 can transmit an enabling level of the input control signal, and store the enabling level of the input control signal in the pre - storage register 114; the transmission gate 115 can be turned on or off under the control of the input control signal stored in the pre - storage register 114, and when the input control signal stored in the pre - storage register 114 is at the enabling level, the transmission gate 115 can be in the on state to transmit the signal on the data line 30 to the data register 12; when the input control signal stored in the pre - storage register 114 is at the non - enabling level, the transmission gate 115 can be in the off state to prevent the signal on the data line 30 from being transmitted to the data register 12. In this way, without judging the signal transmitted on the data line 30, the accuracy of the signal stored in the data register 12 can be ensured, which is beneficial to saving the time required for data signal storage.

[0078] It can be understood that all pixel circuits 10 in the display panel 100 can be electrically connected to the same input control line 70; alternatively, at least some pixel circuits 10 in the same row in the display panel 100 can be electrically connected to the same input control line 70. At this time, the signals transmitted by the input control lines 70 in the same time period can be the same or different. When the signals transmitted by the input control lines 70 in the same time period are the same, the signals transmitted on each input control line 70 will not affect each other, which is beneficial to improving the accuracy of the signals transmitted by the input control lines 70. At this time, the second data clock line 50 can be set in the display panel 100 at the same time to ensure that the signals transmitted by the data lines 30 can be written into the data registers 12 of the pixel circuits 10 one by one, and to ensure the light emission accuracy of the light emitting elements 20 electrically connected to the pixel circuits 10.

[0079] Based on the same inventive concept, an embodiment of the present invention further provides a display device. The display device includes the display panel provided in any embodiment of the present invention. Therefore, the display device includes the technical features of the display panel provided in the embodiment of the present invention, and can achieve the beneficial effects of the display panel provided in the embodiment of the present invention. The same parts can refer to the above description and will not be repeated here.

[0080] Exemplarily, Figure 17 is a schematic structural diagram of a display device provided by an embodiment of the present invention. As Figure 17 shown, the display device 200 includes, but is not limited to, a mobile phone, a tablet computer, a display, a wearable device, etc.

[0081] It should be understood that various forms of structures shown above can be used, and modules, units, etc. can be reordered, added, or deleted. For example, the structures described in the present invention can exist in parallel or some or all of them can exist, as long as the desired results of the technical solutions of the present invention can be achieved. There is no limitation here.

[0082] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that, it includes: a pixel circuit, a light-emitting element, and a data line; the data line is electrically connected to the pixel circuit, and the data line is used to transmit a data signal and an identification signal to the pixel circuit; the pixel circuit is electrically connected to the light-emitting element, and the pixel circuit is used to drive the light-emitting element; the pixel circuit includes a judgment unit and a data register; the judgment unit is used to judge whether the signal transmitted by the data line is the identification signal. If so, it prevents the identification signal from being transmitted to the data register. If not, it controls the signal transmitted by the data line to be written into the data register; the data line is used to transmit the data signal of the current frame display image when the current frame display image of the display panel is different from the previous frame display image, and to transmit the identification signal when the current frame display image of the display panel is the same as the previous frame display image.

2. The display panel according to claim 1, characterized in that, the pixel circuit further includes a pulse generation unit and a switch; the pulse generation unit is used to generate a pulse signal according to the signal stored in the data register; the switch is used to control the time for providing a driving current to the light-emitting element under the control of the pulse signal.

3. The display panel according to claim 1, characterized in that, the judgment unit includes a first comparator and a transmission gate; the first comparator is used to compare the signal transmitted by the data line with a reference value. If it is the first result, it controls the transmission gate to write the signal transmitted by the data line into the data register. If it is the second result, it controls the transmission gate to prevent the signal transmitted by the data line from being written into the data register.

4. The display panel according to claim 3, characterized in that, the judgment unit further includes a pre-storage register arranged between the data line and the first comparator and the transmission gate; the pre-storage register is used to pre-store the signal transmitted by the data line.

5. The display panel according to claim 4, characterized in that, it further includes: a first data clock line; the first data clock line is used to transmit a first data clock signal; within the display time of one frame display image, the first data clock signal includes a valid signal and an invalid signal; the pre-storage register is used to pre-store the signal transmitted by the data line when the first data clock line transmits the valid signal of the first data clock signal.

6. The display panel according to claim 3, characterized in that, the identification signal includes N-bit identification data; the reference value includes M-bit identification data; M < N, and both M and N are positive integers; wherein, the first result is that the first M-bit digital signals of the signal transmitted by the data line are different from the reference value; the second result is that the first M-bit digital signals of the signal transmitted by the data line are the same as the reference value.

7. The display panel according to claim 1, characterized in that, it further includes: an input control line; The input control line is used to transmit a non - enabling level of the input control signal when the data line transmits the identification signal, and transmit an enabling level of the input control signal when the data line transmits the data signal of the current frame display picture; The judgment unit includes a pre - storage register and a transmission gate; The pre - storage register is used to store the input control signal transmitted by the input control line; The transmission gate is used to control the signal transmitted by the data line to be written into the data register when the input control signal stored in the pre - storage register is at the enabling level, and prevent the signal transmitted by the data line from being written into the data register when the input control signal stored in the pre - storage register is at the non - enabling level.

8. The display panel according to any one of claims 3 - 5, wherein, the reference value is the same as the identification signal; wherein, the first result is that the signal transmitted by the data line is different from the reference value; the second result is that the signal transmitted by the data line is the same as the reference value.

9. The display panel according to any one of claims 3 - 7, wherein, further comprising: a second data clock line; the second data clock line is used to transmit a second data clock signal; the data storage unit is used to control the writing of the signal transmitted by the data line under the control of the second data clock signal transmitted by the second data clock line and the judgment unit.

10. The display panel according to claim 2, wherein, further comprising: a pulse clock line; the pulse generation unit includes a counter and a second comparator; the counter is used to output a count value according to the pulse clock signal transmitted by the pulse clock line; the second comparator is used to generate the pulse signal according to the comparison result between the count value and the signal stored in the data register.

11. A display device, wherein, comprising: the display panel according to any one of claims 1 - 10.

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