Memory with device-to-controller communication bus and associated methods

Abstract

Embodiments of the present application relate to memory with device-to-controller communication bus and associated methods. In one embodiment, a memory device includes an input / output terminal separate from data terminals of the memory device. The input / output terminal is operably connected to a memory controller via a communication bus. The memory device is configurable to initiate communication with the memory controller by outputting a signal via the input / output terminal and / or via the communication bus. The memory device is configurable to output the signal according to a different clock signal than a second clock signal used to output or receive data signals via the data terminals. In some embodiments, the memory device is configured to initiate communication via the communication bus only when it possesses a communication token. The communication token is transferable between memory devices operably connected to the communication bus.

Description

Technical Field

[0001] This disclosure relates to memory systems, apparatus, and methods. More specifically, this disclosure relates to memory devices having a communication bus for communication between the memory device and a memory controller, and related systems, apparatus, and methods. Background Technology

[0002] Memory devices are widely used to store information associated with various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Memory devices are frequently provided as internal, semiconductor integrated circuits, and / or external removable devices within computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory, including static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), may require a source of applied power to maintain its data. In contrast, non-volatile memory retains its stored data even without external power. Non-volatile memory is used in various technologies, including flash memory (e.g., NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM). Improvements to memory devices typically include increasing memory cell density, increasing read / write speeds or additionally reducing operating latency, increasing reliability, increasing data retention, reducing power consumption, or lowering manufacturing costs. Summary of the Invention

[0003] Describe a memory device. In some instances, the memory device may include: an input / output terminal configured to be operatively connected to a memory controller, wherein: the input / output terminal is separate from a data terminal of the memory device, the memory device is configured to initiate communication with the memory controller by outputting a signal via the input / output terminal, and the memory device is configured to output the signal via the input / output terminal according to a first clock signal different from a second clock signal used for outputting or receiving data signals via the data terminal.

[0004] Describe a method. In some instances, the method may include: determining that the memory device possesses a communication token; in response to determining that the memory device possesses the communication token, initiating communication with a memory controller, the memory controller being operatively connected to the memory device via a communication bus to an input / output terminal, wherein initiating the communication includes outputting a signal to the memory controller via the input / output terminal and the communication bus, and only if the memory device possesses the communication token.

[0005] A memory system is described. In some instances, the memory system may include: a memory controller; a memory device having data terminals and input / output terminals separate from the data terminals; and a communication bus operatively connecting the input / output terminals of the memory device to the memory controller, wherein: the memory device is configured to initiate communication with the memory controller by transmitting signals to the memory controller via the input / output terminals and the communication bus; and the memory device is configured to transmit the signals according to a first clock signal different from a second clock signal used for transmitting or receiving data signals via the data terminals of the memory device. Attached Figure Description

[0006] Many aspects of this disclosure can be better understood by referring to the following drawings. The components in the drawings are not necessarily drawn to scale. The focus is on clearly illustrating the principles of this disclosure. The drawings should not be construed as limiting this disclosure to the specific embodiments depicted, but are intended for explanation and understanding only.

[0007] Figure 1A A block diagram illustrating various embodiments of a memory system configured according to the present invention.

[0008] Figure 1B A block diagram illustrating various embodiments of a memory device configured according to the present invention.

[0009] Figure 2 A flowchart illustrating a routine for communication via a communication bus according to various embodiments of the present invention.

[0010] Figure 3 A schematic diagram of a system comprising various embodiments of a memory device or system configured according to the technology of the present invention. Detailed Implementation

[0011] As discussed in more detail below, the technology disclosed herein relates to a memory system having a communication bus that operatively connects a memory controller to one or more memory devices. The communication bus may be separate from and / or different from the command / address bus and / or data bus included in a number of memory systems. For example, a communication bus may be provided in addition to the command / address bus and data bus. Unlike the command / address bus and / or data bus, the communication bus facilitates (i) the initiation of communication between the memory device and the memory controller and / or (ii) the transmission of large amounts of information (e.g., reliability information, refresh information, etc.) to the memory controller. Communication transmitted via the communication bus may be governed by a communication protocol (e.g., a token-based communication protocol) and / or may be transmitted according to a clock signal that is separate from and / or different from the clock signal used for communication via the command / address bus and / or data bus. In some embodiments, communication via the communication bus may be performed as one or more background operations of the memory device. Those skilled in the art will understand that the technology may have additional embodiments, and that the technology may be described without further reference. Figures 1A to 3 The described embodiments are practiced in several details.

[0012] In the embodiments described below, memory devices and systems are primarily described in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the invention may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive, and other storage media, including non-volatile, flash (e.g., NAND and / or NOR) storage media.

[0013] A. Overview

[0014] Many memory systems comprise a controller- or processor-centric architecture, meaning that the controller or processor initiates communication between the controller / processor and one or more memory devices operatively connected to the controller / processor. For example, in many memory systems, the memory controller issues commands to the memory devices via a command / address bus. Continuing this example, if the command issued from the memory controller to the memory device is an access command instructing the memory device to output data from the memory device to the memory controller, the memory device responds to the command by (i) accessing the data stored in the memory cell corresponding to the memory address received from the memory controller via the command / address bus and (ii) outputting the data to the memory controller via the data bus. Similarly, if the command issued from the memory controller to the memory device is an access command instructing the memory device to write data to its memory array, the memory device responds to the command by (i) receiving data from the memory controller via the data bus and (ii) writing the data to the memory cell corresponding to the memory address received from the memory controller via the command / address bus. Therefore, the memory device primarily responds to its communication received from the memory controller via the command / address bus. In other words, the command / address bus can be primarily used by the memory controller to initiate communication with the memory device. Conversely, the ability of a memory device to initiate communication with the memory controller via the command / address bus may be limited.

[0015] In some memory systems, memory devices can communicate with a memory controller, but this communication is limited. For example, a memory device may have a programmable mode register to transmit information to the memory controller. The memory controller can then read the information from the programmed mode register. However, in order to read the programmed mode register, the memory controller requires all lines of the command / address bus and data bus to be idle until the memory controller can read the mode register and determine how to respond to the communication. Because the command / address bus and data bus must be idle for the memory controller to read the mode register used, communication via the mode register consumes a significant amount of valuable system bandwidth by consuming these buses until the memory controller has finished reading the mode register and determined how to respond to the communication. Therefore, large amounts of information (e.g., information related to more than one memory row or memory region of the memory device) cannot be transmitted via the mode register without a significant impact on system bandwidth. As another example, some memory devices include alarm pins that can be used to communicate with the memory controller. However, alarm pins are function-specific and are most often used to simply signal to the memory controller that a certain condition has occurred (e.g., a cyclic redundancy check (CRC) error).

[0016] Furthermore, some memory systems include modules of memory devices operatively connected to a memory controller. In these memory systems, the memory controller transmits commands, addresses, and data to each of the memory devices in the module at a time via a command / address bus and / or a data bus. The memory controller also transmits one or more device select signals to identify which memory device in the module will respond to the commands, addresses, and data. In other words, the way the memory controller is operatively connected to each of the memory devices via the command / address bus and the data bus does not facilitate communication with only one memory device without using individual device select signals and / or without entering or using a dedicated operating mode (e.g., per-DRAM addressable capability (PDA) mode).

[0017] To address these issues, a memory system configured according to the present invention may include a communication bus that operatively connects a memory controller to one or more memory devices. The communication bus may be separate from and / or different from the command / address and / or data buses discussed above. For example, a communication bus may be provided in addition to the command / address bus and / or data bus discussed above.

[0018] A communication bus facilitates the initiation of communication between individual memory devices and the memory controller and / or with another memory device operatively connected to the communication bus. Communication via the communication bus can be governed by a communication protocol. This protocol can be separate from and / or different from the communication protocols used for the command / address bus and / or data bus. For example, the communication protocol could be a token-based protocol, in which devices operatively connected to the communication bus (e.g., memory devices, or memory devices and the memory controller) transmit tokens between themselves (e.g., in a circular or other manner). The device currently possessing the token can control the communication transmitted via the communication bus. Thus, a memory device can communicate with the memory controller (and / or one or more other memory devices in the memory system) on an individual basis while it possesses the token.

[0019] In some embodiments, communication may be transmitted via a communication bus based on one or more clock signals. For example, the clock signal may be superimposed on data included in communication transmitted via the communication bus. The receiving device may use a clock recovery circuit to recover the clock signal and the data from the communication. As another example, the memory system of the present invention may include one or more clock traces in addition to the clock traces typically provided in many memory systems. The memory controller and / or memory device (e.g., a dedicated device, a device currently holding a token, etc.) may use the additional clock traces to drive clock signals to other devices in the memory system, which may then use the clock signals for communication transmitted via the communication bus.

[0020] Memory devices and / or memory controllers can use a communication bus to transfer various types of data to any of the devices operatively connected to the communication bus. For example, a memory device can transmit reliability information (e.g., Error Check and Erase (ECS) data, Row Hammer Refresh (RHR) data, refresh counter sequence data, etc.) or other information (e.g., user data, error type information, etc.) to the memory controller via the communication bus. Because the communication bus is separate from the command / address bus and data bus discussed above, communication transmitted via the communication bus does not occupy the command / address bus or data bus. Furthermore, in some embodiments, communication can be transmitted via the communication bus as a background operation. Therefore, continuing with the above examples, memory devices can transmit reliability or other information to the memory controller in batches (e.g., information related to all or subgroups of memory rows in a memory array) and / or without significantly reducing system bandwidth.

[0021] Transmitting large amounts of information via a communication bus can facilitate the implementation of changes in the operation of other memory devices. For example, unlike a memory controller that transmits ECS data to only the address of the memory row with the highest number of failures and / or the number of times the memory row has been serviced, a communication bus allows the memory device to communicate ECS data to a memory controller for all or a larger subgroup of the memory rows of the memory device. This provides a deeper understanding of the reliability of the memory areas of the memory device and can help the memory system determine whether to service or deactivate memory rows within a memory area.

[0022] As another example, unlike statistical sampling techniques used to identify potential victim memory rows of RHR operations (as is typically done in many memory systems), a communication bus can facilitate the implementation of a deterministic RHR solution, in which the memory device tracks the number of times each memory row of the memory device is activated. All or part of this counting information can be communicated via the communication bus to the memory controller to identify victim memory rows of RHR operations. Alternatively, the memory device can compare the activation count of each memory row to a threshold and perform an RHR operation on memory rows adjacent to memory rows whose counts meet or exceed the threshold. As part of this procedure, the memory device can communicate (via the communication bus) a time period during which the memory device will be unavailable to the memory controller, allowing the memory device to perform RHR operations to serve adjacent memory rows. The communicated time period can depend on the number of rows that need to be served. This deterministic RHR solution prevents the memory device from becoming overwhelmed when a large number of memory rows of the memory device are repeatedly activated (e.g., by the actions of a malicious actor) to corrupt data stored in the memory array of the memory device and / or simultaneously trigger RHR operations on a large portion of the memory array.

[0023] Furthermore, by providing a memory system architecture that is not controller-centric or not primarily controller-centric, the memory system configured according to the present invention meets the industry's shift towards improved communication between memory devices and memory controllers and / or less controller-centric technologies and protocols (e.g., Compute Fast Link (CXL), High Bandwidth Memory Generation 3 (HBM3), D6 Discovery, etc.). Alternatively or additionally, data transmitted from the memory device to the memory controller via the communication bus of the present invention can then be relayed to a host device and / or another device operatively connected to the memory controller. Therefore, the memory system of the present invention can help meet the industry's (e.g., cloud and automotive companies) need for greater telemetry opportunities in memory devices (e.g., DRAM memory devices).

[0024] B. Selected embodiments of memory systems and associated apparatus and methods

[0025] Figure 1A A block diagram illustrating a memory system 190 configured according to various embodiments of the present invention is provided. In one embodiment, the memory system 190 is a dual in-line memory module (DIMM). In these and other embodiments, Figure 1A This describes a single module or column of the memory device 100. The well-known components of the memory system 190 have been described... Figure 1A The details are omitted and not described in detail below to avoid unnecessarily obscuring aspects of the invention.

[0026] like Figure 1A As shown, the memory system 190 may include one or more memory devices 100, which may be connected to an electronic device or component thereof capable of temporarily or permanently storing information using the memory. For example, the memory device 100 may be operatively connected to a host device 108 and / or a memory controller 101. The host device 108 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, tablet computer, digital reader, digital media player), or a component thereof (e.g., a central processing unit, coprocessor, dedicated memory controller, etc.). The host device 108 may be a networking device (e.g., a switch, router, etc.); a recorder of digital images, audio, and / or video; a vehicle; an electrical appliance; a toy; or any of a variety of other products. In one embodiment, the host device 108 may be directly connected to the memory device 100 (e.g., via a communication bus (not shown) with signal traces). Alternatively, the host device 108 may be indirectly connected to the memory device 100 (e.g., via a network connection or through an intermediate device, such as through the memory controller 101 and / or through the communication bus 117 via the signal trace).

[0027] The memory device 100 of the memory system 190 is operatively connected to the memory controller 101 via a command / address (CMD / ADDR) bus 118 and a data (DQ) bus 119. (See below for more details.) Figure 1B In more detail, the CMD / ADDR bus 118 and DQ bus 119 are available for the memory controller 101 to transmit commands, memory addresses, and / or data to the memory device 100. In response, the memory device 100 can execute commands received from the memory controller 101. For example, upon receiving a write command from the memory controller 101 via the CMD / ADDR bus 118, the memory device 100 can receive data from the memory controller 101 via the DQ bus 118 and can write the data to the memory cell corresponding to the memory address received from the memory controller 101 via the CMD / ADDR bus 118. As another example, upon receiving a read command from the memory controller 101 via the CMD / ADDR bus 118, the memory device 100 can output data to the memory controller 101 via the DQ bus 118 from the memory cell corresponding to the memory address received from the memory controller 101 via the CMD / ADDR bus 118.

[0028] exist Figure 1AIn the embodiments described herein, the memory device 100 is further operatively connected to the memory controller 101 via a communication bus 120 with one or more signal traces. The communication bus 120 is separate from and / or different from the CMD / ADDR bus 118 and / or DQ bus 119. In some embodiments, the communication bus 120 may be provided in addition to or instead of the CMD / ADDR bus 118 and / or DQ bus 119. Additionally or alternatively, separate and / or different communication protocols may be used to control communication via the communication bus 120 compared to those used to control communication via the CMD / ADDR bus 118 and / or DQ bus 119. In these and other embodiments, the communication bus 120 may be independent of and / or not included in the Joint Institute for Electronics Engineering and Design (JEDEC) specifications.

[0029] Figure 1A The communication bus 120 is operatively connected to one or more (e.g., serial) input / output CBIO pins of the memory device 100. In some embodiments, the communication bus 120 is a shared communication bus. For example, the communication bus 120 may include one or more common signal traces for each of the memory devices 100 to send and receive data (e.g., to / from memory controller 101 and / or to / from another memory device 100). In other embodiments, the communication bus 120 may include one or more signal traces dedicated to one of the memory devices 100 or a subgroup of the memory devices 100, such that only one memory device 100 or only a subgroup of the memory devices 100 can use the dedicated signal traces to send / receive communication (e.g., to / from memory controller 101).

[0030] The following text is about Figure 2 In more detail, memory device 100 may utilize communication bus 120 to initiate communication with memory controller 101 and / or with another memory device 100. In these and other embodiments, memory controller 101 may utilize communication bus 120 to initiate communication with individual memory devices 100. Various communication protocols may be implemented to manage communication between memory devices 100 and / or between memory devices 100 and memory controller 101. One such protocol is a token-based communication protocol (discussed in more detail below), wherein (i) a token is transmitted (e.g., passed) between memory devices 100 and / or between memory devices 100 and memory controller 101, and (ii) any device currently possessing the token controls the communication transmitted via communication bus 120.

[0031] Communication via communication bus 120 can operate using a clock or clock frequency that is separate from and / or different from that used for communication via CMD / ADDR bus 118 and / or via DQ bus 119. For example, communication via CMD / ADDR bus 118 and / or via DQ bus 119 can operate with a clock cycle of approximately 200 picoseconds. Continuing this example, communication via communication bus 120 can operate with a clock cycle of approximately 1 to 2 nanoseconds. Therefore, in this example, the clock cycle used for communication via communication bus 120 can be much larger than the clock cycle used for communication via CMD / ADDR bus 118 and / or via DQ bus 119. The slower clock signal used for communication bus 120 provides a larger timing margin for communication. In these and other embodiments, a much slower clock signal (e.g., a clock signal with a period of approximately 5 nanoseconds) can be used to transmit tokens or control communication on the communication bus 120 between memory devices 100 and / or between memory devices 100 and memory controller 101.

[0032] In some embodiments, memory controller 101 and / or memory device 100 may include clock recovery circuitry (not shown). In these embodiments, memory controller 101 and / or memory device 100 may superimpose a clock signal onto data transmitted via communication bus 120. When memory controller 101 and / or memory device 100 knows or agrees on the frequency of the clock signal, memory controller 101 and / or memory device 100 may use the clock recovery circuitry to recover the data and clock signal from the signals it receives via communication bus 120. In these embodiments, memory system 190 does not require additional clock traces and / or clock terminals for the clock signal.

[0033] In these and other embodiments, memory system 190 may include one or more clock traces 131 operatively connecting one or more external clock terminals of memory device 100 to a memory controller. The clock traces 131 of memory system 190 may be separate from and provided in addition to clock traces (not shown) typically included in the memory system to control communication transmitted via CMD / ADDR bus 118 and / or DQ bus 119. One or more clock signals SCK transmitted via clock trace 131 may be used to control the timing of communication transmitted via communication bus 120. In some embodiments, the clock signal SCK transmitted via clock trace 131 may be driven by memory controller 101. In other embodiments, the clock signal SCK transmitted via clock trace 131 may be driven by one of the memory devices 100 (e.g., the memory device 100 currently possessing a token and / or currently controlling communication transmitted via communication bus 120).

[0034] Figure 1B for Figure 1A A block diagram of a memory device 100 configured according to various embodiments of the present invention. As shown, the memory device 100 may employ multiple external terminals. The external terminals may include those operatively connected to a CMD / ADDR bus 118. Figure 1A The external terminals may further include a chip select terminal for receiving the chip select signal CS, a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, and data terminals DQ, RDQS, DBI, and DMI (e.g., operably connected to...). Figure 1A The memory device 100 further includes a DQ bus 119 and power supply terminals VDD, VSS, and VDDQ. The memory device 100 further includes components operably connected to a communication bus 120. Figure 1A The communication bus 120 can transmit and / or receive data via one or more input / output (I / O) terminals CBIO. For example, in an embodiment where the communication bus 120 includes a single signal trace for use by the memory device 100, the memory device 100 may include a single I / O terminal CBIO. As another example, in an embodiment where the communication bus 120 includes multiple signal traces for use by the memory device 100, the memory device 100 may include multiple I / O terminals CBIO. Additionally, in... Figure 1A In embodiments where the memory system 190 includes one or more additional clock traces 131 to control communication via the communication bus 120, the memory device 100 may further include one or more additional clock terminals to receive one or more clock signals SCK. Figure 1A In embodiments where the memory system 190 does not include one or more additional clock traces 131, the memory device 100 may lack one or more additional clock terminals.

[0035] A power potential V can be supplied to the power supply terminals of the memory device 100. DD and V SS These power supply potentials V DD and V SS It can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can be based on the power supply potential V. DD and V SS Various internal potentials V are generated PP V OD V ARY V PERI Etc. Internal potential V PP It can be used in the line decoder 140, internal potential V OD and V ARYIt can be used in a sense amplifier included in a memory array 150 of a memory device 100, and the internal potential V PERI It can be used in many other circuit blocks.

[0036] It can also supply a power potential V to the power terminals. DDQ The power supply potential V can be... DDQ Together with the power supply potential V SS Together, they are supplied to the input / output (I / O) circuit 160. In an embodiment of the present invention, the power supply potential V DDQ It can be related to the power supply potential V DD The same potential. In another embodiment of the invention, the power supply potential V... DDQ It can be related to the power supply potential V DD Different potentials. However, the potential V of a dedicated power supply. DDQ It can be used in I / O circuit 160 to prevent power supply noise generated by I / O circuit 160 from propagating to other circuit blocks.

[0037] External clock signals and / or complementary external clock signals can be supplied to clock terminals, data clock terminals, and / or additional clock terminals. External clock signals CK, CKF, WCK, WCKF, and / or SCK can be supplied to clock input / output circuit 133. CK and CKF signals can be complementary, and WCK and WCKF signals can also be complementary. Complementary clock signals can simultaneously have relative clock levels and transitions between relative clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0038] An input buffer included in clock input / output circuit 133 can receive an external clock signal. For example, when enabled by a CKE signal from command decoder 115, the input buffer can receive CK and CKF signals, WCK and WCKF signals, and / or SCK signal. Clock input / output circuit 133 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can provide various phase and frequency-controlled internal clock signals based on the received internal clock signal ICLK and the clock enable signal CKE from command decoder 115. For example, internal clock circuit 130 may include a clock path that receives the internal clock signal ICLK and provides various clock signals (not shown) to command decoder 115. Figure 1B(Not shown). Internal clock circuitry 130 can further provide input / output (I / O) clock signals. I / O clock signals can be supplied to I / O circuitry 160 and can be used as timing signals to, for example, determine the timing of data transmission via the DQ bus 119 (…). Figure 1A ) and / or via communication bus 120 ( Figure 1A The output timing and / or input timing of the transmitted data. Multiple clock frequencies can be provided for the I / O clock signal, allowing data to be output from and input to the memory device 100 at different data rates. A higher clock frequency may be desirable when high memory speed is desired. A lower clock frequency may be desirable when lower power consumption and / or looser timing margins are required. An internal clock signal ICLK can also be supplied to the timing generator 135, thus generating various internal clock signals that can be used by the command decoder 115, column decoder 145, I / O circuitry 160, and / or other components of the memory device 100.

[0039] via Figure 1A In embodiments where data transmitted via the communication bus 120 is superimposed with a clock signal, the clock input / output circuit 133, internal clock circuit 130, and / or I / O circuit 160 may include a clock recovery circuit (not shown). As discussed above, the clock recovery circuit can be used to recover the clock signal and data from the signal received at the I / O terminal CBIO. The clock input / output circuit 133, internal clock circuit 130, and / or I / O circuit 160 of the memory device may additionally or alternatively include circuitry for superimposing data transmitted via the communication bus 120 with a clock signal. In these and other embodiments, the clock input / output circuit 133, internal clock circuit 130, and / or I / O circuit 160 may include circuitry configured to output and / or drive a clock signal via a clock trace connected to an external SCK terminal of the memory device 100.

[0040] Memory device 100 may include an array of memory cells, such as memory array 150. The memory cells of memory array 150 may be arranged in multiple memory regions, and each memory region may include multiple word lines (WLs), multiple bit lines (BLs), and multiple memory cells arranged at the intersections of word lines and bit lines. In some embodiments, a memory region may be one or more memory banks or another arrangement of memory cells (e.g., half a memory bank, a subarray within a memory bank, etc.). In these and other embodiments, the memory regions of memory array 150 may be arranged in one or more groups (e.g., one or more groups of memory banks, one or more logical memory columns, or dies, etc.). The memory cells in memory array 150 may include any of a variety of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase-changing, etc. The selection of word lines WLs may be performed by row decoder 140, and the selection of bit lines BLs may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for a corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which may then be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) that can act as a switch. The memory array 150 may also include board lines and corresponding circuitry for managing its operation.

[0041] Address signals and bank address signals can be supplied from outside the memory device 100 to the command terminal and address terminal. The address signals and bank address signals supplied to the address terminal can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive the address signals and supply the decoded row address signal (XADD) to the row decoder 140, and the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive the bank address signal (BADD) and supply the bank address signal to both the row decoder 140 and the column decoder 145.

[0042] Command signals CMD, address signals ADDR, and chip select signals CS can be supplied to command and address terminals (e.g., from memory controller 101 and / or host device 108). Command signals can represent various memory commands (e.g., access commands, which may include read and write commands). The select signal CS can be used to select memory device 100 to respond to commands and addresses provided to the command and address terminals. When an active CS signal is provided to memory device 100, commands and addresses can be decoded, and memory operations can be performed. Command signals CMD can be provided as internal command signals ICMD to command decoder 115 via command / address input circuitry 105. Command decoder 115 may include circuitry for decoding internal command signals ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. Internal command signals may also include output and input activation commands, such as timing commands (not shown) to command decoder 115. The command decoder 115 may further include one or more registers 128 for tracking various counts or values.

[0043] When a read command is issued and promptly supplied to the row and column addresses, read data can be read from the memory cells specified by these row and column addresses in the memory array 150. The read command can be received by a command decoder 115, which provides internal commands to the I / O circuitry 160, enabling read data to be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write (RW) amplifier 155 and the I / O circuitry 160 according to the RDQS clock signal. The data can be programmable in the memory device 100, for example, programmed in the mode register (…). Figure 1B The read delay information RL (not shown in the text) defines the time at which read data is provided. The read delay information RL can be defined in terms of the clock cycle of the CK clock signal. For example, the read delay information RL can be the number of clock cycles of the CK signal after the memory device 100 receives a read command when the associated read data is provided.

[0044] When a write command is issued and the command is supplied to the row and column addresses in a timely manner, write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command can be received by the command decoder 115, which can provide internal commands to the I / O circuit 160, so that the write data can be received by the data receiver in the I / O circuit 160 and supplied to the memory array 150 via the I / O circuit 160 and the RW amplifier 155. The write data can be written to the memory cell specified by the row and column addresses. The write data can be supplied to the data terminals at a time defined by the write delay WL information. The write delay WL information is programmable in the memory device 100, for example, programmed in the mode register ( Figure 1B (Not shown in the text). The write latency WL information can be defined in terms of the clock cycle of the CK clock signal. For example, the write latency WL can be the number of clock cycles of the CK signal after the memory device 100 receives the write command when the associated write data is received.

[0045] As discussed in more detail below, the memory device 100 may additionally or alternatively connect via I / O terminals CBIO and communication bus 120. Figure 1A The memory device 100 sends data to / receives data from memory controller 101 and / or another memory device 100. For example, memory device 100 may transfer data stored in memory array 150 and / or other locations within memory device 100 (e.g., register 118 of command decoder 115 or fuse array (not shown)) to memory controller 101 and / or another memory device 100 via I / O terminal CBIO and communication bus 120. In these and other embodiments, memory device 100 may receive data from memory controller 101 and / or another memory device 100 via communication bus 120 and I / O terminal CBIO. The memory device 100 may then process and / or store the received data. In these and other embodiments, memory device 100 may request (and subsequently receive) specific data from memory controller 101 and / or another memory device 100 via communication bus 120 and I / O terminal CBIO. In some embodiments, communication via I / O terminal CBIO and communication bus 120 can be performed as background operation of memory device 100. Therefore, in these embodiments, DQ bus 119 ( Figure 1AThe system bandwidth on the memory device 100 and data terminals DQ, RDQS, DBI, and DMI is not affected or hindered by communication via I / O terminals CBIO and the communication bus 120. In some embodiments, (i) when additional data is transferred between the memory device 100 and the memory controller 101 via the communication bus 120, and / or (ii) when the memory device 100 or the memory controller 101 communicates using the communication bus 120 instead of using the mode register of the memory device 100, Figure 1A The total bandwidth of the memory system 190 may increase.

[0046] Figure 2 To illustrate various embodiments of the technology according to the present invention for use via a communication bus (e.g., via...) Figure 1A The flowchart of routine 260 for communication via communication bus 120. Routine 260 is described as a set of steps or blocks 261 to 282. All or a subgroup of one or more of blocks 261 to 282 may be provided by a memory system (e.g., Figure 1A The memory system 190) is executed by a component or device. For example, all or a subgroup of one or more of blocks 261 to 282 may be performed by (i) a memory device (e.g., Figure 1A and 1B (i) memory device 100) and / or (ii) memory controller (e.g., Figure 1A The memory controller 101) executes.

[0047] Routine 260 begins at block 261 by determining whether the device currently possesses a communication token (“token”). Possessing a token indicates control over communications transmitted via the communication bus. In other words, in some embodiments, only the device currently possessing the token may transmit communications via the communication bus. The device may be a memory device of a memory system. In these and other embodiments, the device may be a memory controller of the memory system. In other embodiments, only the memory device of the memory system (e.g., not the memory controller) may possess the token, such that communications on the communication bus are reserved for memory device-to-memory controller and / or memory device-to-memory device communications.

[0048] In some embodiments, the device may possess the token by default. For example, a specific memory device or memory controller of the memory system may possess the token by default when the memory system is powered on. In other embodiments, the last device that possessed the token when the memory system was powered off may possess the token when the memory system is subsequently powered on. If the device determines at block 261 that it does not currently possess the token, then routine 260 proceeds to block 266. When routine 260 proceeds to block 266, the device enters listening mode and becomes a monitoring device. On the other hand, if the device determines that it currently possesses the token, then routine 260 proceeds to block 262. When the device possesses the token, the device controls communication via the communication bus. Therefore, when routine 260 proceeds to block 262, the device becomes a control and / or transmission device.

[0049] At block 262, the control device determines whether to transmit communication (e.g., a signal) via the communication bus. In some embodiments, signals transmitted via the communication bus may include data transmission, requests for data, and / or commands to perform operations. For example, the device may send a request for data from one or more other devices operatively connected to the communication bus (e.g., other memory devices and / or memory controllers). As another example, the device may send data to other devices. In these and other embodiments, the device may transmit tokens via the communication bus, and / or the device may transmit clock signals (e.g., superimposed on the data and / or other components of the communication) via the communication bus. If the control device determines that communication is not transmitted via the communication bus, then routine 260 proceeds to block 264. On the other hand, if the control device determines that communication is transmitted via the communication bus, then routine 260 proceeds to block 263.

[0050] At block 263, the control device transmits communication via a communication bus. In some embodiments, the device may transmit communication via the communication bus in a manner recognizable by other devices operatively connected to the communication bus (e.g., having a data structure). For example, communication transmitted via the communication bus may include a header and / or bit length of a preset pattern. The preset pattern and / or bit length may identify whether the communication originates from a memory device or a memory controller. In these and other embodiments, the preset pattern and / or bit length may identify whether the communication is intended for a memory device or a memory controller. In some embodiments, the header may indicate that the communication is memory device-to-memory device communication, memory device-to-memory controller communication, and / or memory controller-to-memory device communication. In these embodiments, the header may therefore indicate whether the request originates from a memory device or memory controller operatively connected to the communication bus and / or whether the communication is intended for a memory device or memory controller operatively connected to the communication bus.

[0051] In some embodiments, communications transmitted via a communication bus may include a device identifier for the control / transmission device and / or a device identifier for the intended recipient of the communications. For example, each device (e.g., each memory device and / or memory controller) may have a unique identifier that can be used to indicate the source of communications transmitted via the communication bus and / or the intended recipient of communications transmitted via the communication bus. In some embodiments, when the memory system operates in a per-DRAM addressable capability (PDA) mode, the unique identifier of the device may correspond to a device identifier. In other embodiments, the device identifier may be different from the PDA mode identifier. In these and other embodiments, the identifier may be provided to the device and / or programmed into the device (e.g., during the manufacture, assembly, and / or testing of the memory system).

[0052] When communication transmitted via a communication bus is the transfer of data from a control / transmission device to another device, the communication may include a unique device identifier of the control / transmission device to indicate to other devices that the data originates from said specific device. The communication may additionally or alternatively include a unique device identifier of the receiving device to indicate to other devices that the data is intended for a device having a device identifier that matches the unique device identifier of the receiving device included in the communication. As another example, when the communication is a request for data, the device identifier included in the communication may indicate which device is requesting data and / or which device intends to respond to the request.

[0053] In these and other embodiments, communications transmitted via the communication bus may include a communication type identifier. The communication type identifier may indicate that the communication is a transmission of data, a request for data, and / or a response to an earlier request for data received from another device operatively connected to the communication bus. In these and other embodiments, the communication type identifier may indicate specific data included within or requested by the communication. In some embodiments, the communication type identifier may indicate that the communication is a token transmission. Alternatively or additionally, the communication type identifier may indicate that the communication is a command. For example, the communication type identifier may indicate that the communication is a reset token command to reset the device currently holding the token. As another example, the communication type identifier may identify the communication as a specific command. Continuing this example, one or more of the multipurpose command (MPC) and / or other commands typically implemented in dual data rate generation 5 (DDR5) and / or other memory devices may be implemented in the communication protocol of the communication bus (e.g., by assigning a unique communication type identifier to each command). Therefore, the communication type identifier can be used to indicate that the communication is a specific one of an MPC or other command.

[0054] In these and other embodiments, the communication may include data intended for operative connection to one or more devices on a communication bus. The data included in the communication may include any type of information stored, generated, and / or processed by the control / transmission device. For example, in memory device-to-memory controller communication, the control / transmission memory device may convey reliability data, alarm information, and / or other information (e.g., user data stored in a portion of the control / transmission device's memory array, information stored in the control / transmission device's registers or fuse array, etc.). Continuing this example, the data may be error checking and erasing (ECS) data for the control / transmission memory device. More specifically, the control / transmission memory device may convey the number of times individual memory rows of its memory array have been corrected during the control / transmission memory device's ECS mode. Because the number of corrections performed on memory rows during the control / transmission memory device's ECS mode can indicate the reliability of the memory rows used to accurately store and retain data, the number of corrections can be considered as reliability data for the memory rows, the memory area containing the memory rows, and / or the control / transmission memory device. In some embodiments, the control / transfer memory device may transmit this information to the memory controller for use with all or subgroups of memory rows of the memory array.

[0055] In another instance, such as in memory device-to-memory controller communication, the data transmitted via the communication bus may be row hammer refresh (RHR) or other refresh information. For example, the control / transfer memory device may track (e.g., the number of times a memory row has been activated or refreshed) via the communication bus. The control / transfer memory device may communicate any one or both of these numbers to the memory controller. Alternatively, the control / transfer memory device may compare the number of times a memory row has been activated to a threshold. When the number of times a memory row has been activated meets or exceeds the threshold, the control / transfer memory device may communicate an amount of time it is unavailable to the memory controller, allowing the control / transfer memory device to perform a row hammer refresh operation to serve adjacent memory rows. The amount of time communicated to the memory controller may depend on the number of memory rows requiring a row hammer refresh operation, and / or may additionally reflect the time the control / transfer memory device predicts it will need to serve the memory array. After notifying the memory controller of the amount of time and / or after transmitting a token to another device, the control / transfer memory device may become unavailable to the memory controller for a time period corresponding to the communicated amount of time. During the time period, the memory device may serve its memory array. Once the time period has elapsed (or earlier), the memory device may become available to the memory controller again.

[0056] In another example, such as in memory device-to-memory device communication or memory controller-to-memory device communication, the data transmitted via the communication bus may be information intended for storage by the receiving memory device. For example, instead of using a DQ bus that operatively connects the control / transmission memory controller to the receiving memory device, the control / transmission memory controller may use the communication bus to send data to the receiving memory device. This can increase the bandwidth of the memory system. In these and other embodiments, the control / transmission memory device may transfer data stored in its memory array to the receiving memory device for storage in the memory array of the receiving memory device. Such capabilities facilitate (i) transferring data between memory devices in the memory system without occupying the DQ bus, (ii) backing up data stored in the control / transmission memory device by storing a copy of the data on the receiving memory device, (iii) deactivating faulty memory areas of the control / transmission memory device by moving data from those memory areas to the memory areas of the receiving memory device, and / or (iv) aggregating data within the memory system.

[0057] In these and other embodiments, the data transmitted via the communication bus may be data previously requested by another device (e.g., via the communication bus). For example, a first control / transmission device (memory device or memory controller) may request data from a first receiving device (another memory device and / or memory controller). When the first receiving device subsequently (e.g., then) possesses a token and thus becomes a second control / transmission device, the second control / transmission device may transmit the data initially requested by the first control / transmission device to the first control / transmission (now the second receiving) device.

[0058] In these and other embodiments, communication transmitted via the communication bus may include a trailer or message tail. The trailer or message tail may be a preset pattern and / or bit length. The preset pattern may indicate the end of communication transmission via the communication bus.

[0059] Communication transmitted via a communication bus can be based on a clock signal. For example, a control / transmission device transmitting communication via the communication bus can superimpose a clock signal onto various components of the communication (e.g., header, device identifier, communication type identifier, data, trailer, or message tail, etc.). The frequency of the clock signal can be known to other devices operatively connected to the communication bus, such that when communication is received via the communication bus, the clock recovery circuitry of the other device can recover the clock signal and the various components of the communication. In these and other embodiments, communication can be transmitted via the communication bus based on a clock signal not transmitted by the communication bus (e.g., a clock signal transmitted to each device via a separate clock trace from the communication bus). In some embodiments, the clock signal and / or the separate clock trace can be dedicated to establishing the timing of signals transmitted via the communication bus. In these and other embodiments, the control / transmission device or another device (e.g., a memory controller or a specific memory device of the memory system) can drive the clock signal transmitted via the clock trace.

[0060] At block 264, the control device determines whether to transmit the token to another device operatively connected to the communication bus. In some embodiments, the token may be transmitted between devices in the memory system based on a clock signal. The clock signal used to transmit the token may be separate from and / or different from the clock signal used for communication (e.g., data transmission) via the communication bus. For example, the clock signal used to transmit the token may be slower than the clock signal used for communication transmission via the communication bus.

[0061] The control device can determine whether to transmit a token at block 264 by referring to a clock signal used for transmitting the token. For example, the period of the clock signal used for transmitting the token could be 5 nanoseconds. Continuing this example, the control device can transmit the token to another device after possessing the token for 30 nanoseconds. Therefore, the control device can determine whether to transmit the token at block 264 by determining whether six cycles of the clock signal have elapsed. If six cycles of the clock signal have not elapsed, then routine 260 can return to block 262 or block 263. On the other hand, if six cycles of the clock signal have elapsed, then routine 260 can proceed to block 265.

[0062] In these and other embodiments, the control device can determine whether to send a token to another device by determining whether the control device has completed the communication transmission via the communication bus. If the control device has completed the communication transmission via the communication bus, the routine can proceed to block 265 and the control device can send the token to the other device. On the other hand, if the control device has not yet completed the communication transmission via the communication bus, the routine 260 can return to block 262 or block 263.

[0063] Alternatively, the control device may determine whether to deliver the token to another device based on previous communications transmitted via the communication bus. For example, at block 263, the control / transmission device may transmit a communication requesting data from the receiving device. After transmitting the request for data (e.g., immediately after the control / transmission device completes transmitting the request via the communication bus and / or when the control / transmission device completes transmitting the request via the communication bus), the control device may determine at block 264 to deliver the token to the receiving device for the receiving device in response to the request for data. (After the receiving device completes its response to the request for data and / or completes transmitting other communications, the receiving device may return the token to the control / transmission device that initially requested the data, or the receiving device may deliver the token to a different device in the memory system, such as the next device in a predetermined sequence.)

[0064] In these and other embodiments, the control device can determine whether to transfer the token to another device by determining whether a reset token command has been received. For example, the memory controller may issue a reset token command via a CMD / ADDR bus, DQ bus, and / or communication bus. In some embodiments, the reset token command may be accompanied by a device identifier indicating which memory device will possess the token. Alternatively or additionally, the memory devices of the memory system may be configured to possess the token by default whenever a reset token command is issued. The memory controller may be configured to issue a reset token command when the memory system is powered on. In other embodiments, the memory controller may issue a reset token command when the memory controller wants to communicate with a specific memory device (e.g., send data to and / or receive data from a specific memory device). In these embodiments, the device identifier accompanying the reset token command identifies the specific memory device that will subsequently possess the token.

[0065] In response to a reset token command, the control device currently holding the token may, at block 263, suspend or disconnect communication via the communication line, release ownership of the token, and / or, at block 264, determine the transfer of the token (e.g., to a device corresponding to the device identifier accompanying the reset token command). Therefore, in some embodiments, blocks 263 and 264 of routine 260 may be executed at least partially simultaneously.

[0066] At block 265, the control device transmits the token to another device operatively connected to the communication bus. In some embodiments, the communication bus may be reserved solely for communication between the memory device and the memory controller and / or between the memory device and another memory device. Therefore, in these embodiments, the memory controller cannot possess the token and / or only the memory device can possess the token. In these and other embodiments, the memory controller may be included in the token ring, such that the memory controller can possess the token.

[0067] In some embodiments, tokens may be transmitted according to a specific and / or preset order. For example, tokens may be transmitted cyclically, such that a first device transmits a token (e.g., always transmits, transmits by default, etc.) to a second device. In these and other embodiments, a control device may transmit a token to a specific device. For example, a control device may transmit a token to a specific device after the control device requests data from said specific device.

[0068] As discussed above, in order to transmit a token, the control device may transmit a header, a receiving device identifier, a token transmission communication type, a trailing or terminating header, and / or other information (e.g., a transmitting device identifier). The receiving device identifier may indicate the specific device that wants to possess the token. In these and other embodiments, the control device may relinquish possession of the token without transmitting the token to the specific device via the communication bus, for example, in response to the control device receiving a reset token command. After transmitting the token, routine 260 may return to block 261.

[0069] Referring again to block 261, if the device determines that it does not currently possess a token, then routine 260 proceeds to block 266. If the device does not possess a token, then the device enters a listening mode and monitors communications transmitted via the communication bus. In other words, the device is a monitoring device. In some embodiments, monitoring communications transmitted via the communication bus includes recovering clock signals and data from signals received via the communication bus (e.g., using one or more clock recovery circuits). In these and other embodiments, monitoring communications transmitted via the communication bus includes referencing clock signals received with reference to clock signals associated with and / or via clock traces separate from the communication bus.

[0070] At block 266, the device monitors a signal on the communication bus that includes a header with the current mode and / or a length of interest. As discussed above, the header of a communication transmitted via communication can indicate whether the communication is intended for a memory device or a memory controller. Therefore, in an embodiment where the monitoring device is a memory device, the monitoring device can monitor a header on the communication bus with a preset mode and / or length indicating that the communication is memory device to memory device or memory controller to memory device communication. Similarly, in an embodiment where the monitoring device is a memory controller, the monitoring device can monitor a header on the communication bus with a preset mode and / or length indicating that the communication is memory device to memory controller communication (or, in an embodiment including multiple memory controllers operatively connected to the communication bus, memory controller to memory controller communication).

[0071] At block 267, the monitoring device determines whether the header received via the communication bus contains a preset pattern and / or the length of interest. If the header received via the communication bus does not contain the preset pattern and / or the length of interest, then routine 260 returns to block 266. On the other hand, if the header received via the communication bus contains the preset pattern and / or the length of interest, then routine 260 proceeds to block 268.

[0072] At box 268, the monitoring device monitors the receiver device identifier and / or control / transmission device identifier of the communication bus. As discussed above, the receiver device identifier indicates the device to which the communication is intended. The control / transmission device identifier indicates which device currently possesses the token and / or transmits communication via the communication bus.

[0073] At block 269, the monitoring device determines whether the receiver device identifier and / or control / transmission device identifier have been received. If the monitoring device determines that the receiver and / or transmission device identifiers have not been received, then routine 260 returns to block 268. On the other hand, if the monitoring device is a memory device and the monitoring device determines that the receiver and / or transmission device identifiers have been received, then routine 260 continues to block 270. In embodiments where the monitoring device is a memory controller and only one memory controller is operatively connected to the communication bus, the receiver device identifier is not required when the header indicates that the communication is intended for the memory controller. In these embodiments, if the monitoring device determines that the transmission device identifier has been received, then routine 260 may proceed to block 272.

[0074] At box 270, the monitoring device compares the receiver device identifier with the monitoring device's device identifier. As discussed above, each device (e.g., each memory device and / or memory controller) may contain a unique device identifier. Therefore, when the receiver identifier matches the monitoring device's unique identifier, the monitoring device can determine that the communication intent is for said device (e.g., contrary to other devices in the memory system).

[0075] At box 271, the monitoring device determines whether the receiver device identifier matches the monitoring device identifier. If the monitoring device determines that the receiver device identifier does not match the monitoring device identifier, then routine 260 may return to box 266. On the other hand, if the monitoring device determines that the receiver device identifier matches the monitoring device identifier, then routine 260 may proceed to box 272.

[0076] At box 272, the monitoring / receiving device monitors the communication type identifier and / or other data transmitted from the transmitting device to the monitoring device via the communication bus. As discussed above, the communication type identifier may indicate whether the communication is a token transfer to the monitoring / receiving device, a data transfer from the transmitting device to the monitoring / receiving device, a request for data from the monitoring / receiving device, and / or a command for the monitoring / receiving device to perform a specific operation. The communication type identifier may additionally or alternatively indicate the type of data contained in the communication (e.g., ECS data, RHR data, alarm information, user data, etc.). When the monitoring / receiving device receives the communication type identifier and / or other data via the communication bus, routine 260 may proceed to box 273.

[0077] At box 273, the monitoring / receiving device determines whether the communication is a token transfer. If the monitoring / receiving device determines that the communication is a token transfer, then routine 260 proceeds to box 274, where the monitoring / receiving device possesses the token. Routine 260 can then proceed to box 281. Alternatively, if the monitoring / receiving device determines at box 273 that the communication is not a token transfer, then the routine proceeds to box 275.

[0078] At box 275, the monitoring / receiving device determines whether the transmitting device is sending monitoring / receiving device data (e.g., reliability information, alarm information, refresh data, user data, etc.). If the monitoring / receiving device determines that the transmitting device is sending monitoring / receiving device data, then routine 260 proceeds to box 276, where the monitoring / receiving device processes and / or stores the data received from the transmitting device via the communication bus. Routine 260 may then proceed to box 281. On the other hand, if the monitoring / receiving device determines at box 275 that the transmitting device is not sending monitoring / receiving device data, then the routine proceeds to box 277.

[0079] At box 277, the monitoring / receiving device determines whether the communication is a command for the monitoring / receiving device to perform an operation. If the monitoring / receiving device determines that the communication is a command for the monitoring / receiving device to perform an operation, then routine 260 proceeds to box 278.

[0080] At block 278, the monitoring / receiving device determines whether the operation involves data transfer from the monitoring / receiving device to the transmitting device. For example, when the communication is a command to transfer data from the monitoring / receiving device to the transmitting device, the monitoring / receiving device may determine at block 278 that the operation involves data transfer from the monitoring / receiving device to the transmitting device. If the monitoring / receiving device determines that the operation involves data transfer from the monitoring / receiving device to the transmitting device, then routine 260 may proceed to block 279, where the monitoring / receiving device may store (i) the device identifier of the transmitting device, (ii) the command and / or operation of the communication received via the communication bus, and / or (iii) the data generated by performing (fully or partially) the operation. As discussed above, when the monitoring / receiving device (e.g., subsequently) receives a control token, it can transfer data to the transmitting device by referring to one or more of these stored information fragments. Routine 260 may then proceed to block 281.

[0081] Returning to box 278, if the monitoring / receiving device determines that the operation does not involve data transmission from the monitoring / receiving device to the transmitting device, then routine 260 may proceed to box 280, where the monitoring / receiving device performs the operation. Routine 260 may then proceed to box 281.

[0082] At box 281, the monitoring / receiving device monitors the tail or trailer of communication on the communication bus. As discussed above, the tail or trailer may be a preset pattern and / or bit length, indicating the end of communication transmitted via the communication bus. At box 282, the monitoring / receiving device determines whether the tail or trailer has been received by the communication bus. If the monitoring / receiving device determines that the tail or trailer has not been received, then routine 260 may return to box 272 (e.g., to receive other information and / or commands from the transmitting device) or to box 281. If the monitoring / receiving device determines at box 282 that the tail or trailer has been received, then routine 260 may return to box 261.

[0083] Although boxes 261 to 282 of routine 260 are discussed and explained in a specific order, Figure 2The routine 260 described herein is not so limited. In other embodiments, routine 260 may be executed in a different order. In these and other embodiments, any one of blocks 261 to 282 of routine 260 may be executed before, during, and / or after any of the other blocks 261 to 282 of routine 260. For example, blocks 273 to 274 and / or blocks 275 to 276 may be executed before, during, and / or after blocks 277 to 279 and / or blocks 277 / 278 / 280 of routine 260. Furthermore, those skilled in the art will recognize that the described routine 260 may be modified but remains within these and other embodiments of the present invention. For example, in some embodiments, it may be omitted and / or repeated. Figure 2 One or more blocks 261 to 282 of routine 260 described herein.

[0084] The above reference Figures 1A to 2 Any of the aforementioned memory systems, devices, and / or methods can be incorporated into any of numerous larger and / or more complex systems, a representative example of which is... Figure 3 The system 390 is schematically shown in the diagram. System 390 may include a semiconductor device assembly 300, a power supply 392, a driver 394, a processor 396, and / or other subsystems and components 398. The semiconductor device assembly 300 may include components generally consistent with those described above. Figures 1A to 2 The described memory system, apparatus, and / or method are characterized by similar features. The resulting system 390 can perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 390 may include, but is not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 390 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communication network). Components of system 390 may also include remote devices and any of a wide variety of computer-readable media.

[0085] C. in conclusion

[0086] The above detailed description of embodiments of this technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. As those skilled in the art will recognize, although specific embodiments and examples of this technology have been described above for illustrative purposes, various equivalent modifications can be made within the scope of this technology. For example, while steps are presented and / or discussed in a given order, alternative embodiments may perform the steps in a different order. Furthermore, the various embodiments described herein may be combined to provide additional embodiments.

[0087] Based on the foregoing, it should be understood that specific embodiments of the present technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the present technology. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, unless the word “or” is explicitly limited to referring only to a single item exclusive to other items in a list referring to two or more items, the use of “or” in this list may be understood to include: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Where the context permits, singular or plural terms may also include plural or singular terms, respectively. Furthermore, as used herein, the phrase “and / or” in phrases such as “A and / or B” means only A, only B, and both A and B. Moreover, the terms “comprising,” “including,” “having,” and “with” are used throughout to mean at least one or more of the described features, such that no larger number of identical features and / or other features of additional types are excluded.

[0088] Based on the foregoing, it should also be understood that various modifications can be made without departing from the present technology. For example, the various components of the present technology can be further divided into sub-components, or the various components and functions of the present technology can be combined and / or integrated. Furthermore, although advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also present these advantages, and not all embodiments are required to present these advantages to fall within the scope of the present technology. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A memory device comprising: Input / output terminals configured to be operatively connected to a memory controller. in: The input / output terminals are separate from the data terminals of the memory device. The memory device is configured to initiate communication with the memory controller by outputting a signal via the input / output terminals, and The memory device is configured to output the signal via the input / output terminal according to a first clock signal that is different from a second clock signal used for outputting or receiving data signals via the data terminal.

2. The memory device according to claim 1, wherein: The memory device further includes a clock terminal; and The memory device is configured to drive or receive the first clock signal via the clock terminal.

3. The memory device of claim 1, wherein the memory device is further configured to superimpose the first clock signal on the information contained in the signal, such that when the signal is output via the input / output terminal, the first clock signal and the information are output via the input / output terminal.

4. The memory device according to claim 1, wherein: The communication is a first communication and the signal is a first signal; The input / output terminals are further configured to be operatively connected to another memory device; and The memory device is further configured to initiate a second communication with the other memory device by outputting a second signal via the input / output terminal.

5. The memory device of claim 4, wherein the second communication includes the transmission of a communication token, the transmission of first data, or a request for second data.

6. The memory device of claim 1, wherein the communication is a transfer of first data to the memory controller or a request for second data from the memory controller.

7. The memory device according to claim 1, wherein: The communication is the transmission of data to the memory controller; The data included in the signal includes error checking and erased data or refresh data; and The refresh data includes the time during which the memory device will be unavailable for the memory controller to perform a row hammer refresh service on one or more memory regions of the memory device.

8. The memory device of claim 1, wherein the memory device is further configured to initiate the communication with the memory controller only when the memory device possesses a communication token.

9. The memory device of claim 1, wherein the signal indicates (i) the intended recipient of the signal, (ii) an identifier of the memory device, and (iii) an identifier of information contained in the signal.

10. The memory device of claim 1, wherein the memory device is further configured to initiate the communication as a background operation of the memory device.

11. A method of operating a memory device, the method comprising: It is determined that the memory device possesses a communication token; In response to determining that the memory device possesses the communication token, communication with the memory controller, which is operatively connected to the input / output terminals of the memory device via a communication bus, is initiated. The initiation of the communication includes outputting a signal to the memory controller via the input / output terminals and the communication bus, and only when the memory device possesses the communication token.

12. The method of claim 11, further comprising: A clock signal is received or driven via the clock terminal of the memory device, wherein the signal transmitted via the communication bus is transmitted according to the clock signal; or The clock signal is superimposed on the information contained in the signal, such that when the signal is output via the input / output terminal, the clock signal and the information are output via the input / output terminal.

13. The method according to claim 11, wherein: The communication is the transmission of data from the memory device to the memory controller; and The data includes refresh data indicating a time period during which the memory device will be unavailable to the memory controller, during which the memory device will perform a row hammer refresh service on the memory area of ​​the memory device.

14. The method of claim 11, wherein the communication is a request for data from the memory controller.

15. The method according to claim 11, wherein: The memory device is a first memory device, the communication is a first communication, and the signal is a first signal; The method further includes, in response to determining that the first memory device possesses the communication token, initiating second communication with a second memory device, the second memory device being operatively connected to the input / output terminal of the first memory device via the communication bus. in: Initiating the second communication includes outputting a second signal to the second memory device via the input / output terminal and the communication bus; and The second communication is the transmission of the communication token from the first memory device to the second memory device.

16. The method of claim 11, wherein: The signal output via the input / output terminal is the first signal; The method further includes, in response to determining that the memory device does not possess the communication token, monitoring a signal of a second signal received via the communication bus for second communication; and The second signal indicates that the second communication intent is for the memory device.

17. The method of claim 16, wherein: The second communication is the transmission of the communication token to the memory device; and The method further includes possessing the communication token in response to receiving the second signal.

18. A memory system comprising: Memory controller; A memory device having a data terminal and separate input / output terminals from the data terminal; as well as A communication bus that operatively connects the input / output terminals of the memory device to the memory controller. in: The memory device is configured to initiate communication with the memory controller by transmitting signals to the memory controller via the input / output terminals and the communication bus; and The memory device is configured to transmit the signal according to a first clock signal that is different from a second clock signal used for transmitting or receiving data signals via the data terminals of the memory device.

19. The memory system of claim 18, wherein: The memory device is a first memory device and the input / output terminal is a first input / output terminal; The memory system further includes a second memory device having a second input / output terminal; The communication bus is further operable to connect (a) the second input / output terminal to the memory controller and (b) the second input / output terminal to the first input / output terminal; The first memory device and the second memory device are configured to transmit communication tokens to each other; and The first memory device is configured to initiate communication with the memory controller only when the first memory device possesses the communication token.

20. The memory system of claim 18, wherein: The memory device is a first memory device and further includes a first clock terminal; The memory system further includes: A second memory device having a second clock terminal; and A clock trace that operatively connects the first clock terminal and the second clock terminal to the memory controller; and The first memory device is configured to receive or drive the first clock signal via the first clock terminal.

Images