A high-resistance semiconductor structure, a spintronic device structure and a method of fabricating the same
By introducing a high-resistance buffer layer between the topological material layer and the substrate, the shunting effect existing in the prior art is solved, the quality of the topological material layer is improved, the problem of shunting effect is solved, and the performance of spintronic devices is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2022-08-16
- Publication Date
- 2026-07-07
AI Technical Summary
In the prior art, the shunting effect caused by the InSb substrate affects the transport properties of the topology material layer. The CdTe substrate is of poor quality and immature, making it difficult to reduce the shunting effect caused by the substrate while ensuring the quality of the topology material layer.
A high-resistivity buffer layer, including a III-V group semiconductor layer such as InxGa1-xSb, InxAl1-xSb or InAs1-xSbx alloy, is used in combination with a CdyZn1-yTe substrate. High-resistivity semiconductor structures are prepared by molecular beam epitaxy and low-temperature growth followed by high-temperature annealing. This reduces carrier concentration and mobility, and lowers the shunting effect.
The growth of high-quality topological material layers was achieved, reducing substrate shunting effects, improving the performance of spintronic devices, and ensuring high resistance and low power consumption characteristics of the devices.
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Figure CN115347114B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of spintronic materials technology, specifically to a high-resistivity semiconductor structure, its fabrication method, and a spintronic device. Background Technology
[0002] Spintronic devices are devices that use electron spin as an information carrier, enabling the generation, transport, and detection of spin. In the post-Moore's Law era, due to the increasingly prominent issues of heat dissipation and miniaturization in semiconductor electronic devices, spintronic devices, with their advantages of low power consumption, non-volatility, high speed, and high integration, have become a current research hotspot.
[0003] In spintronic devices, achieving spin-to-current signal conversion is a crucial step in the device's operation. Traditional spintronic devices primarily utilize magnetic materials to achieve this conversion. In recent years, some topological materials, such as gray tin (… α -Sn) has been found to have high spin-current conversion efficiency, so this type of material has been gradually used in the research of spintronic devices and has good application prospects in spintronic devices.
[0004] However, the fabrication of high-quality topological material layers currently faces several challenges. At present, InSb and CdTe substrates are the primary substrates used for epitaxial growth of topological material layers. InSb substrates, as mature commercial substrates, offer good surface quality and have well-established processing technologies, making them suitable for growing high-quality topological material layers. However, due to their low resistivity and high carrier mobility, InSb substrates can cause shunting effects, negatively impacting the testing of transport properties and device applications. CdTe substrates have even higher resistivity, avoiding shunting effects. However, CdTe is not a mature commercial substrate, with poor surface quality and immature processing technologies, resulting in lower-quality topological material layers. Therefore, for the application of topological material layers in spintronic devices, minimizing the shunting effect caused by the substrate while ensuring film quality is a pressing issue. Summary of the Invention
[0005] The purpose of this invention is to provide a high-resistivity semiconductor structure that can ensure the quality of its topological material layer while reducing the influence of substrate shunting effect, so that the topological material layer can be used in high-performance spintronic devices.
[0006] To achieve the above-mentioned objective, the present invention provides a high-resistivity semiconductor structure, comprising: a substrate, a high-resistivity buffer layer, and a topological material layer, wherein the high-resistivity buffer layer is a III-V group semiconductor layer with a thickness of 5-50 nm.
[0007] Preferably, the material of the high-resistance buffer layer is In.x Ga 1-x Sb、In x Al 1-x Sb or InAs 1-x Sb x Alloy (0≤x≤1).
[0008] Preferably, the substrate material is Cd. y Zn 1-y Te(0≤y≤1).
[0009] Preferably, the topological material layer is α -Sn 1-z Ge z (0≤z≤0.5).
[0010] Preferably, the thickness of the topological material layer is 0.1-200 nm.
[0011] The present invention provides a spintronic device structure based on a high-resistivity semiconductor structure, including the aforementioned high-resistivity semiconductor structure, a spin injection layer located on the upper surface of a topological material layer, and electrodes located on both sides of the interface between the spin injection layer and the topological material layer.
[0012] Preferably, the spin-injection layer consists of a ferromagnetic material layer and a protective layer from top to bottom.
[0013] The present invention also provides a method for fabricating a high-resistivity semiconductor structure, comprising: providing Cd y Zn 1-y A Te substrate is used, where 0 ≤ y ≤ 1; the surface is treated with atomic hydrogen or ion sputtering; a high-resistivity buffer layer with a thickness of 5-50 nm is grown on the substrate by molecular beam epitaxy; the substrate temperature is raised to above 300°C and annealed for 10-30 min; a topological material layer is grown on the high-resistivity buffer layer by molecular beam epitaxy. Preferably, the material of the high-resistivity buffer layer is In. x Ga 1-x Sb、In x Al 1-x Sb or InAs 1-x Sb x Alloy (0≤x≤1), the topological material layer is α -Sn 1-z Ge z (0≤z≤0.5).
[0014] Preferably, the processing time for atomic hydrogen or ion sputtering is 30-120 min.
[0015] Preferably, the substrate temperature is kept below 300°C during the growth of the high-resistivity buffer layer.
[0016] As can be seen from the above technical solution, this invention, by adding a high-resistance buffer layer between the topological material layer and the substrate, can avoid the shunting effect of the substrate while ensuring the quality of the topological material layer, thereby enabling the topological material layer to be used in high-performance spintronic devices. Furthermore, the fabrication method of this invention utilizes low-temperature epitaxial growth and high-temperature annealing on Cd... y Zn 1-y A high-resistivity buffer layer can be obtained on the Te substrate, thus providing a foundation for the subsequent growth of high-quality topological material layers. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the high-resistivity semiconductor structure in this invention.
[0018] Figure 2 This is a schematic diagram of the spintronic device structure in this invention.
[0019] Figure 3 This is a schematic diagram of the spin injection layer structure of the spintronic device in this invention.
[0020] Figure 4 The results are the structural characterization results from Example 1.
[0021] Figure 5 The electrical properties of the high-resistivity InSb buffer layer in Example 1 are shown. Detailed Implementation
[0022] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.
[0023] This invention provides a high-resistivity semiconductor structure, such as Figure 1 As shown, the structure includes: a substrate 1, a high-resistivity buffer layer 2, and a topological material layer 3. The high-resistivity buffer layer is a III-V semiconductor layer, and its thickness is 5-50 nm. In the structure of this invention, since the high-resistivity buffer layer is a III-V semiconductor material, the lattice constant can be effectively adjusted to match the topological material used through alloying of the III-V semiconductor material, forming a more stable structure. Simultaneously, the ultrathin high-resistivity buffer layer and the nanostructure formed within it can effectively reduce carrier concentration and mobility, achieving an order-of-magnitude improvement in resistance, reducing shunting effects, and forming a higher-quality device structure. Preferably, the thickness of the high-resistivity buffer layer is 10-30 nm.
[0024] In this invention, the material of the high-resistivity buffer layer can be In. x Ga 1-x Sb、In x Al 1-x Sb, InAs 1-x Sbx (0≤x≤1). This type of material can have its lattice constant broadened through alloying, making it more widely applicable, especially with α-Sn of different compositions. 1-z Ge z Matching the crystal structure and lattice constant of these materials improves the crystal quality of the topological material and the corresponding device performance. Furthermore, the selection of these three groups of materials can broaden the bandgap range of the buffer layer material, providing more options for bandgap design of the device structure.
[0025] In this invention, substrate 1 is a commonly used high resistivity substrate; preferably, the substrate material is Cd. y Zn 1-y Te, where 0≤y≤1.
[0026] In this invention, the topological material layer 3 is preferably α-Sn. 1-z Ge z Where 0 ≤ z ≤ 0.5. This type of material exhibits high spin-to-current conversion efficiency. The thickness of topological material layer 3 is 0.1-200 nm.
[0027] In this invention, the high-resistivity semiconductor structure can be obtained by sequentially depositing a high-resistivity buffer layer 2 and a topological material layer 3 onto a substrate 1 using molecular beam epitaxy. Specifically, Cd is provided. y Zn 1-y Te substrate; the substrate surface is treated with atomic hydrogen or ion sputtering; a high-resistivity buffer layer is grown on the substrate; the substrate temperature is raised to 300°C and annealed for 10-30 min; finally, a topological material layer is grown on the high-resistivity buffer layer by molecular beam epitaxy. In this invention, the material of the high-resistivity buffer layer is In. x Ga 1-x Sb、In x Al 1-x Sb or InAs 1-x Sb x Alloy (0≤x≤1), topological material layer is α -Sn 1-z Ge z (0≤z≤0.5). In this preparation method, the low-temperature growth followed by high-temperature annealing can more effectively reduce carrier concentration and mobility, and further reduce the generation of shunting effect.
[0028] In this invention, the processing time of atomic hydrogen furnace or ion sputtering is 30-120 min, while the substrate temperature is kept below 300°C when growing the high-resistivity buffer layer.
[0029] The present invention also provides a spintronic device structure based on the above-mentioned high-resistivity semiconductor structure, such as... Figure 2 and Figure 3As shown, the device includes the aforementioned high-resistivity semiconductor structure, a spin injection layer 4 located above the topological material layer 3, and electrodes 5 located on both sides of the interface between the spin injection layer 4 and the topological material layer 3. The spin injection layer 4 consists of a ferromagnetic material layer 4-1 and a protective layer 4-2, from top to bottom. The spin injection layer provides spin current to the device, the ferromagnetic material layer generates the spin current, and the protective layer protects the surface of the topological material layer. The topological material layer is used to achieve spin-to-current signal conversion.
[0030] In this invention, there are no limitations on the electrode material, protective layer material, and ferromagnetic material; any material well-known to those skilled in the art can be used. In this invention, the ferromagnetic material can be Fe, Co, Ni, or alloys thereof, and the protective layer material can be Ag, Al, or AlOx.
[0031] Example 1
[0032] (1) Prepare a CdTe substrate with a (001) crystal plane;
[0033] (2) The CdTe substrate was deoxidized in an atomic hydrogen furnace for 60 min.
[0034] (3) An InSb buffer layer was grown on a CdTe substrate using molecular beam epitaxy. During the growth process, the Sb:In beam current ratio was 1:1, the substrate temperature was 200℃, and the thickness of InSb was 20 nm.
[0035] (4) Increase the substrate temperature to 300°C and anneal for 10 min to obtain a high-resistivity InSb buffer layer;
[0036] (5) Gray tin films of 50 nm, 100 nm and 200 nm were grown in a group IV molecular beam epitaxy apparatus.
[0037] Figure 4 The following are the characterization results for the three gray tin thin film structures of different thicknesses. (a) and (b) show the very clear (2 × 2) reconstructed linear RHEED pattern during the growth of the gray tin film. The clear diffraction peaks and thickness interference fringes of gray tin (004) in the XRD characterization results of (c) indicate that it has good crystal quality and surface / interface quality. The reciprocal space scan (RSM) in Figure (d) shows that the gray tin film is fully strained. Overall, the gray tin film has good crystal quality.
[0038] Figure 5The electrical properties of the obtained high-resistivity InSb buffer layer are characterized. Below 200 K, the resistivity of the high-resistivity InSb buffer layer increases sharply with decreasing temperature (left figure), and the resistivity at low temperature is an order of magnitude larger than that of the ordinary InSb buffer layer; correspondingly, the charge carriers of the high-resistivity InSb buffer layer decrease sharply (right figure), and it exhibits relatively insulating properties overall.
[0039] The gray tin thin film obtained by the above method can achieve a Fermi velocity of 1.0 × 10⁻⁶ for its topological surface states. 6 The speed is on the order of m / s, the momentum relaxation time can reach the order of 100 fs, and the theoretical conversion efficiency (the ratio of current density to spin current density) can reach the order of 100 nm.
[0040] Example 2
[0041] (1) Prepare Cd crystals with (001) crystal plane 0.9 Zn 0.1 Te substrate;
[0042] (2) Cd in an atomic hydrogen furnace 0.9 Zn 0.1 Te substrates were deoxidized and treated in an atomic hydrogen furnace for 60 minutes.
[0043] (3) Using molecular beam epitaxy, on Cd 0.9 Zn 0.1 In grown on Te substrate 0.9 Ga 0.1 Sb buffer layer. During growth, the Sb:(In+Ga) beam current ratio was 1:1, the substrate temperature was 200℃, and In... 0.9 Ga 0.1 The thickness of Sb is 30 nm;
[0044] (4) Increase the substrate temperature to 350°C and anneal for 30 min to obtain a high-resistivity InSb buffer layer;
[0045] (5) Growth of 50 nm α-Sn in a group IV molecular beam epitaxy apparatus 0.9 Ge 0.1 film.
[0046] The α-Sn obtained in this embodiment 0.9 Ge 0.1 The film also has high quality, and In 0.9 Ga 0.1 The carrier concentration in the Sb buffer layer is reduced by an order of magnitude.
[0047] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A high-resistivity semiconductor structure, characterized in that, The system comprises a substrate, a high-resistivity buffer layer, and a topological material layer, sequentially arranged therefrom. The high-resistivity buffer layer is a III-V group semiconductor layer, wherein the thickness of the high-resistivity buffer layer is 10-30 nm, and the material of the high-resistivity buffer layer is In. x Ga 1-x Sb、In x Al 1-x Sb or InAs 1-x Sb x Alloy, wherein 0 ≤ x ≤ 1, and the substrate material is Cd. y Zn 1-y Te, where 0≤y≤1, and the topological material layer is... α -Sn 1-z Ge z , where 0≤z≤0.
5.
2. The high-resistivity semiconductor structure according to claim 1, characterized in that, The thickness of the topological material layer is 0.1-200 nm.
3. A spintronic device structure, characterized in that, It includes the high-resistivity semiconductor structure as described in any one of claims 1-2, a spin-injection layer located on the upper surface of the topological material layer, and electrodes located on both sides of the interface between the spin-injection layer and the topological material layer.
4. The spintronic device structure according to claim 3, characterized in that, The spin-injection layer consists of a ferromagnetic material layer and a protective layer from top to bottom.
5. A method for preparing a high-resistivity semiconductor structure, characterized in that, The specific steps include: (1) Provide Cd y Zn 1-y Te substrate, where 0≤y≤1; (2) Treating Cd with atomic hydrogen or ion sputtering y Zn 1-y Te substrate surface; (3) Using molecular beam epitaxy, in Cd y Zn 1-y A high-resistivity buffer layer with a thickness of 5-50 nm is grown on a Te substrate, and the substrate temperature is kept below 300°C during the growth of the high-resistivity buffer layer. (4) Raise the substrate temperature to above 300°C and anneal for 10-30 min; (5) A topological material layer is grown on the obtained high-resistivity buffer layer by molecular beam epitaxy.
6. The method according to claim 5, characterized in that, In step (2), the treatment time for atomic hydrogen or ion sputtering is 30-120 min.