Array substrate, display panel, display device, and method for preparing array substrate

Abstract

An array substrate (1), a display panel, a display device and a method for preparing the array substrate (1). The array substrate (1) comprises: a base substrate (10); a plurality of pixels (P) arranged on the base substrate (10), the plurality of pixels (p) being arranged in an array on the base substrate (10), at least one pixel (P) comprising a pixel driving circuit and a light emitting unit (4) electrically connected to the pixel driving circuit; a fingerprint recognition structure (3), the fingerprint recognition structure (3) comprising a first capacitor electrode (31), the first capacitor electrode (31) being configured to: in response to at least a portion of a touch subject (F) covering the first capacitor electrode (31), a capacitor (CFP) for fingerprint recognition is formed between at least a portion of the touch subject (F) and the first capacitor electrode (31). The fingerprint recognition structure (3) is located in at least one pixel (P), the pixel driving circuit comprises a thin film transistor, the thin film transistor comprises an active layer (ACT) and a gate, and the first capacitor electrode (31) is located in the same layer as the active layer (ACT) and the gate of the thin film transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular, the present invention relates to an array substrate, a display panel, a display device, and a method for preparing the array substrate. Background Art

[0002] Due to the uniqueness of fingerprint patterns, fingerprint recognition can be performed by comparing the detailed features of different fingerprints, thereby realizing functions such as identity authentication and privacy protection. With the development of technology, fingerprint recognition technology has been widely used in various terminal devices such as display devices. For example, terminal devices include various types of fingerprint recognition technologies such as capacitive, optical, and ultrasonic. In this way, integrating at least one type of fingerprint recognition technology mentioned above into various terminal devices such as display devices has gradually become an important topic of concern to R&D personnel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0004] In one aspect, an array substrate is provided, comprising: a base substrate; a plurality of pixels disposed on the base substrate, the plurality of pixels being arranged in an array on the base substrate, at least one of the pixels comprising a pixel driving circuit and a light-emitting unit electrically connected to the pixel driving circuit; a fingerprint recognition structure, the fingerprint recognition structure comprising a first capacitor electrode, the first capacitor electrode being configured to: in response to at least a portion of a touch subject covering the first capacitor electrode, form a capacitor for fingerprint recognition between at least a portion of the touch subject and the first capacitor electrode, wherein the fingerprint recognition structure is located in the at least one pixel, the pixel driving circuit comprising a thin film transistor, the thin film transistor comprising an active layer and a gate, the first capacitor electrode being located on the same layer as one of the active layer and the gate of the thin film transistor.

[0005] According to some exemplary embodiments, the first capacitor electrode is located on a side of the light emitting unit close to the base substrate.

[0006] According to some exemplary embodiments, the array substrate includes a plurality of the fingerprint recognition structures, and the plurality of fingerprint recognition structures are respectively disposed in a plurality of pixels.

[0007] According to some exemplary embodiments, the substrate includes a first surface away from the active layer and a second surface close to the active layer; the first capacitor electrode and the active layer of the thin film transistor are located on the same layer, the array substrate also includes a buffer layer, and the buffer layer is located between the second surface and the active layer; and the capacitor for fingerprint recognition includes a dielectric layer, and the dielectric layer includes a portion of the substrate and a portion of the buffer layer.

[0008] According to some exemplary embodiments, the first capacitor electrode includes a doped semiconductor material.

[0009] According to some exemplary embodiments, within a same pixel, a distance between the first capacitor electrode and an active layer adjacent thereto is greater than 1 micrometer.

[0010] According to some exemplary embodiments, the substrate includes a first surface away from the active layer and a second surface close to the active layer; the first capacitor electrode and the gate of the thin film transistor are located on the same layer, the array substrate also includes a buffer layer and a first gate insulating layer, the buffer layer is located between the second surface and the active layer, and the first gate insulating layer is located between the active layer and the gate; and the capacitor for fingerprint recognition includes a dielectric layer, and the dielectric layer includes a portion of the substrate, a portion of the buffer layer and a portion of the first gate insulating layer.

[0011] According to some exemplary embodiments, within a same pixel, the distance between the first capacitor electrode and a gate electrode adjacent thereto is greater than 3 micrometers.

[0012] According to some exemplary embodiments, the array substrate further includes a shielding layer, wherein the shielding layer is located between the base substrate and the active layer, and the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the active layer of the thin film transistor on the base substrate; and the fingerprint recognition structure further includes an excitation component, wherein the excitation component is configured to generate an excitation signal for fingerprint recognition, and the excitation component and the shielding layer are located on the same layer.

[0013] According to some exemplary embodiments, an orthographic projection of the excitation component on the substrate surrounds an orthographic projection of the first capacitor electrode on the substrate.

[0014] According to some exemplary embodiments, the light emitting unit includes an anode, a cathode and a light emitting layer sandwiched between the anode and the cathode, the cathode is farther away from the base substrate than the anode, the anode is a transparent anode, and the cathode is a reflective cathode.

[0015] According to some exemplary embodiments, the thin film transistor further includes a source and a drain, and an orthographic projection of each of the active layer, gate, source and drain of the thin film transistor on the substrate does not overlap with an orthographic projection of the first capacitor electrode on the substrate.

[0016] According to some exemplary embodiments, the array substrate also includes a first signal line and a second signal line, the first signal line and the second signal line are respectively configured to provide electrical signals to the pixel driving circuit, the first signal line extends along a first direction, and the second signal line extends along a second direction; and the orthographic projection of each of the first signal line and the second signal line on the base substrate does not overlap with the orthographic projection of the first capacitor electrode on the base substrate.

[0017] According to some exemplary embodiments, the second signal line is configured to provide a data signal to the pixel driving circuit; and the data signal is also provided to the driving component.

[0018] According to some exemplary embodiments, the base substrate comprises a transparent material; and / or the base substrate has a thickness between 5 and 20 micrometers; and / or the buffer layer has a thickness between 1000 and 4000 angstroms.

[0019] In another aspect, a display panel is further provided, wherein the display panel includes the array substrate as described above.

[0020] On the other hand, a display device is provided, wherein the display device includes the array substrate as described above or the display panel as described above.

[0021] In yet another aspect, a method for preparing an array substrate is provided, comprising:

[0022] providing a substrate base plate;

[0023] forming a fingerprint recognition structure on the substrate, wherein the fingerprint recognition structure comprises a first capacitor electrode, and the first capacitor electrode is configured to: in response to at least a portion of a touch subject covering the first capacitor electrode, form a capacitor for fingerprint recognition between at least a portion of the touch subject and the first capacitor electrode;

[0024] A plurality of pixels are formed on the substrate, wherein the plurality of pixels are arranged in an array on the substrate, and at least one of the pixels comprises a pixel driving circuit and a light emitting unit electrically connected to the pixel driving circuit.

[0025] The fingerprint recognition structure is located in the at least one pixel, the pixel driving circuit includes a thin film transistor, the thin film transistor includes an active layer and a gate, and the first capacitor electrode and one of the active layer and the gate of the thin film transistor are formed by the same composition process. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0027] Figure 1 is a plan view of an array substrate according to some exemplary embodiments of the present disclosure;

[0028] Figure 2 According to some exemplary embodiments of the present disclosure, an array substrate is provided along Figure 1 A cross-sectional view taken along line AA';

[0029] Figure 3 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure;

[0030] Figure 4 yes Figure 2 A partial enlarged view of a portion I of FIG. 1 , which schematically shows a partial cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure;

[0031] Figure 5 yes Figure 2 A partial enlarged view of a portion I of FIG. 1 , which schematically shows a partial cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure;

[0032] Figure 6 is a schematic diagram of a capacitive fingerprint recognition technology used in an array substrate according to an embodiment of the present disclosure;

[0033] Figure 7 is a partial plan view of an array substrate according to some exemplary embodiments of the present disclosure, in which a fingerprint recognition structure is schematically shown;

[0034] Figure 8 is a flow chart of a method for preparing an array substrate according to some exemplary embodiments of the present disclosure;

[0035] 9A to 9D is a cross-sectional view of a structure formed after some steps of a method for preparing an array substrate according to some exemplary embodiments of the present disclosure are performed; and

[0036] Fig.10 is a plan view of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0038] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0039] When an element is described as "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on the other element, directly connected to the other element or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." to "directly between...", "adjacent" to "directly adjacent" or "on..." to "directly on...", etc. In addition, the term "connection" may refer to physical connection, electrical connection, communication connection and / or fluid connection. In addition, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. As used herein, the term "and / or" includes any combination and all combinations of one or more of the listed related items.

[0040] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various parts, components, elements, regions, layers and / or parts, these parts, components, elements, regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and / or part from another. Thus, for example, the first part, first member, first element, first region, first layer and / or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and / or second part without departing from the teachings of the present disclosure.

[0041] For ease of description, spatial relational terms, such as "upper", "lower", "left", "right", etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that the spatial relational terms are intended to cover other different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the figure is turned upside down, elements described as "below" or "beneath" other elements or features will be oriented "above" or "above" the other elements or features.

[0042] Those skilled in the art should understand that, in this document, unless otherwise specified, the expression "height" or "thickness" refers to the dimension along the surface of each film layer arranged perpendicular to the display panel, that is, the dimension along the light emitting direction of the display panel, or the dimension along the normal direction of the display device, or the dimension along the Z direction in the accompanying drawings.

[0043] Herein, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0044] It should be noted that the expressions "same layer", "same layer arrangement" or similar expressions refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0045] In this document, unless otherwise specified, the expression "electrically connected" may mean that two parts or elements are directly electrically connected, for example, part or element A is in direct contact with part or element B, and electrical signals can be transmitted between the two parts; it may also mean that two parts or elements are electrically connected through a conductive medium such as a conductive wire, for example, part or element A is electrically connected to part or element B through a conductive wire to transmit electrical signals between the two parts or elements; it may also mean that two parts or elements are electrically connected through at least one electronic component, for example, part or element A is electrically connected to part or element B through at least one thin film transistor to transmit electrical signals between the two parts or elements.

[0046] According to the working principle, fingerprint recognition sensors can be divided into many types, such as optical fingerprint sensors, capacitive fingerprint sensors, inductive fingerprint sensors, pressure-sensitive fingerprint sensors, thermal fingerprint sensors, ultrasonic scanning fingerprint sensors and radio frequency fingerprint sensors.

[0047] For example, in an optical fingerprint sensor, the touch body such as a finger is placed on a substrate, and the light emitted from the built-in light source or display unit is reflected by the finger and projected onto a charge coupled device (CCD), thereby forming a multi-grayscale fingerprint image that can be processed by the fingerprint recognition sensor. Since light cannot penetrate the surface layer of the skin (dead skin layer), it can only scan the surface of the finger skin, or scan the dead skin layer, but cannot penetrate into the dermis. Therefore, the cleanliness of the finger surface has a direct impact on the result of fingerprint recognition.

[0048] For example, in a capacitive fingerprint sensor, when a touch body such as a finger is placed on the substrate, the capacitive fingerprint sensor measures the very small conductivity change signal caused by the fingerprint, and then uses the measured data to form an image of the fingerprint. The outermost layer of the skin of the finger, that is, the fingerprint, is non-conductive, while the subcutaneous layer inside the fingerprint is conductive. In this way, the capacitive fingerprint sensor has lower requirements for the cleanliness of the finger surface than the optical fingerprint sensor, and the capacitive fingerprint sensor can recognize the lines in the inner layer of the finger, thereby improving the security of fingerprint recognition.

[0049] The embodiments of the present disclosure at least provide an array substrate, a display panel, a display device and a method for preparing an array substrate. The array substrate comprises: a base substrate; a plurality of pixels disposed on the base substrate, the plurality of pixels being arranged in an array on the base substrate, at least one of the pixels comprising a pixel driving circuit and a light-emitting unit electrically connected to the pixel driving circuit; a fingerprint recognition structure, the fingerprint recognition structure comprising a first capacitor electrode, the first capacitor electrode being configured to: in response to at least a portion of a touch subject covering the first capacitor electrode, a capacitor for fingerprint recognition is formed between at least a portion of the touch subject and the first capacitor electrode, wherein the fingerprint recognition structure is located in the at least one pixel, the pixel driving circuit comprises a thin film transistor, the thin film transistor comprises an active layer and a gate, and the first capacitor electrode is located in the same layer as one of the active layer and the gate of the thin film transistor. In this way, the fingerprint recognition structure can be disposed in the pixel of the array substrate, thereby facilitating the integration of the fingerprint recognition structure in the display device.

[0050] Figure 1 is a plan view of an array substrate according to some exemplary embodiments of the present disclosure, Figure 2 According to some exemplary embodiments of the present disclosure, an array substrate is provided along Figure 1 A cross-sectional view taken along line AA' in FIG. Figure 1 and Figure 2The array substrate 1 may include: a base substrate 10, for example, the base substrate 10 may be formed of glass, plastic, polyimide, etc. The base substrate 10 includes a display area AA and a peripheral area (or non-display area) NA located on at least one side of the display area AA (for convenience of description, the side is referred to as the first side).

[0051] Continue to refer to Figure 1 The array substrate 1 may include a plurality of pixel units P (in Figure 1 (shown schematically in a dotted box in FIG. 1 ), a plurality of pixel units P may be arranged in an array on the substrate 10 along a first direction X and a second direction Y. Each pixel unit P may further include a plurality of sub-pixels, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel. Figure 1 , one sub-pixel SP is schematically shown.

[0052] For example, Figure 1 As shown, the peripheral area NA may be located on four sides of the display area AA, that is, it surrounds the display area AA.

[0053] It should be noted that in the drawings, the pixel units and sub-pixels are schematically shown in a rectangular shape, but this does not constitute a limitation on the shapes of the pixel units and sub-pixels included in the display panel provided by the embodiments of the present disclosure.

[0054] The array substrate 1 may further include a light emitting unit 4, such as an OLED device. Figure 2 As shown, the light emitting unit 4 includes a first electrode 41 , a second electrode 43 disposed opposite to the first electrode 41 , and a light emitting layer 42 disposed between the first electrode 41 and the second electrode 43 .

[0055] One of the first electrode 41 and the second electrode 43 is an anode, and the other is a cathode. For example, the first electrode 41 may be a transparent anode, for example, it may be formed of a transparent conductive material, and the transparent conductive material may include indium tin oxide (ITO), indium zinc oxide (IZO), etc.; the second electrode 43 may be a reflective cathode, for example, it may be formed of a metal material, and the metal material may include an alloy such as magnesium aluminum alloy (MgAl), lithium aluminum alloy (LiAl), or a single metal such as magnesium, aluminum, lithium, etc. The light-emitting layer 42 may be a multilayer structure, for example, it may include a multilayer structure formed by a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer.

[0056] It should be noted that the light-emitting unit 4 can be actively driven or passively driven. The passively driven OLED array substrate is composed of a cathode and an anode, and the intersection of the anode and the cathode can emit light. The driving circuit can be externally installed by connection methods such as tape carrier packaging or glass chip carrier. The actively driven OLED array substrate can be equipped with a pixel driving circuit for each pixel. The pixel driving circuit can include a thin film transistor with a switching function (i.e., a switching transistor), a thin film transistor with a driving function (i.e., a driving transistor) and a charge storage capacitor. In addition, the pixel driving circuit can also include other types of thin film transistors with compensation functions. It should be understood that in the embodiments of the present disclosure, the display panel can be equipped with various known types of pixel driving circuits, which will not be repeated here.

[0057] For example, Figure 2 As shown, the array substrate 1 includes a driving circuit layer 9, and the above-mentioned pixel driving circuit can be arranged in the driving circuit layer 9. An insulating layer 91 can be arranged between the driving circuit layer 9 and the light-emitting unit 4, and the insulating layer 91 can be a single insulating film layer or a stack of multiple insulating film layers.

[0058] The array substrate 1 may further include various signal lines disposed on the base substrate 10, including scanning signal lines, data signal lines, ELVDD power lines, and ELVSS power lines, etc., so as to provide various signals such as control signals, data signals, and power supply voltages to the pixel driving circuit in each sub-pixel. Figure 1 In the illustrated embodiment, a scan signal line 61 and a data signal line 64 are schematically illustrated. The scan signal line 61 and the data signal line 64 may be electrically connected to each sub-pixel. For example, the scan signal line 61 may extend substantially along a first direction X, and be used to provide an electrical signal such as a scan signal to the pixel driving circuit; the data signal line 64 may extend substantially along a second direction Y, and be used to provide an electrical signal such as a data signal to the pixel driving circuit.

[0059] Below, taking the 7T1C pixel driving circuit as an example, the structure of the pixel driving circuit is described in detail. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit. In the absence of conflict, other known pixel driving circuit structures can be applied to the embodiments of the present disclosure.

[0060] Figure 3 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure. Figures 1 to 3, the pixel driving circuit may include: a plurality of thin film transistors and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (ie, OLED). The plurality of thin film transistors include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. Each transistor includes an active layer, a gate, a source electrode, and a drain electrode.

[0061] The display substrate may further include a plurality of signal lines, for example, the plurality of signal lines include: a scanning signal line 61 for transmitting a scanning signal Sn, a reset signal line 62 for transmitting a reset control signal RESET (for example, the reset control signal RESET may be a scanning signal of a previous row), a light emitting control line 63 for transmitting a light emitting control signal En, a data signal line 64 for transmitting a data signal Dm, a driving voltage line 65 for transmitting a driving voltage VDD, an initialization voltage line 66 for transmitting an initialization voltage Vint, and a power supply line 67 for transmitting a reference voltage VSS.

[0062] The storage capacitor Cst may include two capacitor plates Cst1 and Cst2. In this article, the capacitor plate Cst1 may be referred to as one end, the first end or the first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 may be referred to as the other end, the second end or the second storage capacitor electrode of the storage capacitor Cst.

[0063] For example, the active layer of the thin film transistor may include, for example, polysilicon, and, for example, includes a channel region, a source region, and a drain region. The channel region may not be doped or the doping type is different from that of the source region and the drain region, and thus has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0064] The gate G1 of the first transistor T1 is electrically connected to the reset signal line 62, and the source S1 of the first transistor T1 is electrically connected to the initialization voltage line 66. The drain D1 of the first transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3. Figure 3As shown, the drain D1 of the first transistor T1, one end Cst1 of the storage capacitor Cst, the drain D2 of the second transistor T2, and the gate G3 of the third transistor T3 are electrically connected to the node N1. The first transistor T1 is turned on according to the reset control signal RESET transmitted through the reset signal line 62 to transmit the initialization voltage Vint to the gate G1 of the third transistor T3, thereby performing an initialization operation to initialize the voltage of the gate G3 of the third transistor T3. That is, in this article, the first transistor T1 is also referred to as an initialization transistor or a reset transistor.

[0065] The gate G2 of the second transistor T2 is electrically connected to the scan signal line 61, the source S2 of the second transistor T2 is electrically connected to the node N3, and the drain D2 of the second transistor T2 is electrically connected to the node N1. The second transistor T2 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to electrically connect the gate G3 and the drain D3 of the third transistor T3 to each other, thereby performing the diode connection of the third transistor T3. In this article, the second transistor T2 is also called a compensation transistor.

[0066] The gate G3 of the third transistor T3 is electrically connected to the node N1, the source S3 of the third transistor T3 is electrically connected to the node N2, and the drain D3 of the third transistor T3 is electrically connected to the node N3. The third transistor T3 receives the data signal Dm according to the switching operation of the fourth transistor T4 to supply the driving current Id to the OLED. In this article, the third transistor T3 is also referred to as a driving transistor.

[0067] The fourth transistor T4 is used as a switching device for selecting a light-emitting target sub-pixel. The gate G4 of the fourth transistor T4 is connected to the scan signal line 61, the source S4 of the fourth transistor T4 is connected to the data signal line 64, and the drain D4 of the fourth transistor T4 is connected to the first transistor T1 and the fifth transistor T5, that is, electrically connected to the node N2. The fourth transistor T4 is turned on according to the scan signal Sn transmitted through the scan signal line 61 to perform a switching operation to transmit the data signal Dm to the source S3 of the third transistor T3. In this article, the fourth transistor T4 is also referred to as a switching transistor.

[0068] The gate G5 of the fifth transistor T5 is electrically connected to the light emission control line 63, the source S5 of the fifth transistor T5 is electrically connected to the driving voltage line 65, and the drain D5 of the fifth transistor T5 is electrically connected to the node N2. Herein, the fifth transistor T5 is also referred to as an operation control transistor.

[0069] The gate G6 of the sixth transistor T6 is electrically connected to the light emitting control line 63, the source S6 of the sixth transistor T6 is electrically connected to the node N3, and the drain D6 of the sixth transistor T6 is electrically connected to the node N4, that is, electrically connected to the anode of the OLED. The fifth transistor T5 and the sixth transistor T6 are concurrently (e.g., simultaneously) turned on according to the light emitting control signal En transmitted through the light emitting control line 63 to transmit the driving voltage VDD to the OLED, thereby allowing the driving current Id to flow into the OLED. In this article, the sixth transistor T6 is also referred to as a light emitting control transistor.

[0070] The gate G7 of the seventh transistor T7 is electrically connected to the reset signal line 62, the source S7 of the seventh transistor T7 is electrically connected to the node N4, and the drain D7 of the seventh transistor T7 is electrically connected to the initialization voltage line 66. Under the control of the seventh transistor T7, the initialization voltage Vint transmitted by the initialization voltage line 66 can be supplied to the OLED, for example, to the first electrode (e.g., anode) of the OLED to initialize the voltage on the first electrode of the OLED. In this article, the seventh transistor T7 may also be referred to as the light emitting device initialization transistor T7.

[0071] One end (hereinafter referred to as a first storage capacitor electrode) Cst1 of the storage capacitor Cst is electrically connected to the node N1 , and the other end (hereinafter referred to as a second storage capacitor electrode) Cst2 is electrically connected to the driving voltage line 65 .

[0072] The anode of the OLED is electrically connected to the node N4, and the cathode is electrically connected to the power line 67 to receive the reference voltage VSS. Accordingly, the OLED receives the driving current Id from the third transistor T3 to emit light, thereby displaying an image.

[0073] It should be noted that in Figure 3 In the figure, each thin film transistor T1, T2, T3, T4, T5, T6 and T7 is a p-channel field effect transistor, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 may be an n-channel field effect transistor.

[0074] Figure 4 yes Figure 2 A partial enlarged view of part I of FIG. 1 schematically shows a partial cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure. Figures 1 to 4The array substrate 1 may include: a base substrate 10; a plurality of pixels P disposed on the base substrate 10, the plurality of pixels P being arranged in an array on the base substrate, at least one of the pixels P including a pixel driving circuit and a light-emitting unit 4 electrically connected to the pixel driving circuit; a fingerprint recognition structure 3, the fingerprint recognition structure 3 including a first capacitor electrode 31, the first capacitor electrode 31 being configured to: in response to at least a portion of a touch subject (e.g., a finger) F covering the first capacitor electrode 31, form a capacitor CDP for fingerprint recognition between at least a portion of the touch subject and the first capacitor electrode 31.

[0075] For example, the fingerprint recognition structure 3 is located in the at least one pixel P, the pixel driving circuit includes a thin film transistor (for example, at least one of the above-mentioned transistors T1, T2, T3, T4, T5, T6 and T7), the thin film transistor includes an active layer ACT (for example, the active layer of at least one of the above-mentioned transistors T1, T2, T3, T4, T5, T6 and T7) and a gate (for example, at least one of the gates G1, G2, G3, G4, G5, G6 and G7 of each of the above-mentioned transistors), and the first capacitor electrode 31 is located in the same layer as the active layer ACT and the gate of the thin film transistor. In the embodiment of the present disclosure, the electrode of the fingerprint recognition structure is located in the same layer as the active layer or the gate of the thin film transistor, which is conducive to integrating the fingerprint recognition structure on the array substrate and integrating the fingerprint recognition structure into each pixel.

[0076] Continue to refer to Figures 1 to 4, the array substrate 1 may further include a buffer layer 11 disposed on the base substrate 10. The active layer ACT is disposed on the side of the buffer layer 11 away from the base substrate 10. The array substrate 1 may further include a first gate insulating layer 12 disposed on the side of the active layer ACT away from the base substrate 10. The gates G1, G2, G3, G4, G5, G6 and G7 of the above-mentioned transistors are disposed on the side of the first gate insulating layer 12 away from the base substrate 10. That is, the first gate insulating layer 12 is located between the active layer ACT and the conductive layer (which may be referred to as the first conductive layer) where the gates are located. Optionally, the array substrate 1 may further include a second gate insulating layer 13 and a second conductive layer 14. For example, the above-mentioned second storage capacitor electrode Cst2 may be located in the second conductive layer 14. The second gate insulating layer 13 is located between the above-mentioned first conductive layer and the second conductive layer 14. The array substrate 1 may further include: an interlayer dielectric layer 15 disposed on the side of the second conductive layer 14 away from the base substrate 10; a third conductive layer 16 disposed on the side of the interlayer dielectric layer 15 away from the base substrate 10; a planarization layer PLN disposed on the side of the third conductive layer 16 away from the base substrate 10; and a pixel definition layer PDL disposed on the side of the planarization layer PLN away from the base substrate 10. For example, the source and drain of each transistor may be located in the third conductive layer 16. The source and drain of each transistor may be electrically connected to the source region and drain region of each active layer through via holes penetrating the first gate insulating layer 12, the second gate insulating layer 13 and the interlayer dielectric layer 15, respectively.

[0077] For example, the pixel definition layer PDL may include a plurality of openings 17, each sub-pixel corresponds to at least one opening 17 of the pixel definition layer, and the actual light emitting area or display area of ​​the sub-pixel is substantially equivalent to the opening 17 of the pixel definition layer corresponding to the sub-pixel. In some embodiments, the area of ​​the opening 17 or the actual light emitting area of ​​the pixel definition layer corresponding to each sub-pixel is smaller than the area of ​​the first electrode (e.g., anode) 41, and the projection on the base substrate 10 completely falls within the projection of the first electrode 41 on the base substrate 10.

[0078] Figure 6 is a schematic diagram of the capacitive fingerprint recognition technology used in the array substrate according to an embodiment of the present disclosure. Figure 6When the touch body F, such as a finger, presses on the fingerprint recognition structure 3, a capacitor CFP for fingerprint recognition is formed between the first capacitor electrode 31 in the fingerprint recognition structure 3 and the fingerprint to be recognized in the finger. Since the surface of the fingerprint to be recognized is uneven, the distance between the ridge position of the fingerprint to be recognized and the first capacitor electrode 31 is different, resulting in different capacitors CFP formed by the ridge position of the fingerprint to be recognized and the first capacitor electrode 31. Accordingly, the charge amount signals accumulated on each first capacitor electrode 31 corresponding to the ridge position of the fingerprint to be recognized are different. The signal acquisition circuit can read the charge amount signals accumulated on each first capacitor electrode 31, and then send them to the processing circuit to recognize the fingerprint information.

[0079] For example, in this article, the ridge and valley positions of the fingerprint to be identified correspond to the fingerprint peak and fingerprint valley of the fingerprint to be identified respectively.

[0080] Return to reference Figure 4 In the embodiment of the present disclosure, the light emitting unit 4 is a bottom emission type. The first capacitor electrode 31 is located on a side of the light emitting unit 4 close to the base substrate 10 , that is, the first capacitor electrode 31 is closer to the base substrate 10 than the light emitting unit 4 .

[0081] For example, in the light emitting unit 4, the first electrode 41 may be a transparent anode, the second electrode 43 may be a reflective cathode, and the first electrode 41 is closer to the base substrate 10 than the second electrode 43. Figure 4 As shown, when the light emitting layer 42 emits light under the control of the pixel driving circuit, the light emitted by the light emitting unit 4 is emitted toward the direction of the base substrate 10, as shown in FIG. Figure 4 As shown in the figure, the light L1 in FIG.

[0082] For example, the base substrate 10 may include a transparent material, such as a transparent PI material, which is beneficial for the light emitted by the light emitting unit 4 to be emitted through the base substrate 10 .

[0083] Reference Figure 4 The substrate 10 may include a first surface 101 (ie, Figure 4 and a second surface 102 (i.e., an upper surface in the middle) close to the active layer ACT. Figure 4 It should be understood that the first surface 101 is a light emitting surface. Figure 4In the illustrated embodiment, the first capacitor electrode 31 is located in the same layer as the active layer ACT of the thin film transistor. In this way, when a touch body such as a finger presses the array substrate and a portion of the finger covers the first capacitor electrode 31, the capacitor CPF for fingerprint recognition can be formed between the finger and the first capacitor electrode 31. The capacitor CPF for fingerprint recognition includes a dielectric layer, and the dielectric layer may include a portion of the base substrate 10 and a portion of the buffer layer 11. That is, the portions of the base substrate 10 and the buffer layer 11 located between the finger and the first capacitor electrode 31 constitute the dielectric layer of the capacitor CPF. In this embodiment, the distance between the finger as one electrode of the capacitor CPF and the first capacitor electrode 31 as the other electrode of the capacitor CPF is small, so that the capacitance value of the formed capacitor CPF is large, which is beneficial to subsequent fingerprint recognition.

[0084] For example, the first capacitor electrode 31 may include a doped semiconductor material. The semiconductor material has conductivity after being doped, so that it can be used as an electrode of a capacitor.

[0085] like Figure 4 As shown, the orthographic projections of the first capacitor electrode 31 and each active layer ACT located in the same layer on the substrate do not overlap each other, that is, the first capacitor electrode 31 and each active layer ACT located in the same layer are spaced apart from each other. For example, in the same pixel, the spacing between the first capacitor electrode 31 and the active layer ACT close to it is more than 1 micron. In this way, the active layer ACT can be prevented from having an adverse effect on the capacitor CPF, which is conducive to improving the accuracy of fingerprint recognition.

[0086] Figure 5 yes Figure 2 The partial enlarged view of part I of FIG. 1 schematically shows a partial cross-sectional view of an array substrate according to some exemplary embodiments of the present disclosure. Figure 5 The differences between the illustrated embodiment and the above-mentioned embodiment and the other similarities can be referred to the above description and will not be repeated here.

[0087] Reference Figure 5, the first capacitor electrode 31 can be located in the same layer as the gate of the thin film transistor (for example, at least one of the gates G1, G2, G3, G4, G5, G6 and G7 of each of the above transistors). In this way, when a touch body such as a finger presses the array substrate and a part of the finger covers the first capacitor electrode 31, the capacitor CPF for fingerprint recognition can be formed between the finger and the first capacitor electrode 31. The capacitor CPF for fingerprint recognition includes a dielectric layer, and the dielectric layer may include a part of the base substrate 10, a part of the buffer layer 11 and a part of the first gate insulating layer 12. That is, the base substrate 10, the buffer layer 11 and the first gate insulating layer 12 are located between the finger and the first capacitor electrode 31. The dielectric layer of the capacitor CPF. Since the thickness of the first gate insulating layer 12 is small, in this embodiment, the distance between the finger as one electrode of the capacitor CPF and the first capacitor electrode 31 as the other electrode of the capacitor CPF is small, so that the capacitance value of the formed capacitor CPF is large, which is conducive to subsequent fingerprint recognition.

[0088] like Figure 5 As shown, the orthographic projections of the first capacitor electrode 31 and each gate located on the same layer (such as the gates G1, G2, G3, G4, G5, G6 and G7 of each transistor mentioned above) on the substrate do not overlap each other, that is, the first capacitor electrode 31 and each gate located on the same layer are spaced apart from each other. For example, in the same pixel, the spacing between the first capacitor electrode 31 and the gate close to it is more than 3 microns. In this way, the gate can be prevented from having an adverse effect on the capacitor CPF, which is conducive to improving the accuracy of fingerprint recognition.

[0089] For example, in an embodiment of the present disclosure, the thickness of the substrate is between 5 and 20 microns; and / or the thickness of the buffer layer is between 1000 and 4000 angstroms. By setting such thickness, the distance between the two electrodes of the capacitor CPF used for fingerprint recognition is small, which is conducive to improving the accuracy of fingerprint recognition.

[0090] Reference Figure 4 and Figure 5 In the embodiment of the present disclosure, the array substrate 1 may further include a shielding layer LS, for example, the shielding layer LS is located between the base substrate 10 and the active layer ACT, and the orthographic projection of the shielding layer LS on the base substrate 10 covers the orthographic projection of the active layer ACT of the thin film transistor on the base substrate 10. In this way, the shielding layer LS can be used to protect the active layer ACT of the thin film transistor to prevent the active layer of each transistor of the pixel driving circuit of each sub-pixel from being affected by external light.

[0091] For example, the shielding layer LS may be made of a light-proof metal material. The shielding layer LS may also include a semiconductor film layer such as amorphous silicon, polycrystalline silicon, etc.

[0092] For example, the shielding layer LS may be connected to a fixed voltage to prevent it from being in a suspended state (ie, floating).

[0093] In the embodiment of the present disclosure, the fingerprint recognition structure 3 may further include an excitation component 32, and the excitation component 32 is configured to generate an excitation signal for fingerprint recognition. For example, the excitation component 32 and the shielding layer LS are located in the same layer.

[0094] For example, the excitation component 32 and the shielding layer LS may be formed as one body, that is, the excitation component 32 is a part extending continuously from the shielding layer LS. Alternatively, the excitation component 32 and the shielding layer LS may be separate parts, that is, the excitation component 32 and the shielding layer LS are spaced apart.

[0095] It should be noted that the excitation component 32 can also play an anti-static role.

[0096] Figure 7 FIG. 1 is a partial plan view of an array substrate according to some exemplary embodiments of the present disclosure, in which a fingerprint recognition structure is schematically shown. Figure 4 , Figure 5 and Figure 7 The orthographic projection of the excitation component 32 on the base substrate 10 may surround the orthographic projection of the first capacitor electrode 31 on the base substrate 10 . For example, the excitation component 32 is formed in the form of a metal ring.

[0097] For example, the excitation component 32 can be connected to a fixed voltage. In this way, the excitation component 32 can be configured to increase the voltage of the fingerprint to be identified by the connected fixed voltage, thereby increasing the voltage difference between the fingerprint to be identified and the first capacitor electrode 31, and amplifying the charge signal of the capacitor CPF formed between the fingerprint to be identified and the first capacitor electrode 31, which is beneficial to improving the fingerprint recognition effect.

[0098] Reference Figure 4 and Figure 5 The excitation component 32 can access the data signal Dm. For example, the excitation component 32 can be electrically connected to the data signal line 64 for transmitting the data signal Dm through the via hole VH1 penetrating the buffer layer 11, the first gate insulating layer 12, the second gate insulating layer 13 and the interlayer dielectric layer 15.

[0099] Continue to refer to Figure 4 , Figure 5 and Figure 7In the embodiment of the present disclosure, the orthographic projection of each thin film transistor of the pixel driving circuit on the base substrate 10 does not overlap with the orthographic projection of the first capacitor electrode 31 on the base substrate 10, that is, the orthographic projection of each of the active layer, gate, source and drain of the thin film transistor on the base substrate 10 does not overlap with the orthographic projection of the first capacitor electrode 31 on the base substrate 10. In this way, the first capacitor electrode 31 will not overlap with each thin film transistor, thereby avoiding the generation of coupling capacitance, which is conducive to improving the effect of fingerprint recognition.

[0100] Reference Figure 7 , schematically shows some signal lines, for example, the above-mentioned scanning signal line 61 for transmitting the scanning signal Sn, the reset signal line 62 for transmitting the reset control signal RESET (for example, the reset control signal RESET can be the scanning signal of the previous row), the light control line 63 for transmitting the light control signal En, the data signal line 64 for transmitting the data signal Dm, the driving voltage line 65 for transmitting the driving voltage VDD, and the initialization voltage line 66 for transmitting the initialization voltage Vint. In this document, for the convenience of description, the signal line extending along the first direction X can be referred to as the first signal line, and the signal line extending along the second direction Y can be referred to as the second signal line. For example, the first signal line can include but is not limited to the above-mentioned scanning signal line 61, the reset signal line 62, the light control line 63 and the initialization voltage line 66, and the second signal line can include but is not limited to the above-mentioned data signal line 64 and the driving voltage line 65. In the embodiment of the present disclosure, the positive projection of each of the first signal line and the second signal line on the base substrate 10 does not overlap with the positive projection of the first capacitor electrode 31 on the base substrate 10. In this way, the first capacitor electrode 31 will not overlap with each signal line, thereby avoiding the generation of coupling capacitance, which is beneficial to improving the effect of fingerprint recognition.

[0101] Combined with reference Figure 1 and Figure 7 In the embodiment of the present disclosure, the array substrate 1 may include a plurality of the fingerprint recognition structures 3, and the plurality of fingerprint recognition structures 3 are respectively arranged in a plurality of pixels P. That is, the fingerprint recognition structure 3 may be arranged in the pixel P, so that the fingerprint recognition structure 3 may be respectively arranged in the plurality of pixels P, which is conducive to realizing full-screen fingerprint recognition.

[0102] In the embodiment of the present disclosure, as described above, the light emitted by the light emitting unit 4 is emitted toward the base substrate 10. Figure 4 and Figure 5 That is, in actual use, the array substrate according to the embodiment of the present disclosure is flipped upside down, and the light emitting unit 4 is located away from the display surface (for example, Figure 4and Figure 5 In this way, it is not necessary to provide an encapsulation layer (eg, a thin film encapsulation layer) in the related art on the side of the light emitting unit 4 away from the display surface, thereby simplifying the manufacturing process.

[0103] According to some embodiments of the present disclosure, a display panel and a display device are also provided. The display panel may include the array substrate as described above. Fig.10 , which shows a plan view of a display device according to an embodiment of the present disclosure, and the display device 100 may include an array substrate or a display panel according to some embodiments of the present disclosure. For example, the display device according to an embodiment of the present disclosure may be any product or component with a display function, such as a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a car display, an e-book, etc. Advantageously, the display panel and the display device according to the embodiment of the present disclosure may have all the features and advantages of the array substrate described above, which will not be described in detail here.

[0104] For example, some embodiments of the present disclosure also provide a method for preparing an array substrate. Figure 8 is a flow chart of a method for preparing an array substrate according to some exemplary embodiments of the present disclosure, 9A to 9D 1 is a cross-sectional view of a structure formed after some steps of a method for preparing an array substrate according to some exemplary embodiments of the present disclosure are performed. Figure 8 and 9A to 9D , the preparation method may include the following steps.

[0105] In step S801, a base substrate 10 may be provided. For example, the base substrate 10 may be made of a transparent PI material.

[0106] In step S802, a fingerprint recognition structure 3 may be formed on the base substrate 10, wherein the fingerprint recognition structure 3 may include a first capacitor electrode 31, and the first capacitor electrode 31 is configured to: in response to at least a portion of the touch body covering the first capacitor electrode 31, form a capacitor CPF for fingerprint recognition between at least a portion of the touch body and the first capacitor electrode 31.

[0107] In step S803 , a plurality of pixels P are formed on the base substrate 10 , wherein the plurality of pixels P are arranged in an array on the base substrate 10 , and at least one of the pixels includes a pixel driving circuit and a light emitting unit 4 electrically connected to the pixel driving circuit.

[0108] In an embodiment of the present disclosure, the fingerprint recognition structure 3 is located in the at least one pixel P, the pixel driving circuit includes a thin film transistor, the thin film transistor includes an active layer and a gate, and the first capacitor electrode 31 and one of the active layer ACT and the gate of the thin film transistor are formed by the same composition process.

[0109] For example, refer to Figure 4 The first capacitor electrode 31 and the active layer ACT of the thin film transistor are formed by the same patterning process. Figure 5 The first capacitor electrode 31 and the gate electrode of the thin film transistor are formed by the same patterning process.

[0110] For example, refer to Fig.9A , a substrate substrate 10 having a thickness of 5-10 microns may be manufactured, and then the substrate substrate 10 may be pre-cleaned. Optionally, a barrier layer may be deposited on the substrate substrate 10 by a deposition process such as PECVD, for example, the barrier layer may be made of an insulating material such as silicon nitride, and the thickness of the barrier layer BRL may be between 1000-2000 angstroms.

[0111] Continue to refer to Fig.9A A metal film layer may be formed on the base substrate 10 by a sputtering process, and then a shielding layer LS and an excitation component 32 may be formed by a single patterning process. For example, the metal film layer may include molybdenum (Mo), aluminum (Al) and alloys thereof.

[0112] In the embodiment of the present disclosure, the excitation component 32 and the shielding layer LS are located in the same layer and can be manufactured by the same patterning process without increasing the number of patterning processes, which is conducive to simplifying the manufacturing process.

[0113] Reference Fig. 9B A buffer layer 11 may be formed on the side of the shielding layer LS away from the base substrate 10. For example, the buffer layer 11 may include a multilayer structure. Specifically, a layer of silicon nitride may be deposited first, and then a layer of silicon oxide may be deposited to form a buffer layer 11 including a stacked structure of silicon nitride and silicon oxide.

[0114] Then, an active layer ACT and a first capacitor electrode 31 are formed on the side of the buffer layer 11 away from the base substrate 10. For example, a certain thickness of an amorphous silicon layer can be deposited by a plasma enhanced chemical vapor deposition (PECVD) process; the amorphous silicon layer is heated at a temperature of 400-450°C; an excimer laser annealing (ELA) process is then performed; and then a patterning process is performed to form the active layer ACT and the first capacitor electrode 31 of each thin film transistor. After the patterns of the active layer ACT and the first capacitor electrode 31 are formed, a doping process can be performed to form the source region, the drain region and the first capacitor electrode with conductive properties of each thin film transistor.

[0115] Reference Fig. 9C , conventional processes for forming thin film transistors and OLED light-emitting units can be used to sequentially form various film layer structures for forming thin film transistors and OLED light-emitting units.

[0116] Reference Fig.9D , flip upside down Fig. 9C The structure formed makes the light emitting unit 4 bottom emitting, that is, when the light emitting layer 42 emits light under the control of the pixel driving circuit, the light emitted by the light emitting unit 4 is emitted in the direction of the base substrate 10. In this way, when a touch body such as a finger presses the array substrate, the fingerprint recognition structure 3 can be closer to the finger, which is conducive to improving the effect of fingerprint recognition.

[0117] It should be noted that, refer to Figure 5 In this embodiment, the gates of each thin film transistor and the first capacitor electrode 31 can be formed by the same patterning process.

[0118] Although some embodiments of the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes and modifications may be made to the embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. An array substrate, comprising: substrate substrate; A plurality of pixels are provided on the base substrate, wherein the plurality of pixels are arranged in an array on the base substrate, and at least one of the pixels comprises a pixel driving circuit and a light emitting unit electrically connected to the pixel driving circuit; A fingerprint recognition structure, the fingerprint recognition structure comprising a first capacitor electrode, the first capacitor electrode being configured to: in response to at least a portion of a touch subject covering the first capacitor electrode, form a capacitor for fingerprint recognition between at least a portion of the touch subject and the first capacitor electrode, The fingerprint recognition structure is located in the at least one pixel, the pixel driving circuit includes a thin film transistor, the thin film transistor includes an active layer and a gate, and the first capacitor electrode is located in the same layer as the active layer and the gate of the thin film transistor.

2. The array substrate according to claim 1, wherein: The first capacitor electrode is located on a side of the light emitting unit close to the base substrate.

3. The array substrate according to claim 1 or 2, wherein: The array substrate includes a plurality of the fingerprint recognition structures, and the plurality of fingerprint recognition structures are respectively arranged in a plurality of pixels.

4. The array substrate according to claim 1 or 2, wherein: The substrate includes a first surface away from the active layer and a second surface close to the active layer; The first capacitor electrode and the active layer of the thin film transistor are located in the same layer, and the array substrate further includes a buffer layer, and the buffer layer is located between the second surface and the active layer; and The capacitor for fingerprint identification includes a dielectric layer, and the dielectric layer includes a portion of the substrate and a portion of the buffer layer.

5. The array substrate according to claim 3, wherein: The substrate includes a first surface away from the active layer and a second surface close to the active layer; The first capacitor electrode and the active layer of the thin film transistor are located in the same layer, and the array substrate further includes a buffer layer, and the buffer layer is located between the second surface and the active layer; and The capacitor for fingerprint identification includes a dielectric layer, and the dielectric layer includes a portion of the substrate and a portion of the buffer layer.

6. The array substrate according to claim 5, wherein: The first capacitor electrode includes a doped semiconductor material.

7. The array substrate according to claim 4, wherein: In the same pixel, the distance between the first capacitor electrode and the active layer adjacent thereto is greater than 1 micrometer.

8. The array substrate according to claim 5 or 6, wherein: In the same pixel, the distance between the first capacitor electrode and the active layer adjacent thereto is greater than 1 micrometer.

9. The array substrate according to claim 1 or 2, wherein: The substrate includes a first surface away from the active layer and a second surface close to the active layer; The first capacitor electrode and the gate electrode of the thin film transistor are located in the same layer, the array substrate further comprises a buffer layer and a first gate insulating layer, the buffer layer is located between the second surface and the active layer, and the first gate insulating layer is located between the active layer and the gate electrode; and The capacitor for fingerprint identification includes a dielectric layer, and the dielectric layer includes a portion of the substrate, a portion of the buffer layer, and a portion of the first gate insulating layer.

10. The array substrate according to claim 3, wherein: The substrate includes a first surface away from the active layer and a second surface close to the active layer; The first capacitor electrode and the gate electrode of the thin film transistor are located in the same layer, the array substrate further comprises a buffer layer and a first gate insulating layer, the buffer layer is located between the second surface and the active layer, and the first gate insulating layer is located between the active layer and the gate electrode; and The capacitor for fingerprint identification includes a dielectric layer, and the dielectric layer includes a portion of the substrate, a portion of the buffer layer, and a portion of the first gate insulating layer.

11. The array substrate according to claim 10, wherein: In the same pixel, the distance between the first capacitor electrode and the gate electrode adjacent thereto is more than 3 micrometers.

12. The array substrate according to any one of claims 1-2, 5-7 and 10-11, wherein: The array substrate further comprises a shielding layer, the shielding layer is located between the base substrate and the active layer, and the orthographic projection of the shielding layer on the base substrate covers the orthographic projection of the active layer of the thin film transistor on the base substrate; as well as The fingerprint recognition structure further includes an excitation component, which is configured to generate an excitation signal for fingerprint recognition, and the excitation component and the shielding layer are located in the same layer.

13. The array substrate according to claim 12, wherein: The orthographic projection of the excitation component on the base substrate surrounds the orthographic projection of the first capacitor electrode on the base substrate.

14. The array substrate according to any one of claims 1-2, 5-7, 10-11 and 13, wherein: The light-emitting unit comprises an anode, a cathode and a light-emitting layer sandwiched between the anode and the cathode. The cathode is farther away from the base substrate than the anode. The anode is a transparent anode and the cathode is a reflective cathode.

15. The array substrate according to any one of claims 1-2, 5-7, 10-11 and 13, wherein: The thin film transistor further includes a source electrode and a drain electrode, and the orthographic projection of each of the active layer, the gate electrode, the source electrode and the drain electrode of the thin film transistor on the base substrate does not overlap with the orthographic projection of the first capacitor electrode on the base substrate.

16. The array substrate according to claim 13, wherein: The array substrate further includes a first signal line and a second signal line, wherein the first signal line and the second signal line are respectively configured to provide an electrical signal to the pixel driving circuit, the first signal line extends along a first direction, and the second signal line extends along a second direction; as well as An orthographic projection of each of the first signal line and the second signal line on the base substrate does not overlap with an orthographic projection of the first capacitor electrode on the base substrate.

17. The array substrate according to claim 16, wherein: The second signal line is configured to provide a data signal to the pixel driving circuit; and The data signal is also provided to the driver component.

18. The array substrate according to claim 4, wherein: The substrate comprises a transparent material; and / or, The thickness of the substrate is between 5 and 20 micrometers; and / or, The thickness of the buffer layer is between 1000-4000 angstroms.

19. The array substrate according to claim 9, wherein: The substrate comprises a transparent material; and / or, The thickness of the substrate is between 5 and 20 micrometers; and / or, The thickness of the buffer layer is between 1000-4000 angstroms.

20. A display panel, wherein: The display panel includes the array substrate according to any one of claims 1 to 19.

21. A display device, wherein: The display device comprises the array substrate according to any one of claims 1 to 19 or the display panel according to claim 20.

22. A method for preparing an array substrate, comprising: providing a substrate base plate; forming a fingerprint recognition structure on the substrate, wherein the fingerprint recognition structure comprises a first capacitor electrode, and the first capacitor electrode is configured to: in response to at least a portion of a touch subject covering the first capacitor electrode, form a capacitor for fingerprint recognition between at least a portion of the touch subject and the first capacitor electrode; A plurality of pixels are formed on the substrate, wherein the plurality of pixels are arranged in an array on the substrate, and at least one of the pixels comprises a pixel driving circuit and a light emitting unit electrically connected to the pixel driving circuit. The fingerprint recognition structure is located in the at least one pixel, the pixel driving circuit includes a thin film transistor, the thin film transistor includes an active layer and a gate, and the first capacitor electrode and one of the active layer and the gate of the thin film transistor are formed by the same composition process.

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