Display substrate and display device

Abstract

A display substrate and a display device. In the display substrate, a plurality of data lines are configured to provide data signals to a plurality of pixel drive columns; the plurality of pixel drive columns include a plurality of first pixel drive columns and a plurality of second pixel drive columns, the pixel drive circuits in the first pixel drive columns are connected to the first light-emitting element in the normal display area, and part of the pixel drive circuits in the second pixel drive columns are connected to the second light-emitting element in the transparent display area through a plurality of anode connection lines; the display substrate also includes a first adapter line and a second adapter line, the first adapter line and the second adapter line are connected to the cathode of the first light-emitting element and transmit a first power supply voltage; the first adapter line and the second adapter line are connected through a first via connection structure, and the orthographic projection of the first via connection structure on the base substrate does not overlap with the orthographic projection of the plurality of anode connection lines on the base substrate. Thus, the display substrate can improve the display quality and reduce the risk of disconnection of the anode connection line.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, people have higher and higher requirements for the screen-to-body ratio of electronic products such as smartphones. Therefore, the design of full display with camera (FDC) has gradually become a research hotspot for major manufacturers.

[0003] The under-screen camera design is to set up a transparent display area in the display area of ​​the display panel, which can both display and allow light to pass through; the transparent display area of ​​the display panel is equipped with cameras and other photosensitive devices, so as to achieve a larger screen-to-body ratio, while also realizing functions such as video recording and face recognition. Summary of the invention

[0004] On the basis of realizing the under-screen camera design and narrow bezel, in order to further reduce the load of the power supply voltage (VSS) and improve the image quality, the embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, a plurality of pixel driving circuits, a plurality of data lines, and a plurality of anode connection lines; the base substrate includes a transparent display area and a normal display area surrounding the transparent display area; the plurality of pixel driving circuits are located in the normal display area and are arranged in an array along a first direction and a second direction to form a plurality of pixel driving rows and a plurality of pixel driving columns, each pixel driving row extending along the first direction, and each pixel driving column extending along the second direction; the plurality of data lines extend along the second direction and are configured to provide data signals to the plurality of pixel driving columns; the normal display area includes a first light-emitting element, the transparent display area includes a second light-emitting element, and the plurality of pixel driving columns include a plurality of first pixel driving columns and a plurality of second pixel driving columns , the pixel driving circuit in the first pixel driving column is connected to the first light-emitting element, and some pixel driving circuits in the second pixel driving column are connected to the second light-emitting element through multiple anode connecting lines; the display substrate also includes a first adapter line and a second adapter line, the first adapter line extends along the first direction, the second adapter line extends along the second direction, the first adapter line and the second adapter line are arranged in different layers, the first adapter line and the second adapter line are connected to the cathode of the first light-emitting element, and are configured to transmit a first power supply voltage; the first adapter line and the second adapter line are connected through a first via connection structure, and the orthographic projection of the first via connection structure on the substrate substrate does not overlap with the orthographic projection of multiple anode connecting lines on the substrate substrate. Therefore, the display substrate can reduce the load of the signal line used to transmit the first power supply voltage while realizing the design of the under-screen camera, thereby improving the display quality. On the other hand, the display substrate can also reduce the risk of disconnection of the anode connecting line.

[0005] At least one embodiment of the present disclosure provides a display substrate, comprising: a base substrate, comprising a transparent display area and a normal display area surrounding the transparent display area; a plurality of pixel driving circuits, located in the normal display area and arranged in an array along a first direction and a second direction to form a plurality of pixel driving rows and a plurality of pixel driving columns, each of the pixel driving rows extending along the first direction, and each of the pixel driving columns extending along the second direction; a plurality of data lines extending along the second direction and configured to provide data signals to the plurality of pixel driving columns; a plurality of anode connecting lines, the normal display area comprising a first light-emitting element, the transparent display area comprising a second light-emitting element, the plurality of pixel driving columns comprising a plurality of first pixel driving columns and a plurality of second pixel driving columns, the first pixel driving columns The pixel driving circuit is connected to the first light-emitting element, and some of the pixel driving circuits in the second pixel driving column are connected to the second light-emitting element through the multiple anode connecting lines; the display substrate also includes a first adapter line and a second adapter line, the first adapter line extends along the first direction, the second adapter line extends along the second direction, the first adapter line and the second adapter line are arranged in different layers, the first adapter line and the second adapter line are connected to the cathode of the first light-emitting element, and are configured to transmit a first power supply voltage; the first adapter line and the second adapter line are connected through a first via connection structure, and the orthographic projection of the first via connection structure on the base substrate does not overlap with the orthographic projection of the multiple anode connecting lines on the base substrate.

[0006] For example, in a display substrate provided in an embodiment of the present disclosure, the display substrate also includes a third adapter wire and a fourth adapter wire, the third adapter wire and the fourth adapter wire are located in the normal display area, the third adapter wire extends along the first direction, the fourth adapter wire extends along the second direction, one end of the third adapter wire is connected to the data line, and the other end of the third adapter wire is connected to the fourth adapter wire.

[0007] For example, in a display substrate provided in an embodiment of the present disclosure, the third adapter line and the first adapter line are arranged in the same layer.

[0008] For example, in a display substrate provided in an embodiment of the present disclosure, the fourth adapter line and the second adapter line are provided in the same layer.

[0009] For example, in a display substrate provided in an embodiment of the present disclosure, the display substrate also includes: a connecting line segment, which is arranged on the same layer as the third transfer line and is insulated from each other, the connecting line segment and the third transfer line both overlap with a virtual straight line extending along the first direction, and the connecting line segment connects multiple second transfer lines arranged along the first direction.

[0010] For example, in the display substrate provided in an embodiment of the present disclosure, in at least one of the pixel driving columns, the second transfer line and the fourth transfer line both overlap with a virtual straight line extending along the second direction and are insulated from each other.

[0011] For example, in the display substrate provided in one embodiment of the present disclosure, the normal display area includes a first sub-display area and a second sub-display area arranged in the first direction, the data line located at the edge of the first sub-display area is connected to the fourth adapter line located in the first sub-display area through the third adapter line, and the data line located at the edge of the second sub-display area is connected to the fourth adapter line located in the second sub-display area through the third adapter line.

[0012] For example, in a display substrate provided by an embodiment of the present disclosure, two first pixel driving columns are arranged between two adjacent second pixel driving columns.

[0013] For example, in a display substrate provided in an embodiment of the present disclosure, the multiple data lines include a first data line and a second data line, the first data line is connected to the first pixel driving column and is disconnected in the transparent display area to form a first sub-data line segment and a second sub-data line segment, the second data line is connected to the second pixel driving column and includes a third sub-data line segment and a fourth sub-data line segment, the orthographic projection of the third sub-data line segment on a reference straight line extending in the second direction covers the orthographic projection of the transparent display area on the reference straight line, the display substrate also includes a fifth adapter line and a sixth adapter line, the fifth adapter line is located at a first side of the transparent display area in the second direction, the sixth adapter line is located at a second side of the transparent display area in the second direction, the first sub-data line is connected to the third sub-data line segment through the fifth adapter line, and the second sub-data line is connected to the third sub-data line segment through the sixth adapter line.

[0014] For example, in a display substrate provided in an embodiment of the present disclosure, the fifth adapter line and the sixth adapter line are arranged on the same layer as the first adapter line.

[0015] For example, in a display substrate provided in an embodiment of the present disclosure, the fourth sub-data line segment is connected to the first transfer line through a second via connection structure.

[0016] For example, in the display substrate provided in an embodiment of the present disclosure, the base substrate further includes a peripheral area surrounding the normal display area, and the fifth transfer line is located in the peripheral area.

[0017] For example, in a display substrate provided in an embodiment of the present disclosure, the display substrate also includes: a plurality of power lines extending along the second direction and configured to provide a second power supply voltage to the plurality of pixel driving columns; and a first conductive structure arranged in the same layer as the plurality of power lines, the orthographic projection of the first conductive structure on the base substrate overlaps with the orthographic projection of the pixel driving circuit in the second pixel driving column that is not connected to the anode connecting line on the base substrate, and the first conductive structure is connected to the first transfer line through a third via connection structure.

[0018] For example, in the display substrate provided in an embodiment of the present disclosure, each of the pixel driving circuits includes a second conductive structure, which is arranged on the same layer as the first switching line; the second conductive structure in the pixel driving circuit in the second pixel driving column that is not connected to the anode connection line is connected to the second switching line through a fourth via connection structure.

[0019] For example, in a display substrate provided in an embodiment of the present disclosure, the base substrate also includes a peripheral area surrounding the normal display area, and the display substrate also includes a power supply voltage line located in the peripheral area, and the power supply voltage line is configured to transmit a first power supply voltage; at least one of the first adapter line and the second adapter line extends to the peripheral area and is electrically connected to the power supply voltage line.

[0020] At least one embodiment of the present disclosure further provides a display device, which includes any one of the above display substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0022] Figure 1 A schematic plan view of a display substrate provided in one embodiment of the present disclosure;

[0023] Figure 2 A schematic diagram of the connection between a first adapter wire and a second adapter wire in a display substrate provided by an embodiment of the present disclosure;

[0024] Figure 3 A schematic plan view of another display substrate provided in one embodiment of the present disclosure;

[0025] Figure 4 A schematic plan view of another display substrate provided in one embodiment of the present disclosure;

[0026] Figure 5 A schematic plan view of another display substrate provided in one embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of stacking of a display substrate provided in one embodiment of the present disclosure;

[0028] Fig. 7A A schematic diagram of stacking another display substrate provided by an embodiment of the present disclosure;

[0029] Figure 7B A schematic diagram of stacking another display substrate provided by an embodiment of the present disclosure;

[0030] Figure 8 A schematic diagram of a display device provided by an embodiment of the present disclosure;

[0031] Fig. 9 A schematic diagram of stacking of a display substrate provided in one embodiment of the present disclosure;

[0032] Fig.10 An equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure; and

[0033] Figure 11-16 A schematic diagram of multiple film layers in a display substrate provided by one embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. "First", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0036] Typically, a pixel unit includes a pixel driving circuit and a light-emitting element connected to the pixel driving circuit, and the pixel driving circuit is usually opaque. Therefore, in the design of an under-screen camera, the transparent display area of ​​the display substrate can achieve a transparent display function by removing the pixel driving circuit and retaining the light-emitting element, that is, it can both display and allow light to pass through. In this technical solution, the pixel driving circuit corresponding to the light-emitting element in the transparent display area needs to be set in the normal display area outside the transparent display area.

[0037] On the other hand, the display area of ​​a conventional display substrate includes a plurality of signal lines for driving the pixel units in the display substrate to perform light-emitting display, and these signal lines need to be driven by an external drive circuit or drive chip. Therefore, the display substrate also includes a lead area and a binding area located in the peripheral area, the lead area includes a plurality of leads, and the binding area is used to bind with an external drive circuit or drive chip; at this time, the plurality of leads can be connected to the plurality of signal lines and extend to the binding area, thereby binding with an external drive circuit or drive chip. Obviously, the presence of the lead area and the binding area in the peripheral area of ​​the display substrate is bound to affect the border width of the display substrate using the display substrate, especially the width of the lower border. Therefore, in order to narrow the lower border of the display device, the size of the lead area (Fan-out area) can be reduced by setting the leads of signal lines such as data lines in the display area to achieve a narrow border design.

[0038] On the basis of the above technical solution, in order to further reduce the load of the power supply voltage (VSS) and improve the image quality, the embodiment of the present disclosure provides a display substrate and a display device. The display substrate includes a base substrate, a plurality of pixel driving circuits, a plurality of data lines and a plurality of anode connection lines; the base substrate includes a transparent display area and a normal display area surrounding the transparent display area; the plurality of pixel driving circuits are located in the normal display area and are arranged in an array along a first direction and a second direction to form a plurality of pixel driving rows and a plurality of pixel driving columns, each pixel driving row extends along the first direction, and each pixel driving column extends along the second direction; a plurality of data lines extend along the second direction and are configured to provide data signals to a plurality of pixel driving columns; the normal display area includes a first light-emitting element, the transparent display area includes a second light-emitting element, and the plurality of pixel driving columns include a plurality of first pixel driving columns and a plurality of second pixel driving columns. The display substrate further comprises a first adapter wire and a second adapter wire, the first adapter wire extends along a first direction, the second adapter wire extends along a second direction, the first adapter wire and the second adapter wire are arranged in different layers, the first adapter wire and the second adapter wire are connected to the cathode of the first light-emitting element, and are configured to transmit a first power supply voltage; the first adapter wire and the second adapter wire are connected through a first via connection structure, and the orthographic projection of the first via connection structure on the substrate substrate does not overlap with the orthographic projection of the multiple anode connection wires on the substrate substrate. As a result, the display substrate can reduce the load of the signal line used to transmit the first power supply voltage while realizing the design of the under-screen camera, thereby improving the display quality. On the other hand, the display substrate can also reduce the risk of disconnection of the anode connection wire.

[0039] The display substrate and the display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0040] An embodiment of the present disclosure provides a display substrate. Figure 1 FIG. 1 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure. Figure 1 As shown, the display substrate 100 includes a base substrate 110, a plurality of pixel driving circuits 120, a plurality of data lines 130 and a plurality of anode connection lines 140; the base substrate 110 includes a transparent display area 112 and a normal display area 114 surrounding the transparent display area 112; the transparent display area 112 and the normal display area 114 can constitute a display area for light-emitting display. The plurality of pixel driving circuits 120 are located in the normal display area 114 and are arranged in an array along a first direction X and a second direction Y to form a plurality of pixel driving rows 210 and a plurality of pixel driving columns 220, each pixel driving row 210 extends along the first direction X, and each pixel driving column 220 extends along the second direction Y; the plurality of data lines 130 extend along the second direction Y and are configured to provide data signals to the plurality of pixel driving columns 220.

[0041] like Figure 1 As shown, the normal display area 114 includes a first light-emitting element 151, the transparent display area 112 includes a second light-emitting element 152, and the plurality of pixel drive columns 220 include a plurality of first pixel drive columns 220A and a plurality of second pixel drive columns 220B; the pixel drive circuit 120 in the first pixel drive column 220A is connected to the first light-emitting element 151, for example, the first light-emitting element 151 and the pixel drive circuit 120 are overlapped and directly connected through a via connection structure; part of the pixel drive circuit 120 in the second pixel drive column 220B is connected to the second light-emitting element 152 through a plurality of anode connection lines 140, so that part of the pixel drive circuit 120 located in the normal display area 114 can drive the second light-emitting element 152 located in the transparent display area 112 to emit light. It should be noted that in order to clearly show the pixel drive circuit and various signal lines under the first light-emitting element, Figure 1 Only one first light-emitting element and two second light-emitting elements are shown; the embodiments of the present disclosure include but are not limited to this, each pixel driving circuit in the first pixel driving column can be correspondingly provided with a first light-emitting element, and the transparent display area can be provided with multiple second light-emitting elements according to the required brightness, resolution, transmittance and other parameters.

[0042] like Figure 1 As shown, the display substrate 100 further includes a first adapter line 171 and a second adapter line 172, the first adapter line 171 extends along a first direction X, the second adapter line 172 extends along a second direction Y, the first adapter line 171 and the second adapter line 172 are arranged in different layers, the first adapter line 171 and the second adapter line 172 are connected to the cathode of the first light-emitting element 151, and are configured to transmit a first power supply voltage, such as a VSS voltage; the first adapter line 171 and the second adapter line 172 are connected through a first via hole connection structure V1, and the orthographic projection of the first via hole connection structure V1 on the base substrate 110 does not overlap with the orthographic projection of the plurality of anode connection lines 140 on the base substrate 110. For example, as Figure 1 As shown in the middle line frame 290 , the orthographic projection of the first via connection structure V1 on the base substrate 110 does not overlap with the orthographic projection of the plurality of anode connection lines 140 on the base substrate 110 .

[0043] In the display substrate provided in the embodiment of the present disclosure, since the display substrate includes a transparent display area, a photosensitive device such as a camera can be correspondingly arranged in the transparent display area, thereby the display substrate can realize a Full Display with Camera (FDC) design. In addition, since the first adapter wire and the second adapter wire for transmitting the first power supply voltage are connected through the first via connection structure, the display substrate can reduce the load of the first adapter wire and the second adapter wire, so that the uniformity of the first power supply voltage signal on the entire display substrate is higher, thereby improving the display quality. On the other hand, since the orthographic projection of the first via connection structure on the base substrate does not overlap with the orthographic projection of the plurality of anode connection wires on the base substrate, the display substrate can also avoid the risk of disconnection of the anode connection wire caused by the recessed structure formed by the first via connection structure.

[0044] For example, the material of the substrate 110 may be transparent materials such as glass, plastic, quartz, etc., or may be silicon-based semiconductor materials. Of course, the embodiments of the present disclosure include but are not limited to these, and the material of the substrate may also be other suitable materials.

[0045] Figure 2 A schematic diagram of the connection between a first adapter wire and a second adapter wire in a display substrate provided by an embodiment of the present disclosure. Figure 2 As shown, an insulating flat layer 180 is arranged between the first adapter line 171 and the second adapter line 172; at this time, the first via connection structure V1 includes a first via H1 located in the flat layer 180, and the first via H1 exposes a portion of the first adapter line 171; a portion of the second adapter line 172 is located in the first via H1 and is connected to the first adapter line 171.

[0046] like Figure 2 As shown, an insulating layer 191 is also provided on the side of the second adapter line 172 away from the flat layer 180; due to the existence of the first via hole connection structure V1, a recessed structure will be formed at the position of the insulating layer 191 corresponding to the first via hole connection structure V1. If the anode connection line is overlapped with the first via hole connection structure, it is easy to cause the anode connection line to be disconnected at the position where the recessed structure is located, so that the second element located in the transparent display area cannot emit light and display. In the display substrate provided in the embodiment of the present disclosure, since the orthographic projection of the first via hole connection structure on the base substrate does not overlap with the orthographic projection of multiple anode connection lines on the base substrate, the display substrate can also avoid the risk of disconnection of the anode connection line caused by the recessed structure formed by the first via hole connection structure, and improve the product yield.

[0047] For example, the planarization layer 180 may include one of an organic planarization layer and an inorganic planarization layer or a stack of these layers; the material of the organic planarization layer may be at least one of polyimide, resin, and acrylic; the material of the inorganic planarization layer may be at least one of silicon oxide, silicon nitride, or silicon oxynitride. The material of the passivation layer may be at least one of silicon oxide, silicon nitride, or silicon oxynitride. Of course, the embodiments of the present disclosure include but are not limited to these, and the planarization layer may also be made of other materials.

[0048] For example, the material of the insulating layer 191 may be one or more of silicon oxide, silicon nitride, and silicon oxynitride. Of course, the embodiments of the present disclosure include but are not limited to these, and the material of the gate insulating layer may also be other materials.

[0049] In some examples, such as Figure 1 As shown, the base substrate 110 further includes a peripheral area 118 surrounding the normal display area 114; the display substrate 100 further includes a power supply voltage line 260 located in the peripheral area 118, and the power supply voltage line 260 is configured to transmit a first power supply voltage. At least one of the first adapter line 171 and the second adapter line 172 extends to the peripheral area 118 and is electrically connected to the power supply voltage line 260.

[0050] In some examples, such as Figure 1 As shown, the plurality of first adapter lines 171 and the plurality of second adapter lines 172 may form a grid structure through the plurality of first via connection structures V1, thereby further reducing the load and improving the uniformity of the first power supply voltage on the entire display substrate, thereby improving the display quality.

[0051] In some examples, such as Figure 1 As shown, the display substrate 100 further includes a third adapter line 173 and a fourth adapter line 174; the third adapter line 173 and the fourth adapter line 174 are both located in the normal display area 114; the third adapter line 173 extends along the first direction X, and the fourth adapter line 174 extends along the second direction Y; one end of the third adapter line 173 is connected to the data line 130, and the other end of the third adapter line 173 is connected to the fourth adapter line 174. Therefore, the display substrate can set the lead of the data line in the normal display area to reduce the size of the lead area (Fan-out area), or even cancel the lead area to achieve a narrow frame design.

[0052] In some examples, such as Figure 1As shown, the display substrate 100 further includes a peripheral area 118 surrounding the normal display area 114. The fourth adapter line 174 extends from the normal display area 114 to the peripheral area 118 to lead out the data line 130 through the third adapter line 173. It should be noted that the fourth adapter line can be directly extended to the peripheral area and connected to the driver IC providing the data signal; of course, the embodiments of the present disclosure include but are not limited to this, and the fourth adapter line can also be extended to the peripheral area and connected to the driver IC providing the data signal by changing the layer, and the position of the layer change can be outside the normal display area.

[0053] In some examples, such as Figure 1 As shown, the third transfer line 173 is disposed on the same layer as the first transfer line 171. It should be noted that the above-mentioned “disposed on the same layer” means that the third transfer line and the first transfer line are formed by the same conductive layer through the same patterning process.

[0054] In some examples, such as Figure 1 As shown, the fourth transfer line 174 is disposed on the same layer as the second transfer line 172. It should be noted that the above-mentioned "disposed on the same layer" means that the fourth transfer line and the second transfer line are formed by the same conductive layer through the same patterning process.

[0055] In some examples, although the third patch cord 173 and the first patch cord 171 can be arranged on the same layer, the first patch cord 171 is used to transmit the first power supply voltage, and the third patch cord 173 is used to transmit the data signal. Similarly, although the fourth patch cord 174 and the second patch cord 172 can be arranged on the same layer, the second patch cord 172 is used to transmit the first power supply voltage, and the fourth patch cord 174 is used to transmit the data signal.

[0056] In some examples, such as Figure 1 As shown, the display substrate 100 also includes a connecting line segment 179, which is arranged in the same layer as the third adapter line 173 and is insulated from each other; the connecting line segment 179 and the third adapter line 173 overlap along the straight line extending in the first direction X, and the connecting line segment 179 connects a plurality of second adapter lines 172 arranged along the first direction X. Since the third adapter line is used to connect the data line to the corresponding fourth adapter line, it cannot extend from one edge of the normal display area to another edge. At this time, in the first direction, if the third adapter line exists in part of the normal display area and does not exist in part of the normal display area, it is easy to cause the third adapter line to be seen by the user when the display substrate is not lit, affecting the display quality. However, in the display substrate, by setting the connecting line segment and making the connecting line segment and the third adapter line approximately on the straight line extending in the first direction X, the display substrate can prevent the third adapter line from being noticed by the user. On the other hand, the connecting line segment can also further reduce the overall load of the first adapter line and the second adapter line.

[0057] Figure 3 FIG. 1 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. Figure 3 As shown, the third patch cord 173 may be located as shown in Figure 3 In the M-shaped area shown, by setting the above-mentioned connecting line segment 179, the connecting line segment 179 and the third adapter line 173 can have the same light reflectivity, thereby preventing the third adapter line from being noticed by the user. It should be noted that the third adapter line can also be located in a V-shaped area, a W-shaped area, a triangular area, etc. in the normal display area, and the embodiments of the present disclosure are not limited thereto.

[0058] In some examples, such as Figure 1 As shown, the connecting line segment 179 and the third patch cord 173 are arranged in the same layer and are spaced apart in the first direction. That is, the connecting line segment 179 and the third patch cord 173 can be formed by the same conductive layer through the same patterning process, so that the connecting line segment 179 and the third patch cord 173 have the same light reflectivity, thereby preventing the third patch cord from being noticed by the user.

[0059] In some examples, such as Figure 1 As shown, the spacing between the connecting line segment 179 and the third transfer line 173 in the first direction is smaller than the size of a pixel driving circuit 130 in the first direction, thereby preventing the spacing from being noticed by the user. It should be noted that the size of the above-mentioned pixel driving circuit in the first direction may be the size of the positive projection of each film layer in the pixel driving circuit on the substrate in the first direction, or may be the size of the positive projection of the active layer in the pixel driving circuit on the substrate in the first direction.

[0060] In some examples, the orthographic projection of the gap between the connecting line segment and the third transfer line on the base substrate may overlap with the orthographic projection of the anode of the light-emitting element on the base substrate, so as to further make the gap imperceptible to the user, thereby further improving the display quality.

[0061] In some examples, such as Figure 1 As shown, the width of the connecting line segment 179 in the second direction is equal to the width of the third patch line 173 in the second direction, thereby further preventing the third patch line from being noticed by the user.

[0062] In some examples, such as Figure 1 As shown, in at least one pixel driving column 220, the second transfer line 172 and the fourth transfer line 174 overlap with the virtual straight line extending along the second direction Y and are insulated from each other. Therefore, by making the second transfer line and the fourth transfer line substantially located on the virtual straight line extending along the second direction, the display substrate can prevent the second transfer line and the fourth transfer line from being noticed by the user.

[0063] In some examples, such as Figure 1 As shown, in at least one pixel driving column 220, the second transfer line 172 and the fourth transfer line 174 are arranged in the same layer and are spaced apart in the first direction. That is, the second transfer line 172 and the fourth transfer line 174 can be formed by the same conductive layer through the same patterning process, so that the second transfer line 172 and the fourth transfer line 174 can have the same light reflectivity, thereby preventing the second transfer line and the fourth transfer line from being noticed by the user.

[0064] In some examples, such as Figure 1 As shown, the distance between the second transfer line 172 and the fourth transfer line 174 in the second direction is smaller than the size of one pixel driving circuit 130 in the second direction, thereby preventing the distance from being noticed by the user.

[0065] In some examples, such as Figure 1 As shown, the width of the second patch cord 172 in the first direction is equal to the width of the fourth patch cord 174 in the first direction, thereby further preventing the second patch cord and the fourth patch cord from being noticed by the user.

[0066] In some examples, such as Figure 1 As shown, the normal display area 114 includes a first sub-display area 114A and a second sub-display area 114B arranged in a first direction, and the data line 130 located at the edge of the first sub-display area 114A is connected to the fourth adapter line 174 located in the first sub-display area 114A through the third adapter line 173, and the data line 130 located at the edge of the second sub-display area 114B is connected to the fourth adapter line 174 located in the second sub-display area 114B through the third adapter line 173. With such a configuration, the display substrate can gather the leads of the data lines in the normal display area to realize the function of the leads. Of course, the embodiments of the present disclosure include but are not limited to this, and the above-mentioned first sub-display area and second sub-display area may not be set, and the data lines at the edge of the normal display area are connected to the fourth adapter line located in the normal display area through the third adapter line.

[0067] In some examples, such as Figure 1 As shown, one second pixel driving column 220B is inserted into every three first pixel driving columns 220A, that is, two first pixel driving columns 220A are arranged between two adjacent second pixel driving columns 220B. Of course, the disclosed embodiments include but are not limited to this, and one second pixel driving column may be inserted into every two first pixel driving columns, and one second pixel driving column may be inserted into every four first pixel driving columns; that is, one first pixel driving column, three first pixel driving columns, or four first pixel driving columns are arranged between two adjacent second pixel driving columns.

[0068] In some examples, one second pixel driving column is inserted into every N first pixel driving columns, and the value range of N is 2-10.

[0069] Figure 4 FIG. 1 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. Figure 1 and Figure 4 As shown, the plurality of data lines 130 include a first data line 131 and a second data line 132, the first data line 131 is connected to the first pixel driving column 220A and is disconnected in the transparent display area 112 to form a first sub-data line segment 131A and a second sub-data line segment 131B, the second data line 132 is connected to the second pixel driving column 220B and includes a third sub-data line segment 132A and a fourth sub-data line segment 132B, the orthographic projection of the third sub-data line segment 132A on the reference straight line extending along the second direction Y covers the orthographic projection of the transparent display area 112 on the reference straight line. That is, the first data line 131 is disconnected by the transparent display area 112 to form a first sub-data line segment 131A and a second sub-data line segment 131B, the second data line 132 is disconnected at the lower boundary position corresponding to the transparent display area 112 and the normal display area 114 to form a third sub-data line segment 132A and a fourth sub-data line segment 132B. It should be noted that in order to clearly show the connection relationship between the above signal lines or signal line segments, Figure 3 Only some signal lines and signal line segments are shown.

[0070] like Figure 1 and Figure 4 As shown, since the fourth sub-data line segment 132B does not need to drive the light-emitting element, the fourth sub-data line segment 132B does not need to be loaded with a data signal. At this time, the fourth sub-data line segment 132 can be electrically connected to the first adapter line 171 and loaded with the first power supply voltage to reduce the load of the first adapter line 171.

[0071] like Figure 1 and Figure 4As shown, the display substrate 100 further includes a fifth adapter line 175 and a sixth adapter line 176, the fifth adapter line 175 is located at the first side of the transparent display area 112 in the second direction, the sixth adapter line 176 is located at the second side of the transparent display area 112 in the second direction, the first sub-data line 131A is connected to the third sub-data line segment 132A through the fifth adapter line 175, and the second sub-data line 131B is connected to the third sub-data line segment 132A through the sixth adapter line 176. Thus, the display substrate can connect the first sub-data line and the second sub-data line separated by the transparent display area through the fifth adapter line and the sixth adapter line to realize signal transmission. In addition, the third sub-data line can be used as a data line of the pixel driving circuit corresponding to the second light-emitting element in the transparent display area, and the first sub-data line, the third sub-data line and the second sub-data line are connected to each other to provide data signals for the light-emitting elements in the same column in the display substrate.

[0072] In some examples, such as Figure 1 and Figure 4 As shown, the fifth adapter line 175 and the sixth adapter line 176 are arranged on the same layer as the first adapter line 171, so that the reflectivity of the fifth adapter line 175, the sixth adapter line 176 and the first adapter line 171 to light is the same while making better use of the conductive film layer on the display substrate, thereby preventing the fifth adapter line 175, the sixth adapter line 176 and the first adapter line 171 from being noticed by the user. Of course, the embodiments of the present disclosure include but are not limited to this, and the fifth adapter line and the sixth adapter line can also be arranged on other conductive layers.

[0073] In some examples, such as Figure 1 and Figure 4 As shown, the sixth patch cord 176 and the first patch cord 171 may both overlap with a virtual straight line extending along the first direction X, thereby further preventing the sixth patch cord 176 and the first patch cord 171 from being noticed by the user.

[0074] In some examples, such as Figure 1 and Figure 4 As shown, the width of the sixth patch cord 176 in the second direction Y is equal to the width of the first patch cord 171 in the second direction Y, thereby further preventing the sixth patch cord 176 and the first patch cord 171 from being noticed by the user.

[0075] In some examples, such as Figure 1 and Figure 4As shown, the fourth sub-data line segment 132B is connected to the first adapter line 171 through the second via connection structure V2. Since the pixel driving circuit 120 corresponding to the fourth sub-data line segment 132B is not actually used to drive the light-emitting element, it is a dummy pixel driving circuit (Dummy Pixel Driving Circuit), so the fourth sub-data line 132B does not need to transmit data signals. At this time, the fourth sub-data line segment is connected to the first adapter line through the second via connection structure, and the fourth sub-data line segment can also be used to further reduce the load of the first adapter line and the second adapter line, thereby improving the display quality. It should be noted that the specific structure of the second via connection structure can refer to the first via connection structure, which will not be repeated here.

[0076] In some examples, such as Figure 1 and Figure 4 As shown, the base substrate 110 further includes a peripheral area 118 surrounding the normal display area 114, and the fifth patch cord 175 is located in the peripheral area 118. Thus, the display substrate can use the space in the peripheral area to set the fifth patch cord, thereby improving the space utilization of the display substrate and reducing the number of signal lines in the display area.

[0077] In some examples, such as Figure 1 and Figure 4 As shown, the fifth transfer line 175 and the sixth transfer line 176 can be arranged on the same layer. However, the embodiments of the present disclosure include but are not limited to this. Since there are fewer signal lines in the peripheral area, the fifth transfer line and the sixth transfer line can also be arranged on different layers, but made of other conductive layers.

[0078] In some examples, such as Figure 4 As shown, the second sub-data line segment 131B can also be connected to the fourth switching line 174 through the third switching line 173, and the fourth switching line 174 is then extended from the normal display area 114 to the peripheral area.

[0079] Figure 5 FIG. 1 is a schematic plan view of another display substrate provided by an embodiment of the present disclosure. Figure 5As shown, the display substrate 100 includes a base substrate 110, a plurality of pixel driving circuits 120, a plurality of data lines 130 and a plurality of anode connection lines 140; the base substrate 110 includes a transparent display area 112 and a normal display area 114 surrounding the transparent display area 112; the transparent display area 112 and the normal display area 114 can constitute a display area for light-emitting display. The plurality of pixel driving circuits 120 are located in the normal display area 114 and are arranged in an array along a first direction X and a second direction Y to form a plurality of pixel driving rows 210 and a plurality of pixel driving columns 220, each pixel driving row 210 extends along the first direction X, and each pixel driving column 220 extends along the second direction Y; the plurality of data lines 130 extend along the second direction Y and are configured to provide data signals to the plurality of pixel driving columns 220.

[0080] like Figure 5 As shown, the normal display area 114 includes a first light-emitting element 151, the transparent display area 112 includes a second light-emitting element 152, and the plurality of pixel drive columns 220 include a plurality of first pixel drive columns 220A and a plurality of second pixel drive columns 220B; the pixel drive circuit 120 in the first pixel drive column 220A is connected to the first light-emitting element 151, for example, the first light-emitting element 151 and the pixel drive circuit 120 are overlapped and directly connected through a via connection structure; part of the pixel drive circuit 120 in the second pixel drive column 220B is connected to the second light-emitting element 152 through a plurality of anode connection lines 140, so that part of the pixel drive circuit 120 located in the normal display area 114 can drive the second light-emitting element 152 located in the transparent display area 112 to emit light. It should be noted that the sizes of the first light-emitting element and the second light-emitting element are only schematic, and the size of the first light-emitting element may be smaller than the size of the second light-emitting element.

[0081] like Figure 5 As shown, the display substrate 100 also includes a first adapter line 171 and a second adapter line 172, the first adapter line 171 extends along a first direction X, and the second adapter line 172 extends along a second direction Y, the first adapter line 171 and the second adapter line 172 are arranged in different layers, the first adapter line 171 and the second adapter line 172 are connected to the cathode of the first light-emitting element 151, and are configured to transmit a first power supply voltage, such as VSS; the first adapter line 171 and the second adapter line 172 are connected through a first via connection structure V1, and the orthographic projection of the first via connection structure V1 on the base substrate 110 does not overlap with the orthographic projection of the plurality of anode connection lines 140 on the base substrate 110.

[0082] In the display substrate provided in the embodiment of the present disclosure, since the display substrate includes a transparent display area, a photosensitive device such as a camera can be correspondingly arranged in the transparent display area, thereby the display substrate can realize a Full Display with Camera (FDC) design. In addition, since the first adapter wire and the second adapter wire for transmitting the first power supply voltage are connected through the first via connection structure, the display substrate can reduce the load of the first adapter wire and the second adapter wire, so that the uniformity of the first power supply voltage signal on the entire display substrate is higher, thereby improving the display quality. On the other hand, since the orthographic projection of the first via connection structure on the base substrate does not overlap with the orthographic projection of the plurality of anode connection wires on the base substrate, the display substrate can also avoid the risk of disconnection of the anode connection wire caused by the recessed structure formed by the first via connection structure.

[0083] In some examples, such as Figure 5 As shown, the display substrate 100 further includes a plurality of power lines 160 and a first conductive structure 251; the plurality of power lines 160 extend along the second direction and are configured to provide a second power voltage, such as VDD, to a plurality of pixel drive columns 220; the first conductive structure 251 is disposed on the same layer as the plurality of power lines 160; the orthographic projection of the first conductive structure 251 on the base substrate 110 overlaps with the orthographic projection of the pixel drive circuit 120 in the second pixel drive column 220B that is not connected to the anode connection line 140 on the base substrate 110, and the first conductive structure 251 is connected to the first adapter line 171 through a third via connection structure V3. Since the pixel drive circuit 120 in the second pixel drive column 220B that is not connected to the anode connection line 140 does not need to actually drive the light-emitting element to emit light for display, the portion of these pixel drive circuits corresponding to the power lines, i.e., the first conductive structure, can be used to transmit the first power voltage, thereby further reducing the load of the first adapter line and the second adapter line, and improving the display quality.

[0084] In some examples, such as Figure 5 As shown, the plurality of power lines 160 include a first power line 161 and a second power line 162; the first power line 161 is arranged corresponding to the first pixel driving column 220A, and is configured to provide a second power supply voltage to the pixel driving circuit 120 in the first pixel driving column 220A. It should be noted that the first power line may be electrically connected to the anode of the first light-emitting element, or the anode of the first light-emitting element is configured to load the second power supply voltage through the pixel driving circuit.

[0085] In some examples, such as Figure 5 As shown, the orthographic projection of the second power line 162 on the reference straight line extending along the second direction covers the orthographic projection of the transparent display area 112 on the reference straight line.

[0086] In some examples, an orthographic projection of the second power line 162 on the base substrate 110 overlaps with an orthographic projection of the at least one anode connection line 140 on the base substrate 110 .

[0087] In some examples, such as Figure 5 As shown, part of the first power line 161 is also divided into two sub-first power line segments by the transparent display area 112 .

[0088] In some examples, such as Figure 5 As shown, the length of the second power line 162 is less than the length of the first power line 161; the second power line 162 and the first conductive structure 251 can both overlap with a virtual straight line extending along the second direction Y; the second power line 162 and the first conductive structure 251 are arranged in the same layer, that is, formed by the same conductive layer through the same patterning process. Since the pixel driving circuit corresponding to the first conductive structure is not actually used to drive the light-emitting element, it is a dummy pixel driving circuit (Dummy Pixel Driving Circuit), so the first conductive structure does not need to transmit the second power supply voltage. At this time, the first conductive structure can be used to transmit the first power supply voltage, thereby further reducing the load of the first adapter and the second adapter, and improving the display quality.

[0089] In some examples, such as Figure 5 As shown, the width of the second power line 162 in the first direction is equal to the width of the first conductive structure 251 in the first direction.

[0090] In some examples, such as Figure 5 As shown, the power line 160 is located on the base substrate 110 , the first adapter line 171 may be located on a side of the power line 160 away from the base substrate 110 , and the second adapter line 172 may be located on a side of the first adapter line 171 away from the base substrate 110 .

[0091] In some examples, such as Figure 5 As shown, the anode connection line 140 may be located on a side of the second transfer line 172 away from the base substrate 110 .

[0092] In some examples, the power line 160 may be located in the first conductive layer or the first source-drain metal layer on the base substrate 110; the first adapter line 171, the third adapter line 173, the connecting line segment 179, the fifth adapter line 175 and the sixth adapter line 176 may be located in the second conductive layer or the second source-drain metal layer of the first conductive layer away from the base substrate 110; the second adapter line 172 and the fourth adapter line 174 may be located in the third conductive layer or the third source-drain metal layer on the side of the second conductive layer away from the first conductive layer.

[0093] In some examples, the first conductive layer, the second conductive layer, and the third conductive layer may be made of metal materials; and the anode connecting line may be made of transparent conductive oxide.

[0094] Figure 6 FIG. 1 is a schematic diagram of a stacking of a display substrate provided by an embodiment of the present disclosure. Figure 6 As shown, Figure 6 As shown, part of the pixel driving circuit 120 located in the normal display area 114 is connected to multiple anode connecting lines 140, and the multiple anode connecting lines 140 extend from the normal display area 114 to the transparent display area 112 to provide driving voltage for the second light-emitting element in the transparent display area 112.

[0095] Fig. 7A A schematic diagram of stacking another display substrate provided by an embodiment of the present disclosure; Figure 7B A schematic diagram of stacking of another display substrate provided in one embodiment of the present disclosure. Fig. 7A The figure shows a schematic diagram of the stacking of the region where the anode connection line is provided, and for the sake of clarity, the anode connection line is omitted; Figure 7B The diagram shows a stacking diagram of a region where an anode connection line is provided and a region where an anode connection line is not provided.

[0096] like Fig. 7A and Figure 7B As shown, in the area where the anode connection line 140 is provided, the first adapter line 171 and the second adapter line 172 are not connected through the via connection structure; while in the area where the anode connection line 140 is not provided, the first adapter line 171 and the second adapter line 172 are connected through the first via connection structure V1. In other words, the first adapter line 171 and the second adapter line 172 are connected through the first via connection structure V1, and the orthographic projection of the first via connection structure V1 on the base substrate 110 does not overlap with the orthographic projection of the plurality of anode connection lines 140 on the base substrate 110. As a result, the display substrate can also avoid the risk of disconnection of the anode connection line caused by the recessed structure formed by the first via connection structure.

[0097] like Figure 7B As shown, each pixel driving circuit 120 includes a second conductive structure 252; the second conductive structure 252 is arranged in the same layer as the first transfer line 171; the second conductive structure 252 in the pixel driving circuit 120 in the second pixel driving column 220B that is not connected to the anode connection line 140 is connected to the second transfer line 172 through the fourth via connection structure V4. Since the pixel driving circuit 120 in the second pixel driving column 220B that is not connected to the anode connection line 140 does not need to actually drive the light-emitting element to emit light for display, the second conductive structure in these pixel driving circuits can be used to transmit the first power supply voltage, thereby further reducing the load of the first transfer line and the second transfer line, and improving the display quality.

[0098] An embodiment of the present disclosure further provides a display device. Figure 8Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 8 As shown, the display device 300 includes the above-mentioned display substrate 100. Thus, the display device can realize a narrow frame design and an under-screen camera design. In addition, the display device also reduces the load of the first power supply voltage and improves the display quality.

[0099] For example, in some examples, the display device may be any product or component with a display function, such as a smart phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0100] An embodiment of the present disclosure provides a display substrate. Fig. 9 A schematic diagram of stacking of a display substrate provided in one embodiment of the present disclosure; Fig.10 An equivalent schematic diagram of a pixel driving circuit in a display substrate provided by an embodiment of the present disclosure; Figure 11-Figure 16 A schematic diagram of multiple film layers in a display substrate provided by one embodiment of the present disclosure.

[0101] like Figure 9-Figure 16 As shown, the display substrate 100 includes a base substrate 110, a semiconductor layer 410, a first gate layer 420, a second gate layer 430, a first conductive layer 440, a second conductive layer 450 and a third conductive layer 460. The semiconductor layer 410, the first gate layer 420, the second gate layer 430, the first conductive layer 440, the second conductive layer 450 and the third conductive layer 460 are sequentially arranged in a direction perpendicular to the base substrate 110. It should be noted that an insulating layer, such as a gate insulating layer, an interlayer insulating layer or a passivation layer, is arranged between any two of the semiconductor layer, the first gate layer, the second gate layer, the first conductive layer, the second conductive layer and the third conductive layer, which will not be described in detail herein.

[0102] In the display substrate provided in the embodiment of the present disclosure, the pixel driving circuit may adopt a 7T1C structure, that is, a circuit structure including seven transistors and one storage capacitor. Of course, the embodiment of the present disclosure includes but is not limited to this, and the pixel driving circuit may also adopt other types of circuit structures, such as 8T1C, 8T2C, etc.

[0103] Next, combine Figure 9-Figure 16 Taking the pixel driving circuit adopting the 7T1C structure as an example, the multiple film layers of the display substrate provided by the embodiment of the present disclosure are described in detail.

[0104] like Fig. 9 and Fig.10As shown, the pixel driving circuit 120 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst. The drain of the first transistor T1, the drain of the second transistor T2 and the gate of the first transistor T1 are connected to the first node N1, the source of the third transistor T3, the drain of the fourth transistor T4 and the drain of the sixth transistor T6 are connected to the second node N2, the drain of the third transistor T3, the source of the fifth transistor T5 and the source of the second transistor T2 are connected to the third node, the drain of the fifth transistor T5 and the drain of the seventh transistor T7 are connected to the anode of the light emitting element (for example, the first light emitting element or the second light emitting element mentioned above); the first electrode plate CE1 of the storage capacitor Cst and the gate of the third transistor T3 are connected to the first node N1, and the second electrode plate CE2 of the storage capacitor Cst is connected to the source of the sixth transistor T6 and is configured to be connected to the power line.

[0105] In some examples, such as Fig. 9 and Fig.11 As shown, the semiconductor layer 410 includes a first unit 411, a second unit 412, a third unit 413, a fourth unit 414, a fifth unit 415, a sixth unit 416, and a seventh unit 417. The first unit 411 includes a first channel region C1 and a first source region S1 and a first drain region D1 located on both sides of the first channel region C1, the second unit 412 includes a second channel region C2 and a second source region S2 and a second drain region D2 located on both sides of the second channel region C2, the third unit 413 includes a third channel region C3 and a third source region S3 and a third drain region D3 located on both sides of the third channel region C3, the fourth unit 414 includes a fourth channel region C4 and a fourth source region S5 and a third drain region D6 located on both sides of the fourth channel region C4. The fifth unit 415 includes a fifth channel region C5 and a fifth source region S5 and a fifth drain region S5 located on both sides of the fifth channel region C5, the sixth unit 416 includes a sixth channel region C6 and a sixth source region S6 and a sixth drain region D6 located on both sides of the sixth channel region C6, and the seventh unit 417 includes a seventh channel region C7 and a seventh source region S7 and a seventh drain region D7 located on both sides of the seventh channel region C7.

[0106] For example, the semiconductor layer may be made of silicon-based semiconductor materials, such as polysilicon. Of course, the embodiments of the present disclosure include but are not limited to this, and the semiconductor layer may also be made of other semiconductor materials such as oxide semiconductor materials.

[0107] It should be noted that each of the above-mentioned channel regions may be an undoped portion of the semiconductor layer, and each of the source region and the drain region may be a doped portion of the semiconductor. In addition, the above-mentioned first unit 411 is an active layer of the first transistor T1, the above-mentioned second unit 412 is an active layer of the second transistor T2, the above-mentioned third unit 413 is an active layer of the third transistor T3, the above-mentioned fourth unit 414 is an active layer of the fourth transistor T4, the above-mentioned fifth unit 415 is an active layer of the fifth transistor T5, the above-mentioned sixth unit 416 is an active layer of the sixth transistor T6, and the above-mentioned seventh unit 417 is an active layer of the seventh transistor T7.

[0108] For example, Fig.11 As shown, the first drain region D1 is connected to the second drain region D2, the second source region S2, the third drain region D3 and the fifth source region S5 are connected, the fourth drain region D4, the third source region S3 and the sixth drain region D6 are connected, and the fifth drain region D5 and the seventh drain region D7 are connected.

[0109] In some examples, such as Fig.12 As shown, the first gate layer 420 includes a reset signal line 421 extending along a first direction, a gate line 422 extending along the first direction, a first electrode block CE1, and a light emitting control line 423 extending along the first direction.

[0110] For example, Figure 9-Figure 16 As shown, the reset signal line 421 overlaps with the seventh channel region C7 and the first channel region C1 of the semiconductor layer 410, so that the portions where the reset signal line 421 overlaps with the seventh channel region C7 and the first channel region C1 can be used as the gate of the seventh transistor T7 and the gate of the first transistor T1, respectively. The gate line 422 overlaps with the second channel region C2 and the fourth channel region C4 of the semiconductor layer 410, so that the portions where the gate line 422 overlaps with the second channel region C2 and the fourth channel region C4 can be used as the gate of the second transistor T2 and the gate of the fourth transistor T4, respectively. The light emission control line 423 overlaps with the fifth channel region C5 and the sixth channel region C6, so that the portions where the light emission control line 423 overlaps with the fifth channel region C5 and the sixth channel region C6 can be used as the gate of the fifth transistor T5 and the gate of the sixth transistor T6, respectively. The first electrode block CE1 overlaps with the third channel region C3, so that the first electrode block CE1 can be used as the gate of the third transistor T3.

[0111] For example, Fig.12 As shown, the reset signal line 421, the gate line 422 and the light emitting control line 423 all extend substantially along the first direction; the reset signal line 421, the gate line 422, the first electrode block CE1 and the light emitting control line 423 are sequentially arranged along a second direction perpendicular to the first direction.

[0112] In some examples, such as Fig.13As shown, the second gate layer 430 includes a first initialization signal line 431, a second initialization signal line 432 and a second electrode block CE2 extending along the first direction. The first initialization signal line 431, the second initialization signal line 432 and the second electrode block CE2 are sequentially arranged along the second direction.

[0113] For example, Figure 9-Figure 16 As shown, the first initialization signal line 431 is electrically connected to the first source region S1 and the seventh source region S7, thereby providing an initialization signal to the first transistor T1 and the seventh transistor T7. The orthographic projection of the second electrode block CE2 on the substrate 110 at least partially overlaps with the orthographic projection of the first electrode block CE1 on the substrate 110 to form a storage capacitor Cst.

[0114] For example, Fig.13 As shown, the second electrode block CE2 includes an opening OP, and an orthographic projection of the opening OP on the base substrate 110 overlaps with an orthographic projection of the first electrode layer CE1 on the base substrate 110 to expose a portion of the first electrode layer CE1.

[0115] In some examples, such as Fig.14 As shown, the first conductive layer 440 includes the power line 160 extending along the second direction, a first adapter block 441 , a second adapter block 442 , a third adapter block 443 , a fourth adapter block 444 and a fifth adapter block 445 .

[0116] For example, Figure 9-Figure 16 As shown, the first switching block 441 is connected to the fifth drain region D5 of the fifth transistor T5 and is configured to be connected to the anode of the subsequently formed light-emitting element, thereby transmitting a driving signal (e.g., a power supply voltage) from the fifth source region D5 of the fifth transistor T5 to the anode of the light-emitting element.

[0117] For example, Figure 9-Figure 16 As shown, one end of the second transfer block 442 is connected to the first drain region D1 of the first transistor T1, and the other end of the second transfer block 442 can pass through the opening OP to connect to the gate of the third transistor T3, that is, the first electrode block CE1. At this time, the second transfer block can also be regarded as a node connection block of the first node N1.

[0118] For example, Figure 9-Figure 16 As shown, one end of the third transfer block 443 is connected to the seventh source region D7 of the seventh transistor T7, and the other end of the third transfer block 443 is connected to the first initialization signal line 431, so that the first initialization signal line 431 can be connected to the source of the seventh transistor T7.

[0119] For example, Figure 9-Figure 16As shown, the fourth transfer block 444 is connected to the fourth source region S4 of the fourth transistor T4 and is configured to be connected to a subsequently formed data line, so as to transmit the data signal to the fourth source region S4 of the fourth transistor T4.

[0120] For example, Figure 9-Figure 16 As shown, one end of the fifth transfer block 445 is connected to the sixth source region S6 of the sixth transistor T6, and the other end of the fifth transfer block 445 is connected to the second initialization signal line 432, so that the second initialization signal line 432 can be connected to the source of the sixth transistor T6.

[0121] In some examples, such as Fig.15 As shown, the second conductive layer 450 includes the above-mentioned first transfer line 171 and the second conductive structure 252; the first transfer line 171 includes a main body 171A extending along the first direction and a first extension part 171B and a second extension part 171C extending from the main body 171A along the second direction; the first extension part 171B is configured to be electrically connected to the second transfer line 172 formed subsequently, and is also the location of the first connecting via structure. The second extension part 171C is only located in the second pixel driving column 220B, and is configured to be electrically connected to the fourth sub-data line segment 132B formed subsequently.

[0122] For example, Fig.15 As shown, the second conductive structure 252 in the first pixel driving column 220A can be electrically connected to the power line 160, while the second conductive structure 252 in the pixel driving circuit 120 in the second pixel driving column 220B that is not connected to the anode connection line 140 is connected to the second transfer line 172 through the fourth via connection structure V4.

[0123] For example, Fig. 9 and Fig.15 As shown, the orthographic projection of the second conductive structure 252 on the base substrate 110 overlaps with the orthographic projection of the second transfer block 442 on the base substrate 110 , thereby making the voltage on the first node N1 more stable.

[0124] For example, Fig. 9 and Fig.15 As shown, the orthographic projection of the second conductive structure 252 on the base substrate 110 overlaps with the orthographic projection of the second transfer line 172 on the base substrate.

[0125] In some examples, such as Fig.16 As shown, the third conductive layer 460 includes a data line 130, a second adapter line 172 and a connection electrode 461. The data line 130 is electrically connected to the fourth adapter block 444, the second adapter line 172 is electrically connected to the first adapter line 171, and the connection electrode 461 is electrically connected to the first adapter block 441.

[0126] The following will Fig.10 A working mode of the pixel driving circuit shown is schematically described. First, when a reset signal is transmitted to the reset signal line 421 and the seventh transistor T7 is turned on, the residual current flowing through the anode of each light-emitting element is discharged through the seventh transistor T7, thereby suppressing the light emission caused by the residual current flowing through the anode of each light-emitting element. Then, when a reset signal is transmitted to the reset signal line 421, a first initialization signal is transmitted to the first initialization signal line 431, and a second initialization signal is transmitted to the second initialization signal line 432, the first transistor T1 and the seventh transistor T7 are turned on, the first initialization signal initializes the anode of each light-emitting element through the seventh transistor T7, and the second initialization signal initializes the gate of the third thin transistor T3 and the first electrode block CE1 of the storage capacitor Cst through the first transistor T1. And the initialization of the gate of the third thin transistor T3 can turn on the third transistor T3.

[0127] Subsequently, when a gate signal is transmitted to the gate line 422 and a data signal is transmitted to the data line 130, the second transistor T2 and the fourth transistor T4 are both turned on, and the data line 130 applies the data voltage Vd to the gate of the third transistor T3 through the second transistor T2 and the fourth transistor T4. At this time, the voltage applied to the gate of the third thin transistor T3 is the compensation voltage Vd+Vth, and the compensation voltage applied to the gate of the third transistor T3 is also applied to the first electrode block CE1 of the storage capacitor Cst.

[0128] Subsequently, the power line 160 applies the driving voltage Vel to the second electrode block CE2 of the storage capacitor Cst, and applies the compensation voltage Vd+Vth to the first electrode block CE1, so that the charge corresponding to the difference between the voltages respectively applied to the two electrodes of the storage capacitor Cst is stored in the storage capacitor Cst, and the third transistor T3 is turned on for a predetermined time.

[0129] Subsequently, when an emission control signal is applied to the light-emitting control line 423, the sixth transistor T6 and the fifth transistor T5 are both turned on, so that the power line 160 applies a driving voltage Vel to the source of the sixth transistor T6. At this time, when the driving voltage Vel passes through the third transistor T3 turned on by the storage capacitor Cst, the voltage of the drain of the third transistor T3 is Vel, and the voltage of the gate of the third transistor T3 is Vd+Vth, so that the third transistor T3 can be in a saturated state, so that the third transistor T3 generates a driving current Ids; then, the driving current Id is applied to the anode of the light-emitting element through the fifth transistor T5, so that the light-emitting element emits light.

[0130] It should be noted that the working mode of the above-mentioned driving circuit is only one possible driving mode of the driving circuit, and the embodiments of the present disclosure include but are not limited to this.

[0131] In some examples, the first conductive layer may be a first source-drain metal layer, the second conductive layer may be a second source-drain metal layer, and the third conductive layer may be a third source-drain metal layer.

[0132] There are a few points to note:

[0133] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0134] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0135] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, comprising: A base substrate, comprising a transparent display area and a normal display area surrounding the transparent display area; A plurality of pixel driving circuits are located in the normal display area and are arranged in an array along a first direction and a second direction to form a plurality of pixel driving rows and a plurality of pixel driving columns, each of the pixel driving rows extending along the first direction, and each of the pixel driving columns extending along the second direction; a plurality of data lines extending along the second direction and configured to provide data signals to the plurality of pixel drive columns; Multiple anode connection wires, The normal display area includes a first light-emitting element, the transparent display area includes a second light-emitting element, the plurality of pixel drive columns include a plurality of first pixel drive columns and a plurality of second pixel drive columns, the pixel drive circuits in the first pixel drive columns are connected to the first light-emitting element, and part of the pixel drive circuits in the second pixel drive columns are connected to the second light-emitting element through the plurality of anode connection lines; The display substrate further includes a first adapter wire and a second adapter wire, the first adapter wire extends along the first direction, the second adapter wire extends along the second direction, the first adapter wire and the second adapter wire are arranged in different layers, the first adapter wire and the second adapter wire are connected to the cathode of the first light-emitting element, and are configured to transmit a first power supply voltage. The first adapter wire and the second adapter wire are connected via a first via connection structure, and an orthographic projection of the first via connection structure on the base substrate does not overlap with an orthographic projection of the plurality of anode connection wires on the base substrate.

2. The display substrate according to claim 1, wherein: The display substrate further includes a third adapter line and a fourth adapter line, wherein the third adapter line and the fourth adapter line are located in the normal display area, the third adapter line extends along the first direction, and the fourth adapter line extends along the second direction. One end of the third adapter line is connected to the data line, and the other end of the third adapter line is connected to the fourth adapter line.

3. The display substrate according to claim 2, wherein: The third adapter line is arranged at the same layer as the first adapter line.

4. The display substrate according to claim 2, wherein: The fourth adapter line is arranged at the same layer as the second adapter line.

5. The display substrate according to claim 2, further comprising: The connecting line segment is arranged at the same layer as the third adapter line and is insulated from each other. The connecting line segment and the third transfer line both overlap with a virtual straight line extending along the first direction, and the connecting line segment connects a plurality of the second transfer lines arranged along the first direction.

6. The display substrate according to claim 2, wherein: In at least one of the pixel driving columns, the second transfer line and the fourth transfer line both overlap with a virtual straight line extending along the second direction and are insulated from each other.

7. The display substrate according to any one of claims 2 to 6, wherein: The normal display area includes a first sub-display area and a second sub-display area arranged in the first direction, the data line located at the edge of the first sub-display area is connected to the fourth adapter line located in the first sub-display area through the third adapter line, and the data line located at the edge of the second sub-display area is connected to the fourth adapter line located in the second sub-display area through the third adapter line.

8. The display substrate according to any one of claims 1 to 6, wherein: Two first pixel driving columns are arranged between two adjacent second pixel driving columns.

9. The display substrate according to any one of claims 1 to 6, wherein: The plurality of data lines include a first data line and a second data line, the first data line is connected to the first pixel drive column and is disconnected in the transparent display area to form a first sub-data line segment and a second sub-data line segment, the second data line is connected to the second pixel drive column and includes a third sub-data line segment and a fourth sub-data line segment, the orthographic projection of the third sub-data line segment on a reference straight line extending along the second direction covers the orthographic projection of the transparent display area on the reference straight line, The display substrate also includes a fifth adapter line and a sixth adapter line, the fifth adapter line is located at a first side of the transparent display area in the second direction, the sixth adapter line is located at a second side of the transparent display area in the second direction, the first sub-data line is connected to the third sub-data line segment through the fifth adapter line, and the second sub-data line is connected to the third sub-data line segment through the sixth adapter line.

10. The display substrate according to claim 9, wherein: The fifth patch cord and the sixth patch cord are arranged on the same layer as the first patch cord.

11. The display substrate according to claim 9, wherein: The fourth sub-data line segment is connected to the first transfer line through a second via connection structure.

12. The display substrate according to claim 9, wherein: The base substrate further includes a peripheral area surrounding the normal display area, and the fifth transfer line is located in the peripheral area.

13. The display substrate according to any one of claims 1 to 6, further comprising: a plurality of power supply lines extending along the second direction and configured to provide a second power supply voltage to the plurality of pixel drive columns; as well as A first conductive structure is provided at the same layer as the plurality of power lines, Among them, the orthographic projection of the first conductive structure on the base substrate overlaps with the orthographic projection of the pixel driving circuit in the second pixel driving column that is not connected to the anode connecting line on the base substrate, and the first conductive structure is connected to the first adapter line through a third via connection structure.

14. The display substrate according to any one of claims 1 to 6, wherein: Each of the pixel driving circuits comprises a second conductive structure, which is arranged in the same layer as the first adapter wire; The second conductive structure in the pixel driving circuit in the second pixel driving column that is not connected to the anode connecting line is connected to the second transfer line through a fourth via connection structure.

15. The display substrate according to any one of claims 1 to 6, wherein: The base substrate further includes a peripheral area surrounding the normal display area, and the display substrate further includes a power supply voltage line located in the peripheral area, and the power supply voltage line is configured to transmit a first power supply voltage; At least one of the first switching line and the second switching line extends to the peripheral area and is electrically connected to the power supply voltage line.

16. A display device comprising the display substrate according to any one of claims 1 to 15.

Images