A data storage management apparatus and processing core
By using a combination of DMAC and multiple RAMs in the chip to directly access the data memory, the problem of decreased computational efficiency caused by cache access failures is solved, resulting in more efficient data processing and simplified chip design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STREAM COMPUTING INC
- Filing Date
- 2020-04-03
- Publication Date
- 2026-06-26
AI Technical Summary
When processing large amounts of data, existing chips suffer from decreased computational efficiency due to cache access failures, and the complexity of the cache circuitry increases the difficulty and cost of chip design.
By employing a combination of a direct memory access controller (DMAC) and at least two random access memories (RAMs), data can be read and stored by directly accessing the RAM, avoiding the need for a cache and enabling parallel data processing.
It improves the controllability of program efficiency, reduces the decline in computational efficiency caused by cache access failures, simplifies chip design, and saves costs.
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