A data storage management apparatus and processing core
By using a combination of DMAC and multiple RAMs in the chip to directly access the data memory, the problem of decreased computational efficiency caused by cache access failures is solved, resulting in more efficient data processing and simplified chip design.
CN115380292BActive Publication Date: 2026-06-26STREAM COMPUTING INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STREAM COMPUTING INC
- Filing Date
- 2020-04-03
- Publication Date
- 2026-06-26
AI Technical Summary
Technical Problem
When processing large amounts of data, existing chips suffer from decreased computational efficiency due to cache access failures, and the complexity of the cache circuitry increases the difficulty and cost of chip design.
Method used
By employing a combination of a direct memory access controller (DMAC) and at least two random access memories (RAMs), data can be read and stored by directly accessing the RAM, avoiding the need for a cache and enabling parallel data processing.
Benefits of technology
It improves the controllability of program efficiency, reduces the decline in computational efficiency caused by cache access failures, simplifies chip design, and saves costs.
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Figure CN115380292B_ABST
Abstract
A data storage management device and processing core, the device comprising: at least two random access memories (RAM); a control unit receiving instructions, generating and sending control signals (S101) according to the instructions; a direct memory access controller (DMAC) realizing access to data in the random access memories (RAM) according to the control signals (S102). The data storage management device receives and responds to instructions sent from an external processing unit, reads data from an external storage unit, so that the external processing unit can directly read the data required for executing a program from the data storage management device when executing the program, and the external processing unit does not need to take data from the external storage unit through a cache (Cache), eliminating the decline in computing efficiency caused by Cache access invalidation, and improving the controllability of program efficiency.
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Citation Information
Patent Citations
CN108416422A