Detection substrate and manufacturing method thereof, flat panel detector and manufacturing method thereof

Abstract

The present disclosure relates to the field of photoelectric detection technology, and in particular, to a detection substrate, a method for manufacturing a detection substrate, a flat-panel detector, and a method for manufacturing a flat-panel detector. The detection substrate comprises: a substrate (10), comprising a detection area (D), a binding area (C), a controllable on / off area (B), and a cutting area (A); a plurality of detection units, arranged on the substrate (10), the detection units comprising a transistor and a photosensitive device located on the detection area (D), the transistor comprising a gate (21), a first electrode (24), and a second electrode (25); the photosensitive device is connected to the first electrode (24) or the second electrode (25) of the transistor; a plurality of wires (212), arranged on the substrate (10), one end of which is connected to the plurality of wires (212). The gates (21) of the transistors in the detection units are connected one by one, and the other ends extend to the binding area (C); the conductive ring (210) is arranged on the cutting area (A) of the substrate (10); a plurality of detection lines (211) are arranged on the substrate (10), one end is connected to the conductive ring (210), and the other end is connected one by one to the plurality of wires (212), and passes through the controllable on-off area (B); wherein the detection line (211) located on the controllable on-off area (B) can have an off state. The detection substrate of this solution can reduce the risk of static electricity being introduced from the edge, and realize the timely conduction of static electricity to avoid damaging the device.

Description

Technical Field

[0001] The present disclosure relates to the field of photoelectric detection technology, and in particular, to a detection substrate, a method for manufacturing the detection substrate, a flat panel detector, and a method for manufacturing the flat panel detector. Background Art

[0002] X-ray detection is widely used in the fields of medical treatment, safety, non-destructive testing, scientific research, etc. Taking the application of X-ray detection in the medical field as an example, the development of medical treatment has driven the positive development of the entire society, and the progress of medical imaging can enable clinicians to have more accurate judgments when diagnosing different diseases and treating them. The application range of X-ray flat-panel detectors covers chest cavity, limb joints, breast detection, etc., and has been widely used. However, there is still the problem of ESD (Electro-Static discharge) introduced in the manufacturing process of flat-panel detectors.

[0003] Public Content

[0004] The purpose of the embodiments of the present disclosure is to provide a detection substrate, a method for manufacturing a detection substrate, a flat panel detector, and a method for manufacturing a flat panel detector, which can reduce the risk of static electricity being introduced from the edge and achieve timely conduction of static electricity to avoid damage to the device.

[0005] A first aspect of the present disclosure provides a detection substrate, the detection substrate comprising:

[0006] A substrate, including a detection area, a binding area, a controllable on / off area and a cutting area;

[0007] A plurality of detection units are arranged on the substrate, wherein the detection units include a transistor and a photosensitive device located on the detection area, wherein the transistor includes a gate, a first electrode and a second electrode; and the photosensitive device is connected to the first electrode or the second electrode of the transistor;

[0008] A plurality of wires are arranged on the substrate, one end of which is connected to the gates of the transistors in the plurality of detection units in a one-to-one correspondence, and the other end of which extends to the binding area;

[0009] A conductive ring, disposed on the cutting area of ​​the substrate;

[0010] A plurality of detection lines are arranged on the substrate, one end of which is connected to the conductive ring, and the other end of which is connected to the plurality of wires one by one, and passes through the controllable on-off area;

[0011] Wherein, the detection line located on the controllable on-off region can have an off state.

[0012] In an exemplary embodiment of the present disclosure, the detection line located on the controllable on-off region has a cutting opening, and the cutting opening puts the detection line in the disconnected state.

[0013] In an exemplary embodiment of the present disclosure, the detection line located on the controllable on-off region has a tip discharge portion, and the tip discharge portion can be melted by tip discharge, so that the detection line is in the disconnected state.

[0014] In an exemplary embodiment of the present disclosure, the controllable on-off area is located between the binding area and the cutting area; an etching hole is formed on the controllable on-off area, and the etching hole cuts off the multiple detection lines so that the detection lines form the cutting openings.

[0015] In an exemplary embodiment of the present disclosure, the detection unit includes:

[0016] A routing layer, comprising the plurality of detection lines;

[0017] A gate insulating layer, disposed on a side of the wiring layer away from the substrate;

[0018] A first passivation layer is provided on a side of the gate insulating layer away from the substrate;

[0019] A second passivation layer is disposed on a side of the first passivation layer away from the substrate;

[0020] An etching hole penetrating the second passivation layer, the first passivation layer, the gate insulation layer and the wiring layer is formed on the controllable on-off region, and the etching hole cuts off the multiple detection lines to form the cutting openings on the detection lines.

[0021] In an exemplary embodiment of the present disclosure, the plurality of conductive lines and the plurality of detection lines are arranged in the same layer.

[0022] In an exemplary embodiment of the present disclosure, the controllable on-off region is located between the binding region and the cutting region; the plurality of wires extend to the controllable on-off region, an insulating layer is formed on a side of the plurality of wires away from the substrate, and the plurality of detection lines are formed on a side of the insulating layer away from the substrate;

[0023] Among them, a plurality of first vias and a plurality of second vias are formed on the insulating layer, the first vias are projected on the substrate to be located in the controllable on-off area, and the second vias are projected on the substrate to be located in the binding area; each of the wires is exposed simultaneously through the first via and the second via; the area of ​​the first via projected on the substrate is smaller than the area of ​​the second via projected on the substrate; the plurality of detection lines are connected to the plurality of wires one by one through the first via; and the detection line forms the tip discharge portion in the first via.

[0024] In an exemplary embodiment of the present disclosure, a width of the first via hole is 1 μm-2 μm.

[0025] In an exemplary embodiment of the present disclosure, a depth of the first via hole is 0.2 μm-1 μm.

[0026] In an exemplary embodiment of the present disclosure, an angle between a sidewall of the first via hole and the substrate is less than 90°.

[0027] In an exemplary embodiment of the present disclosure, a plurality of first conductive portions are formed on a side of the insulating layer facing away from the substrate, the plurality of first conductive portions are connected one-to-one with each of the conductive wires through the first via holes, and the plurality of first conductive portions form the plurality of detection lines.

[0028] In an exemplary embodiment of the present disclosure, a plurality of second conductive portions are formed on a side of the insulating layer facing away from the substrate, and the plurality of second conductive portions are connected to the respective conductive wires in a one-to-one correspondence through the second via holes.

[0029] In an exemplary embodiment of the present disclosure, the plurality of first conductive parts and the plurality of second conductive parts are arranged in the same layer.

[0030] In an exemplary embodiment of the present disclosure, each of the conductive lines is exposed through a plurality of the first via holes.

[0031] A second aspect of the present disclosure provides a method for manufacturing a detection substrate, the method comprising:

[0032] Providing a substrate, the substrate comprising a detection area, a binding area, a controllable on / off area and a cutting area;

[0033] A plurality of detection units are formed on the substrate, wherein the detection units include a transistor and a photosensitive device located on the detection area, wherein the transistor includes a gate, a first electrode and a second electrode; and the photosensitive device is connected to the first electrode or the second electrode of the transistor;

[0034] forming a plurality of wires on the substrate, wherein one end of the plurality of wires is connected to the gates of the transistors in the plurality of detection units in a one-to-one correspondence, and the other end of the plurality of wires extends to the binding area;

[0035] forming a conductive ring on a cutting area of ​​the substrate;

[0036] A plurality of detection lines are formed on the substrate, one end of the plurality of detection lines is connected to the conductive ring, the other end of the plurality of detection lines is connected one-to-one with the plurality of conductive wires, and passes through the controllable on-off area; wherein the detection lines located on the controllable on-off area can have an off state.

[0037] In an exemplary embodiment of the present disclosure, a cutting opening is formed on the detection line located in the controllable on-off region, and the detection line is placed in a disconnected state through the cutting opening.

[0038] In an exemplary embodiment of the present disclosure, a tip discharge portion is formed on the detection line located in the controllable on-off region, and the detection line is disconnected by the tip discharge portion.

[0039] A third aspect of the present disclosure provides a method for manufacturing a flat panel detector, the method comprising:

[0040] A method for manufacturing a detection substrate provided by any of the above embodiments;

[0041] The cutting area on the detection substrate is removed.

[0042] A fourth aspect of the present disclosure provides a flat panel detector, which is formed by the above-mentioned flat panel detector manufacturing method.

[0043] The detection substrate provided by the present invention can have a detection line on a controllable on-off area that is in a disconnected state. When the AT line is removed at the end of the process, it can ensure that the AT line at the edge of the subsequent process cannot be connected to the inside of the array substrate, thereby reducing the probability of static electricity failure caused by personnel taking and placing the array substrate after the process.

[0044] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0046] Figure 1 A schematic structural diagram of a detection substrate according to an embodiment of the present disclosure is shown.

[0047] Figure 2 A top view of a detection substrate according to an embodiment of the present disclosure is shown.

[0048] Figure 3-Figure 6 A structural diagram of a process for forming a hole on a hole-digging area of ​​a detection substrate according to an embodiment of the present disclosure is shown.

[0049] Figure 7 A top view of a detection substrate according to another embodiment of the present disclosure is shown.

[0050] Figure 8 A schematic diagram of a first via hole and a second via hole according to another embodiment of the present disclosure is shown.

[0051] Fig. 9 A schematic diagram of detecting static electricity introduction in a substrate manufacturing process according to an embodiment of the present disclosure is shown.

[0052] Fig.10 A schematic diagram of detecting static electricity introduced after a substrate manufacturing process according to an embodiment of the present disclosure is shown.

[0053] Fig.11 A flow chart of a method for manufacturing a detection substrate according to an embodiment of the present disclosure is shown.

[0054] Fig.12 A schematic diagram showing the release of static electricity before the detection line is removed in the related art.

[0055] Fig.13 A schematic diagram showing the release of static electricity after the detection line is removed in the related art. DETAILED DESCRIPTION

[0056] The technical solution of the present disclosure is further specifically described below through examples and in conjunction with the accompanying drawings. In the specification, the same or similar figure numbers indicate the same or similar parts. The following description of the embodiments of the present disclosure with reference to the accompanying drawings is intended to explain the overall inventive concept of the present disclosure and should not be construed as a limitation of the present disclosure.

[0057] In addition, in the following detailed description, for the purpose of explanation, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details.

[0058] The human body generates static electricity because the electrons in the outer layer of atoms are transferred under the influence of various external forces, forming positive and negative ions respectively. When any two objects of different materials come into contact, charge transfer and accumulation will occur, forming static electricity. Static electricity on the human body is mainly caused by friction between clothes or between clothes and the body. Therefore, the amount of "charge" when wearing clothes of different materials is different. For example, clothes made of chemical fibers are more likely to generate static electricity, while cotton clothes generate less. In addition, since a dry environment is more conducive to the transfer and accumulation of charges, people will feel that the static electricity on their bodies is greater in winter. Under different humidity conditions, the static electricity potential generated by human activities is different. In dry seasons, the static electricity of the human body can reach several thousand volts or even tens of thousands of volts. Experiments have shown that the human body does not feel uncomfortable when the static electricity voltage is 50,000 volts, and there is no life-threatening situation when carrying 120,000 volts of high-voltage static electricity. However, the harm that such high static electricity can cause to electronic devices is very huge.

[0059] The process detection traces (AT traces) of traditional FPXD (Flat Panel X-ray Detector) products are made of a whole piece of metal, and static electricity is easily conducted from the cross section to the inside of the FPXD. The metal trace itself has good conductivity, and static electricity is not easily released at the trace. Therefore, the ESD (damage point) is mostly located at the internal device structure of the FPXD product, causing device function failure.

[0060] Specifically, after the array substrate is cut, there is a metal cross section of the AT trace at the edge of the array substrate. When taking and placing the array substrate, the human hand is likely to touch the metal trace cross section and conduct the static electricity carried to the inside of the array substrate, causing static electricity burning of the device, resulting in line failure and making the array substrate ineffective.

[0061] In related technologies, such as Fig.12 and Fig.13 As shown, in order to solve the electrostatic failure caused by touch, a more effective method is to remove the AT wiring. After removal, no metal wiring is leaked at the edge of the array substrate, reducing the risk of people accidentally touching the metal wiring and introducing static electricity.

[0062] However, after the AT traces were removed, the distance between the metal traces and the edge of the array substrate increased, and it was not easy for personnel to touch the metal traces when taking and placing the array substrate, which reduced the incidence of ESD in the back-end. The client found that the dark line was bad during the whole machine online inspection. This phenomenon was very minor and the CT equipment used in the production line could not effectively detect it. It could only be observed after Bonding ROIC, so it had a greater impact on the company's shipments. The product with the AT traces removed was found to have a bad dark line during the whole machine online inspection. The reason was that the static electricity in the process caused the electrostatic ring to fail, resulting in a bad dark line.

[0063] In response to the above technical problems, the inventors have conducted detailed analysis and confirmed that the cause of the dark lines is related to the removal of the AT lines. After the AT lines are removed, the static electricity in the array substrate manufacturing process cannot be quickly dissipated. If there is a large amount of static electricity introduced, after the static electricity is introduced locally, the static electricity is only distributed to each line by the static electricity ring, and the speed is slow. When the introduced voltage is large, it is very easy to cause static electricity damage to the device due to untimely charge evacuation.

[0064] In view of the above technical problems, the embodiments of the present disclosure first provide a detection substrate, such as Figure 1 and Figure 2 As shown, the detection substrate includes: a substrate 10, a plurality of detection units, a plurality of wires 212, a plurality of detection lines 211 and a conductive ring 210; the substrate 10 includes a detection area D, a binding area C, a controllable on-off area B and a cutting area A; a plurality of detection units are arranged on the substrate 10, and the detection unit includes a transistor and a photosensitive device located in the detection area D, and the transistor includes a gate 21, a first electrode 24 and a second electrode 25; the photosensitive device is connected to the first electrode 24 or the second electrode 25 of the transistor; one end of the plurality of wires 212 is connected to the gate 21 of the transistor in the plurality of detection units in a one-to-one correspondence, and the other end extends to the binding area C; the conductive ring 210 is arranged on the cutting area A of the substrate 10; a plurality of detection lines 211 are arranged on the substrate 10, one end is connected to the conductive ring 210, and the other end is connected to the plurality of wires 212 in a one-to-one correspondence, and passes through the controllable on-off area B; wherein the detection line 211 located in the controllable on-off area B can have a disconnected state.

[0065] The detection substrate provided by the present invention can have a detection line 211 on the controllable on-off area B that can be in a disconnected state. When the AT line is removed at the end of the process, it can ensure that the AT line at the edge of the subsequent process cannot be connected to the inside of the array substrate, thereby reducing the probability of static electricity failure caused by the personnel's operation of taking and placing the array substrate after the process.

[0066] In one embodiment of the present disclosure, Figure 2 As shown, the controllable on-off area B is located between the binding area C and the cutting area A; multiple detection lines 211 pass through the controllable on-off area B and are connected to multiple wires 212 one by one; the detection line 211 located on the controllable on-off area B has a cutting opening, which puts the detection line 211 in a disconnected state.

[0067] The present invention removes the AT wiring after the detection unit is formed, that is, when the process is about to end. On the one hand, the AT wiring is connected to the internal wiring of the array substrate during the process. When static electricity is locally introduced during the process, the static electricity can be quickly conducted to each wiring by the static electricity ring, so that the charge is quickly conducted and distributed, avoiding the situation where a single device is subjected to a large charge and fails, ensuring that static electricity in the process does not damage the device, thereby playing a role in protecting the device; on the other hand, removing the AT wiring when the process is about to end can ensure that the AT wiring at the edge of the subsequent process cannot be connected to the inside of the array substrate, thereby reducing the probability of static electricity failure caused by personnel taking and placing the array substrate after the process.

[0068] Specifically, Figure 1 As shown, the detection unit includes a gate 21 formed on a substrate 10, a gate insulating layer 22 formed on the substrate 10 and covering the gate 21; an active layer 23 located on the side of the gate insulating layer 22 away from the substrate 10; a source-drain metal layer (SD layer) located on the side of the active layer 23 away from the substrate 10, the source-drain metal layer includes a first electrode 24 and a second electrode 25, and the first electrode 24 and the second electrode 25 are spaced apart on the active layer 23; the gate 21, the gate insulating layer 22, the active layer 23, the first electrode 24 and the second electrode 25 form a transistor. Among them, the first electrode 24 is a source electrode, and the second electrode 25 is a drain electrode; or the first electrode 24 is a drain electrode, and the second electrode 25 is a source electrode.

[0069] For example, the material of the substrate 10 may be an inorganic material, such as glass materials such as soda-lime glass, quartz glass, sapphire glass, or metal materials such as various metals or their alloys such as stainless steel, aluminum, nickel, etc. In other embodiments, the material of the substrate 10 may also be an organic material, such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. In other embodiments, the material of the substrate 10 may also be a flexible material, such as polyimide (PI). The substrate 10 may be a single-layer structure or a multi-layer structure, and the multi-layer structure may be formed using different materials.

[0070] For example, the material of the gate 21 can be a conductive material. The conductive material is, for example, a metal, a conductive metal oxide, a conductive polymer, a conductive composite material, or a combination thereof. For example, the metal can be platinum, gold, silver, aluminum, chromium, nickel, copper, molybdenum, titanium, magnesium, calcium, barium, sodium, palladium, iron, manganese, or a combination thereof. The conductive metal oxide can be InO2, SnO2, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), or a combination thereof. The conductive polymer can be polyaniline, polypyrrole, polythiophene, polyacetylene, poly (3,4-ethylenedioxythiophene) / polystyrene sulfonic acid (PEDOT / PSS) or a combination thereof. The conductive composite material can be a conductive composite material dispersed with carbon black, graphite powder, metal particles, etc. The formation method of the gate 21 is, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), spin coating, or a combination thereof.

[0071] For example, the gate insulating layer 22 can be silicon oxide, silicon oxynitride, silicon nitride or other suitable insulating materials (such as organic polymer compounds) or a combination of the above materials. The gate insulating layer 22 can be formed by physical vapor deposition, chemical vapor deposition, spin coating or a combination thereof.

[0072] For example, the materials of the first pole 24 and the second pole 25 may include metals, conductive oxides or combinations thereof. For example, the metal may be titanium, platinum, ruthenium, gold, silver, molybdenum, aluminum, tungsten, copper, neodymium, chromium, tantalum or alloys thereof or combinations thereof. The conductive oxide may be indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), indium tin oxide (ITO), gallium zinc oxide (GZO), zinc tin oxide (ZTO) or combinations thereof. The formation method of the first pole 24 and the second pole 25 is, for example, PVD, CVD or a combination thereof. The materials of the first pole 24 and the second pole 25 may be the same or different. Using the same material can reduce the process cost and difficulty of forming the first pole 24 and the second pole 25.

[0073] For example, the material of the active layer 23 may be amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, oxide semiconductor material, organic silicon material, organic oxide semiconductor material or a combination thereof. The active layer 23 may be formed by PVD, CVD or a combination thereof.

[0074] In the embodiments of the present disclosure, the transistor may be a top gate type or a bottom gate type. In the embodiments of the present disclosure, the bottom gate type transistor is mainly used as an example for explanation. When the transistor is a bottom gate type, the gate 21 is formed on the substrate 10, and the gate 21 may include a metal material or an alloy material, such as molybdenum, aluminum and titanium, to ensure its good conductivity; the gate insulating layer 22 is formed on the substrate 10 and covers the gate 21; the active layer 23 is formed on the side of the insulating layer 90 away from the substrate 10, and the first pole 24 and the second pole 25 are respectively connected to the two doping regions of the active layer 23. In addition, the transistor is also divided into N-type and P-type, etc., depending on the specific situation.

[0075] For example, Figure 1 As shown, the detection unit also includes a gate electrode 21 and a first passivation layer 31 formed on the substrate 10, forming a lower electrode 41 on the side of the first passivation layer 31 away from the substrate 10, and the lower electrode 41 is electrically connected to the second electrode 25 through a via hole on the first passivation layer 31; a photoelectric layer 42 is formed on the side of the lower electrode 41 away from the substrate 10, and the photoelectric layer 42 is, for example, a photodiode; an upper electrode 44 is formed on the side of the photoelectric layer 42 away from the substrate 10, and the upper electrode 44 is a transparent electrode so that light can enter the photoelectric layer 42. Among them, the lower electrode 41, the photoelectric layer 42 and the upper electrode 44 form a photosensitive device. The photosensitive device generates an electrical signal when it senses light, which is transmitted to the transistor, and the transistor transmits the signal to the control end. Among them, a transparent conductive layer 43 can also be formed between the photoelectric layer 42 and the upper electrode 44.

[0076] For example, the first passivation layer 31 may be made of an inorganic insulating film, such as silicon nitride, or an organic insulating film, such as a resin material. The lower electrode 41 may be made of a metal or metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper. The material of the upper electrode 44 may be indium tin oxide (ITO) or indium doped zinc oxide (IZO), so as to prevent the upper electrode 44 from blocking the light and affecting the light collection of the photoelectric layer 42.

[0077] Among them, Figure 1 As shown, a planarization layer (Resin) is also formed on the substrate 10, a second passivation layer (PVX2) 32 located on the side of the planarization layer facing away from the substrate 10, a metal wiring layer (TopMetal) located on the side of the second passivation layer 32 facing away from the substrate 10, a third passivation layer (PVX3) 60 located on the side of the metal wiring layer facing away from the substrate 10, a transparent conductive layer (Top ITO, not shown in the figure) located on the side of the third passivation layer 60 facing away from the substrate 10, and other related film layers, depending on the specific situation.

[0078] For example, the second passivation layer 32 may be made of an inorganic insulating film, such as silicon nitride, or an organic insulating film, such as a resin material. The material of the second passivation layer 32 may be the same as or different from that of the first passivation layer 31. The metal wiring layer may be made of a metal or a metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper and other conductive materials. The third passivation layer 60 may be made of an inorganic insulating film, such as silicon nitride, or an organic insulating film, such as a resin material. The material of the third passivation layer 60 may be the same as or different from that of the second passivation layer 32 and the first passivation layer 31. The transparent conductive layer is a transparent conductive material such as indium tin oxide or indium-doped zinc oxide.

[0079] The photodiode is a PIN photodiode, and the PIN photodiode includes a lower electrode 41, an N-type amorphous silicon layer, an intrinsic amorphous silicon layer, a P-type amorphous silicon layer and an upper electrode 44. For example, the N-type amorphous silicon may be amorphous silicon doped with phosphorus ions, and the P-type amorphous silicon may be amorphous silicon doped with boron ions.

[0080] Among them, Figure 3-Figure 6 As shown, a second passivation layer 32, a first passivation layer 31, a gate insulating layer 22 and a wiring layer are formed on the substrate 10 located in the controllable on-off region B. Through dry etching processes such as plasma etching (PE), reactive particle etching (RIE), enhanced capacitive coupled plasma etching (ECCP) and inductively coupled plasma etching (ICP), or through wet etching processes such as spraying and dipping, etching holes penetrating the second passivation layer 32, the first passivation layer 31, the gate insulating layer 22 and the wiring layer are formed on the controllable on-off region B, and the etching holes cut off a plurality of detection lines 211, so that cutting openings are formed on the detection lines 211. This ensures that the AT traces at the edge of the back-end process cannot be connected to the inside of the array substrate, thereby reducing the probability of static electricity failure caused by personnel taking and placing the array substrate after the process.

[0081] Among them, the multiple wires 212 and the multiple detection lines 211 are arranged in the same layer, that is, they can be made by the same composition process to reduce the mask cost; but not limited to this, they can also be made by different composition processes, depending on the specific situation. The multiple wires 212 and the multiple detection lines 211 can be formed through the same conductive material layer and the same composition process (film formation, exposure, development, wet etching or dry etching), that is, the correspondingly connected wires 212 and the detection lines 211 can be different parts of the same wire.

[0082] In one embodiment of the present disclosure, the detection line 211 located on the controllable on-off region B has a tip discharge portion, and the tip discharge portion can be melted by tip discharge, so that the detection line 211 is in an off state.

[0083] In one embodiment of the present disclosure, Figure 7 As shown, the controllable on-off area B is located between the binding area C and the cutting area A; multiple wires 212 extend to the controllable on-off area B, and an insulating layer 90 is formed on the side of the multiple wires 212 away from the substrate 10, and multiple detection lines 211 are formed on the side of the insulating layer 90 away from the substrate 10.

[0084] Among them, Figure 8-Figure 10 As shown, a plurality of first via holes 321 and a plurality of second via holes 322 are formed on the insulating layer 90, the first via holes 321 are projected on the substrate 10 in the controllable on-off region B, and the second via holes 322 are projected on the substrate 10 in the binding region C; each conductor 212 is exposed simultaneously through the first via hole 321 and the second via hole 322; the area of ​​the first via hole 321 projected on the substrate 10 is smaller than the area of ​​the second via hole 322 projected on the substrate 10; a plurality of detection lines 211 are connected to a plurality of conductors 212 in a one-to-one correspondence through the first via hole 321; the detection line 211 forms a tip discharge portion in the first via hole 321 (for example, the tip discharge portion can be formed at the portion where the area of ​​the first via hole 321 projected on the substrate 10 is the smallest).

[0085] In the process, AT traces are used to evacuate static electricity, and the voltage actually distributed to a single trace is relatively small, which can be conducted through ITO small-sized lap vias; after the process, when static electricity is introduced by the AT traces, the ITO small-sized lap vias cannot conduct excessive voltage and burn, and the static electricity conduction path is cut off, and cannot be further conducted to the inside of FPXD to damage devices and traces. The present disclosure uses lap vias of different sizes in different areas by designing different areas, which can ensure that most of the processes in the process have AT traces connecting the traces, and can achieve ESD protection throughout the process, reducing ESD damage to a single device in the process, and can ensure that the AT traces at the edge of the back-end process cannot be connected to the inside of the array substrate, thereby avoiding the burning of the lap vias when the subsequent personnel in the process touch and introduce a large voltage, reducing the probability of static electricity defects caused by the personnel taking and placing the array substrate after the process, thereby avoiding the further introduction of static electricity into the inside of the FPXD product, playing a role in protecting the device.

[0086] In one embodiment of the present disclosure, Figure 8 and Fig.10 As shown, a plurality of first conductive portions 81 are formed on a side of the insulating layer 90 facing away from the substrate 10 , and the plurality of first conductive portions 81 form a plurality of detection lines 211 .

[0087] Furthermore, a plurality of second conductive portions 82 are formed on a side of the insulating layer 90 facing away from the substrate 10 , and the plurality of second conductive portions 82 are connected to the conductive wires 212 in a one-to-one correspondence through the second vias 322 .

[0088] The plurality of first conductive parts 81 and the plurality of second conductive parts 82 are disposed in the same layer, that is, they can be formed by the same patterning process.

[0089] For example, the cross-sectional shape of the first via 321 may be cylindrical, trapezoidal or irregular. The width of the first via 321 (the extension width of the first via 321 on the plane where the substrate 10 is located, when the first via 321 is an unequal diameter via and a non-cylindrical via, it has multiple width values) may be 1μm-2μm, such as 1μm, 1.2μm, 1.5μm, 1.7μm, 1.8μm, 2μm, etc., which are not listed here in the present disclosure. Of course, the diameter of the first via 321 may also be less than 1μm or greater than 2μm, and the present disclosure does not limit this, as long as a pointed discharge portion can be formed to achieve a more likely melting effect of the conductive material in the first via 321 when a large voltage is introduced by a subsequent person in the process.

[0090] For example, the depth of the first via hole 321 (the depth direction is the direction of the insulating layer 90 away from the substrate 10) is 0.2 μm-1 μm, such as 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.8 μm, 1 μm, etc., which are not listed here. Of course, the depth of the first via hole 321 can also be less than 0.2 μm or greater than 1 μm, which is not limited by the present disclosure.

[0091] For example, the angle between the sidewall of the first via hole 321 and the substrate 10 is less than 90°. Fig. 9 As shown, the angle between the side wall of the first via hole 321 and the substrate 10 toward the periphery of the substrate 10 is less than 90°, and may be, for example, 80°, 70°, 60°, 50°, 40°, 30°, etc., which are not listed here in the present disclosure. Of course, when the first via hole 321 is a hole of unequal diameter, the angles between the first via hole 321 at different heights and the substrate 10 are different, or greater than 90°, which is not limited in the present disclosure.

[0092] Among them, the cross-sectional shape of the second via 322 may be cylindrical, trapezoidal or irregular. When the cross-sectional shape of the second via 322 may be cylindrical, the diameter of the second via 322 may be 6μm-10μm, such as 6.0μm, 6.5μm, 7.0μm, 7.5μm, 8μm, etc., which are not listed here in the present disclosure. Of course, the diameter of the second via 322 may also be less than 6μm or greater than 10μm, and the present disclosure does not limit this. Among them, the diameter ratio of the second via 322 to the first via 321 may be 5:1, but is not limited thereto, and may also be 4:1 or 6:1, depending on the specific circumstances.

[0093] In one embodiment of the present disclosure, each wire 212 is exposed through a plurality of first vias 321. Figure 8 As shown, each wire 212 is exposed through two first via holes 321. Since the size of the first via holes 321 is small, multiple first via holes 321 are provided to ensure the reliability of the connection between the detection line 211 and the wire 212. Of course, each wire 212 can also be exposed through three or more first via holes 321, and each wire 212 can be exposed through the same number of first via holes 321 or through different numbers of first via holes 321.

[0094] In one embodiment of the present disclosure, each conductive line 212 is exposed through a plurality of second vias 322. Figure 8 As shown, each wire 212 is exposed through four second vias 322 to ensure binding reliability. Of course, each wire 212 can also be exposed through five or more first vias 321, and each wire 212 can be exposed through the same number of second vias 322 or different numbers of second vias 322.

[0095] In one embodiment of the present disclosure, the detection line 211 located on the controllable on-off region (B) has an oxidized portion, and the detection line 211 is subjected to metal oxidation treatment to form an oxidized portion with poor conductivity or insulation, so that the detection line 211 is in a disconnected state and cannot conduct electricity normally. This ensures that the edge AT wiring cannot be connected to the inside of the array substrate, thereby reducing the probability of static electricity failure caused by personnel taking and placing the array substrate.

[0096] The embodiment of the present disclosure also provides a method for manufacturing a detection substrate, such as Fig.11 As shown, the manufacturing method includes:

[0097] Step S100, providing a substrate, the substrate comprising a detection area, a binding area, a controllable on / off area and a cutting area;

[0098] Step S200, forming a plurality of detection units on a substrate, wherein the detection units include transistors and photosensitive devices located on a detection area, wherein the transistors include a gate, a first electrode, and a second electrode; and the photosensitive devices are connected to the first electrode or the second electrode of the transistors;

[0099] Step S300, forming a plurality of wires on a substrate, wherein one end of the plurality of wires is connected to the gates of the transistors in the plurality of detection units in a one-to-one correspondence, and the other end of the plurality of wires extends to the binding region;

[0100] Step S400, forming a conductive ring on the cutting area of ​​the substrate;

[0101] Step S500, forming a plurality of detection lines on the substrate, wherein one end of the plurality of detection lines is connected to the conductive ring, and the other end is connected to a plurality of wires one by one, and passes through the controllable on-off area; wherein the detection lines located on the controllable on-off area can have an off state.

[0102] The manufacturing method of the detection substrate provided by the present invention enables the detection line on the controllable on-off area to have a disconnected state. When the AT line is removed at the end of the process, it can ensure that the AT line at the edge of the back-end process cannot be connected to the inside of the array substrate, thereby reducing the probability of static electricity failure caused by the personnel's operation of taking and placing the array substrate after the process.

[0103] Next, each step in the method for manufacturing the detection substrate provided by the present disclosure will be described in detail.

[0104] In step S100 , a substrate is provided, the substrate comprising a detection area, a binding area and a cutting area.

[0105] Specifically, Figure 1 As shown, the material of the substrate 10 may be an inorganic material, such as glass materials such as soda lime glass, quartz glass, sapphire glass, or metal materials such as various metals or their alloys such as stainless steel, aluminum, nickel, etc. In other embodiments, the material of the substrate 10 may also be an organic material, such as polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof. In other embodiments, the material of the substrate 10 may also be a flexible material, such as polyimide (PI). The substrate 10 may be a single-layer structure or a multi-layer structure, and the multi-layer structure may be formed using different materials.

[0106] In step S200, a plurality of detection units are formed on a substrate. The detection units include transistors and photosensitive devices located on a detection area. The transistors include a gate, a first electrode and a second electrode. The photosensitive devices are connected to the first electrode or the second electrode of the transistors.

[0107] Specifically, Figure 1As shown, the gate electrode 21, the gate insulating layer 22, the active layer 23, the first electrode 24 and the second electrode 25 of the thin film transistor are sequentially formed on the substrate 10 through a patterning process. First, a gate metal film layer is formed on the substrate 10 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition. Then, a half tone mask (Half Tone Mask, HTM) or a gray tone mask (Gray Tone Mask, GTM) is used to form the pattern of the gate through a patterning process (film formation, exposure, development, wet etching or dry etching). The gate electrode can be formed of metal or metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper and other conductive materials; then, a gate insulating layer 22 covering the gate electrode 21 is formed on the substrate 10 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering; then, an amorphous silicon film is deposited by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition or other methods, and the pattern of the active layer 23 is formed by crystallizing the amorphous silicon film by patterning; then, a source-drain metal layer is formed by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering, and a pattern including a first electrode 24 and a second electrode 25 is formed by a single patterning process. The first electrode 24 is a source electrode, and the second electrode 25 is a drain electrode; or the first electrode 24 is a drain electrode, and the second electrode 25 is a source electrode.

[0108] Next, a first passivation layer 31 is formed by a patterning process, and a via hole is formed at a position of the first passivation layer 31 corresponding to the second pole 25. For example, the first passivation layer 31 can be formed by deposition using a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, or an electron cyclotron resonance chemical vapor deposition method, and the via hole is formed by a patterning process such as masking and dry etching. The material of the first passivation layer 31 may include materials such as silicon nitride and silicon oxide.

[0109] Next, a pattern including the lower electrode 41 of the photodiode is formed by a patterning process, and the lower electrode 41 is connected to the second electrode 25 of the thin film transistor through a via. Similar to the process of forming the first electrode 24 and the second electrode 25 of the thin film transistor, in this step, a metal film layer can be deposited on the first passivation layer 31 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering, and the pattern of the lower electrode 41 of the photodiode is formed by a patterning process such as masking and wet etching. Among them, the metal film layer material can be metal, metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper and other conductive materials.

[0110] Then, if Figure 1 As shown, a photoelectric layer 42 is deposited on the lower electrode 41. The steps of forming the photoelectric layer 42 include: depositing an etching barrier material layer by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition; depositing a semiconductor material layer on the etching barrier material layer by plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition; removing the semiconductor material layer outside the photodiode region by dry etching processes such as plasma etching (PE), reactive ion etching (RIE), enhanced capacitive coupled plasma etching (ECCP) and inductively coupled plasma etching (ICP) to form a photoelectric layer.

[0111] In order to make the photoelectric layer 42 of the photodiode have good ohmic contact with the upper electrode 44 of the photodiode to be formed, a transparent conductive layer 43 can be formed on the photoelectric layer 42 after the photoelectric layer 42 is formed; then, the transparent conductive layer 43 is etched to form a transparent electrode. The material of the transparent electrode can be ITO, IGZO, etc.

[0112] like Figure 1 As shown, a flat layer is formed on the substrate 10 on which the first passivation layer 31 and the photoelectric layer 42 of the photodiode are formed, a second passivation layer 32 is formed on the flat layer on a side away from the substrate 10, and via holes are formed at positions corresponding to the second passivation layer 32 and the flat layer and the photoelectric layer 42.

[0113] The material of the second passivation layer 32 may include silicon nitride and silicon oxide layer materials; the material of the flat layer includes resin, and its thickness is relatively large, so as to flatten the flat panel detector substrate 10. The interlayer insulating material film may be deposited layer by layer by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition, and a via hole may be formed at a position corresponding to the photoelectric layer 42 through a patterning process such as masking and etching.

[0114] In one embodiment of the present disclosure, since the thickness of the single-layer resin material flat layer is relatively large and is easy to fall off, in order to further ensure the performance of the product, the flat layer preferably includes a first flat layer 51 and a second flat layer 52 arranged in sequence. The material of the first flat layer 51 may include silicon nitride or silicon oxide layer materials, and the material of the second flat layer 52 may include resin. Figure 1 As shown, the thickness of the second planar layer 52 is greater than the thickness of the first planar layer 51 .

[0115] like Figure 8 As shown, a pattern including an upper electrode 44 of a photodiode is formed by a patterning process, and the upper electrode 44 of the photodiode is connected to the photoelectric layer 42 through a via. Specifically, a metal film layer can be deposited on the second passivation layer 32 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition, or sputtering, and a pattern of the upper electrode 44 (bias electrode) of the photodiode is formed by a patterning process such as masking and wet etching. Among them, the metal film layer material can be a metal or a metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper and other conductive materials.

[0116] The lower electrode 41, the photoelectric layer 42 and the upper electrode 44 sequentially arranged on the substrate 10 constitute a photodiode. The lower electrode 41 of the photodiode is connected to the second electrode 25 of the thin film transistor to realize the connection between the photodiode and the thin film transistor, thereby controlling the conduction state of the thin film transistor to realize the detection of the light signal collected by the photodiode. At this point, the preparation of the thin film transistor and the photodiode in the flat panel detector substrate 10 is completed.

[0117] It should be noted that the lower electrode 41 of the photodiode in this embodiment may be directly connected to the second electrode 25 of the thin film transistor, or may be indirectly connected through a conductive layer.

[0118] In step S300, a plurality of conductive wires are formed on a substrate, one end of the plurality of conductive wires is connected to the gates of transistors in a plurality of detection units in a one-to-one correspondence, and the other end of the plurality of conductive wires extends to a binding region.

[0119] Specifically, a gate metal film layer is formed on the substrate 10 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition; then a halftone mask or a gray tone mask is used to form the pattern of the gate 21 through a composition process (film formation, exposure, development, wet etching or dry etching). The same composition process can be used to form multiple wires 212 that are connected one-to-one to the gates 21 of the transistors in the multiple detection units, and the multiple wires 212 extend to the binding area C.

[0120] In step S400 , a conductive ring is formed on a cutting area of ​​a substrate.

[0121] Specifically, Figure 2 As shown, a gate metal film layer is formed on the substrate 10 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition; and then a halftone mask or a gray tone mask is used to form a conductive ring 210 through a patterning process (film formation, exposure, development, wet etching or dry etching).

[0122] In step S500, a plurality of detection lines are formed on the substrate, one end of the plurality of detection lines is connected to the conductive ring, the other end is connected to a plurality of conductive wires one by one, and passes through a controllable on-off area; wherein the detection lines located on the controllable on-off area can have an off state.

[0123] Specifically, the conductive ring 210 and the plurality of detection lines 211 can be formed by the same patterning process. Figure 2 As shown, the controllable on-off area B is located between the binding area C and the cutting area A. One end of multiple detection lines 211 is connected to the conductive ring 210, and the other end is connected to multiple wires 212 one by one and passes through the controllable on-off area B.

[0124] In one embodiment of the present disclosure, a cutting opening is formed on the detection line 211 located in the controllable on-off area B, and the detection line 211 is placed in a disconnected state through the cutting opening.

[0125] Specifically, the substrate 10 is formed with a wiring layer, a gate insulating layer 22, a first passivation layer 31 and a second passivation layer 32 on the controllable on-off region B, and a patterned mask layer (photoresist layer 70) is formed on the second passivation layer 32, and the patterned mask layer exposes the portion of the second passivation layer 32 corresponding to the controllable on-off region B; plasma etching (PE), reactive ion etching (RIE), enhanced capacitive coupled plasma etching (ECCP) and inductively coupled plasma etching (ICP) are used to perform etching. By using dry etching processes such as plasma etching (ICP), or wet etching processes such as spraying and dipping, an etching hole penetrating the second passivation layer 32, the first passivation layer 31, the gate insulation layer 22 and the wiring layer is formed on the controllable on-off region B, and the etching hole cuts off a plurality of detection lines 211, so that a cutting opening is formed on the detection line 211. The method for forming the cutting opening is not limited thereto, and a cutting opening can also be formed on the detection line 211 by grinding, cutting, etc. By forming the cutting opening on the detection line 211, it is ensured that the AT wiring at the edge of the back-end process cannot be connected to the inside of the array substrate, thereby reducing the probability of electrostatic failure caused by the personnel taking and placing the array substrate after the process.

[0126] In one embodiment of the present disclosure, a tip discharge portion is formed on the detection line 211 located in the controllable on-off region B, and the detection line 211 is disconnected by the tip discharge portion. Figure 7 As shown, the controllable on-off area B is located between the binding area C and the cutting area A; and multiple wires 212 are extended to the controllable on-off area B; an insulating layer 90 is formed on the side of the multiple wires 212 away from the substrate 10; multiple first vias 321 and multiple second vias 322 are formed on the insulating layer 90, and the first vias 321 are projected on the substrate 10 and located in the controllable on-off area B, and the second vias 322 are projected on the substrate 10 and located in the binding area C; each wire 212 is exposed at the same time through the first via 321 and the second via 322; the area of ​​the first via 321 projected on the substrate 10 is smaller than the area of ​​the second via 322 projected on the substrate 10; multiple detection lines 211 are formed on the side of the insulating layer 90 away from the substrate 10, and the multiple detection lines 211 are connected one-to-one with the multiple wires 212 through the first vias 321. The first via hole 321 and the second via hole 322 can be formed on the insulating layer 90 by masking, etching and other patterning processes. The detection line 211 forms a tip discharge portion in the first via hole 321 (for example, the tip discharge portion can be formed at the location where the first via hole 321 has the smallest orthographic projection area on the substrate 10).

[0127] In the process, AT traces are used to evacuate static electricity, and the voltage actually distributed to a single trace is relatively small, which can be conducted through ITO small-sized lap vias; after the process, when static electricity is introduced by the AT traces, the ITO small-sized lap vias cannot conduct excessive voltage and burn, and the static electricity conduction path is cut off, and cannot be further conducted to the inside of FPXD to damage devices and traces. The present disclosure uses lap vias of different sizes in different areas by designing different areas, which can ensure that most of the processes in the process have AT traces connecting the traces, and can achieve ESD protection throughout the process, reducing ESD damage to a single device in the process, and can ensure that the AT traces at the edge of the back-end process cannot be connected to the inside of the array substrate, thereby avoiding the burning of the lap vias when the subsequent personnel in the process touch and introduce a large voltage, reducing the probability of static electricity defects caused by the personnel taking and placing the array substrate after the process, thereby avoiding the further introduction of static electricity into the inside of the FPXD product, playing a role in protecting the device.

[0128] In one embodiment of the present disclosure, the detection line 211 located on the controllable on-off region (B) can be subjected to metal oxidation treatment to form an oxidized portion with poor conductivity or insulation, so that the detection line 211 is in a disconnected state and cannot conduct electricity normally. This ensures that the edge AT wiring cannot be connected to the inside of the array substrate, thereby reducing the probability of static electricity failure caused by personnel taking and placing the array substrate.

[0129] In one embodiment of the present disclosure, the manufacturing method further includes: forming a first conductive portion 81 on the side of the insulating layer 90 away from the substrate 10, and a plurality of first conductive portions 81 form a plurality of detection lines 211. A gate metal film layer is formed on the insulating layer 90 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition; and then a halftone mask or a gray tone mask is used to form a pattern of the first conductive portion 81 by a patterning process. The insulating layer 90 and the gate insulating layer 22 are formed by the same patterning process.

[0130] In one embodiment of the present disclosure, the manufacturing method further includes: forming a plurality of second conductive portions 82 on a side of the insulating layer 90 away from the substrate 10, and the plurality of second conductive portions 82 are connected one-to-one with the plurality of wires 212 through the second vias 322. A gate metal film layer is formed on the insulating layer 90 by sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition or electron cyclotron resonance chemical vapor deposition; and then a halftone mask or a gray tone mask is used to form a pattern of the second conductive portion 82 by a patterning process.

[0131] The first conductive portion 81 and the second conductive portion 82 can be formed by the same process, that is, they can be arranged in the same layer.

[0132] For other details not disclosed in the manufacturing method of the detection substrate provided in the embodiment of the present disclosure, please refer to the above description of the detection substrate embodiment, which will not be repeated here.

[0133] An embodiment of the present disclosure also provides a method for manufacturing a flat panel detector, which includes: the method for manufacturing a detection substrate provided in the above embodiment; removing a cutting area A on the detection substrate, and the cutting area on the detection substrate can be removed by cutting along the virtual line where the cutting area A and the controllable on-off area B intersect.

[0134] In one embodiment of the present disclosure, the manufacturing method may further include forming a scintillation layer on a substrate provided with a plurality of detection units, the scintillation layer being used to convert X-rays into visible light, the photosensitive device being used to convert the visible light into an electrical signal, and the transistor being used as a switch for reading the electrical signal.

[0135] The material of the scintillating layer may include cesium iodide, which is a light-sensitive material. The scintillating layer may include a crystal array arranged in a columnar shape. Optionally, a passivation layer may be provided between the scintillating layer and the photosensitive device, and the passivation layer may be used to protect the photosensitive device.

[0136] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0137] The embodiment of the present disclosure also provides a flat panel detector, which can be formed by the above-mentioned flat panel detector manufacturing method. The flat panel detector can be an X-ray flat panel detector. The beneficial effects thereof refer to the description of the beneficial effects of the detection substrate and the manufacturing method thereof, which will not be repeated here.

[0138] It should be noted that the terms “on…”, “formed on…” and “disposed on…” mentioned herein may mean that one layer is directly formed or disposed on another layer, or may mean that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers.

[0139] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.

[0140] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various regions, layers and / or parts, these regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one region, layer and / or part from another.

[0141] In the present disclosure, unless otherwise specified, the term "same-layer arrangement" is used to mean that two layers, parts, components, elements or portions can be formed by the same patterning process, and the two layers, parts, components, elements or portions are generally formed of the same material.

[0142] In the present disclosure, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0143] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing what is disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A detection substrate, wherein: include: A substrate (10) comprising a detection area (D), a binding area (C), a controllable on / off area (B) and a cutting area (A); A plurality of detection units are arranged on the substrate (10), the detection units comprising a transistor and a photosensitive device located on the detection area (D), the transistor comprising a gate (21), a first electrode (24) and a second electrode (25); the photosensitive device is connected to the first electrode (24) or the second electrode (25) of the transistor; A plurality of wires (212) are arranged on the substrate (10), one end of which is connected to the gates (21) of the transistors in the plurality of detection units in a one-to-one correspondence, and the other end of which extends to the binding area (C); A conductive ring (210) is disposed on the cutting area (A) of the substrate (10); A plurality of detection lines (211) are arranged on the substrate (10), one end of which is connected to the conductive ring (210), and the other end of which is connected to the plurality of conductive lines (212) in a one-to-one correspondence, and passes through the controllable on-off area (B); The detection line (211) located on the controllable on-off region (B) can have an off state.

2. The detection substrate according to claim 1, wherein: The detection line (211) located on the controllable on-off area (B) has a cutting opening, and the cutting opening puts the detection line (211) in the disconnected state.

3. The detection substrate according to claim 1, wherein: The detection line (211) located on the controllable on-off region (B) has a tip discharge portion, and the tip discharge portion can be melted by tip discharge, so that the detection line (211) is in the disconnected state.

4. The detection substrate according to claim 2, wherein: The controllable on-off area (B) is located between the binding area (C) and the cutting area (A); an etching hole is formed on the controllable on-off area (B), and the etching hole cuts off the plurality of detection lines (211), so that the detection lines (211) form the cutting openings.

5. The detection substrate according to claim 4, wherein: The detection unit includes: A routing layer, comprising the plurality of detection lines (211); A gate insulating layer (22) is provided on a side of the wiring layer facing away from the substrate (10); A first passivation layer (31) is provided on a side of the gate insulating layer (22) facing away from the substrate (10); A second passivation layer (32) is provided on a side of the first passivation layer (31) facing away from the substrate (10); An etching hole penetrating the second passivation layer (32), the first passivation layer (31), the gate insulation layer (22) and the wiring layer is formed on the controllable on-off region (B), and the etching hole cuts off the multiple detection lines (211), so that the cutting openings are formed on the detection lines.

6. The detection substrate according to claim 2, wherein: The plurality of conductive lines (212) are arranged in the same layer as the plurality of detection lines (211).

7. The detection substrate according to claim 3, wherein: The controllable on-off area (B) is located between the binding area (C) and the cutting area (A); the plurality of wires (212) extend to the controllable on-off area (B), an insulating layer (90) is formed on a side of the plurality of wires (212) away from the substrate (10), and the plurality of detection lines (211) are formed on a side of the insulating layer (90) away from the substrate (10); Wherein, a plurality of first via holes (321) and a plurality of second via holes (322) are formed on the insulating layer (90); the orthographic projection of the first via holes (321) on the substrate (10) is located in the controllable on-off area (B), and the orthographic projection of the second via holes (322) on the substrate (10) is located in the binding area (C); each of the wires (212) is exposed simultaneously through the first via holes (321) and the second via holes (322); the orthographic projection area of ​​the first via holes (321) on the substrate (10) is smaller than the orthographic projection area of ​​the second via holes (322) on the substrate (10); the plurality of detection lines (211) are connected to the plurality of wires (212) in a one-to-one correspondence through the first via holes (321); and the detection lines (211) form the tip discharge portion in the first via holes (321).

8. The detection substrate according to claim 7, wherein: The width of the first via hole (321) is 1 μm-2 μm.

9. The detection substrate according to claim 7, wherein: The depth of the first via hole (321) is 0.2 μm-1 μm.

10. The detection substrate according to claim 7, wherein: The angle between the side wall of the first via hole (321) and the substrate (10) is less than 90°.

11. The detection substrate according to claim 7, wherein: A plurality of first conductive parts (81) are formed on a side of the insulating layer (90) facing away from the substrate (10); the plurality of first conductive parts (81) are connected to each of the conductive wires (212) in a one-to-one correspondence through the first via holes (321); and the plurality of first conductive parts (81) form the plurality of detection lines (211).

12. The detection substrate according to claim 11, wherein A plurality of second conductive parts (82) are formed on a side of the insulating layer (90) facing away from the substrate (10), and the plurality of second conductive parts (82) are connected to each of the conductive wires (212) in a one-to-one correspondence through the second via holes (322).

13. The detection substrate according to claim 12, wherein: The plurality of first conductive parts (81) and the plurality of second conductive parts (82) are arranged in the same layer.

14. The detection substrate according to claim 7, wherein: Each of the conductive lines (212) is exposed through a plurality of the first via holes (321).

15. A method for manufacturing a detection substrate, wherein: include: A substrate (10) is provided, wherein the substrate (10) comprises a detection area (D), a binding area (C), a controllable on / off area (B) and a cutting area (A); A plurality of detection units are formed on the substrate (10), the detection units comprising a transistor and a photosensitive device located on the detection area (D), the transistor comprising a gate (21), a first electrode (24) and a second electrode (25); the photosensitive device is connected to the first electrode (24) or the second electrode (25) of the transistor; A plurality of wires (212) are formed on the substrate (10), one end of the plurality of wires (212) being connected to the gates (21) of the transistors in the plurality of detection units in a one-to-one correspondence, and the other end of the plurality of wires (212) extending to the binding area (C); forming a conductive ring (210) on a cutting area (A) of the substrate (10); A plurality of detection lines (211) are formed on the substrate (10), one end of the plurality of detection lines (211) is connected to the conductive ring (210), and the other end is connected to the plurality of conductive lines (212) in a one-to-one correspondence, and passes through the controllable on-off area (B); wherein the detection lines (211) located on the controllable on-off area (B) can have an off state.

16. The manufacturing method according to claim 15, wherein: A cutting opening is formed on the detection line (211) located in the controllable on-off area (B), and the detection line (211) is placed in an off state through the cutting opening.

17. The manufacturing method according to claim 15, wherein: A tip discharge portion is formed on the detection line (211) located in the controllable on-off region (B), and the detection line (211) is disconnected by the tip discharge portion.

18. A method for manufacturing a flat panel detector, wherein: include: The method for manufacturing a detection substrate according to any one of claims 15 to 17; The cutting area (A) on the detection substrate is removed.

19. A flat panel detector, wherein: The flat panel detector is formed by the method for manufacturing the flat panel detector according to claim 18.

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