Pull-down circuit, GOA circuit, driving method thereof and display panel

Abstract

The present application provides a pull-down circuit, a GOA circuit, a driving method for a GOA circuit, and a display panel, wherein the pull-down circuit includes a forward scan pull-down module and a reverse scan pull-down module. The forward scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal during forward scan driving, and the reverse scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal during reverse scan driving. The pull-down circuit provided in the embodiment of the present application is compatible with forward scan and reverse scan, meeting the application scenario of the same screen being compatible with forward mounting and reverse mounting, thereby meeting the needs of product diversification.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pull-down circuit, a GOA circuit, a driving method thereof, and a display panel. Background Art

[0002] At present, display devices as display components of electronic devices have been widely used in various electronic products, and the gate driver on array (GOA) circuit is an important component of the display device. The GOA circuit uses the existing display array substrate manufacturing process to make the row scanning drive signal circuit on the array substrate, thereby realizing line-by-line scanning.

[0003] Among them, the existing GOA circuit usually adopts a unidirectional scanning mode, and can only select one of forward scanning or reverse scanning. Therefore, in the pull-down circuit of the GOA circuit, it can only be used for pull-down during forward scanning driving or pull-down during reverse scanning driving. Two pull-down circuits need to be set to perform pull-down during forward scanning driving and pull-down during reverse scanning driving, which cannot meet the needs of product diversification.

[0004] Therefore, how to make a pull-down circuit compatible with forward scanning and reverse scanning is a difficult problem that existing panel manufacturers need to work hard to overcome. Summary of the invention

[0005] The present application provides a pull-down circuit, a GOA circuit, a driving method thereof and a display panel, which can solve the technical problem of how to make a pull-down circuit compatible with forward scanning and reverse scanning.

[0006] In a first aspect, the present application provides a pull-down circuit, comprising:

[0007] A positive scan pull-down module, the positive scan pull-down module is connected to a reference low level signal and is electrically connected to an n-th level scan signal output terminal, an (n+m)-th level scan signal output terminal and a first control terminal, the positive scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal to the potential of the reference low level signal under the control of a signal connected to the first control terminal and a signal output from the (n+m)-th level scan signal output terminal during positive scan driving;

[0008] A reverse scan pull-down module, the reverse scan pull-down module is connected to the reference low level signal and is electrically connected to the nth level scan signal output terminal, the (nm)th level scan signal output terminal and the second control terminal. The reverse scan pull-down module is used to pull down the potential of the nth level scan signal output terminal to the potential of the reference low level signal under the control of the signal connected to the second control terminal and the signal output from the (nm)th level scan signal output terminal during reverse scan driving; wherein n and m are both positive integers, and n is greater than m.

[0009] In the pull-down circuit described in the present application, the positive-scan pull-down module includes a first transistor, and the reverse-scan pull-down module includes a second transistor;

[0010] The gate of the first transistor is electrically connected to the first control terminal, and the gate of the second transistor is electrically connected to the second control terminal.

[0011] In the pull-down circuit described in the present application, one of the first transistor and the second transistor is an N-type transistor, the other of the first transistor and the second transistor is a P-type transistor, and the phases of the signals connected to the first control terminal and the second control terminal are the same.

[0012] In the pull-down circuit described in the present application, the first transistor and the second transistor are both N-type transistors or P-type transistors, and the phase of the signal connected to the first control terminal is opposite to that of the signal connected to the second control terminal.

[0013] In the pull-down circuit described in the present application, the forward-scanning pull-down module further includes a third transistor, and the reverse-scanning pull-down module further includes a fourth transistor;

[0014] The gate of the third transistor is electrically connected to the (n+m)th level scanning signal output terminal, and the gate of the fourth transistor is electrically connected to the (nm)th level scanning signal output terminal.

[0015] In the pull-down circuit described in the present application, the first electrode of the first transistor and the first electrode of the second transistor are both connected to the reference low-level signal, the second electrode of the first transistor is electrically connected to the first electrode of the third transistor, the second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor, and the second electrode of the third transistor and the second electrode of the fourth transistor are both electrically connected to the n-th level scan signal output terminal.

[0016] In the pull-down circuit described in the present application, the first electrode of the first transistor and the first electrode of the second transistor are both electrically connected to the nth level scan signal output terminal, the second electrode of the first transistor is electrically connected to the first electrode of the third transistor, the second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor, and the second electrode of the third transistor and the second electrode of the fourth transistor are both connected to the reference low level signal.

[0017] In a second aspect, the present application further provides a GOA circuit, comprising a multi-stage cascaded gate driving unit, wherein the gate driving unit comprises the pull-down circuit as described above.

[0018] In a third aspect, the present application further provides a driving method of the GOA circuit as described above, the driving method comprising:

[0019] When the GOA circuit adopts forward scanning drive, the forward scanning pull-down module pulls down the potential of the n-th level scanning signal output terminal to the potential of the reference low-level signal under the control of the signal connected to the first control terminal and the signal output from the (n+m)-th level scanning signal output terminal;

[0020] When the GOA circuit adopts reverse scanning drive, the reverse scanning pull-down module pulls down the potential of the nth level scanning signal output terminal to the potential of the reference low level signal under the control of the signal connected to the second control terminal and the signal output from the (nm)th level scanning signal output terminal.

[0021] In a fourth aspect, the present application also provides a display panel, comprising the GOA circuit as described above.

[0022] In the pull-down circuit, GOA circuit, driving method of the GOA circuit and display panel provided in the present application,

[0023] The pull-down circuit includes a forward scan pull-down module and a reverse scan pull-down module. The forward scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal when the forward scan is driven, and the reverse scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal when the reverse scan is driven. The pull-down circuit provided in the embodiment of the present application is compatible with forward scan and reverse scan, meeting the application scenario of the same screen being compatible with forward mounting and reverse mounting, thereby meeting the needs of product diversification. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a first structural schematic diagram of the pull-down circuit provided in an embodiment of the present application.

[0025] Figure 2 A second structural schematic diagram of the pull-down circuit provided in an embodiment of the present application.

[0026] Figure 3 A third structural schematic diagram of the pull-down circuit provided in an embodiment of the present application.

[0027] Figure 4 This is a fourth structural schematic diagram of the pull-down circuit provided in an embodiment of the present application.

[0028] Figure 5 A first circuit diagram of a pull-down circuit provided in an embodiment of the present application.

[0029] Figure 6 A second circuit diagram of the pull-down circuit provided in an embodiment of the present application.

[0030] Figure 7 This is a first positive scan timing diagram of the pull-down circuit provided in an embodiment of the present application.

[0031] Figure 8 This is a first reverse scan timing diagram of the pull-down circuit provided in an embodiment of the present application.

[0032] Fig. 9 A third circuit diagram of the pull-down circuit provided in an embodiment of the present application.

[0033] Fig.10 This is a fourth circuit diagram of the pull-down circuit provided in an embodiment of the present application.

[0034] Fig.11 This is a second positive scan timing diagram of the pull-down circuit provided in an embodiment of the present application.

[0035] Fig.12 This is a second reverse scan timing diagram of the pull-down circuit provided in an embodiment of the present application.

[0036] Fig.13 This is a fifth circuit diagram of the pull-down circuit provided in an embodiment of the present application.

[0037] Fig.14 This is a sixth circuit diagram of the pull-down circuit provided in an embodiment of the present application.

[0038] Fig.15 This is the third positive scan timing diagram of the pull-down circuit provided in an embodiment of the present application.

[0039] Fig.16 This is a third reverse scan timing diagram of the pull-down circuit provided in an embodiment of the present application.

[0040] Fig.17 A schematic diagram of the structure of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0042] In addition, the terms "first", "second", etc. in the specification and claims of this application are used to distinguish different objects rather than to describe a specific order. The terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. Since the source and drain of the transistor used in this application are symmetrical, their source and drain are interchangeable. According to the form in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end is the source, and the output end is the drain.

[0043] See also Figure 1 , Figure 1 This is a first structural diagram of the pull-down circuit provided in the embodiment of the present application. Figure 1 As shown, the pull-down circuit 10 provided in the embodiment of the present application includes a forward-scanning pull-down module 101 and a reverse-scanning pull-down module 102 .

[0044] The forward scan pull-down module 101 is connected to the reference low level signal VGL, and is electrically connected to the nth level scan signal output terminal Gn, the (n+m)th level scan signal output terminal G(n+m), and the first control terminal switch1. The downward scan pull-down module 102 is connected to the reference low level signal VGL, and is electrically connected to the nth level scan signal output terminal Gn, the (nm)th level scan signal output terminal G(nm), and the second control terminal switch2.

[0045] Specifically, the forward scan pull-down module 101 is used to pull down the potential of the n-th level scan signal output terminal Gn to the potential of the reference low level signal VGL under the control of the signal connected to the first control terminal switch1 and the signal output from the (n+m)-th level scan signal output terminal G(n+m) during the forward scan process. The reverse scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal Gn to the potential of the reference low level signal VGL under the control of the signal connected to the second control terminal switch2 and the signal output from the (nm)-th level scan signal output terminal G(nm) during the reverse scan process.

[0046] It should be noted that n and m are positive constants, and n is greater than m. Specifically, m can be 1, 2, 3 or 4.

[0047] It should be noted that the pull-down circuit 10 provided in the embodiment of the present application is compatible with forward scanning and reverse scanning, meeting the application scenario of the same screen being compatible with forward mounting and reverse mounting, thereby meeting the needs of product diversification.

[0048] It should be noted that the pull-down circuit 10 provided in the embodiment of the present application can be integrated into the display panel surface, so as to improve the uniformity of the output signal, avoid the pixel kick-back voltage difference caused by the output signal difference, and expand the reference voltage difference within the surface, thereby improving the display effect of the display panel.

[0049] It should be noted that the potential of the reference low-level signal VGL may be the potential of the ground terminal. Of course, it is understandable that the potential of the reference low-level signal VGL may also be other potentials.

[0050] Please visit Figure 2 , Figure 2 This is a second structural diagram of the pull-down circuit provided in the embodiment of the present application. Figure 2 As shown, the forward scanning pull-down module 101 includes a first transistor T1. The reverse scanning pull-down module 102 includes a second transistor T2. The gate of the first transistor T1 is electrically connected to the first control terminal switch1. The gate of the second transistor T2 is electrically connected to the second control terminal switch2.

[0051] One of the first transistor T1 and the second transistor T2 is an N-type transistor, the other of the first transistor T1 and the second transistor T2 is a P-type transistor, and the phases of the signals connected to the first control terminal switch1 and the second control terminal switch2 are the same.

[0052] In the pull-down circuit 10 provided in the embodiment of the present application, the phases of the signals connected to the first control terminal switch1 and the second control terminal switch2 are the same, that is, the first control terminal switch1 and the second control terminal switch2 are connected to the same control signal. In other words, the first control terminal switch1 and the second control terminal switch2 are the same control terminal switch.

[0053] It should be noted that when the potential of the control terminal switch is at a high level, the first transistor T1 is turned on and the second transistor T2 is turned off; when the potential of the control terminal switch is at a low level, the first transistor T1 is turned off and the second transistor T2 is turned on. Therefore, in the pull-down circuit 10 provided in the embodiment of the present application, only one control signal is set to realize the pull-down circuit 10 to pull down the potential of the n-th level scanning signal output terminal Gn in the forward scanning stage and the reverse scanning stage, thereby reducing the number of control signals and the number of wirings, which is beneficial to improving the display effect of the display panel and the realization of a narrow frame, and is more conducive to the realization of a large-size and high-resolution display panel, and can also play a role in improving the aperture ratio of the display panel.

[0054] Please visit Figure 3 , Figure 3 This is a third structural diagram of the pull-down circuit provided in the embodiment of the present application. Figure 3 As shown, Figure 3 The pull-down circuit 10 shown is Figure 2 The difference of the pull-down circuit 10 shown is that the first transistor T1 and the second transistor T2 are both N-type transistors or P-type transistors, and the phases of the signals connected to the first control terminal switch1 and the second control terminal switch2 are opposite.

[0055] It should be noted that the signals connected to the first control terminal switch1 and the second control terminal switch2 are different, which is beneficial to avoid mutual interference between the signals connected to the control terminals in the forward scanning stage and the reverse scanning stage, and avoid problems in one control terminal, resulting in malfunction of the forward scanning stage and the reverse scanning stage.

[0056] Please visit Figure 4 , Figure 4 This is a fourth structural diagram of the pull-down circuit provided in the embodiment of the present application. Figure 4 As shown, Figure 4 The pull-down circuit 10 shown and Figure 2 The difference of the pull-down circuit 10 shown is that the forward scanning pull-down module 101 further includes a third transistor T3, and the reverse scanning pull-down module 102 further includes a fourth transistor T4. The gate of the third transistor T3 is electrically connected to the (n+m)th level scanning signal output terminal G(n+m), and the gate of the third transistor T3 is electrically connected to the (nm)th level scanning signal output terminal G(nm).

[0057] In the pull-down circuit 10 provided in the embodiment of the present application, in the forward scanning process, the first transistor T1 and the third transistor T3 are used to jointly control the pull-down of the (n)-th level scanning signal output terminal G(n). In the reverse scanning process, the second transistor T2 and the fourth transistor T4 are used to jointly control the pull-down of the (n)-th level scanning signal output terminal G(n).

[0058] The first transistor T1 , the third transistor T3 , and the fourth transistor T4 are all N-type transistors or P-type transistors, thereby avoiding the influence of differences between different types of transistors on the pull-down circuit 10 .

[0059] It should be noted that the first transistor T1 , the second transistor T2 , the third transistor T3 and the fourth transistor T4 may be one or more of a low-temperature polysilicon thin film transistor, an oxide semiconductor thin film transistor or an amorphous silicon thin film transistor.

[0060] Please visit Figure 6 , Figure 6 A second circuit diagram of a pull-down circuit provided in an embodiment of the present application. Figure 4 , Figure 6 As shown, the first electrode of the first transistor T1 and the first electrode of the second transistor T2 are both electrically connected to the nth level scanning signal output terminal G(n), the second electrode of the first transistor T1 is electrically connected to the first electrode of the third transistor T3, the second electrode of the second transistor T2 is electrically connected to the first electrode of the fourth transistor T4, and the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 are both connected to the reference low level signal VGL.

[0061] Among them, in the pull-down circuit 10 provided by the embodiment of the present application, in the forward scanning stage, when the forward scanning pull-down module 101 is used to pull down the potential of the n-th level scanning signal output terminal G(n), the fourth transistor T4 in the reverse scanning pull-down module 102 is not directly connected to the n-th level scanning signal output terminal G(n), and they are separated by the second transistor T2. Therefore, the disturbance and jump of the output signal of the nm-th level scanning signal output terminal G(nm) connected to the gate of the fourth transistor T4 will not affect the potential of the n-th level scanning signal output terminal G(n), and the signal output by the n-th level scanning signal output terminal G(n) will not be distorted or attenuated due to signal noise.

[0062] Similarly, in the reverse scanning stage, when the reverse scanning pull-down module 102 is used to pull down the potential of the n-th level scanning signal output terminal G(n), the third transistor T3 in the forward scanning pull-down module 101 is not directly connected to the n-th level scanning signal output terminal G(n), and they are separated by the first transistor T1. Therefore, the disturbance and jump of the output signal of the nm-th level scanning signal output terminal G(nm) connected to the gate of the third transistor T3 will not affect the potential of the n-th level scanning signal output terminal G(n), and the signal output by the n-th level scanning signal output terminal G(n) will not be distorted or attenuated due to signal noise.

[0063] Please visit Figure 5 , Figure 5The first circuit diagram of the pull-down circuit provided in the embodiment of the present application is shown in FIG. Figure 4 , Figure 5 As shown, the first electrode of the first transistor T1 and the first electrode of the second transistor T2 are both connected to the reference low-level signal VGL, the second electrode of the first transistor T1 is electrically connected to the first electrode of the third transistor T3, the second electrode of the second transistor T2 is electrically connected to the first electrode of the fourth transistor T4, and the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4 are both electrically connected to the n-th level scanning signal output terminal G(n).

[0064] See also Figure 7 , Figure 7 This is the first positive scan timing diagram of the pull-down circuit provided in the embodiment of the present application. Figure 7 As shown, the falling edge of the output signal of the (nm)th level scanning signal output terminal G(nm) is aligned with the rising edge of the output signal of the nth level scanning signal output terminal G(n), and the falling edge of the output signal of the nth level scanning signal output terminal G(n) is aligned with the rising edge of the output signal of the (n+m)th level scanning signal output terminal G(n+m).

[0065] In the positive scanning stage, the potential of the control terminal switch is at a high level, so the first transistor T1 is in a normally open state and the second transistor T2 is in a normally closed state. When the potential of the (n+m)th level scanning signal output terminal G(n+m) changes from a low potential to a high potential, the third transistor T3 is turned on, and the potential of the nth level scanning signal output terminal G(n) is pulled down to the potential of the reference low level signal VGL.

[0066] It should be noted that the pull-down circuit provided in the embodiment of the present application can quickly pull down the potential of the output signal of the n-th level scanning signal output terminal G(n), thereby reducing the scanning signal load, improving the deterioration of the output signal falling edge, avoiding pixel misshooting and charging time reduction, thereby improving the display effect of the display panel, and is more conducive to the realization of large-size and high-resolution display panels.

[0067] See also Figure 8 , Figure 8 This is a first reverse scan timing diagram of the pull-down circuit provided in the embodiment of the present application. Figure 8 As shown, the falling edge of the output signal of the (n+m)th level scanning signal output terminal G(n+m) is aligned with the rising edge of the output signal of the nth level scanning signal output terminal G(n), and the falling edge of the output signal of the nth level scanning signal output terminal G(n) is aligned with the rising edge of the output signal of the (nm)th level scanning signal output terminal G(nm).

[0068] In the reverse scanning stage, the potential of the control terminal switch is at a low level, so the first transistor T1 is in a normally closed state and the second transistor T2 is in a normally open state. When the potential of the (nm)-th level scanning signal output terminal G(nm) changes from a low potential to a high potential, the fourth transistor T4 is turned on, and the potential of the n-th level scanning signal output terminal G(n) is pulled down to the potential of the reference low level signal VGL.

[0069] It should be noted that the pull-down circuit provided in the embodiment of the present application can quickly pull down the potential of the output signal of the n-th level scanning signal output terminal G(n), thereby reducing the scanning signal load, improving the deterioration of the output signal falling edge, avoiding pixel misshooting and charging time reduction, thereby improving the display effect of the display panel, and is more conducive to the realization of large-size and high-resolution display panels.

[0070] Among them, see Figure 9-Figure 16 . Figure 9-Figure 16 Schematic diagram of an embodiment of output signals of different previous stages.

[0071] Specifically, Fig. 9 A third circuit diagram of the pull-down circuit provided in an embodiment of the present application. Fig.10 This is a fourth circuit diagram of the pull-down circuit provided in an embodiment of the present application. Fig.11 This is a second positive scan timing diagram of the pull-down circuit provided in an embodiment of the present application. Fig.12 This is a second reverse scan timing diagram of the pull-down circuit provided in an embodiment of the present application.

[0072] Among them, Figure 6-Figure 9 As shown, m is 1. At this time, in the forward scanning stage, the falling edge of the output signal of the (n-1)th level scanning signal output terminal G(n-1) is aligned with the rising edge of the output signal of the nth level scanning signal output terminal G(n), and the falling edge of the output signal of the nth level scanning signal output terminal G(n) is aligned with the rising edge of the output signal of the (n+1)th level scanning signal output terminal G(n+1). In the reverse scanning stage, the falling edge of the output signal of the (n+1)th level scanning signal output terminal G(n+1) is aligned with the rising edge of the output signal of the nth level scanning signal output terminal G(n), and the falling edge of the output signal of the nth level scanning signal output terminal G(n) is aligned with the rising edge of the output signal of the (n-1)th level scanning signal output terminal G(n-1).

[0073] Specifically, Fig.13 This is a fifth circuit diagram of the pull-down circuit provided in an embodiment of the present application. Fig.14 This is a sixth circuit diagram of the pull-down circuit provided in an embodiment of the present application. Fig.15 This is the third positive scan timing diagram of the pull-down circuit provided in an embodiment of the present application. Fig.16 This is a third reverse scan timing diagram of the pull-down circuit provided in an embodiment of the present application.

[0074] Among them, Figure 13-Figure 16 As shown, m is 2. At this time, in the forward scanning stage, the falling edge of the output signal of the (n-2)th level scanning signal output terminal G (n-2) is aligned with the rising edge of the output signal of the nth level scanning signal output terminal G (n), and the falling edge of the output signal of the nth level scanning signal output terminal G (n) is aligned with the rising edge of the output signal of the (n+2)th level scanning signal output terminal G (n+2). In the reverse scanning stage, the falling edge of the output signal of the (n+2)th level scanning signal output terminal G (n+2) is aligned with the rising edge of the output signal of the nth level scanning signal output terminal G (n), and the falling edge of the output signal of the nth level scanning signal output terminal G (n) is aligned with the rising edge of the output signal of the (n-2)th level scanning signal output terminal G (n-2).

[0075] In the pull-down circuit provided in the embodiment of the present application, the pull-down circuit includes a forward scan pull-down module and a reverse scan pull-down module. The forward scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal during forward scan driving, and the reverse scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal during reverse scan driving. The pull-down circuit provided in the embodiment of the present application is compatible with forward scan and reverse scan, meeting the application scenario of the same screen being compatible with forward mounting and reverse mounting, thereby meeting the needs of product diversification.

[0076] The embodiment of the present application further provides a GOA circuit, the GOA circuit includes a multi-stage cascaded gate driving unit, and the gate driving unit includes the pull-down circuit 10 as described above.

[0077] The embodiment of the present application also provides a driving method of a GOA circuit, the driving method comprising:

[0078] When the GOA circuit adopts forward scanning drive, the forward scanning pull-down module pulls down the potential of the n-th level scanning signal output terminal to the potential of the reference low-level signal under the control of the signal connected to the first control terminal and the signal output from the (n+m)-th level scanning signal output terminal;

[0079] When the GOA circuit adopts reverse scanning drive, the reverse scanning pull-down module pulls down the potential of the nth level scanning signal output terminal to the potential of the reference low level signal under the control of the signal connected to the second control terminal and the signal output from the (nm)th level scanning signal output terminal.

[0080] See also Fig.17 , Fig.17 The present invention also provides a display panel 200, comprising a plurality of pixel units 2000 arranged in an array, each pixel unit 2000 comprising the pull-down circuit 10 described above, and the details can be referred to the above description of the pull-down circuit 10, which will not be described here.

[0081] The pull-down circuit 10 is integrated into the display panel 200 , thereby reducing the influence of the left and right frames of the pull-down circuit 10 , facilitating the realization of a narrow frame, and providing a basis for realizing a higher resolution of the display panel 200 .

[0082] In the display panel provided in the embodiment of the present application, the pull-down circuit includes a forward scan pull-down module and a reverse scan pull-down module. The forward scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal during forward scan driving, and the reverse scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal during reverse scan driving. The pull-down circuit provided in the embodiment of the present application is compatible with forward scan and reverse scan, meeting the application scenario of the same screen being compatible with forward mounting and reverse mounting, thereby meeting the needs of product diversification.

[0083] The above is a detailed introduction to a pull-down circuit, a GOA circuit, a driving method of a GOA circuit and a display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for technical personnel in this field, according to the ideas of the present application, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A pull-down circuit, characterized in that: include: A positive scan pull-down module, the positive scan pull-down module is connected to a reference low level signal and is electrically connected to an n-th level scan signal output terminal, an (n+m)-th level scan signal output terminal and a first control terminal, the positive scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal to the potential of the reference low level signal under the control of a signal connected to the first control terminal and a signal output from the (n+m)-th level scan signal output terminal during positive scan driving; A reverse scan pull-down module, the reverse scan pull-down module is connected to the reference low level signal and is electrically connected to the n-th level scan signal output terminal, the (nm)-th level scan signal output terminal and the second control terminal, and the reverse scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal to the potential of the reference low level signal under the control of the signal connected to the second control terminal and the signal output from the (nm)-th level scan signal output terminal during reverse scan driving; wherein n and m are both positive integers, and n is greater than m; The forward scanning pull-down module includes a first transistor, and the reverse scanning pull-down module includes a second transistor; The gate of the first transistor is electrically connected to the first control terminal, and the gate of the second transistor is electrically connected to the second control terminal; One of the first transistor and the second transistor is an N-type transistor, the other of the first transistor and the second transistor is a P-type transistor, and the phases of the signals connected to the first control terminal and the second control terminal are the same; The forward scanning pull-down module further includes a third transistor, and the reverse scanning pull-down module further includes a fourth transistor; The gate of the third transistor is electrically connected to the (n+m)th level scanning signal output terminal, and the gate of the fourth transistor is electrically connected to the (nm)th level scanning signal output terminal; The first electrode of the first transistor and the first electrode of the second transistor are both connected to the reference low-level signal, the second electrode of the first transistor is electrically connected to the first electrode of the third transistor, the second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor, and the second electrode of the third transistor and the second electrode of the fourth transistor are both electrically connected to the nth-level scanning signal output terminal.

2. A pull-down circuit, characterized in that: include: A positive scan pull-down module, the positive scan pull-down module is connected to a reference low level signal and is electrically connected to an n-th level scan signal output terminal, an (n+m)-th level scan signal output terminal and a first control terminal, the positive scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal to the potential of the reference low level signal under the control of a signal connected to the first control terminal and a signal output from the (n+m)-th level scan signal output terminal during positive scan driving; A reverse scan pull-down module, the reverse scan pull-down module is connected to the reference low level signal and is electrically connected to the n-th level scan signal output terminal, the (nm)-th level scan signal output terminal and the second control terminal, and the reverse scan pull-down module is used to pull down the potential of the n-th level scan signal output terminal to the potential of the reference low level signal under the control of the signal connected to the second control terminal and the signal output from the (nm)-th level scan signal output terminal during reverse scan driving; wherein n and m are both positive integers, and n is greater than m; The forward scanning pull-down module includes a first transistor, and the reverse scanning pull-down module includes a second transistor; The gate of the first transistor is electrically connected to the first control terminal, and the gate of the second transistor is electrically connected to the second control terminal; One of the first transistor and the second transistor is an N-type transistor, the other of the first transistor and the second transistor is a P-type transistor, and the phases of the signals connected to the first control terminal and the second control terminal are the same; The forward scanning pull-down module further includes a third transistor, and the reverse scanning pull-down module further includes a fourth transistor; The gate of the third transistor is electrically connected to the (n+m)th level scanning signal output terminal, and the gate of the fourth transistor is electrically connected to the (nm)th level scanning signal output terminal; The first electrode of the first transistor and the first electrode of the second transistor are both electrically connected to the nth level scan signal output terminal, the second electrode of the first transistor is electrically connected to the first electrode of the third transistor, the second electrode of the second transistor is electrically connected to the first electrode of the fourth transistor, and the second electrode of the third transistor and the second electrode of the fourth transistor are both connected to the reference low level signal.

3. A GOA circuit, characterized in that: A gate driving unit is provided, wherein the gate driving unit comprises a pull-down circuit as claimed in any one of claims 1 to 2.

4. A driving method of the GOA circuit as claimed in claim 3, characterized in that: The driving method comprises: When the GOA circuit adopts forward scanning drive, the forward scanning pull-down module pulls down the potential of the n-th level scanning signal output terminal to the potential of the reference low-level signal under the control of the signal connected to the first control terminal and the signal output from the (n+m)-th level scanning signal output terminal; When the GOA circuit adopts reverse scanning drive, the reverse scanning pull-down module pulls down the potential of the nth level scanning signal output terminal to the potential of the reference low level signal under the control of the signal connected to the second control terminal and the signal output from the (nm)th level scanning signal output terminal.

5. A display panel, characterized in that: Comprising the GOA circuit as claimed in claim 3.

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