Display panel and driving method thereof, and display device

Abstract

The embodiments of the present disclosure provide a display panel and a driving method thereof, and a display device, which relate to the field of display technology and are used to solve the technical problem of flickering and drifting when the display panel is turned on in the related technology. The display panel includes a driving circuit, a first switching circuit and a second switching circuit, the first switching circuit is coupled to the scanning signal line, the first voltage terminal and the second voltage terminal; the second switching circuit is coupled to the data signal line, the third voltage terminal and the ground terminal. The first switching circuit transmits the voltage from the second voltage terminal to the scanning signal line; the writing subcircuit transmits the voltage of the first plate of the storage capacitor to the data signal line; the second switching circuit transmits the voltage from the data signal line to the ground terminal; so that the voltage of the first plate of the storage capacitor is transmitted to the ground terminal, thereby eliminating the charge in the storage capacitor, and avoiding the phenomenon of flickering and drifting when the display panel is turned on. The above-mentioned display panel is used to display images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] Currently, liquid crystal displays have been widely used in people's lives, and with the development of display technology, people's requirements for the images displayed by liquid crystal displays are getting higher and higher.

[0003] The liquid crystal display comprises a display panel, and the display panel comprises a plurality of drive circuits arranged in an array, wherein the drive circuits in the same row are connected to the same scan signal line, and the drive circuits in the same column are connected to the same data signal line, and each drive circuit is driven by a scan signal provided by the scan signal line and a data signal provided by the data signal line to perform display. However, the related art still has a phenomenon that the display panel flickers when the liquid crystal display is turned on. Summary of the invention

[0004] The purpose of the embodiments of the present disclosure is to provide a display panel and a driving method thereof, and a display device, so as to solve the technical problem of flickering and drifting when the display panel is turned on in the related art.

[0005] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0006] On the one hand, a display panel is provided. The display panel includes a driving circuit, a first switching circuit and a second switching circuit. The driving circuit includes a writing subcircuit and a storage capacitor, and the writing subcircuit is coupled to a scanning signal line, a data signal line and a first plate of the storage capacitor. The first switching circuit is coupled to the scanning signal line, a first voltage terminal and a second voltage terminal; the first switching circuit is configured to: under the control of the first voltage terminal, transmit the voltage from the second voltage terminal to the scanning signal line, so that the writing subcircuit transmits the voltage from the first plate of the storage capacitor to the data signal line under the control of the voltage from the scanning signal line. The second switching circuit is coupled to the data signal line, a third voltage terminal and a ground terminal; the second switching circuit is configured to: under the control of the third voltage terminal, transmit the voltage from the data signal line to the ground terminal.

[0007] The display panel in the above embodiment includes a driving circuit, a first switching circuit and a second switching circuit. The driving circuit includes a writing subcircuit and a storage capacitor. The writing subcircuit is coupled to the scanning signal line, the data signal line and the first plate of the storage capacitor; the first switching circuit is coupled to the scanning signal line, the first voltage terminal and the second voltage terminal; the second switching circuit is coupled to the data signal line, the third voltage terminal and the ground terminal. Through the above configuration, the first switching circuit transmits the voltage from the second voltage terminal to the scanning signal line under the control of the first voltage terminal; the writing subcircuit transmits the voltage from the first plate of the storage capacitor to the data signal line under the control of the voltage from the scanning signal line; the second switching circuit transmits the voltage from the data signal line to the ground terminal under the control of the third voltage terminal; thereby, the voltage of the first plate of the storage capacitor is transmitted to the ground terminal, thereby eliminating the charge in the storage capacitor, and avoiding the display panel from flickering and drifting when it is turned on.

[0008] In some embodiments, the write subcircuit includes a write transistor; the gate of the write transistor is coupled to the scan signal line, the first electrode of the write transistor is coupled to the first plate of the storage capacitor, and the second electrode of the write transistor is coupled to the data signal line; the second plate of the storage capacitor is coupled to the common electrode terminal.

[0009] In some embodiments, the first switching circuit includes a first transistor; a gate of the first transistor is coupled to the first voltage terminal, a first electrode of the first transistor is coupled to the second voltage terminal, and a second electrode of the first transistor is coupled to the scan signal line.

[0010] In some embodiments, the second switch circuit includes a second transistor; a gate of the second transistor is coupled to the third voltage terminal, a first electrode of the second transistor is coupled to the data signal line, and a second electrode of the second transistor is coupled to the ground terminal.

[0011] In some embodiments, the second voltage terminal and the first voltage terminal are the same signal terminal.

[0012] In some embodiments, the third voltage terminal and the first voltage terminal are the same signal terminal.

[0013] In some embodiments, the display panel includes a display area and a peripheral area, and the display area is adjacent to the peripheral area; the number of the driving circuits is multiple and located in the display area, and the multiple driving circuits are arranged in multiple rows and columns; wherein the number of the first switching circuits is multiple and located in the peripheral area; the number of the scanning signal lines is multiple, and one scanning signal line is coupled to one first switching circuit and one row of the sub-pixels; and / or the number of the second switching circuits is multiple and located in the peripheral area; the number of the data signal lines is multiple, and one data signal line is coupled to one second switching circuit and a column of the sub-pixels.

[0014] In some embodiments, it also includes: a timing controller configured to input a first signal; a level converter coupled to the timing controller and the first voltage terminal; the level converter is configured to convert the first signal into a voltage of a valid level and provide it to the first voltage terminal.

[0015] In some embodiments, the driving circuit further includes: a liquid crystal capacitor and a resistor. The first plate of the liquid crystal capacitor is coupled to the first plate of the storage capacitor, and the second plate of the liquid crystal capacitor is coupled to the second plate of the storage capacitor; the first end of the resistor is coupled to the first plate of the liquid crystal capacitor, and the second end of the resistor is coupled to the second plate of the liquid crystal capacitor.

[0016] In another aspect, a display device is provided, comprising a backlight module and a display panel as in any of the above embodiments. The backlight module is located at one side of the display panel.

[0017] On the other hand, a method for driving a display panel is provided, wherein the display panel includes: a driving circuit, a first switching circuit, and a second switching circuit. The driving circuit includes a writing subcircuit and a storage capacitor, wherein the writing subcircuit is coupled to a scanning signal line, a data signal line, and a first plate of the storage capacitor; the first switching circuit is coupled to the scanning signal line, a first voltage terminal, and a second voltage terminal; the second switching circuit is coupled to the data signal line, a third voltage terminal, and a ground terminal. The driving method includes: the first switching circuit, under the control of the first voltage terminal, transmits the voltage from the second voltage terminal to the scanning signal line, so that the writing subcircuit, under the control of the voltage from the scanning signal line, transmits the voltage from the first plate of the storage capacitor to the data signal line; the second switching circuit, under the control of the third voltage terminal, transmits the voltage from the data signal line to the ground terminal.

[0018] In some embodiments, the display panel also includes: a timing controller, a level converter and a gate drive circuit; the level converter is coupled to the timing controller and the first voltage terminal; the gate drive circuit is coupled to the level converter and the scan signal line; the driving method includes: the timing controller inputs a first signal and a reset signal, and the reset signal is input after the first signal; the level converter performs level conversion on the voltage from the first signal and provides it to the first voltage terminal, and performs level conversion on the voltage from the reset signal and provides it to the gate drive circuit; the gate drive circuit resets the scan signal line under the control of the reset signal.

[0019] The above-mentioned display device and driving method of the display panel have the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0021] Figure 1 is a structural diagram of a display device according to some embodiments;

[0022] Figure 2 The structure of the display panel according to some embodiments Figure 1 ;

[0023] Figure 3 is a structural diagram of a driving circuit according to some embodiments;

[0024] Figure 4 The structure of the display panel according to some embodiments Figure 2 ;

[0025] Figure 5 is a timing diagram of output signals of a timing controller according to some embodiments;

[0026] Figure 6 is a flow chart of a method for driving a display panel according to some embodiments;

[0027] Figure 7 A flow chart of inputting a first signal in a method for driving a display panel according to some embodiments;

[0028] Figure 8 The present invention is a flow chart of inputting a reset signal in a method for driving a display panel according to some embodiments. DETAILED DESCRIPTION

[0029] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0030] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "examples" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0031] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0032] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0033] In the circuit structure (e.g., pixel driving circuit) provided in the embodiments of the present disclosure, the transistors used in the circuit structure may be thin film transistors (TFT), field effect transistors (MOS), or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0034] In the circuit structure provided in the embodiment of the present disclosure, the first pole of each transistor used is one of the source and the drain, and the second pole of each transistor is the other of the source and the drain. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure, that is, the first pole and the second pole of the transistor in the embodiment of the present disclosure can be indistinguishable in structure. Exemplarily, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source, and the second pole is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain, and the second pole is the source.

[0035] In the circuit structure provided by the embodiments of the present disclosure, nodes such as test nodes do not represent actual existing components, but represent the junction points of related couplings in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related couplings in the circuit diagram.

[0036] The transistors included in the circuit structure provided in the embodiments of the present disclosure may all be N-type transistors, or may all be P-type transistors, or a portion may be N-type transistors and the other portion may be P-type transistors. In the present disclosure, "effective level" refers to a level that enables a transistor to be turned on. Among them, a P-type transistor can be turned on under the control of a low-level signal, and an N-type transistor can be turned on under the control of a high-level signal.

[0037] In the following, a schematic description is given by taking the case where all transistors included in the circuit structure provided in the embodiment of the present disclosure are P-type transistors as an example.

[0038] In the present disclosure, a P-type transistor may be turned on under the control of a low-level signal, and an N-type transistor may be turned on under the control of a high-level signal.

[0039] Figure 1 FIG. 1 is a structural diagram of a display device 100 according to some embodiments. Figure 1 As shown, a display device 100 in some embodiments of the present disclosure includes: a display panel 10 and a backlight module (not shown in the figure), wherein the display panel 10 is located on one side of the backlight module. The display device 100 is an LCD (Liquid Crystal Display) display device.

[0040] Exemplarily, the display device 100 further includes a frame, a display driver IC (Integrated Circuit), and other electronic components.

[0041] Exemplarily, the display device 100 described above may be any display device 100 that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device 100 of the embodiments described above may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controls and / or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0042] Figure 2 The structure of the display panel 10 according to some embodiments Figure 1 . Reference Figure 2 Some embodiments of the present disclosure provide a display panel 10 . The display panel 10 may include a display area 11 and a peripheral area 12 . The display area 11 may be adjacent to the peripheral area 12 .

[0043] The display panel 10 includes a driving circuit 21, and the driving circuit 21 may be located in the display area 11. Exemplarily, there may be a plurality of driving circuits 21, and the plurality of driving circuits 21 may be arranged in a plurality of rows and columns.

[0044] The display panel 10 includes scanning signal lines Vg and data signal lines Vs, wherein the number of scanning signal lines Vg can be multiple, and the multiple scanning signal lines Vg can be arranged in parallel and spaced apart from each other; the number of data signal lines Vs can be multiple, and the multiple data signal lines Vs can be arranged in parallel and spaced apart from each other. The scanning signal lines Vg and the data signal lines Vs are arranged crosswise, and the area defined by the scanning signal lines Vg and the data signal lines Vs is a sub-pixel area 31. Exemplarily, the multiple sub-pixel areas 31 are arranged in an array, and each driving circuit 21 corresponds to a sub-pixel area 31. The sub-pixel area 31 may include a red sub-pixel area, a green sub-pixel area, and a blue sub-pixel area. Figure 2As shown, the sub-pixel regions 31 in a column corresponding to each column driving circuit 21 have the same color. For example, the sub-pixel regions 31 corresponding to each row driving circuit 21 may be arranged in the order of red sub-pixel regions, green sub-pixel regions, and blue sub-pixel regions.

[0045] Figure 3 FIG. 2 is a structural diagram of a driving circuit 21 according to some embodiments. Figure 3 Combined with Figure 2 The drive circuit 21 includes a write subcircuit 213, a liquid crystal capacitor Clc, a resistor R1 and a storage capacitor Cs. The write subcircuit 213 is coupled to the scan signal line Vg, the data signal line Vs and the first plate of the storage capacitor Cs. The write subcircuit 213 can also be coupled to the first plate of the liquid crystal capacitor Clc. The write subcircuit 213 can be configured to: under the control of the voltage from the scan signal line Vg, transmit the voltage from the data signal line Vs to the first plate of the storage capacitor Cs; under the control of the voltage from the scan signal line Vg, transmit the voltage from the data signal line Vs to the first plate of the liquid crystal capacitor Clc.

[0046] Exemplarily, the writing sub-circuit 213 may include a writing transistor Tc, a gate of the writing transistor Tc coupled to the scanning signal line Vg, a first electrode of the writing transistor Tc coupled to the first electrode plate of the storage capacitor Cs, and a second electrode of the writing transistor Tc coupled to the data signal line Vs. Figure 2 As shown, the driving circuit 21 also includes a gate driving circuit 22, which is coupled to the scanning signal line Vg. The gate driving circuit 22 is used to provide a scanning signal for the scanning signal line Vg. The scanning signal line Vg transmits the scanning signal to the gate of the write transistor Tc to control the conduction or closing of the write transistor Tc.

[0047] like Figure 3 As shown, the first plate of the liquid crystal capacitor Clc can be coupled to the first plate of the storage capacitor Cs, and the second plate of the liquid crystal capacitor Clc is coupled to the second plate of the storage capacitor Cs; the first plate of the storage capacitor Cs is coupled to the first electrode of the write transistor Tc, and the second plate of the storage capacitor Cs is coupled to the common electrode terminal Vcom; the first end of the resistor R1 is coupled to the first plate of the liquid crystal capacitor Clc, and the second end of the resistor R1 is coupled to the second plate of the liquid crystal capacitor Clc. In some embodiments, the storage capacitor Cs includes a first plate, a second plate, and an insulating layer and a passivation layer sandwiched therebetween. In some embodiments, the liquid crystal capacitor Clc may include a first plate, a second plate, and a liquid crystal, wherein the liquid crystal is sandwiched between the first plate and the second plate, the first plate may be coupled to the pixel electrode terminal, and the second plate may be coupled to the common electrode terminal Vcom.

[0048] Through the above settings, under the control of the voltage of the scanning signal line Vg, when the voltage of the gate of the write transistor Tc is greater than the threshold value, the first electrode and the second electrode of the write transistor Tc are turned on, and the voltage of the data signal line Vs is transmitted to the first electrode plate of the liquid crystal capacitor Clc, so that the voltage from the data signal line Vs charges the liquid crystal capacitor Clc. At the same time, the voltage from the data signal line Vs is also transmitted to the first electrode plate of the storage capacitor Cs, so that the voltage from the data signal line Vs charges the storage capacitor Cs. By charging the liquid crystal capacitor Clc, the liquid crystal molecules corresponding to the sub-pixel area 31 can be deflected, so that the sub-pixel area 31 displays the corresponding grayscale. By charging the storage capacitor Cs, the charging voltage of the sub-pixel area 31 can be maintained, so that the display state of the sub-pixel area 31 continues until the next charging. By setting the liquid crystal capacitor Clc and the storage capacitor Cs, when displaying each frame of the picture, the charging voltage of each sub-pixel area 31 can be stably maintained until the next frame of the picture.

[0049] Reference Figure 2 and Figure 3 , the display panel 10 may further include a test transistor T1, and the test transistor T1 may be located in the peripheral area 12. The gate of the test transistor T1 may be coupled to the test signal terminal DS, the first electrode of the test transistor T1 may be coupled to the test node, and the second electrode of the test transistor T1 may be coupled to the data signal line Vs, wherein the test node may be coupled to the ground terminal GND. In some embodiments, the number of the test transistors T1 is multiple, and one data signal line Vs is coupled to one test transistor T1 and one column drive circuit 21. As described in the above embodiment, each column drive circuit 21 corresponds to a column of sub-pixel areas 31 with the same color, and accordingly, the test node may include a red test signal terminal DR, a green test signal terminal DG, and a blue test signal terminal DB, wherein the red test signal terminal DR is coupled to a column drive circuit 21 corresponding to the red sub-pixel area, the green test signal terminal DG is coupled to a column drive circuit 21 corresponding to the green sub-pixel area; the blue test signal terminal DB is coupled to a column drive circuit 21 corresponding to the blue sub-pixel area.

[0050] Through the above arrangement, during the shutdown process of the display panel 10, since the voltage signal provided by the test signal terminal DS is at a high level, the first and second electrodes of the test transistor T1 are turned on, and since the gate drive circuit 22 outputs a scan signal to the drive circuit 21, the write transistor Tc in the drive circuit 21 is turned on, so that the voltage from the first plate of the storage capacitor Cs is transmitted to the test node, and further transmitted to the ground terminal GND, so that the charge in the storage capacitor Cs is eliminated before shutdown, achieving the shutdown discharge effect.

[0051] It is worth noting that, through the above-mentioned setting, after the display panel 10 is turned off each time, some charges will still remain in the storage capacitor Cs. When the display panel 10 is turned on next time, in the process of charging the capacitor of each sub-pixel area 31 to display the picture, the remaining charges in the storage capacitor Cs will cause the positive and negative polarities of the voltages of each pixel electrode to deviate, and this deviation will cause the voltage of the common electrode to deviate from the standard value, causing the display panel 10 to flicker (Flicker) phenomenon, resulting in a decrease in the quality of the picture displayed by the liquid crystal display, and in severe cases, it will also cause discomfort to people.

[0052] Based on this, some embodiments of the present disclosure provide a display panel 10 , which further includes a first switch circuit 23 and a second switch circuit 24 .

[0053] Continue to refer to Figure 2 and Figure 3 , the first switch circuit 23 is coupled to the scan signal line Vg, the first voltage terminal V1 and the second voltage terminal V2; the first switch circuit 23 is configured to: under the control of the first voltage terminal V1, transmit the voltage from the second voltage terminal V2 to the scan signal line Vg, so that the write sub-circuit 213 transmits the voltage from the first plate of the storage capacitor Cs to the data signal line Vs under the control of the voltage from the scan signal line Vg. In some embodiments, the level signal provided by the first voltage terminal V1 and the second voltage terminal V2 can be a high level. After the first switch circuit 23 transmits the high level to the scan signal line Vg, the first and second electrodes of the write transistor Tc in the write sub-circuit 213 are turned on, so that the voltage from the first plate of the storage capacitor Cs is transmitted to the data signal line Vs.

[0054] It is worth noting that, in some embodiments, Figure 2 As shown, there are multiple first switch circuits 23, and they are located in the peripheral area 12. As in the above embodiment, there are multiple scan signal lines Vg, and there are multiple data signal lines Vs. One scan signal line Vg can be coupled to one first switch circuit 23 and one row of driving circuits 21, so that different first switch circuits 23 transmit the voltage from the second voltage terminal V2 to the corresponding scan signal line Vg.

[0055] In some other embodiments, the number of first switch circuits 23 can also be single, and multiple scan signal lines Vg are connected to the same first switch circuit 23, so that the same first switch circuit 23 transmits the voltage from the second voltage terminal V2 to the multiple scan signal lines Vg.

[0056] Continue to refer to Figure 2 and Figure 3, the second switch circuit 24 is coupled to the data signal line Vs, the third voltage terminal V3 and the ground terminal GND; the second switch circuit 24 is configured to: under the control of the third voltage terminal V3, transmit the voltage from the data signal line Vs to the ground terminal GND. In some embodiments, after the write subcircuit 213 transmits the voltage of the first plate of the storage capacitor Cs to the data signal line Vs, the level signal provided by the third voltage terminal V3 can be a high level, and the third switch circuit transmits the voltage from the data signal line Vs to the ground terminal GND, so that the voltage from the first plate of the storage capacitor Cs is transmitted to the ground terminal GND.

[0057] It is worth noting that, in some embodiments, Figure 3 As shown, the number of the second switch circuits 24 is multiple and located in the peripheral area 12. As in the above embodiment, the number of the scan signal lines Vg is multiple, the number of the data signal lines Vs is multiple, and one data signal line Vs can be coupled to one second switch circuit 24 and one column driving circuit 21, so that different second switch circuits 24 transmit the data signal from the data signal line Vs to the ground terminal GND.

[0058] In some other embodiments, the number of second switch circuits 24 can also be single, and multiple data signal lines Vs are connected to the same second switch circuit 24, so that the same second switch circuit 24 transmits the voltages from the multiple data signal lines Vs to the ground terminal GND.

[0059] To sum up, through the above settings, the first switch circuit 23, under the control of the first voltage terminal V1, transmits the voltage from the second voltage terminal V2 to the scanning signal line Vg; the write sub-circuit 213, under the control of the voltage from the scanning signal line Vg, transmits the voltage from the first plate of the storage capacitor Cs to the data signal line Vs; the second switch circuit 24, under the control of the third voltage terminal V3, transmits the voltage from the data signal line Vs to the ground terminal GND; thereby, the voltage from the first plate of the storage capacitor Cs is transmitted to the ground terminal GND, thereby eliminating the charge in the storage capacitor Cs, realizing power-on discharge, and avoiding the display panel 10 from flickering and drifting when it is turned on.

[0060] Reference Figure 2 and Figure 3, the first switch circuit 23 may include a first transistor T2; the gate of the first transistor T2 is coupled to the first voltage terminal V1, the first electrode of the first transistor T2 is coupled to the second voltage terminal V2, and the second electrode of the first transistor T2 is coupled to the scanning signal line Vg. In some embodiments, the level signal provided by the first voltage terminal V1 and the second voltage terminal V2 may be a high level, when the voltage of the gate of the first transistor T2 is greater than the threshold value, the first electrode and the second electrode of the first transistor T2 are turned on, and the voltage of the first electrode of the first transistor T2 is transmitted to the second electrode of the first transistor T2, so that the voltage from the second voltage terminal V2 is transmitted to the scanning signal line Vg.

[0061] In some embodiments, the second voltage terminal V2 and the first voltage terminal V1 can be the same signal terminal DN, that is, the second voltage terminal V2 and the first voltage terminal V1 can receive the same voltage signal, which is beneficial to improving the performance of the first transistor T2. At the same time, it is also beneficial to simplify the wiring in the display panel 10 and simplify the process steps. Of course, in some other embodiments, the second voltage terminal V2 can also be the same signal terminal as the voltage signal terminal (not shown in the figure), and the voltage signal terminal level signal is a high level. When the voltage of the gate of the first transistor T2 is greater than the threshold value, the first electrode and the second electrode of the first transistor T2 are turned on.

[0062] Reference Figure 2 and Figure 3 , the second switch circuit 24 may include a second transistor T3; the gate of the second transistor T3 is coupled to the third voltage terminal V3, the first electrode of the second transistor T3 is coupled to the data signal line Vs, and the second electrode of the second transistor T3 is coupled to the ground terminal GND. In some embodiments, the level signal provided by the third voltage terminal V3 may be a high level, and when the voltage of the gate of the second transistor T3 is greater than the threshold value, the first electrode and the second electrode of the second transistor T3 are turned on, and the voltage of the first electrode of the second transistor T3 is transmitted to the second electrode of the first transistor T2, so that the voltage from the data signal line Vs is transmitted to the ground terminal GND.

[0063] In some embodiments, the third voltage terminal V3 and the first voltage terminal V1 are the same signal terminal DN, that is, the third voltage terminal V3 and the first voltage terminal V1 receive the same voltage signal, which is beneficial to improving the performance of the second transistor T3 and simplifying the wiring in the display panel 10 and simplifying the process steps.

[0064] It is worth noting that, in some embodiments, the first transistor T2 is of the same type as the test transistor T1, and / or the second transistor T3 is of the same type as the test transistor T1. For example, the first transistor T2 and the test transistor T1 may both be P-type transistors, and the second transistor T3 may also be a P-type transistor. The above arrangement is conducive to simplifying the manufacturing process of the display panel 10 and improving the manufacturing efficiency of the display panel 10. Furthermore, in some embodiments, the first transistor T2 is of the same size as the test transistor T1, and / or the second transistor T3 is of the same size as the test transistor T1, which is conducive to further simplifying the manufacturing process of the display panel 10 and further improving the manufacturing efficiency of the display panel 10.

[0065] Figure 4 The structure of the display panel 10 according to some embodiments Figure 2 ; Figure 5 is a timing diagram of output signals of the timing controller 41 according to some embodiments.

[0066] Reference Figure 4 and Figure 5 , and combined with Figure 2 The display panel 10 may further include: a timing controller 41, configured to input a first signal X1; a level converter 42, coupled to the timing controller 41 and the first voltage terminal V1; the level converter 42 is configured to: perform level conversion on the voltage from the first signal X1 and provide it to the first voltage terminal V1.

[0067] Exemplarily, the timing controller 41 includes a first pin 411, and the timing controller 41 sends a first signal X1 to the level converter 42 through the first pin 411; after receiving the first signal X1 transmitted from the timing controller 41, the level converter 42 performs a level conversion on the voltage of the first signal X1, converts it to an effective level X1', and transmits the converted effective level X1' to the first voltage terminal V1 to achieve the effect of power-on discharge. In some embodiments, the level converter 42 can pull the voltage of the first signal X1 to a high level, and transmit the high level to the first voltage terminal V1, so that the first electrode and the second electrode of the first transistor T2 are turned on.

[0068] In some embodiments, the level converter 42 is further configured to: perform level conversion on the voltage from the first signal X1 and provide it to the first voltage terminal V1, the second voltage terminal V2 and the third voltage terminal V3. Figure 2 The first voltage terminal V1, the second voltage terminal V2 and the third voltage terminal V3 are all the same signal terminal DN, and all receive the first signal X1. This is beneficial to further simplify the wiring in the display panel 10 and simplify the process steps.

[0069] It is worth noting that in some other embodiments, before shutdown, the timing controller 41 may also input the first signal X1. After receiving the first signal X1 transmitted by the timing controller 41, the level converter 42 performs level conversion on the voltage of the first signal X1, converts it into an effective level X1', and transmits the converted effective level X1' to the first voltage terminal V1, so that the first electrode and the second electrode of the first transistor T2 are turned on, thereby realizing the discharge of the storage capacitor Cs before shutdown.

[0070] Continue to refer to Figure 4 and Figure 5 , and combined with Figure 2 The gate driving circuit 22 can be coupled to the level converter 42 and the scanning signal line Vg; the timing controller 41 is further configured to input a reset signal RST. The level converter 42 is further configured to perform level conversion on the voltage from the reset signal RST and provide it to the gate driving circuit 22. The gate driving circuit 22 is configured to reset the scanning signal line Vg under the control of the reset signal RST.

[0071] Exemplarily, the timing controller 41 further includes a second pin 412, and the timing controller 41 sends a reset signal RST to the level converter 42 through the second pin 412; after receiving the reset signal RST transmitted from the timing controller 41, the level converter 42 performs a level conversion on the voltage of the reset signal RST, converts it to an effective level RST', and transmits the converted effective level RST' to the gate drive circuit 22. In some embodiments, the level converter 42 can pull the voltage of the reset signal RST to a high level, and transmit the high level to the gate drive circuit 22, so that the gate drive circuit 22 resets the scanning signal line Vg.

[0072] It is worth noting that the reset signal RST is input after the first signal X1, so that after power-on, the storage capacitor Cs in the drive circuit 21 is first discharged, and then the scanning signal line Vg is reset, so that the display panel 10 displays the picture, which is conducive to achieving the power-on discharge effect and avoiding the flickering drift of the display panel 10.

[0073] Continue to refer to Figure 4 and Figure 5, the timing controller 41 further includes a third pin 413, and the number of the third pin 413 can be multiple. The timing controller 41 sends a gate line control signal STV and a clock signal CLK to the level converter 42 through the third pin 413, wherein the clock signal CLK may include, for example, CLK1, CLK2, ... CLK10; after receiving the gate line control signal STV and the clock signal CLK transmitted from the timing controller 41, the level converter 42 performs level conversion on the voltage of the gate line control signal STV and the clock signal CLK, converts them to an effective level CLK', and transmits the converted effective level CLK' to the gate drive circuit 22. In some embodiments, the level converter 42 can pull up the voltage of the gate line control signal STV and the clock signal CLK to a high level, and transmit the high level to the gate drive circuit 22, so that the gate drive circuit 22 controls the drive circuit 21 to be turned on or off.

[0074] Some embodiments of the present disclosure further provide a method for driving a display panel, and the driving method is applied to the display panel in any of the above embodiments.

[0075] Please refer to Figure 2 and Figure 3 , the display panel includes: a driving circuit 21, a first switch circuit 23 and a second switch circuit 24. The driving circuit 21 includes a writing sub-circuit 213 and a storage capacitor Cs, the writing sub-circuit 213 is coupled to the scanning signal line Vg, the data signal line Vs and the first plate of the storage capacitor Cs; the first switch circuit 23 is coupled to the scanning signal line Vg, the first voltage terminal V1 and the second voltage terminal V2; the second switch circuit 24 is coupled to the data signal line Vs, the third voltage terminal V3 and the ground terminal GND;

[0076] Figure 6 is a flow chart of a method for driving a display panel according to some embodiments, referring to Figure 6 , the driving method of the display panel includes steps S101 to S102:

[0077] S101, the first switch circuit, under the control of the first voltage terminal, transmits the voltage from the second voltage terminal to the scan signal line, so that the write sub-circuit, under the control of the voltage from the scan signal line, transmits the voltage from the first plate of the storage capacitor to the data signal line.

[0078] S102, the second switch circuit, under the control of the third voltage terminal, transmits the voltage from the data signal line to the ground terminal.

[0079] In summary, in the driving method of the display panel provided by some embodiments of the present disclosure, the first switch circuit 23 transmits the voltage from the second voltage terminal V2 to the scanning signal line Vg under the control of the first voltage terminal V1; the write sub-circuit 213 transmits the voltage from the first plate of the storage capacitor Cs to the data signal line Vs under the control of the voltage from the scanning signal line Vg; the second switch circuit 24 transmits the voltage from the data signal line Vs to the ground terminal GND under the control of the third voltage terminal V3; thereby, the voltage from the first plate of the storage capacitor Cs is transmitted to the ground terminal GND, thereby eliminating the charge in the storage capacitor Cs, realizing power-on discharge, and avoiding the display panel 10 from flickering and drifting when it is turned on.

[0080] Reference Figure 2 , and combined with Figure 4 and Figure 5 The display panel may further include: a timing controller 41, a level converter 42 and a gate driving circuit 22. The level converter 42 is coupled to the timing controller 41 and the first voltage terminal V1; the gate driving circuit 22 is coupled to the level converter 42 and the scanning signal line Vg.

[0081] Figure 7 A flow chart of inputting a first signal in a method for driving a display panel according to some embodiments; Figure 8 The present invention is a flow chart of inputting a reset signal in a method for driving a display panel according to some embodiments.

[0082] Reference Figure 7 The display panel driving method further includes: S201, a timing controller, inputting a first signal. S202, a level converter, performing level conversion on a voltage from the first signal and providing it to a first voltage terminal.

[0083] For example, see Figure 4 The timing controller 41 includes a first pin 411, and the timing controller 41 sends a first signal X1 to the level converter 42 through the first pin 411; after receiving the first signal X1 transmitted from the timing controller 41, the level converter 42 performs level conversion on the voltage of the first signal X1, converts it into a valid level X1', and transmits the converted valid level X1' to the first voltage terminal V1 to achieve the effect of power-on discharge.

[0084] In some embodiments, the level converter 42 also performs level conversion on the voltage from the first signal X1 and provides it to the first voltage terminal V1, the second voltage terminal V2 and the third voltage terminal V3. Figure 2The first voltage terminal V1, the second voltage terminal V2 and the third voltage terminal V3 are all the same signal terminal DN, and all receive the first signal X1. Through the above configuration, the first switch circuit 23 and the second switch circuit 24 are turned on at the same time, achieving the effect of power-on discharge.

[0085] Reference Figure 8 The display panel driving method further includes: S301, a timing controller, inputting a reset signal, the reset signal being input after the first signal. S302, a level converter, converting the level of a voltage from the reset signal and providing it to a gate driving circuit. S303, a gate driving circuit, resetting the scanning signal line under the control of the reset signal.

[0086] For example, see Figure 4 The timing controller 41 also includes a second pin 412, and the timing controller 41 sends a reset signal RST to the level converter 42 through the second pin 412; after the level converter 42 receives the reset signal RST transmitted by the timing controller 41, the voltage of the reset signal RST is level-converted to the effective level RST', and the converted effective level RST' is transmitted to the gate drive circuit 22.

[0087] It is worth noting that the reset signal RST is input after the first signal X1, so that after power-on, the storage capacitor Cs in the drive circuit 21 is first discharged, and then the scanning signal line Vg is reset, so that the display panel 10 displays the picture, which is conducive to achieving the power-on discharge effect and avoiding the flickering drift of the display panel 10.

[0088] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be thought of by any person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display panel, characterized in that: include: A driving circuit, the driving circuit comprising a writing subcircuit and a storage capacitor, the writing subcircuit being coupled to a scanning signal line, a data signal line and a first plate of the storage capacitor; a first switch circuit coupled to the scan signal line, the first voltage terminal and the second voltage terminal; the first switch circuit is configured to: under the control of the first voltage terminal, transmit the voltage from the second voltage terminal to the scan signal line, so that the write sub-circuit, under the control of the voltage from the scan signal line, transmits the voltage from the first plate of the storage capacitor to the data signal line; The second switch circuit is coupled to the data signal line, the third voltage terminal and the ground terminal; the second switch circuit is configured to: under the control of the third voltage terminal, transmit the voltage from the data signal line to the ground terminal.

2. The display panel according to claim 1, characterized in that: The write subcircuit includes a write transistor; The gate of the write transistor is coupled to the scan signal line, the first electrode of the write transistor is coupled to the first plate of the storage capacitor, and the second electrode of the write transistor is coupled to the data signal line; The second plate of the storage capacitor is coupled to the common electrode terminal.

3. The display panel according to claim 2, characterized in that: The first switch circuit includes a first transistor; The gate of the first transistor is coupled to the first voltage terminal, the first electrode of the first transistor is coupled to the second voltage terminal, and the second electrode of the first transistor is coupled to the scan signal line.

4. The display panel according to claim 3, characterized in that: The second switch circuit includes a second transistor; A gate of the second transistor is coupled to the third voltage terminal, a first electrode of the second transistor is coupled to the data signal line, and a second electrode of the second transistor is coupled to the ground terminal.

5. The display panel according to any one of claims 1 to 4, characterized in that: The second voltage terminal and the first voltage terminal are the same signal terminal.

6. The display panel according to any one of claims 1 to 4, characterized in that: The third voltage terminal and the first voltage terminal are the same signal terminal.

7. The display panel according to any one of claims 1 to 4, characterized in that: The display panel comprises a display area and a peripheral area, wherein the display area is adjacent to the peripheral area; There are multiple driving circuits located in the display area, and the multiple driving circuits are arranged in multiple rows and columns; There are a plurality of first switch circuits located in the peripheral area; there are a plurality of scan signal lines, and one scan signal line is coupled to one first switch circuit and one row of drive circuits; And / or, there are multiple second switch circuits located in the peripheral area; there are multiple data signal lines, and one data signal line is coupled to one second switch circuit and one column of the driving circuits.

8. The display panel according to any one of claims 1 to 4, characterized in that: Also includes: A timing controller is configured to input a first signal; A level converter, coupled to the timing controller and the first voltage terminal; The level converter is configured to perform level conversion on a voltage from the first signal and provide the voltage to the first voltage terminal.

9. The display panel according to claim 8, characterized in that: Also includes: A gate driving circuit coupled to the level converter and the scanning signal line; The timing controller is also configured to: input a reset signal, which is input after the first signal; the level converter is also configured to: level convert the voltage from the reset signal and provide it to the gate drive circuit; the gate drive circuit is configured to: reset the scan signal line under the control of the reset signal.

10. The display panel according to any one of claims 1 to 4, characterized in that: The driving circuit further includes: A liquid crystal capacitor, wherein a first electrode plate of the liquid crystal capacitor is coupled to a first electrode plate of the storage capacitor, and a second electrode plate of the liquid crystal capacitor is coupled to a second electrode plate of the storage capacitor; A resistor, wherein a first end of the resistor is coupled to the first electrode plate of the liquid crystal capacitor, and a second end of the resistor is coupled to the second electrode plate of the liquid crystal capacitor.

11. A display device, characterized in that: The display panel according to any one of claims 1 to 10; The backlight module is located on one side of the display panel.

12. A method for driving a display panel, characterized in that: The display panel comprises: a driving circuit, a first switching circuit and a second switching circuit; The driving circuit includes a writing subcircuit and a storage capacitor, wherein the writing subcircuit is coupled to the scanning signal line, the data signal line and the first plate of the storage capacitor; The first switch circuit is coupled to the scan signal line, the first voltage terminal and the second voltage terminal; The second switch circuit is coupled to the data signal line, the third voltage terminal and the ground terminal; The driving method comprises: The first switch circuit, under the control of the first voltage terminal, transmits the voltage from the second voltage terminal to the scan signal line, so that the write subcircuit, under the control of the voltage from the scan signal line, transmits the voltage from the first plate of the storage capacitor to the data signal line; The second switch circuit, under the control of the third voltage terminal, transmits the voltage from the data signal line to the ground terminal.

13. The method for driving a display panel according to claim 12, wherein: The display panel further includes: a timing controller, a level converter and a gate driving circuit; The level converter is coupled to the timing controller and the first voltage terminal; The gate driving circuit is coupled to the level converter and the scanning signal line; The driving method comprises: The timing controller is input with a first signal and a reset signal, and the reset signal is input after the first signal; The level converter performs level conversion on the voltage from the first signal and provides it to the first voltage terminal, and performs level conversion on the voltage from the reset signal and provides it to the gate drive circuit; The gate driving circuit resets the scanning signal line under the control of the reset signal.

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