Word line driver and storage device

Abstract

The disclosed embodiment provides a word line driver and a storage device, the word line driver comprising: a first holding transistor and a second holding transistor; an active region, the active region comprising: a main body extending along a first direction and a protrusion adjacent to a part of the main body and located on one side of the main body, the protrusion having a first source region and a second source region; a gate, the gate being located at least above a part of the main body directly opposite to the protrusion; a first drain region and a second drain region, respectively located on the main body on opposite sides of the gate along the first direction; wherein the first drain region, the gate and the first source region are used to constitute the first holding transistor, and the second drain region, the gate and the second source region are used to constitute the second holding transistor. The disclosed embodiment is conducive to reducing the turn-off current of the first holding transistor and the second holding transistor without increasing the layout area.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a word line driver and a storage device. Background Art

[0002] Memory is a common semiconductor structure. As the size of semiconductor structures continues to shrink, more memory can be incorporated on the chip, which helps increase product capacity. In dynamic random access memory (DRAM), data needs to be written / read to / from memory cells using word lines and bit lines, and operates based on the voltage applied to the word lines.

[0003] As the capacity of DRAM increases, the number of memory cells connected to one word line increases, and the distance between word lines decreases, speed delay problems may occur. In order to improve the delay of the word line voltage, one word line may be divided into a plurality of sub-word lines and each sub-word line may be driven by using a sub word-line driver (SWD), wherein the sub-word-line driver may be provided in the word line driving circuit. Summary of the invention

[0004] The embodiments of the present disclosure provide a word line driver and a storage device, which are at least beneficial for reducing the off-current of the holding transistor without increasing the layout area.

[0005] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a word line driver, comprising: a first sub-word line driver, comprising a first holding transistor, the first holding transistor being configured to provide a first preset voltage to the first word line in response to a driving signal; a second sub-word line driver, comprising a second holding transistor, the second holding transistor being configured to provide the first preset voltage to the second word line in response to the driving signal; wherein the first holding transistor and the second holding transistor comprise: an active area, the active area comprising: a main body extending along a first direction and a protruding portion adjacent to a portion of the main body and located on one side of the main body, the protruding portion having a first source area and a second source area; a gate, the gate being located at least above a portion of the main body that is directly opposite to the protruding portion; a first drain area and a second drain area, respectively located in the main body on opposite sides of the gate along the first direction; wherein the first drain area, the gate and the first source area are used to constitute the first holding transistor, and the second drain area, the gate and the second source area are used to constitute the second holding transistor.

[0006] In some embodiments, the first source region and the second source region are the same source region.

[0007] In some embodiments, the active region further includes: a first recessed portion, the first recessed portion is located in the main body and is recessed from the side wall of the main body away from the protruding portion toward the protruding portion; the gate is also located directly above the first recessed portion.

[0008] In some embodiments, a bottom surface of the first recessed portion facing the protruding portion is located directly below the gate.

[0009] In some embodiments, the gate covers the entire first recess and also covers a portion of the main body adjacent to the first recess along the first direction.

[0010] In some embodiments, the first recessed portion has two end surfaces opposite to each other along the first direction; along the first direction, a length of the main body portion adjacent to one of the end surfaces covered by the gate is a first length, and a length of the main body portion adjacent to the other end surface covered by the gate is a second length, and the first length is equal to the second length.

[0011] In some embodiments, the gate includes a first portion and a second portion forming a T-shape, the first portion is closer to the protruding portion relative to the second portion, and the first portion serves as a lateral side of the T-shape; the first recessed portion is located within the orthographic projection of the second portion on the active region.

[0012] In some embodiments, a shape of an orthographic projection of the gate on the active region includes a rectangle or an H-shape.

[0013] In some embodiments, the active area also includes: a second recessed portion, the second recessed portion is located in the main body, recessed from the main body toward the side wall of the protruding portion in a direction away from the protruding portion, the second recessed portion is located between the first source region and the first drain region, and the second recessed portion and the protruding portion are staggered along the first direction; the gate is also located directly above a portion of the second recessed portion; a third recessed portion, the third recessed portion is located in the main body, recessed from the main body toward the side wall of the protruding portion in a direction away from the protruding portion, the third recessed portion is located between the second source region and the second drain region, and the third recessed portion and the protruding portion are staggered along the first direction; the gate is also located directly above a portion of the third recessed portion.

[0014] In some embodiments, the protrusion includes: a first protrusion and a second protrusion respectively located on two opposite sides of the main body, wherein the first protrusion has the first source region, and the second protrusion has the second source region.

[0015] In some embodiments, the first retention transistor and the second retention transistor constitute a retention transistor unit; the word line driver includes a plurality of the retention transistor units; wherein the two retention transistor units are mirror-symmetric in a second direction, the second direction is perpendicular to the first direction, and the active areas corresponding to the two retention transistor units facing each other in the second direction share the same protrusion and the source area.

[0016] In some embodiments, the first sub-word line driver further includes: a first pull-up transistor configured to pull up the first word line to a second preset voltage in response to a first enable signal provided by the first main word line, the second preset voltage being greater than the first preset voltage; a first pull-down transistor configured to pull down the first word line to the first preset voltage in response to the first enable signal provided by the first main word line; wherein the first pull-down transistor is arranged on a side of the first holding transistor away from the second holding transistor, and the first pull-down transistor is arranged adjacent to the first holding transistor; the second sub-word line driver further includes: a second pull-up transistor configured to pull up the second word line to a second preset voltage in response to a second enable signal provided by the second main word line, the second preset voltage being greater than the first preset voltage; a second pull-down transistor configured to pull down the second word line to the first preset voltage in response to the second enable signal provided by the second main word line; wherein the second pull-down transistor is arranged on a side of the second holding transistor away from the first holding transistor, and the second pull-down transistor is arranged adjacent to the second holding transistor.

[0017] In some embodiments, the first pull-down transistor and the first holding transistor share the first drain region; and the second pull-down transistor and the second holding transistor share the second drain region.

[0018] In some embodiments, the first holding transistor and the second holding transistor are both NMOS transistors.

[0019] According to some embodiments of the present disclosure, another aspect of the present disclosure provides a storage device, comprising: a storage cell array including a plurality of storage cells, a plurality of word lines and a plurality of bit lines, and the storage cells are connected to corresponding word lines and corresponding bit lines; and a word line driver provided in any of the above embodiments.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0021] The word line driver provided by the embodiment of the present disclosure includes a first sub-word line driver having a first holding transistor and a second sub-word line driver having a second holding transistor, wherein the length direction of the channel region between the first source region and the first drain region of the first holding transistor is inclined relative to the extension direction of the active region, and the length of the channel region of the first holding transistor can be increased without increasing the layout area, thereby facilitating the reduction of the turn-off current of the first holding transistor, thereby ensuring that the first word line can be completely turned off. In other words, the first holding transistor can be used to completely pull down the first word line to the first preset voltage. Similarly, the length direction of the channel region between the second source region and the second drain region of the second holding transistor is inclined relative to the extension direction of the active region, and the length of the channel region of the second holding transistor can be increased without increasing the layout area, thereby facilitating the reduction of the turn-off current of the second holding transistor, thereby ensuring that the second word line can be completely turned off. In other words, the second holding transistor can be used to completely pull down the second word line to the first preset voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the layout structure of a word line driver;

[0024] Figure 2 A schematic diagram of a circuit structure of a word line driver provided in an embodiment of the present disclosure;

[0025] Figures 3 to 8 Schematic diagrams of various different layout structures of word line drivers provided in embodiments of the present disclosure;

[0026] Fig. 9 Another circuit structure diagram of a word line driver provided in an embodiment of the present disclosure;

[0027] Fig.10 for Fig. 9 A schematic diagram of the layout structure of the corresponding word line driver. DETAILED DESCRIPTION

[0028] The word line driver includes a plurality of sub word line drivers, each of which includes a pull-down transistor and a holding transistor. Figure 1 A schematic diagram of the layout structure of a word line driver is shown in FIG. Figure 1 The word line driver includes: a plurality of mutually discrete active areas 10, each active area 10 is used to define a plurality of pull-down transistors and a plurality of holding transistors, wherein the plurality of pull-down transistors are respectively indicated by N12, N13, N16 and N17, the plurality of holding transistors are respectively indicated by N23, N22, N26 and N27, N13 and N23 are used to constitute a sub-word line driver, N17 and N27 are used to constitute a sub-word line driver, N12 and N22 are used to constitute a sub-word line driver, and N16 and N26 are used to constitute a sub-word line driver. N12 and N13 share a first gate 11 and belong to different active areas 10, N23 and N27 belong to the same active area 10 and share a second gate 12, N22 and N26 belong to the same active area 10 and share a third gate 13, N16 and N17 belong to different active areas 10 and share a fourth gate 14; multiple conductive plugs 15, each conductive plug 15 is used to electrically connect the source or drain of the pull-down transistor and the source or drain of the holding transistor.

[0029] The channel length of the holding transistor is determined by the length of the corresponding gate in the extension direction of the active region. In order to reduce the off current of the holding transistor, the channel length can be increased and the length of the corresponding gate in the extension direction of the active region 10 can be increased. However, the area occupied by the gate will also increase accordingly, which will lead to a smaller area in the layout where the conductive plug 15 can be designed, and the requirements for the photolithography process of forming the conductive plug 15 will also be higher. In particular, the area surrounded by the gate 12 becomes smaller, which will increase the difficulty of forming the conductive plug 15 in the area surrounded by the second gate 12, and this method will also be limited by the process limit.

[0030] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0031] Figure 2 A circuit structure diagram of a word line driver provided in an embodiment of the present disclosure is shown in FIG. Figures 3 to 8 Schematic diagrams of various different layout structures of word line drivers provided in embodiments of the present disclosure.

[0032] Combined with reference Figures 2 to 8The word line driver provided by the embodiment of the present disclosure includes: a first sub-word line driver SWD1, including a first holding transistor N23, the first holding transistor N23 is configured to provide a first preset voltage VL to the first word line WL3 in response to a driving signal; a second sub-word line driver SWD1, including a second holding transistor N27, the second holding transistor is configured to provide a first preset voltage VL to the second word line WL7 in response to a driving signal PXID; wherein the first holding transistor N23 and the second holding transistor N27 include: an active area 101, the active area 101 includes: a main body portion 1 extending along a first direction X 11 and a protruding portion 121 adjacent to a portion of the main body 111 and located on one side of the main body 111, the protruding portion 121 having a first source region S1 and a second source region S2; a gate 102, the gate 102 is at least located above a portion of the main body 111 that is directly opposite to the protruding portion 121; a first drain region D1 and a second drain region D2, which are respectively located in the main body 111 on opposite sides of the gate 102 along the first direction; wherein the first drain region D1, the gate 102 and the first source region S1D are used to form a first holding transistor N23, and the second drain region D2, the gate 102 and the second source region S2 are used to form a second holding transistor N27.

[0033] In the above embodiment, since the first source region S1 of the first holding transistor N23 is located at the protruding portion 121, and the protruding portion 121 is located outside the main body 111 extending along the first direction X, that is, the first drain region D1 and the first source region S1 are not arranged along the first direction X, compared with the solution in which the first drain region and the first source region are located on opposite sides of the gate along the first direction, the direction from the first source region S11 to the first drain region D1 in the above embodiment is inclined relative to the first direction X, so that the first holding transistor N23 has a larger channel length, which is conducive to reducing the turn-off current of the first holding transistor N23, so that the first word line can be completely turned off. Similarly, in the above embodiment, the direction from the second source region S2 to the second drain region D2 is also inclined relative to the first direction X, which also makes the second holding transistor N27 have a larger channel length, which is conducive to reducing the turn-off current of the second holding transistor N27.

[0034] The word line driver provided by the embodiment of the present disclosure will be described in more detail below with reference to the accompanying drawings.

[0035] The active area 101 is the AA area, usually called the Active Area. The first source area S1 and the first drain area D1 are used to define the source and drain of the first holding transistor N23 respectively; the second source area S2 and the second drain area D2 are used to define the source and drain of the second holding transistor N27 respectively.

[0036] The function of the first holding transistor N23 includes that after the first word line WL3 changes from a selected state (i.e., an activated state) to an unselected state (i.e., an off state), the first holding transistor N23 can ensure that the voltage of the first word line WL3 is pulled down to the first preset voltage VL, thereby avoiding the problem that the first word line WL3 cannot be completely turned off due to interference such as noise. The function of the second holding transistor N27 includes that after the second word line WL7 changes from a selected state to an unselected state, the second holding transistor N27 can ensure that the voltage of the second word line WL7 is pulled down to the first preset voltage VL, thereby avoiding the problem that the second word line WL7 cannot be completely turned off due to interference such as noise.

[0037] The first source region S1 and the second source region S2 are both used to connect to a preset power source, the level of the preset power source is the first preset voltage, or the level of the preset power source is equivalent to the first preset voltage VL. It can be understood that "equivalent" means that the difference between the level of the preset power source and the first preset voltage VL is within an allowable range, and within this allowable range, the levels of the two can be considered to be the same. In other words, in the circuit corresponding to the word line driver, the first source region S1 and the second source region S2 can be considered to be nodes with the same potential, that is, the first source region S1 and the second source region S2 are electrically connected.

[0038] In some embodiments, reference Figure 3 , the first source region S1 and the second source region S2 may be the same source region, that is, the first source region S1 and the second source region S2 are located in the same protrusion 121 and are the same source region, Figure 3 In the figure, the source region is indicated by S1 / S2. In this way, on the one hand, the layout area can be saved and the area of ​​the word line driver can be reduced; on the other hand, the source region can be used to realize the electrical connection between the first source region S1 and the second source region S2, without forming the contact structure and metal layer required for realizing the electrical connection, which is conducive to reducing the manufacturing difficulty of the word line driver and saving the manufacturing cost. Figure 3 The solid lines with arrows indicate the channel length direction of the first holding transistor and the channel length direction of the second holding transistor. Accordingly, a contact structure (LiCon, local interconnect contact) can be provided in the same source region to serve as a source lead terminal.

[0039] In other embodiments, reference Figure 4, the first source region S1 and the second source region S2 can be in the same protrusion 121, and the first source region S1 and the second source region S2 can be separated from each other. The benefits of such a setting include: the first source region S1 and the second source region S2 are separated from each other, and the doping concentrations of the first source region S1 and the second source region S2 can be different to meet the electrical requirements of the first holding transistor N23 and the second holding transistor N27, and the doping concentration refers to the doping concentration of N-type ions or P-type ions; in addition, the first holding transistor N23 has a first channel, and the second holding transistor N27 has a second channel. Since the first source region S1 and the second source region S2 are independent of each other, the first channel and the second channel can be independent of each other, which is conducive to increasing the size of the first channel and the size of the second channel, and reducing the carrier crowding effect of the first drain region D1 and the carrier crowding effect of the second drain region D2. In a specific example, the first holding transistor N23 and the second holding transistor N27 can both be NMOS tubes, and the above doping concentration refers to the doping concentration of N-type ions. It is understandable that the electrical connection between the first source region S1 and the second source region S2 can be achieved by respectively providing a contact structure above the first source region S1 and the second source region S2 and a metal layer electrically connected to the two contact structures. Figure 4 The solid lines with arrows indicate the channel length direction of the first holding transistor and the channel length direction of the second holding transistor.

[0040] Figure 5 A layout of a word line driver and a schematic diagram of the structure of the active area, wherein: Figure 5 The left figure is a schematic diagram of the layout structure of the word line driver, and the right figure is a schematic diagram of the structure of the active area in the left figure. Figure 5 In some embodiments, the active region 101 may further include: a first recessed portion 131, the first recessed portion 131 is located in the main body 111, and is recessed from the side wall of the main body 111 away from the protruding portion 121 to the direction close to the protruding portion 121. The first recessed portion 131 is provided to reduce the conduction area between the first drain region D1 and the second drain region D2, which is beneficial to suppress the leakage between the first drain region D1 and the second drain region D2. In addition, the first drain region D1 can be electrically connected to the first word line WL3, and the second drain region D2 can be electrically connected to the second word line WL7. The provision of the first recessed portion 131 can reduce the leakage between the first word line WL3 and the second word line WL7. It can be understood that the word line driver may further include: an isolation structure, and the isolation structure is filled in the first recessed portion 131.

[0041] In addition, in some embodiments, the gate 102 may also be located directly above the first recessed portion 131 , which is beneficial to increase the volume of the gate 102 and reduce the resistance of the gate 102 .

[0042] The first recessed portion 131 may be a square recessed portion or an arc-shaped recessed portion. In some embodiments, in a direction perpendicular to the first direction X1, the maximum recessed depth of the first recessed portion 131 is defined as the first width W1, and the maximum width of the main body portion 111 is defined as the second width W2. To ensure that the first recessed portion 131 has sufficient capacity to suppress the leakage problem between the first drain region D1 and the second drain region D2, the first holding transistor N23 and the second holding transistor N27 have a relatively large saturation current Idast, and the first holding transistor N23 and the second holding transistor N27 have a relatively small off current Ioff, and the ratio of the first width W1 to the second width W2 is in the range of 0.3-0.7. In a specific example, the ratio of the first width W1 to the second width W2 is in the range of 0.4-0.6, for example, it can be 0.45, 0.5, 0.55, so that it is conducive to further ensuring a relatively small off current Ioff under the premise of ensuring a relatively large saturation current.

[0043] In some embodiments, the gate 102 may cover the entire first recessed portion 131, and also cover a portion of the main body 101 adjacent to the first recessed portion 131 along the first direction X. In other words, the first recessed portion 131 falls completely within the region covered by the gate 102. On the one hand, the region covered by the gate 102 is relatively large, so that the gate 102 has a relatively large volume, which is conducive to reducing the resistance of the gate 102. On the other hand, the gate 102 covers the entire first recessed portion 131. Under the premise of satisfying this positional relationship, the gate 102 will also cover a portion of the main body 111 adjacent to the first recessed portion 131, so that the first holding transistor N23 and the second holding transistor N27 both have a relatively large size, that is, the area of ​​the active area occupied by the first holding transistor and the second holding transistor is relatively large, which is conducive to increasing the saturation current. In addition, the gate 102 covers the entire first recessed portion 131, so that the process of forming the gate 102 has a relatively large process window, which is conducive to reducing the difficulty of the formation process of the gate 102.

[0044] In some embodiments, the first recess 131 may be filled with an isolation structure. In other embodiments, the gate 102 may cover the bottom and side surfaces of the first recess 131. In this way, the bottom and side walls of the first recess 131 covered by the gate 102 will also serve as part of the channel, which can not only increase the area of ​​the channel controlled by the gate 102, thereby improving the ability of the gate 102 to control the conduction of the channel, but also because the gate conductive layer in the gate 102 is also correspondingly located in the first recess 131, the volume of the gate 102 can be increased, and the resistance of the gate 120 can be further reduced. It can be understood that the channel includes a first channel corresponding to the first holding transistor N23 and a second channel corresponding to the second holding transistor N27; the gate 102 includes a gate dielectric layer and a gate electrode layer located on the surface of the gate dielectric layer, and the gate 102 covers the bottom and side walls of the first recess 131, which means that the gate dielectric layer is located on the bottom and side walls of the first recess 131, and the gate conductive layer is also located in the first recess 131.

[0045] In one specific example, the gate 102 may cover part of the bottom surface and part of the side surface, and accordingly, an isolation structure may be filled under the gate 102 in the first recess 131 ; in another specific example, the gate 102 may cover the entire bottom surface and the entire top surface.

[0046] In other embodiments, the gate 102 may only cover a portion of the first recessed portion 131, for example, a portion of the first recessed portion 131 facing the protruding portion 121 is covered by the gate 102, while the remaining portion of the first recessed portion 131 away from the protruding portion 121 is not covered by the gate 102. Alternatively, the gate 102 and the first recessed portion 131 may be completely staggered.

[0047] In some embodiments, the bottom surface of the first recessed portion 131 facing the protruding portion 121 may be located directly below the gate 102. In other embodiments, the bottom surface of the first recessed portion 131 facing the protruding portion 121 may also be flush with the side surface of the gate 102 away from the protruding portion 121.

[0048] In addition, the first recessed portion 131 may have two end faces opposite to each other along the first direction X; along the first direction X, the length of the main body 111 adjacent to one end face covered by the gate 102 is a first length L1, and the length of the main body 111 adjacent to the other end face covered by the gate 102 is a second length L2, and the first length L1 may be equal to the second length L2. That is, along the first direction X, the first recessed portion 131 is located in the middle of the gate 102, which is conducive to improving the symmetry of the first holding transistor N23 and the second holding transistor N27 and reducing the mismatch of different transistors.

[0049] It can be understood that in other embodiments, the first length L1 may also be different from the second length L2. For example, the first length L1 may be less than or greater than the second length L1.

[0050] In some embodiments, referring to Figure 4 , the gate 102 may include a first part 112 and a second part 122 that form a T shape. The first part 112 is closer to the protruding part 121 than the second part 122, and the first part 112 serves as the horizontal side of the T shape. That is, the first part 112 serves as the "one" part of the T shape, and the second part 122 serves as the "vertical" part of the T shape. For the T-shaped gate 102, while increasing the volume of the gate 102 to reduce the resistance of the gate 102, the "vertical" part can reserve space positions for forming contact structures on opposite sides along the first direction X. One contact structure is used for electrically connecting to the first drain region D1, and the other contact structure is used for electrically connecting to the second drain region D2.

[0051] The first recess 131 may be located within the orthographic projection of the second part 122 on the active region 101. Additionally, the first recess 131 may have two end faces opposite to each other along the first direction; along the first direction X, the length of the main body part 111 covered by the second part 122 adjacent to one end face is the first length L1, and the length of the main body part 111 covered by the second part 122 adjacent to the other end face is the second length L2, and the first length L1 may be equal to the second length L2.

[0052] In some other embodiments, the shape of the orthographic projection of the gate 102 on the active region 101 may also be rectangular or H-shaped. In a specific example, the H-shaped gate 102 includes two opposite cross beams and a connecting part located between the cross beams. Among them, the two cross beams are arranged along the first direction X, and the first recess 131 may also be located directly below the connecting part.

[0053] Figure 6 Another layout structure schematic diagram of the word line driver, referring to Figure 6 , the active region 101 may further include: a second recess 141, which is located within the main body part 111, recessed from the side wall of the main body part 111 facing the protruding part 121 in a direction away from the protruding part 121, located between the first drain region D1 and the protruding part 121, and the second recess 141 is offset from the protruding part 121 in the first direction X. Among them, the second recess 141 may be located between the first source region S1 and the first drain region D1.

[0054] The setting of the second recess 141 is beneficial to further increase the length of the channel region in the first holding transistor N23 and further reduce the off-current of the first holding transistor N23.

[0055] Continuing to refer to Figure 6The active region 101 may further include: a third recessed portion 151, which is located in the main body 111, recessed from the main body 111 toward the side wall of the protruding portion 121 in a direction away from the protruding portion 111, and located between the second drain region D2 and the protruding portion 121, and the third recessed portion 151 and the protruding portion 121 are staggered along the first direction X. The third recessed portion 151 may also be located between the second source region S2 and the second drain region D2.

[0056] The provision of the third recessed portion 151 is beneficial to further increase the length of the channel region in the second holding transistor N27 and further reduce the turn-off current of the second holding transistor N27.

[0057] Continue to refer Figure 6 The gate 102 may also be located directly above a portion of the second recessed portion 141, and the gate 102 may also be located directly above a portion of the third recessed portion 151. In this way, the volume of the gate 102 is further increased and the resistance of the gate 102 is reduced.

[0058] It can be understood that, in a specific example, the active region 101 may include any one of the first recess 131 , the second recess 141 , or the third recess 151 , or a combination of more than one of the first recess 131 , the second recess 141 , or the third recess 151 .

[0059] Figure 7 is a schematic structural diagram of the active area 101 including the first recessed portion 131, the second recessed portion 141 and the third recessed portion 151, referring to Figure 7 In some embodiments, at least one of the first recess 131, the second recess 141 and the third recess 151 may be an arc-shaped recess, so that corner rounding can be achieved to avoid problems such as discharge at the corner tip.

[0060] Figure 8 Another schematic diagram of the word line driver layout is shown in FIG. Figure 8 In some embodiments, the protrusion 121 may further include: a first protrusion 1 and a second protrusion 2 respectively located on opposite sides of the main body 111, wherein the first protrusion 1 has a first source region S1, and the second protrusion 2 has a second source region S2. In other words, the first source region S1 and the second source region S2 are respectively located in different protrusions 121, which can provide a larger process window for forming the first source region S1 and the second source region S2, and is conducive to increasing the area of ​​the first source region S1 and the second source region S2, thereby reducing the contact resistance of the first source region S1 and the second source region S2.

[0061] Accordingly, reference Figure 8The active area 101 may include two second recessed portions 141 and two third recessed portions 151, one first recessed portion 141 is located between the first drain region D1 and the first protruding portion 1, another first recessed portion 141 is located between the first drain region D1 and the second protruding portion 2, one second recessed portion 151 is located between the second drain region D1 and the first protruding portion 1, and another second recessed portion 151 is located between the second drain region D2 and the second protruding portion 2.

[0062] refer to Figures 2 to 7 , the first sub-word line driver SWD1 may further include: a first pull-up transistor P13, configured to pull up the first word line WL3 to a second preset voltage PXID in response to a first enable signal provided by the first main word line MWLa, the second preset voltage PXID being greater than the first preset voltage VL; a first pull-down transistor N13, configured to pull down the first word line WL3 to the first preset voltage VL in response to the first enable signal provided by the first main word line MWLa. The second sub-word line driver SWD2 further includes: a second pull-up transistor P17, configured to pull up the second word line WL7 to a second preset voltage PXID in response to a second enable signal provided by the second main word line MWLb, the second preset voltage PXID being greater than the first preset voltage VL; a second pull-down transistor N17, configured to pull down the second word line WL7 to the first preset voltage VL in response to a second enable signal provided by the second main word line MWLb. Correspondingly, the word line driver further includes: a first pull-down gate 201, used as the gate of the first pull-down transistor N13; a second pull-down gate 202, used as the gate of the second pull-down transistor N17. The extension directions of the first pull-down gate 201 and the second pull-down gate 202 are both perpendicular to the first direction X.

[0063] The working principle of the first sub-word line driver SWD1 will be described below by taking the first sub-word line driver SWD1 as an example:

[0064] The first enable signal includes a first state and a second state, and the level of the first state is different from the level of the second state; while the first enable signal is in the first state, the first sub-word line driver SWD11 receives a valid drive signal, and the first pull-up transistor P13 is turned on, then the first word line WL3 is pulled up to the second preset voltage PXID, and the voltage of the second preset voltage PXID is the same as or equivalent to the voltage of the drive signal; then, while the first enable signal is in the second state, the first pull-down transistor N13 is turned on, the first word line WL3 is pulled down to the first preset voltage VL, and the first holding transistor N23 is turned on, which is beneficial to further ensure that the first word line WL3 is pulled down to the first preset voltage VL, thereby avoiding signal noise from interfering with the first word line WL3.

[0065] The working principle of the second sub-word line driver can refer to the working principle of the first sub-word line driver, which will not be repeated here. In a specific example, the first pull-up transistor P13 and the second pull-up transistor P17 can both be PMOS transistors, and the first pull-down transistor N13 and the second pull-down transistor N17 can both be NMOS transistors. The first holding transistor N23 and the second holding transistor N27 can both be NMOS transistors.

[0066] refer to Figure 3 In some embodiments, the first pull-down transistor N13 may be disposed on a side of the first holding transistor N23 away from the second holding transistor N27, and the first pull-down transistor N13 may be disposed adjacent to the first holding transistor N23. The second pull-down transistor N17 may be disposed on a side of the second holding transistor N27 away from the first holding transistor N23, and the second pull-down transistor N17 may be disposed adjacent to the second holding transistor N27.

[0067] It should be noted that for the convenience of illustration and description, Figure 3 N13, N23, P13, N17, N27, and P17 are used to indicate that the channel regions of each transistor correspond to the areas where the active regions are located.

[0068] The first pull-down transistor N13 and the first holding transistor N23 can share the first drain region D1. By sharing the first drain region D1, the drain of the first pull-down transistor is electrically connected to the drain of the first holding transistor without additionally forming a contact structure and a metal layer, which is conducive to reducing the complexity of the layout structure. The second pull-down transistor N17 and the second holding transistor N27 can share the second drain region D2. By sharing the second drain region D2, the drain of the second pull-down transistor is electrically connected to the drain of the second holding transistor without additionally forming a contact structure and a metal layer, which is conducive to reducing the complexity of the layout structure.

[0069] Fig. 9 Another circuit structure diagram of a word line driver provided in an embodiment of the present disclosure is shown in FIG. Fig.10 for Fig. 9 A schematic diagram of the layout structure of the corresponding word line driver. Fig. 9 and Fig.10 In some embodiments, the first holding transistor N23 and the second holding transistor N27 constitute a holding transistor unit 10; the word line driver includes a plurality of holding transistor units 10; wherein the two holding transistor units 10 are mirror-imaged in a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0070] It should be noted that for the convenience of illustration and description, Fig. 9 and Fig.10In the embodiment, the first holding transistors in different holding transistor units 10 are marked with different reference numerals, including N20, N21, N22, and N23, and the first word lines connected to the different first holding transistors are marked with WL0, WL1, WL2, and WL3, respectively; the second holding transistors in different holding transistor units 10 are marked with different reference numerals, including N24, N25, N26, and N27, and the second word lines connected to the different second holding transistors are marked with WL4, WL5, WL6, and WL7, respectively; the different first pull-down transistors are marked with N10, N11, N12, and N13, respectively; the different second pull-down transistors are marked with N14, N15, N16, and N17, respectively; the different first pull-up transistors are marked with P10, P11, P12, and P13, respectively; and the different second pull-up transistors are marked with P14, P15, P16, and P17, respectively.

[0071] In some embodiments, reference Fig.10 , the active regions 101 corresponding to the two holding transistor units 10 facing each other in the second direction Y share the same protrusion 121, and the two holding transistor units 10 facing each other in the second direction Y may also share the source region. For example, the first holding transistor N23 / N22 and the second holding transistor N27 / N26 in the two holding transistor units 10 may share the same active region, that is, the four holding transistors share the same active region, and the active region is located at the same protrusion 121. In this way, it is beneficial to further save the layout area and reduce the complexity of the layout structure.

[0072] In other embodiments, the two first holding transistors in the two holding transistor units 10 may share the same source region located at the same protrusion 121, and the two second holding transistors do not share the source region with the first holding transistor. Alternatively, the two second holding transistors in the two holding transistor units 10 may share the same source region located at the same protrusion 121, and the two first holding transistors do not share the source region with the second holding transistor.

[0073] The word line driver may further include: a plurality of contact structures 105, each contact structure 105 being used to be electrically connected to the corresponding first source region S1, the second source region S2, the first drain region D1 or the second drain region D2, and also being used to be electrically connected to the source region or the drain region of the first pull-down transistor, the second pull-down transistor, the first pull-up transistor and the second pull-up transistor.

[0074] In the word line driver provided in the above embodiment, the channel length direction of the two holding transistors is designed to be inclined relative to the extension direction of the active area 101. Without increasing the layout area, the channel region length of the holding transistor can be increased, thereby reducing the turn-off current of the holding transistor and improving the ability of the holding transistor to turn off the word line connected to the holding transistor. In addition, the channel length direction is inclined relative to the extension direction of the active area 101, which can also reserve more space for the layout of the contact structure 105, thereby improving the space utilization rate of the layout.

[0075] Correspondingly, an embodiment of the present disclosure also provides a storage device, including the word line driver provided by the above embodiment. The storage device provided by the embodiment of the present disclosure will be described in detail below. For the parts that are the same or corresponding to the above embodiment, please refer to the detailed description of the above embodiment and will not be repeated below.

[0076] The storage device provided by the embodiment of the present disclosure includes: a storage cell array including a plurality of storage cells, a plurality of word lines and a plurality of bit lines, the storage cells are connected to corresponding word lines and corresponding bit lines; and the word line driver provided by the above embodiment.

[0077] Each sub-word line driver in the word line driver is electrically connected to a corresponding word line and is used to select / activate the corresponding word line or turn off the corresponding word line.

[0078] The storage device may be a DRAM storage system, such as a DDR5 DRAM storage system or a DDR4 DRAM storage system. In other embodiments, the storage device may also be an SRAM storage system, an SDRAM storage system, a ROM storage system, or a flash memory storage system.

[0079] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A word line driver, characterized in that: include: a first sub-word line driver including a first holding transistor configured to provide a first preset voltage to the first word line in response to a driving signal; a second sub-word line driver including a second holding transistor configured to provide the first preset voltage to a second word line in response to the driving signal; Wherein, the first holding transistor and the second holding transistor include: An active region, the active region comprising: a main body extending along a first direction and a protruding portion adjacent to a portion of the main body and located on one side of the main body, the protruding portion having a first source region and a second source region; A gate, the gate being located at least above a portion of the main body portion that is directly opposite to the protruding portion; A first drain region and a second drain region are respectively located in the main body at two opposite sides of the gate along the first direction; The gate comprises a first portion and a second portion arranged along a second direction, the second portion is farther away from the protruding portion than the first portion, and the second direction is perpendicular to the first direction; The active area further includes: a first recessed portion, the first recessed portion is located in the main body portion and is recessed from a side wall of the main body portion away from the protruding portion toward a direction close to the protruding portion; The second portion covers at least a portion of the first recessed portion, and the orthographic projection of the second portion in the first direction falls within the orthographic projection of the first portion in the first direction, and the edge of the orthographic projection of the second portion in the first direction does not overlap with the edge of the orthographic projection of the first portion in the first direction, so as to reserve a space position for forming a first drain region contact structure and a second drain region contact structure, wherein the first drain region contact structure is used to be electrically connected to the first drain region; and the second drain region contact structure is used to be electrically connected to the second drain region; The first drain region, the gate region and the first source region are used to constitute the first holding transistor, and the second drain region, the gate region and the second source region are used to constitute the second holding transistor.

2. The word line driver according to claim 1, wherein: The gate is composed of the first portion and the second portion.

3. The word line driver according to claim 1, wherein: The gate only covers a portion of the first recessed portion facing the protruding portion, but does not cover the remaining portion of the first recessed portion away from the protruding portion.

4. The word line driver according to any one of claims 1 to 3, characterized in that: The first source region and the second source region are the same source region.

5. The word line driver according to any one of claims 1 to 3, characterized in that: The bottom surface of the first recessed portion facing the protruding portion is located directly below the gate.

6. The word line driver according to any one of claims 1 to 3, characterized in that: The gate covers the entire first recessed portion, and also covers a portion of the main body portion adjacent to the first recessed portion along the first direction.

7. The word line driver according to claim 6, wherein: The first recessed portion has two end faces opposite to each other along the first direction; along the first direction, the length of the main body portion adjacent to one end face covered by the gate is a first length, and the length of the main body portion adjacent to the other end face covered by the gate is a second length, and the first length is equal to the second length.

8. The word line driver according to any one of claims 1 to 3, characterized in that: The gate includes a first portion and a second portion forming a T-shape, wherein the first portion is closer to the protruding portion than the second portion; and the first recessed portion is located within the orthographic projection of the second portion on the active region.

9. The word line driver according to claim 1, wherein: The active region further comprises: a second recessed portion, the second recessed portion being located in the main body portion, and being recessed from the main body portion toward the side wall of the protruding portion in a direction away from the protruding portion, the second recessed portion being located between the first source region and the first drain region, and the second recessed portion and the protruding portion being staggered along the first direction; and the gate being located directly above a portion of the second recessed portion; A third recessed portion, wherein the third recessed portion is located in the main body portion, and is recessed from the main body portion toward the side wall of the protruding portion in a direction away from the protruding portion, wherein the third recessed portion is located between the second source region and the second drain region, and the third recessed portion and the protruding portion are staggered along the first direction; and the gate is also located directly above a portion of the third recessed portion.

10. The word line driver according to claim 1, wherein: The first holding transistor and the second holding transistor constitute a holding transistor unit; the word line driver includes a plurality of the holding transistor units; The two holding transistor units are mirror-symmetric in the second direction, and the active regions corresponding to the two holding transistor units facing each other in the second direction share the same protrusion and the source region.

11. The word line driver according to claim 1, wherein: The first sub-word line driver further includes: A first pull-up transistor is configured to pull up the first word line to a second preset voltage in response to a first enable signal provided by the first main word line, wherein the second preset voltage is greater than the first preset voltage; a first pull-down transistor configured to, in response to the first enable signal provided by the first main word line, pull the first word line down to the first preset voltage; Wherein, the first pull-down transistor is arranged on a side of the first holding transistor away from the second holding transistor, and the first pull-down transistor is arranged adjacent to the first holding transistor; The second sub-word line driver further includes: A second pull-up transistor is configured to pull up the second word line to a second preset voltage in response to a second enable signal provided by the second main word line, wherein the second preset voltage is greater than the first preset voltage; A second pull-down transistor is configured to pull down the second word line to the first preset voltage in response to the second enable signal provided by the second main word line; wherein the second pull-down transistor is arranged on a side of the second holding transistor away from the first holding transistor, and the second pull-down transistor is arranged adjacent to the second holding transistor.

12. The word line driver according to claim 11, wherein: The first pull-down transistor and the first holding transistor share the first drain region; the second pull-down transistor and the second holding transistor share the second drain region.

13. The word line driver according to claim 1, wherein: The first holding transistor and the second holding transistor are both NMOS transistors.

14. A storage device, characterized in that: include: A memory cell array comprising a plurality of memory cells, a plurality of word lines and a plurality of bit lines, wherein the memory cells are connected to corresponding word lines and corresponding bit lines; A word line driver as claimed in any one of claims 1 to 13.

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