FPGA acceleration method based on programmable hardware floating-point library

Abstract

The present invention provides an FPGA acceleration method based on a programmable hardware floating-point library, which relates to the technical field of FPGA acceleration methods. The method includes adopting a dspfloat data type; the dspfloat data type includes a 1-bit wide sign bit, an exponent bit, and a mantissa bit; a sign bit value of 0 indicates a positive number, and a sign bit value of 1 indicates a negative number; the exponent bit is the NEXP bit; the mantissa bit is the NFRAC bit; the exponent bits are stored in a two's complement format; the mantissa bit represents the valid floating-point data, hiding the high-order bit 1; and the bit widths of the exponent and mantissa bits can be customized. The exponent and mantissa bit widths of the dspfloat provided by the present invention can be customized, avoiding the defects of insufficient precision of the float data type and excessive bit width of the double data type. While ensuring the precision required by the application, the method achieves a higher frequency, reduces computing resource usage, and improves computing speed.

Description

Technical Field

[0001] The present invention belongs to the technical field of FPGA acceleration methods, and in particular relates to an FPGA acceleration method based on a programmable hardware floating-point library. Background Art

[0002] Modern FPGAs often use DSPs to implement high-speed floating-point libraries. The standard floating-point libraries provided by DSPs are primarily based on two data types: float and double. The float type uses fewer bits, has a higher frequency, and offers faster computation speeds. However, its precision in calculations, especially multiplication, often falls short of application requirements. The double type, on the other hand, offers sufficient precision, but requires a larger DSP bit width, consumes more resources, and is relatively slow. Summary of the Invention

[0003] To address the above technical issues, the present invention provides an FPGA acceleration method based on a programmable hardware floating-point library. This method combines the advantages of the float and double data types in the prior art and avoids their defects. While ensuring the accuracy required by the application, it can achieve higher frequencies, reduce computing resource usage, and improve computing speed.

[0004] To achieve the above objectives, the technical solution provided by the present invention is:

[0005] The present invention provides an FPGA acceleration method based on a programmable hardware floating-point library, comprising adopting a dspfloat data type; the dspfloat data type comprises a 1-bit wide sign bit, an exponent bit, and a mantissa bit; a sign bit value of 0 indicates a positive number, and a sign bit value of 1 indicates a negative number; the exponent bit is a NEXP bit; the mantissa bit is an NFRAC bit; the exponent bit is stored in a two's complement manner; the mantissa bit indicates valid floating-point data, and the high-order bit 1 is hidden; the bit widths of the exponent bit and the mantissa bit can be customized;

[0006] The steps to calculate the actual value of a floating-point number based on the dspfloat data type include:

[0007] S101: Get the NEXP bit of the exponent bit and obtain the value V_exp represented by the exponent bit;

[0008] S102: Determine whether the value of the extracted NEXP bit is -2 (NEXP-1) ; If yes, the actual value of the floating point number is 0, and the step is terminated; if no, step S103 is executed;

[0009] S103: Extract the NFRAC bit of the mantissa;

[0010] S104: Add the high-order bit 1 to obtain the value V_frac represented by the mantissa;

[0011] S105: extract the sign bit;

[0012] S106: Determine whether the sign bit is 0; if the sign bit is 0, the actual value of the floating point number is V_frac*2^V_exp; if the sign bit is 1, the actual value of the floating point number is -V_frac*2^V_exp;

[0013] When using the dspfloat data type for addition, the steps for determining the high-order bit of the mantissa include:

[0014] S201: The mantissa bits after addition are fr, and the mantissa width is NFRAC+3 bits;

[0015] S202: Determine whether the addition is of the same sign; if it is the same sign, execute step S203; if it is different signs, execute steps S204 to S205;

[0016] S203: Determine whether the value of the NFRAC+1th bit of fr is 1; if it is 1, fr is right-shifted by 1, and the exponent after addition is incremented by 1; if it is 0, fr remains unchanged, and the exponent after addition remains unchanged; the high-order bit of the mantissa is determined;

[0017] S204: Search fr from high to low to find the most significant bit 1, and determine the position nlz where the most significant bit 1 is located;

[0018] S205: fr is right-shifted by nlz-NFRAC bits; the exponent after addition is added by nlz-NFRAC bits; and the high-order bit judgment of the mantissa is completed.

[0019] The FPGA acceleration method based on the programmable hardware floating-point library provided by the present invention preferably has, in an initial state, a dspfloat data type of 38 bits wide; a sign bit of 1 bit wide; an exponent bit of 11 bits wide; and a mantissa bit of 26 bits wide.

[0020] The FPGA acceleration method based on the programmable hardware floating-point library provided by the present invention preferably:

[0021] Using the dspfloat data type to find the reciprocal of the modulus value When, including:

[0022] S301: Since x is of dspfloat data type, let the exponent value of x be e and the mantissa value be f. x can be expressed as x=f*2 e ;

[0023] S302: x=f*2e Bring it into In, you can get

[0024]

[0025] S303: When the exponent e of x is an even number, its inverse square root can be converted to the mantissa to obtain the inverse square root, the exponent is shifted right by 1 bit and then negated; when the exponent e of x is an odd number, its inverse square root can be converted to the mantissa to obtain the inverse square root after shifting right, the exponent is increased by 1, shifted right by 1 bit and then negated;

[0026] Among them, the square root inverse is obtained according to the Newton iteration method, specifically: Where p is the input value and q is the estimate of the inverse square root of p.

[0027] The FPGA acceleration method based on a programmable hardware floating-point library provided by the present invention is characterized in that, in order to quickly obtain the initial value of q, the specific steps include:

[0028] S401: Perform linear fitting, q = a + bp, select the 2 closest to b n ; Calculate q+2 n The maximum and minimum values ​​of p in a given interval are averaged as M;

[0029] S402: Calculate q0=M-2 n p.

[0030] The above technical solution has the following advantages:

[0031] The present invention provides an FPGA acceleration method based on a programmable hardware floating-point library, including a dspfloat data type; the dspfloat data type includes a 1-bit wide sign bit, an exponent bit, and a mantissa bit; a sign bit value of 0 indicates a positive number, and a sign bit value of 1 indicates a negative number; the exponent bit is the NEXP bit; the mantissa bit is the NFRAC bit; the exponent bits are stored in a two's complement format; the mantissa bit represents valid floating-point data, hiding the high-order bit 1; and the bit widths of the exponent and mantissa bits can be customized. The exponent bit width and mantissa bit width of the dspfloat provided by the present invention can be customized according to different application scenarios, combining the advantages of the float and double data types in the prior art while avoiding the shortcomings of the float and double data types in the prior art. While ensuring the accuracy required by the application, it can achieve higher frequencies, reduce computing resource usage, and improve computing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention and its features, configurations, and advantages will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Like reference numerals indicate like parts throughout the drawings. The drawings are not drawn to scale, emphasis instead being placed on illustrating the subject matter of the present invention.

[0033] Figure 1 This is a flow chart of the FPGA acceleration method based on the programmable hardware floating-point library provided in Example 1 of the present invention.

[0034] Figure 2 This is a flow chart of determining the high-order bits of a mantissa in an FPGA acceleration method based on a programmable hardware floating-point library provided in Example 1 of the present invention. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present invention are described below in conjunction with the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Therefore, the detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] Example 1:

[0037] The present invention provides an FPGA acceleration method based on a programmable hardware floating-point library, including adopting a dspfloat data type; the dspfloat data type includes a 1-bit wide sign bit, an exponent bit, and a mantissa bit; a sign bit value of 0 indicates a positive number, and a sign bit value of 1 indicates a negative number; the exponent bit is the NEXP bit; the mantissa bit is the NFRAC bit; the exponent bit is stored in a two's complement manner; the mantissa bit represents the valid data of the floating point, and the high-order bit 1 is hidden; the bit widths of the exponent bit and the mantissa bit can be customized;

[0038] like Figure 1 As shown, the steps for calculating the actual value of a floating-point number using the dspfloat data type include:

[0039] S101: Get the NEXP bit of the exponent bit and obtain the value V_exp represented by the exponent bit;

[0040] S102: Determine whether the value of the extracted NEXP bit is -2 (NEXP-1) ; If yes, the actual value of the floating point number is 0, and the step is terminated; if no, step S103 is executed;

[0041] S103: Extract the NFRAC bit of the mantissa;

[0042] S104: Add the high-order bit 1 to obtain the value V_frac represented by the mantissa;

[0043] S105: extract the sign bit;

[0044] S106: Determine whether the sign bit is 0; if the sign bit is 0, the actual value of the floating point number is V_frac*2^V_exp; if the sign bit is 1, the actual value of the floating point number is -V_frac*2^V_exp.

[0045] In this embodiment, a special index value is used to indicate a zero value, and the index value is -2. (NEXP-1) The floating-point number is set to 0, and the zero judgment function only needs to judge the exponent bit; this method can make it possible to judge that the result is 0 when the exponent overflows in saturated addition (that is, the addition result is extremely small), without considering the mantissa part.

[0046] The normal addition operation of the standard floating point library requires a complete high-order determination of the mantissa, but in the embodiment of the present invention, 1 is directed to a specific algorithm, such as the Hamming distance formula x 2 +y 2 , to determine whether the addition is of the same sign, it is only necessary to determine whether there is overflow, which reduces resource overhead. In this embodiment, the high-order digit judgment step of the mantissa only needs to be as follows Figure 2 Shown, including:

[0047] S201: The mantissa bits after addition are fr, and the mantissa width is NFRAC+3 bits;

[0048] S202: Determine whether the addition is of the same sign; if it is of the same sign, execute step S203; if it is of different signs, execute step S204;

[0049] S203: Determine whether the value of the NFRAC+1th bit of fr is 1; if it is 1, fr is right-shifted by 1, and the exponent after addition is incremented by 1; if it is 0, fr remains unchanged, and the exponent after addition remains unchanged; the high-order bit of the mantissa is determined;

[0050] S204: Search fr from high to low to find the most significant bit 1, and determine the position nlz where the most significant bit 1 is located;

[0051] S205: fr is right-shifted by nlz-NFRAC bits; the exponent after addition is added by nlz-NFRAC bits; and the high-order bit judgment of the mantissa is completed.

[0052] The dspfloat data type in the FPGA acceleration method based on a programmable hardware floating-point library provided in Example 1 of the present invention is similar to the float or double data type supported by standard floating-point libraries, consisting of a sign bit, an exponent bit, and a mantissa bit. However, the exponent and mantissa bit widths of the dspfloat data type in the present invention can be customized based on different application scenarios. This combines the advantages of the float and double data types in the prior art while avoiding their drawbacks. While ensuring the required accuracy for the application, it can achieve higher frequencies, reduce computing resource usage, and improve computing speed.

[0053] Without customization, the dspfloat data type defaults to a 38-bit width; the sign bit is 1 bit wide; the exponent bit is 11 bits wide; and the mantissa bit is 26 bits wide.

[0054] The inverse square root function invsqrt() is commonly used in trigonometric functions. Standard floating-point libraries use square root and division operations to implement this directly, which is costly. This invention uses an iterative method based on hardware characteristics, specifically:

[0055] Using the dspfloat data type to find the reciprocal of the modulus value When, including:

[0056] S301: Since x is of dspfloat data type, let the exponent value of x be e and the mantissa value be f. x can be expressed as x=f*2 e ;

[0057] S302: x=f*2 e Bring it into In, you can get

[0058]

[0059] S303: When the exponent e of x is an even number, its inverse square root can be converted to the mantissa to obtain the inverse square root, the exponent is shifted right by 1 bit and then negated; when the exponent e of x is an odd number, its inverse square root can be converted to the mantissa to obtain the inverse square root after shifting right, the exponent is increased by 1, shifted right by 1 bit and then negated;

[0060] Among them, the square root inverse is obtained according to the Newton iteration method, specifically: Where p is the input value and q is the estimate of the inverse square root of p;

[0061] In order to quickly obtain the initial value of q, the specific steps include:

[0062] S401: Perform linear fitting, q = a + bp, select the 2 closest to b n ; Calculate q+2 nThe maximum and minimum values ​​of p in a given interval are averaged as M;

[0063] S402: Calculate q0=M-2 n p.

[0064] Therefore, in this embodiment, using the dspfloat data type to calculate the reciprocal of the modulo value only requires one fixed-point shift and subtraction to obtain q0. Taking the 26-bit mantissa version as an example, the mantissa padded with 1 is regarded as a 27-bit fixed-point number, and the final parameters used are:

[0065]

[0066] To compare with the default data type library in existing systems, the short-range force calculation component uses dspfloat data and its mathematical library in the molecular dynamics application scenario. This is programmed using the Vivado HLS platform and implemented on a Xilinx Virtex ULtraScale+HBM VCU128 FPGA, where dspfloat is in 38-bit mode.

[0067] Ultimately, the system frequency reached 400 MHz, with a maximum error of 2.2e-6. This achieved significantly lower error than the float type, while utilizing only 52 DSP48 devices. Resource utilization was significantly lower than that of the double type, and even lower than that of the float type. The following table shows the results, comparing the error and resource utilization of dspfloat and the system's default float / double type libraries. Considering both error and resource utilization, the dspfloat solution is superior to both float and double types for specific application requirements.

[0068] Data Type Maximum error Number of DSP48 resources used dspfloat 2.2e-6 52 float 5.5e-4 93 double 1.4e-14 187

[0069] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformation made by using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An FPGA acceleration method based on a programmable hardware floating-point library, characterized in that: Including using the dspfloat data type; the dspfloat data type includes a 1-bit wide sign bit, an exponent bit, and a mantissa bit; the value of the sign bit is 0 for a positive number, and the value of the sign bit is 1 for a negative number; the exponent bit is the NEXP bit; the mantissa bit is the NFRAC bit; the exponent bit is stored in a two's complement manner; the mantissa bit represents the valid data of the floating point, and the high-order bit 1 is hidden; the bit widths of the exponent bit and the mantissa bit can be customized; The steps to calculate the actual value of a floating-point number based on the dspfloat data type include: S101: Get the NEXP bit of the exponent bit and obtain the value V_exp represented by the exponent bit; S102: Determine whether the value of the extracted NEXP bit is -2 (NEXP-1) ; If yes, the actual value of the floating point number is 0, and the step is terminated; if no, step S103 is executed; S103: Extract the NFRAC bit of the mantissa; S104: Add the high-order bit 1 to obtain the value V_frac represented by the mantissa; S105: extract the sign bit; S106: Determine whether the sign bit is 0; if the sign bit is 0, the actual value of the floating point number is V_frac*2^V_exp; if the sign bit is 1, the actual value of the floating point number is -V_frac*2^V_exp; When using the dspfloat data type for addition, the steps for determining the high-order bit of the mantissa include: S201: The mantissa bits after addition are fr, and the mantissa width is NFRAC+3 bits; S202: Determine whether the addition is of the same sign; if it is the same sign, execute step S203; if it is different signs, execute steps S204 to S205; S203: Determine whether the value of the NFRAC+1th bit of fr is 1; if it is 1, fr is right-shifted by 1, and the exponent after addition is incremented by 1; if it is 0, fr remains unchanged, and the exponent after addition remains unchanged; the high-order bit of the mantissa is determined; S204: Search fr from high to low to find the most significant bit 1, and determine the position nlz where the most significant bit 1 is located; S205: fr is right-shifted by nlz-NFRAC bits; the exponent after addition is added by nlz-NFRAC bits; and the high-order bit judgment of the mantissa is completed.

2. The FPGA acceleration method based on a programmable hardware floating-point library as claimed in claim 1, wherein: In an initial state, the dspfloat data type is 38 bits wide; the sign bit is 1 bit wide; the exponent bit is 11 bits wide; and the mantissa bit is 26 bits wide.

3. The FPGA acceleration method based on a programmable hardware floating-point library as claimed in claim 1, wherein: Using the dspfloat data type to find the reciprocal of the modulus value When, including: S301: Since x is of dspfloat data type, let the exponent value of x be e and the mantissa value be f. x is expressed as x=f*2 e ; S302: x=f*2 e Bring it into In, you can get S303: When the exponent e of x is an even number, its inverse square root can be converted to the mantissa to obtain the inverse square root, the exponent is shifted right by 1 bit and then negated; when the exponent e of x is an odd number, its inverse square root can be converted to the mantissa to obtain the inverse square root after shifting right, the exponent is increased by 1, shifted right by 1 bit and then negated; Among them, the square root inverse is obtained according to the Newton iteration method, specifically: Where p is the input value and q is the estimate of the inverse square root of p.

4. The FPGA acceleration method based on a programmable hardware floating-point library as claimed in claim 3, wherein: In order to quickly obtain the initial value of q, the specific steps include: S401: Perform linear fitting, q = a + bp, select the 2 closest to b n ; Calculate q+2 n The maximum and minimum values ​​of p in a given interval are averaged as M; S402: Calculate q0=M-2 n p.

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