A display substrate, an aging control method for a display substrate, and a display device

Abstract

The present invention relates to the field of display control technologies, and discloses a display substrate, an aging control method for the display substrate, and a display device. The display substrate includes: a display area and a peripheral area surrounding the display area. The display area includes at least two display partitions, and each display partition has multiple power voltage signal lines. The peripheral area includes gating devices corresponding to each display partition one by one. The input ends of the gating devices are all connected to a power voltage bus, and the output ends of the gating devices are connected to the multiple power voltage signal lines in the corresponding display partition. Each gating device is used to conduct each power voltage signal line and the power voltage bus in the display partition at different times. In this way, the light-emitting devices in different display partitions can be conducted at different times, avoiding the situation where the current is too large when the light-emitting devices corresponding to all pixels in the display substrate are aged simultaneously, and improving the qualification rate of the display product.

Description

Technical Field

[0001] The present invention relates to the technical field of display control, and particularly to a display substrate, an aging control method for the display substrate, and a display device. Background Art

[0002] In the display industry, organic light-emitting diode (OLED) products are always aged before leaving the factory, that is, the Lifetime-Aging process is used to age the light-emitting devices in advance, and the inherent rapid decay stage of the light-emitting devices is consumed in advance, so as to improve the lifespan of the light-emitting devices and ensure the passing rate of the products leaving the factory.

[0003] Currently, when the Lifetime-Aging process is performed on a large-size OLED display panel, the following problems exist: The Lifetime-Aging current (i.e., the aging current) is generally larger than the normal lighting current of the pixels. Since the display panel is large in size and all pixels are lit during Lifetime-Aging, the current of the display panel during Lifetime-Aging is too large, and in severe cases, the power supply line may even be burned. Summary of the Invention

[0004] Embodiments of the present invention provide a display substrate, an aging control method for the display substrate, and a display device, which are used to solve the problem that the aging current of all pixels of the display panel is too large in the prior art.

[0005] A display substrate provided by an embodiment of the present invention includes a display area and a peripheral area surrounding the display area;

[0006] The display area includes at least two display partitions, and each display partition has multiple power voltage signal lines;

[0007] The peripheral area includes gating devices corresponding to each display partition one by one. The input ends of each gating device are all connected to the power voltage bus, and the output ends of each gating device are connected to the multiple power voltage signal lines in the corresponding display partition; each gating device is used to conduct each power voltage signal line and the power voltage bus in the display partition in a time-sharing manner.

[0008] Optionally, the control ends of each gating device are respectively connected to different external control lines.

[0009] Optionally, the control ends of some of all the gating devices are short-circuited and then respectively connected to different external control lines.

[0010] Optionally, the display partitions corresponding to the gating devices with short-circuited control ends are arranged at intervals.

[0011] Optionally, the number of power supply voltage signal lines in each display partition is the same.

[0012] Optionally, the gating device is a P-type transistor and / or an N-type transistor.

[0013] Optionally, the power supply voltage bus is a high-level power supply bus, and the power supply voltage signal line is a high-level power supply signal line; and / or,

[0014] The power supply voltage bus is a low-level power supply bus, and the power supply voltage signal line is a low-level power supply signal line.

[0015] Optionally, the peripheral area has a bending area, and the gating device and the power supply voltage bus are both arranged on a side of the bending area away from the display area.

[0016] Accordingly, an embodiment of the present invention further provides an aging control method for a display substrate, comprising:

[0017] All the gating devices are controlled to be turned on in time division, and when some of the gating devices are turned on, other gating devices are controlled to be turned off so that each display partition is subjected to aging treatment in time division.

[0018] Correspondingly, an embodiment of the present invention further provides a display device, comprising any one of the display substrates described above.

[0019] The beneficial effects of the present invention are as follows:

[0020] The embodiments of the present invention provide a display substrate, an aging control method for a display substrate, and a display device. The display substrate includes: a display area and a peripheral area surrounding the display area. The display area includes at least two display partitions, each display partition has a plurality of power supply voltage signal lines, and the peripheral area includes gating devices corresponding to each display partition one by one. The input end of each gating device is connected to a power supply voltage bus, and the output end of each gating device is connected to a plurality of power supply voltage signal lines in the corresponding display partition. Each gating device is used to time-share conduct each power supply voltage signal line and the power supply voltage bus in the display partition. In this way, the light-emitting devices in different display partitions can be time-sharedly conducted, thereby avoiding the situation where the current is too large when the light-emitting devices corresponding to all pixels in the display substrate are aged at the same time, thereby improving the qualified rate of the display products. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of a display substrate in the prior art;

[0022] Figure 2 A schematic diagram of the structure of a display substrate provided in an embodiment of the present application;

[0023] Figure 3Schematic diagram of a display substrate for performing partitioned aging controlled by a high-level power bus provided by an embodiment of the present application;

[0024] Figure 4 Schematic diagram of a display substrate for performing partitioned aging controlled by a low-level power bus provided by an embodiment of the present application;

[0025] Figure 5 Schematic diagram of a display substrate for performing partitioned aging controlled by a high-level power bus and a low-level power bus provided by an embodiment of the present application. Detailed implementation manners

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. And, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0027] Unless otherwise defined, the technical terms or scientific terms used in the present application shall have the ordinary meanings understood by those of ordinary skill in the art to which the present application pertains. The "first", "second", and similar terms used in the present application do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0028] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of the present application. And, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout.

[0029] First, a common display substrate in the prior art will be introduced. Refer to Figure 1 As shown, the display area of the display substrate includes a plurality of power voltage signal lines. Some of the plurality of power voltage signal lines are arranged horizontally, and the remaining power voltage signal lines are arranged vertically. Each power voltage signal line converges in the pad area below the display area.

[0030] During the normal light-emitting process, each of the above-mentioned power supply voltage signal lines is respectively connected to the power supply voltage buses VDD and VSS to trigger the light-emitting devices corresponding to the pixel units to emit light. Usually, during normal light emission, the above-mentioned VDD voltage is 4.6V and the above-mentioned VSS voltage is -2.4V. During the Lifetime-Aging process, the voltage corresponding to the power supply voltage bus VDD connected by each of the above-mentioned power supply voltage signal lines increases, and the voltage corresponding to VSS decreases, so as to determine the aging voltage. Through the above-mentioned aging voltage, the light-emitting devices corresponding to the pixel units are further triggered to perform aging treatment. Obviously, the light-emitting devices in the entire display substrate are aged simultaneously.

[0031] An embodiment of the present application provides a display substrate. Refer to Figure 2 As shown, it includes a display area and a peripheral area surrounding the display area.

[0032] The display area includes at least two display partitions, and each display partition has multiple power supply voltage signal lines.

[0033] The above-mentioned display area specifically refers to the area covered by all the power supply voltage signal lines in the display substrate. Some of the above-mentioned all power supply voltage signal lines are arranged horizontally, and the rest of the power supply voltage signal lines are arranged vertically. It should be noted that the horizontal distance between any two horizontally arranged power supply voltage signal lines can be equal or unequal, and the vertical distance between any two vertically arranged power supply voltage signal lines can be equal or unequal.

[0034] In the embodiment of the present application, the above-mentioned display area is divided into multiple display partitions, and the above-mentioned multiple display partitions do not perform the Lifetime-Aging process at the same time, that is, the time-sharing aging of each display partition is realized. Correspondingly, each display partition includes at least one power supply voltage signal line, and the number of power supply voltage signal lines included in each display partition can be equal or unequal.

[0035] The peripheral area includes gating devices corresponding to each display partition one by one. The input ends of each gating device are all connected to the power supply voltage bus, and the output ends of each gating device are connected to multiple power supply voltage signal lines in the corresponding display partition; each gating device is used to conduct each power supply voltage signal line and the power supply voltage bus in the display partition in a time-sharing manner.

[0036] The above-mentioned peripheral area surrounds the display area. Specifically, the power supply voltage buses connected to the power supply voltage signal lines in the peripheral area surround the display area, and gating devices are also arranged in the peripheral area. The number of gating devices is the same as the number of display partitions. The input ends of the gating devices corresponding to each display partition are connected to the power supply voltage buses in the display partition, and the output ends of the gating devices corresponding to each display partition are connected to multiple power supply voltage signal lines in the display partition.

[0037] When the above-mentioned gating devices are turned on, each power supply voltage signal line in the display partition is connected to the power supply voltage bus, so that an aging current is generated in the pixel units in the display partition; when the gating devices are turned off, each power supply voltage signal line in the display partition is not connected to the power supply voltage bus, so that the pixel units in the display partition cannot generate an aging current.

[0038] In order to make the aging effect of the display substrate more uniform, the number of power supply voltage signal lines in each display partition is the same.

[0039] In one embodiment, the number of horizontally arranged power supply voltage signal lines included in each display partition in the display area is the same, and the number of vertically arranged power supply voltage signal lines included in each display partition in the display area is also the same. In this way, the number of pixels covered in the display partition is the same, and each pixel can be evenly aged under the same aging current.

[0040] In the embodiments of the present application, the control ends of the gating devices are respectively connected to different external control lines. In order to be able to independently control each display partition, the control ends of the above-mentioned gating devices can be controlled by different external control lines. Usually, the above-mentioned different external control lines are arranged in a terminal block and are connected to different gating devices through different pins. During the aging process, different voltage values are applied to different pins in the terminal block to achieve the conduction and closing of each gating device.

[0041] Optionally, the gating device is a P-type transistor and / or an N-type transistor.

[0042] The first case: When the gating device is a P-type transistor, the control end of the gating device is the G pole of the P-type transistor, the input end of the gating device is the S pole of the P-type transistor, and the output end of the gating device is the D pole of the P-type transistor.

[0043] The second case: When the gating device is an N-type transistor, the control end of the gating device is the G pole of the N-type transistor, the input end of the gating device is the D pole of the N-type transistor, and the output end of the gating device is the S pole of the N-type transistor.

[0044] In one embodiment, some of the all-gating devices are P-type transistors, and the remaining gating devices among the all-gating devices are N-type transistors, without further limitation here.

[0045] Considering that the number of display partitions in the display area may be relatively large, and accordingly the number of corresponding gating devices is also relatively large. For the convenience of control, in the embodiments of the present application, the control terminals of some of the all-gating devices are short-circuited and then respectively connected to different external control lines. That is, some of the gating devices are controlled by the same external control line, so that in the implementation process, it is convenient to control them when the number of gating devices is large.

[0046] Optionally, the display partitions corresponding to the gating devices with short-circuited control terminals are arranged at intervals.

[0047] Since the pixels in the display partition will affect the surrounding pixels under the control of the aging current, in order to eliminate the above effects (such as heat dissipation effects, etc.), in the implementation process, the display partitions corresponding to the gating devices with short-circuited control terminals are arranged at intervals. In this way, the pixels in the entire display area can be aged more uniformly under the control of the aging current, so that the aging current in the display area is relatively balanced, and the influence of the aging current on the life of the light-emitting device is reduced.

[0048] Optionally, the power voltage bus is a high-level power voltage bus, and the power voltage signal line is a high-level power voltage signal line; and / or,

[0049] The power voltage bus is a low-level power voltage bus, and the power voltage signal line is a low-level power voltage signal line.

[0050] Case 1: The above power voltage bus is a high-level power voltage bus, and the power voltage signal line is a high-level power voltage signal line.

[0051] In the implementation process, the power voltage bus is a high-level power voltage bus, that is, VDD. Correspondingly, the high-level power voltage bus VDD is connected to the input end of the gating device, and the high-level power voltage signal line is connected to the output end of the gating device, realizing the high-level control of the light-emitting device.

[0052] Case 2: The power voltage bus is a low-level power voltage bus, and the power voltage signal line is a low-level power voltage signal line.

[0053] In the implementation process, the power voltage bus is a low-level power voltage bus, that is, VSS. Correspondingly, the low-level power voltage bus VSS is connected to the input end of the gating device, and the low-level power voltage signal line is connected to the output end of the gating device, realizing the low-level control of the light-emitting device.

[0054] In order to achieve a better display effect in the display area, the peripheral area in the embodiments of the present application has a bending area, and the gating device and the power voltage bus are both arranged on the side of the bending area away from the display area. Specifically, each gating device for controlling each display partition is separately arranged from the display area, and the above-mentioned power voltage bus, etc. are also separately arranged from the display area. Preferably, the gating device and the power voltage bus are both arranged in the bending area. In this way, while each display partition is turned on in a time-division manner for aging, the display effect of the display area is not affected.

[0055] The above is only an example to illustrate the specific structures of the circuits in the calibration system provided by the embodiments of the present application. In specific implementation, the specific structures of the above circuits are not limited to those provided by the embodiments of the present application, and may also be other structures known to those skilled in the art, all of which are within the protection scope of the present application and are not specifically limited herein.

[0056] The embodiments of the present invention also provide an aging control method for a display substrate, which may include the following steps:

[0057] Control all gating devices to be turned on in a time-division manner, and when some gating devices are turned on, control other gating devices to be turned off so that each display partition is aged in a time-division manner.

[0058] It should be noted that during the aging process, only some display partitions in the display area are turned on at the same time, and the rest of the display partitions are not turned on. The on / off state of the display partitions in the above process is controlled by the corresponding gating devices, that is, each gating device is turned on in a time-division manner under the control of different external control lines, so that each display partition in the display area is correspondingly turned on and aged.

[0059] The following will be specifically described through the following two examples.

[0060] Example 1, the display area in the display substrate includes four sequentially arranged display partitions. Suppose the four display partitions are display partition a, display partition b, display partition c, and display partition d from left to right, and each display partition has multiple power voltage signal lines (two vertically arranged power voltage signal lines).

[0061] A peripheral area is provided outside the above-mentioned display area. The peripheral area includes four gating devices. Refer to Figure 3As shown, the input ends of the above four gating devices are all connected to the power supply voltage bus VDD, and the output ends of the above four gating devices are all connected to multiple power supply voltage signal lines in the above display partition. At the same time, it is assumed that the four gating devices are P-type transistors T1, P-type transistor T2, P-type transistor T3, and P-type transistor T4 respectively. The above display partition a corresponds to P-type transistor T1, the above display partition b corresponds to P-type transistor T2, the above display partition c corresponds to P-type transistor T3, and the above display partition d corresponds to P-type transistor T4.

[0062] The following takes Figure 3 as an example to illustrate in detail. During the Lifetime-Aging process, the input ends of each gating device are all connected to the high-level power supply bus VDD (for example, any voltage value between 5V and 8V), and the output ends of each gating device are connected to multiple power supply voltage signal lines in the corresponding display partition. In this case, the low-level power supply bus VSS is usually -2.4V.

[0063] During the first aging period, P-type transistor T1 conducts under the voltage control of the external control line VG1, P-type transistor T3 conducts under the voltage control of the external control line VG3, P-type transistor T2 is cut off under the voltage control of the corresponding external control line VG2, and P-type transistor T4 is cut off under the voltage control of the corresponding external control line VG4. The above display partition a conducts the high-level power supply bus VDD and each power supply voltage signal line included in the display partition a when P-type transistor T1 conducts, and the display partition c conducts the high-level power supply bus VDD and each power supply voltage signal line included in the display partition c when P-type transistor T3 conducts. That is, the display partitions a and c are aged under the voltage trigger of VDD, while the display partitions b and d are not aged.

[0064] During the second aging period, P-type transistor T2 conducts under the voltage control of the external control line VG2, P-type transistor T4 conducts under the voltage control of the external control line VG4, P-type transistor T1 is cut off under the voltage control of the corresponding external control line VG1, and P-type transistor T3 is cut off under the voltage control of the corresponding external control line VG3. The above display partition b conducts the high-level power supply bus VDD and each power supply voltage signal line included in the display partition b when P-type transistor T2 conducts, and the display partition d conducts the high-level power supply bus VDD and each power supply voltage signal line included in the display partition d when P-type transistor T4 conducts. That is, the display partitions b and d are aged under the voltage trigger of VDD, while the display partitions a and c are not aged.

[0065] Example 2. The display area on the display substrate includes four sequentially arranged display partitions. Assume that the four display partitions are, from left to right, display partition a, display partition b, display partition c, and display partition d, and each display partition has multiple power voltage signal lines (two vertically arranged power voltage signal lines).

[0066] A peripheral area is provided around the above display area, and the peripheral area includes four gating devices. Refer to Figure 4 and Figure 5 As shown, the input ends of the above four gating devices are all connected to the power voltage bus VSS, and the output ends of the above four gating devices are all connected to the multiple power voltage signal lines in the above display partition. At the same time, assume that the four gating devices are P-type transistors T1, P-type transistors T2, P-type transistors T3, and P-type transistors T4 respectively. The above display partition a corresponds to the P-type transistor T1, the above display partition b corresponds to the P-type transistor T2, the above display partition c corresponds to the P-type transistor T3, and the above display partition d corresponds to the P-type transistor T4.

[0067] The following takes Figure 4 as an example to illustrate in detail. During the Lifetime-Aging process, the input ends of each gating device are all connected to the low-level power voltage bus VSS (for example, any voltage value between -3V and -8V), and the output ends of each gating device are connected to the multiple power voltage signal lines in the corresponding display partition.

[0068] During the first aging period, the P-type transistor T1 is turned on under the voltage control of the external control line VG1, the P-type transistor T3 is turned on under the voltage control of the external control line VG3, the P-type transistor T2 is turned off under the voltage control of the corresponding external control line VG2, and the P-type transistor T4 is turned off under the voltage control of the corresponding external control line VG4. The above display partition a turns on the low-level power voltage bus VSS and each power voltage signal line included in the display partition a under the condition that the P-type transistor T1 is turned on, and the display partition c turns on the low-level power voltage bus VSS and each power voltage signal line included in the display partition c under the condition that the P-type transistor T3 is turned on. In this case, VDD is the normal lighting current (for example, 4.6V), that is, the display partition a and the display partition c are aged under the voltage trigger of VDD and VSS, while the display partition b and the display partition d are not aged.

[0069] During the second aging period, the P-type transistor T2 is turned on under the voltage control of the external control line VG2, the P-type transistor T4 is turned on under the voltage control of the external control line VG4, the P-type transistor T1 is turned off under the voltage control of the corresponding external control line VG1, and the P-type transistor T3 is turned off under the voltage control of the corresponding external control line VG3. The above display partition b turns on the low-level power supply bus VSS and each power supply voltage signal line included in the display partition b when the P-type transistor T2 is turned on. The display partition d turns on the low-level power supply bus VSS and each power supply voltage signal line included in the display partition d when the P-type transistor T4 is turned on. In this case, VDD is the normal lighting current (for example, 4.6V), that is, the display partitions b and d are aged under the voltage trigger of VDD and VSS, while the display partitions a and c are not aged.

[0070] An embodiment of the present invention further provides a display device, including the display substrate described in any one of the above.

[0071] The display substrate included in the above display device can perform the Lifetime-Aging process under the time-division conduction control of each gating device, that is, different display partitions of the display substrate are aged at different times respectively, thereby avoiding the situation of excessive current when the display device is aging.

[0072] A display substrate, an aging control method of the display substrate, and a display device provided by an embodiment of the present application. The above display substrate includes: a display area and a peripheral area surrounding the display area. The display area includes at least two display partitions, and each display partition has multiple power supply voltage signal lines. The peripheral area includes gating devices corresponding to each display partition one by one. The input ends of each gating device are all connected to the power supply voltage bus, and the output ends of each gating device are connected to multiple power supply voltage signal lines in the corresponding display partition. Each gating device is used to conduct each power supply voltage signal line and the power supply voltage bus in the display partition in a time-division manner. In this way, the light-emitting devices in different display partitions can be conducted in a time-division manner, avoiding the situation of excessive current when all the light-emitting devices corresponding to all pixels in the display substrate are aged at the same time, and improving the qualification rate of the display product.

[0073] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0074] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to the application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to generate a machine, such that the instructions executed by the processors of the computer or other programmable data processing devices produce means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0075] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0076] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in multiple blocks.

[0077] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.

Claims

1. A display substrate, characterized in that, Comprising: A display area and a peripheral area surrounding the display area; The display area includes at least two display partitions, and each display partition has a plurality of power voltage signal lines; The peripheral area includes gating devices corresponding to each of the display partitions one by one. The input ends of the gating devices are all connected to a power voltage bus, and the output ends of the gating devices are connected to the plurality of power voltage signal lines in the corresponding display partition; each of the gating devices is used to conduct each power voltage signal line and the power voltage bus in the display partition in a time-sharing manner; The control ends of some of the gating devices among all the gating devices are short-circuited and then respectively connected to different external control lines, and the display partitions corresponding to the gating devices with short-circuited control ends are arranged at intervals.

2. The display substrate according to claim 1, characterized in that The control ends of each of the gating devices are respectively connected to different external control lines.

3. The display substrate according to claim 1, wherein The number of the power voltage signal lines in each of the display partitions is the same.

4. The display substrate according to any one of claims 1 to 3, characterized in that, The gating device is a P-type transistor and / or an N-type transistor.

5. The display substrate according to any one of claims 1 to 3, characterized in that, The power voltage bus is a high-level power bus, and the power voltage signal line is a high-level power signal line; and / or, The power voltage bus is a low-level power bus, and the power voltage signal line is a low-level power signal line.

6. The display substrate according to any one of claims 1 to 3, characterized in that, The peripheral area has a bent area, and the gating device and the power voltage bus are both arranged on a side of the bent area away from the display area.

7. An aging control method for a display substrate according to any one of claims 1-6, characterized in that, Comprising: Controlling all the gating devices to conduct in a time-sharing manner, and controlling other gating devices to be turned off when some of the gating devices conduct, so that each display partition is subjected to aging treatment in a time-sharing manner.

8. A display device, characterized in that, Including the display substrate according to any one of claims 1 to 6.

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